A longitudinal structure TVS chip for vehicle overvoltage protection and a manufacturing method thereof

Abstract

The application provides a longitudinal structure TVS chip for vehicle overvoltage protection and a manufacturing method thereof. The TVS chip comprises a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, an isolation layer and an isolation deep groove. The second conductive layer and the first conductive layer jointly form a lower diode, and the fourth conductive layer and the third conductive layer jointly form an upper diode. The upper diode and the lower diode are connected in series and isolated by the isolation layer. The TVS chip can realize bidirectional medium and high voltage by using a single chip. The breakdown voltage can be adjusted by doping concentration, and the TVS chip can meet various vehicle circuit protection requirements. The high-temperature characteristic of the TVS chip is good, the product performance is stable at 125 DEG C, and there is no obvious fluctuation. The chip adopts a longitudinal structure, can save area and is suitable for surface mount packaging.

Description

Technical Field

[0001] This invention relates to transient voltage suppressor chips, and more particularly to a longitudinal structure TVS chip for automotive overvoltage protection and its manufacturing method. Background Technology

[0002] Electronic circuits are easily damaged by overvoltage, overcurrent, and surges. With technological advancements, electronic circuit products are becoming increasingly diverse and complex, and circuit protection components are also becoming more diverse and offer increasingly superior protection performance. Vehicle-mounted equipment operates in harsher environments than general electronic products. Vehicle driving conditions are highly variable, and large instantaneous peak voltages are generated during vehicle startup. Therefore, power adapters for these electronic devices typically require overvoltage protection components.

[0003] Automotive chips have higher requirements for reliability and high-temperature performance compared to ordinary chips. They also have a wider operating temperature range than ordinary industrial-grade chips, which range from -40℃ to 85℃. Therefore, overvoltage protection chips with high reliability and good high-temperature performance are an indispensable component in automotive circuit applications, and the commonly used overvoltage protection chips still need improvement. Summary of the Invention

[0004] The purpose of this invention is to provide a longitudinal structure TVS chip for vehicle overvoltage protection and its manufacturing method, so as to improve its reliability in protecting vehicle circuits.

[0005] The technical solution adopted by this invention to solve its technical problem is as follows:

[0006] A longitudinally structured TVS chip for automotive overvoltage protection includes:

[0007] A first conductive layer, wherein the first conductive layer is of a first conductive type;

[0008] The second conductive layer is formed on the surface of the first conductive layer and is of the second conductivity type. Its resistivity is less than that of the first conductive layer. The second conductivity type is the opposite of the first conductivity type. A breakdown voltage will be generated between the two, forming diode characteristics, so that the second conductive layer and the first conductive layer together form a lower diode.

[0009] A third conductive layer, wherein the third conductive layer is of the first conductive type;

[0010] The fourth conductive layer is formed on the surface of the third conductive layer and is of the second conductivity type. Its resistivity is less than that of the third conductive layer. The second conductivity type is the opposite of the first conductivity type. A breakdown voltage will be generated between the two, forming diode characteristics, so that the fourth conductive layer and the third conductive layer together form an upper diode.

[0011] An isolation layer is formed between the fourth conductive layer and the second conductive layer, and is of the second conductivity type. The isolation layer connects and isolates the upper diode and the lower diode in series, so that the upper diode and the lower diode do not affect each other and avoid forming transistor characteristics.

[0012] An isolation trench extends through the third conductive layer, the fourth conductive layer, and the second conductive layer before reaching the first conductive layer. The isolation trench is filled with insulating material.

[0013] The resistivity of the first and third conductive layers is 10–50 Ω·cm, and the resistivity of the second and fourth conductive layers is 0.1–10 Ω·cm. The breakdown voltages of the upper and lower diodes are symmetrical in both directions.

[0014] The method for manufacturing the longitudinal structure TVS chip for automotive overvoltage protection includes the following steps:

[0015] A substrate of the first conductivity type is selected as the first conductive layer, and its resistivity is 10 to 50 Ω·cm;

[0016] An epitaxial layer of a second conductivity type is grown on the substrate as a second conductive layer, with a resistivity of 0.1 to 10 Ω·cm, depending on the required breakdown voltage;

[0017] An implantation masking layer was grown on the epitaxial layer using a thermal oxidation process, with a thickness of [missing information].

[0018] Ion implantation of the second conductivity type was performed, with an implantation energy of 40–120 keV and an implantation dose on the order of E15.

[0019] The thermal diffusion process is carried out at a temperature of 900–1200℃ for a time of 20–100 min.

[0020] Wet process is used to remove SiO2 from the front side of the wafer;

[0021] Epitaxial growth of a second conductivity type with a resistivity of 0.1–10 Ω·cm, depending on the required breakdown voltage;

[0022] The implantation masking layer is grown using a thermal oxidation process, and its thickness is [missing information].

[0023] Ion implantation of the first conductivity type was performed, with an implantation energy of 40–100 keV and an implantation dose on the order of E14.

[0024] The thermal diffusion process is carried out at a temperature of 900–1200℃ for a time of 20–100 min.

[0025] Hard mask deposition was performed using PESiO2, with a thickness of 1.5 μm;

[0026] Deep trench lithography includes processes such as coating, exposure, and development.

[0027] Hard mask etching is performed using a dry etching process.

[0028] Remove the photoresist remaining after deep trench photolithography;

[0029] Deep trench etching is performed, with an etching depth of 20 μm;

[0030] Remove the hard mask;

[0031] For deep trench filling, linear oxide filling is used first. Then, a low-pressure tetraethyl orthosilicate deposition process is used for filling;

[0032] Contact hole photolithography is performed, including the processes of coating, exposure, and development.

[0033] Contact hole etching is performed using either dry or wet methods.

[0034] Front-side metal sputtering was performed using Ti / TiN+4UM AlSiCu;

[0035] Perform front-side metal lithography, including the processes of coating, exposure, and development;

[0036] Metal etching is performed using either dry or wet etching processes;

[0037] A passivation layer with a thickness of 1.5 μm was deposited using USG+Si3N4.

[0038] The passivation layer photolithography process includes coating, exposure, and development.

[0039] The passivation layer was etched using a dry etching process.

[0040] Perform backside grinding; the grinding thickness depends on the packaging requirements.

[0041] The backside is metallized, and the type and thickness of the metal are determined according to the packaging requirements.

[0042] The advantages of this invention are:

[0043] This TVS chip can achieve bidirectional medium and high voltage using a single chip. The breakdown voltage can be adjusted by the doping concentration, which can meet various automotive circuit protection requirements. It has good high temperature characteristics, and the product performance is stable at 125℃ without significant fluctuations. The chip adopts a vertical structure, which can save area and is suitable for surface mount packaging. Attached Figure Description

[0044] Figure 1 This is a schematic cross-sectional view of the longitudinal structure TVS chip for vehicle overvoltage protection proposed in this invention.

[0045] Figure 2 This is the equivalent circuit of the TVS chip;

[0046] Figure 3 This is the transmission line pulse test curve of the TVS chip;

[0047] Figure 4 This is a flowchart of the TVS chip manufacturing process. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0049] like Figure 1As shown, the longitudinal structure TVS chip for vehicle overvoltage protection proposed in this invention includes a first conductive layer 1, a second conductive layer 2, a third conductive layer 3, a fourth conductive layer 4, an isolation layer 5, and an isolation trench 6. The first conductive layer is of the first conductivity type. The second conductive layer is formed on the surface of the first conductive layer and is of the second conductivity type, with a resistivity less than that of the first conductive layer. The second conductivity type is opposite to the first conductivity type, and a breakdown voltage will be generated between them, forming diode characteristics. The second conductive layer and the first conductive layer together form a lower diode. The third conductive layer is of the first conductivity type. The fourth conductive layer is formed on the surface of the third conductive layer and is of the second conductivity type, with a resistivity less than that of the third conductive layer. The second conductivity type is opposite to the first conductivity type, and a breakdown voltage will be generated between them, forming diode characteristics. The fourth conductive layer and the third conductive layer together form an upper diode. The isolation layer is formed between the fourth conductive layer and the second conductive layer and is of the second conductivity type. The isolation layer connects the upper diode and the lower diode in series and isolates them, so that the upper diode and the lower diode do not affect each other and avoid forming transistor characteristics. Its equivalent circuit is as follows: Figure 2 As shown, the isolation trench penetrates the third conductive layer, the fourth conductive layer, and the second conductive layer before reaching the first conductive layer. The isolation trench is filled with insulating material.

[0050] It is important to note that there needs to be a significant concentration difference between the isolation layer and the second and fourth conductive layers. The isolation layer needs to be sufficiently concentrated to better isolate the parasitic transistor characteristics between the upper and lower diodes. The thickness of the second and fourth conductive layers has strict requirements. After thermal processing, the first and third conductive layers must not be in contact with the isolation layer, and there needs to be a flat area between the second and fourth conductive layers. A deep isolation trench must be present around the active area to prevent leakage current in the chip and improve the reliability and performance of the product. At the same time, the depth of the isolation trench must reach the bottom of the first conductive layer, and the filling medium in the trench must be an insulating material. The passivation layer is grown first with silicon dioxide and then with silicon nitride. The combination of these two materials can better protect the active area of ​​the chip and improve the reliability of the chip.

[0051] The resistivity of the first and third conductive layers is 10–50 Ω·cm, and the resistivity of the second and fourth conductive layers is 0.1–10 Ω·cm. The breakdown voltages of the upper and lower diodes are symmetrical in both directions. Figure 3 In one embodiment, the breakdown voltage of the TVS chip is around 30V. The breakdown voltage of the lower diode can be adjusted by adjusting the doping concentration of the second conductivity type A, and the breakdown voltage of the upper diode can be adjusted by adjusting the doping concentration of the second conductivity type C. All medium and high voltages can be adjusted using this structure to meet the application requirements of automotive circuits.

[0052] like Figure 4The fabrication method of the aforementioned vertical structure TVS chip for automotive overvoltage protection includes: selecting a substrate of a first conductivity type as the first conductive layer, with a resistivity of 10–50 Ω·cm; growing an epitaxial layer of a second conductivity type on the substrate as the second conductive layer, with a resistivity of 0.1–10 Ω·cm, depending on the required breakdown voltage; and growing an implantation masking layer on the epitaxial layer using a thermal oxidation process, the thickness of which is… Ion implantation of the second conductivity type is performed at an implantation energy of 40–120 keV, with an implantation dose on the order of E15. Thermal diffusion is then carried out at a temperature of 900–1200 °C for 20–100 min. SiO2 on the front side of the wafer is removed using a wet process. An epitaxial layer of the second conductivity type is grown with a resistivity of 0.1–10 Ω·cm, depending on the required breakdown voltage. An implantation masking layer is grown using a thermal oxidation process, with a thickness of [missing information]. Ion implantation of the first conductivity type was performed at an implantation energy of 40–100 keV, with an implantation dose on the order of E14. Thermal diffusion was then carried out at temperatures of 900–1200 °C for 20–100 min. A hard mask deposition of PESiO2 with a thickness of 1.5 μm was performed. Deep trench lithography was then performed, including resist coating, exposure, and development. Dry etching was then used to etch the hard mask. The resist remaining after deep trench lithography was removed. Deep trench etching was performed to a depth of 20 μm. The hard mask was then removed. Deep trench filling was then performed, initially using linear oxides. Next, a low-pressure tetraethyl orthosilicate deposition process is used for filling; contact hole photolithography is performed, including resist coating, exposure, and development; contact hole etching is performed using dry or wet processes; front-side metal sputtering is performed using Ti / TiN+4μm AlSiCu; front-side metal photolithography is performed, including resist coating, exposure, and development; metal etching is performed using dry or wet etching processes; a passivation layer with a thickness of 1.5μm is deposited using USG+Si3N4; passivation layer photolithography is performed, including resist coating, exposure, and development; passivation layer etching is performed using dry etching processes; back-side grinding is performed, with the grinding thickness determined according to packaging requirements; back-side metallization is performed, with the type and thickness of the metal determined according to packaging requirements.

[0053] In the description of this invention, it should be noted that the terms "upper," "lower," "inner," "outer," "left," and "right," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this invention is in use, or the orientation or positional relationship commonly understood by those skilled in the art. These terms are used only for the convenience of describing this invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention. Furthermore, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance. In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, terms such as "set" and "connect" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

Claims

1. A longitudinally structured TVS chip for automotive overvoltage protection, characterized in that, include: A first conductive layer, wherein the first conductive layer is of a first conductive type; The second conductive layer is formed on the upper surface of the first conductive layer and is of the second conductivity type. Its resistivity is less than that of the first conductive layer. The second conductivity type is the opposite of the first conductivity type, so that the second conductive layer and the first conductive layer together form a lower diode. A third conductive layer, wherein the third conductive layer is of the first conductive type; The fourth conductive layer is formed on the lower surface of the third conductive layer and is of the second conductivity type. Its resistivity is less than that of the third conductive layer. The second conductivity type is the opposite of the first conductivity type, so that the fourth conductive layer and the third conductive layer together form an upper diode. An isolation layer is formed between the fourth conductive layer and the second conductive layer, and is of the second conductivity type. The isolation layer connects and isolates the upper diode and the lower diode in series. An isolation trench extends through the third conductive layer, the fourth conductive layer, and the second conductive layer before reaching the first conductive layer. The isolation trench is filled with insulating material.

2. The longitudinal structure TVS chip for vehicle overvoltage protection according to claim 1, characterized in that: The resistivity of the first and third conductive layers is 10–50 Ω·cm, and the resistivity of the second and fourth conductive layers is 0.1–10 Ω·cm. The breakdown voltages of the upper and lower diodes are symmetrical in both directions.

3. The method for manufacturing a longitudinal structure TVS chip for vehicle overvoltage protection according to claim 1, characterized in that, Includes the following steps: A substrate of the first conductivity type is selected as the first conductive layer, and its resistivity is 10 to 50 Ω·cm; An epitaxial layer of a second conductivity type is grown on the substrate as a second conductive layer, with a resistivity of 0.1 to 10 Ω·cm, depending on the required breakdown voltage; An implantation masking layer with a thickness of 50-300 Å is grown on the epitaxial layer using a thermal oxidation process. Ion implantation of the second conductivity type is performed with an implantation energy of 40-120 keV and an implantation dose on the order of E15. Thermal diffusion is then performed at a temperature of 900-1200 °C for 20-100 min to form the isolation layer. The SiO2 on the front side of the wafer is removed by a wet process; an epitaxial layer of the second conductivity type is grown with a resistivity of 0.1 to 10 Ω·cm, depending on the required breakdown voltage, to form the fourth conductive layer; A thermal oxidation process was used to grow an implantation masking layer with a thickness of 50-300 Å. Ion implantation of the first conductivity type was performed with an implantation energy of 40-100 keV and an implantation dose on the order of E14. A thermal diffusion process is carried out at a temperature of 900–1200°C for 20–100 minutes to form the third conductive layer; Hard mask deposition with PESiO2 was performed, with a thickness of 1.5μm; deep trench lithography was performed, including resist coating, exposure, and development processes; and hard mask etching was performed using a dry etching process. Remove the photoresist remaining after deep trench photolithography; perform deep trench etching to a depth of 20 μm; Remove the hard mask; The deep trench is filled by first using linear oxide filling and then using a low-pressure tetraethyl orthosilicate deposition process to form the isolation deep trench. Contact hole photolithography is performed, including the processes of coating, exposure, and development. Contact hole etching is performed using either dry or wet methods. Front-side metal sputtering was performed using Ti / TiN+4μm AlSiCu; Perform front-side metal lithography, including the processes of coating, exposure, and development; Metal etching is performed using either dry or wet etching processes; A passivation layer with a thickness of 1.5 μm was deposited using USG+Si3N4. The passivation layer photolithography process includes coating, exposure, and development. The passivation layer was etched using a dry etching process. Perform backside grinding; the grinding thickness depends on the packaging requirements. The backside is metallized, and the type and thickness of the metal are determined according to the packaging requirements.

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