A method, apparatus, and base station for multiple frame structure configurations

Abstract

The present invention discloses a method, apparatus and base station for configuring multiple frame structures. The configuration method includes: configuring N frame structure timings; calculating the uplink and downlink times of each frame mode; configuring the uplink and downlink times of each frame mode into corresponding registers; opening / closing the bus interface AXIQ according to the calculated accurate uplink and downlink times; the decision feedback equalizer fills IQ data for N*10 time slots according to the configured timings; receiving and transmitting according to the configured multiple frame structure timings. The present invention proposes that it can support configuring multiple completely different frame structure timings, such as 4 frame structure timings, with each 5 ms being a frame timing ratio, and the 20 ms frame structure time window is composed of four different frame timings; it proposes a mechanism for supporting simultaneous communication of terminals with four different frame structure timings; it saves three sets of communication devices; it improves the terminal access capability, which is equivalent to saving the construction costs of three sets of base stations and greatly reducing the construction cost of the communication system.

Description

Technical Field

[0001] The present invention belongs to the field of mobile communications, and relates to a configuration method for supporting multiple frame structure timings, in particular to a method and device for a same base station to support multiple frame structure timings. Background Art

[0002] The frame structure of a mobile communication system has a great impact on transmission performance. Some low-latency services require sub-frame designs with shorter Transmission Time Intervals (TTIs), but sub-frames with too short TTIs may cause segmentation of large data packet services, affecting continuous transmission performance. However, the current frame structure design is relatively fixed. Generally, communication base station equipment only supports one frame structure timing configuration. Therefore, it can only communicate with the same type of terminal. If it is necessary to support terminal communications with four different frame structure timings simultaneously, the operator needs to lay four sets of different communication base stations. Therefore, the prior art is difficult to meet the diverse service transmission requirements.

[0003] For example, a patent application with the application number CN201710969079.2 discloses a wireless frame structure, its configuration method, configuration device, and physical channel structure. The wireless frame structure therein includes: a first type of frame structure and a second type of frame structure. The sub-frame lengths of the first type of frame structure and the second type of frame structure are the same, and at least one of the number of TTIs included in the sub-frame and the number of symbols included in the TTI is different. The wireless frame structure provided by this invention includes different types of frame structures, and these different types of frame structures have different transmission time interval information, which can meet the diverse service transmission requirements. However, this invention not only has a complex software architecture, but also each frame structure can only communicate with a corresponding type of frame structure terminal. Summary of the Invention

[0004] A brief overview of the embodiments of the present invention is given below to provide a basic understanding of certain aspects of the present invention. It should be understood that the following overview is not an exhaustive overview of the present invention. It is not intended to identify the key or important parts of the present invention, nor is it intended to limit the scope of the present invention. Its purpose is only to present certain concepts in a simplified form as a prelude to the more detailed description to follow.

[0005] According to one aspect of the present application, a method for configuring multiple frame structures is provided, which includes:

[0006] Configuring N frame structure timings;

[0007] Calculating the uplink and downlink times of each frame mode;

[0008] Configuring the uplink and downlink times of each frame mode into corresponding registers;

[0009] Open / close the bus interface AXIQ according to the calculated accurate uplink and downlink times;

[0010] The decision feedback equalizer fills the IQ data of N*10 time slots according to the configured timing;

[0011] Receive and transmit according to the configured timing of multiple frame structures.

[0012] Furthermore, configuring the timing of multiple frame structures can be achieved by writing each frame structure into the code, and four different frame structure timings will run automatically during program operation; or four different frame structure configurations can be manually changed in the core network.

[0013] As a specific example, the configuration of multiple frame structure timings is to configure 4 frame structure timings, specifically including: configuring a 20ms wireless window, filling a 5ms frame structure 1, filling a 5ms frame structure 2, filling a 5ms frame structure 3, filling a 5ms frame structure 4, and finally running the 20ms wireless window. These 4 frame structure timings include 4 frame structures arranged in sequence to form a frame structure combination timing. Each frame structure has 10 time slots, and for four frame structures, it is 10*4 = 40. Then the decision feedback equalizer fills the IQ data of 40 time slots according to the configured timing.

[0014] As a specific example, the configuration of multiple frame structure timings can be to configure other numbers of frame structure timings, such as 3 frame structure timings, that is, writing three frame structures into the register, with each frame structure being 5ms, and then the transceiver IQ time can be changed to 15ms.

[0015] Furthermore, the multiple frame structure timings include multiple frame structures arranged in sequence to form a frame structure combination timing. The parameters of each frame structure include frame structure parameters such as the downlink frame time slot d_slot, special symbol s, and the number of uplink time slots u_slot. One frame structure contains 10 time slots, and each time slot contains 14 symbols.

[0016] According to another aspect of the present application, there is provided a device for configuring multiple frame structures, which includes:

[0017] A configuration unit for configuring the timing of multiple frame structures;

[0018] An uplink and downlink time calculation unit for calculating the uplink and downlink times of each frame mode;

[0019] An uplink and downlink time configuration unit for configuring the uplink and downlink times of each frame mode into the corresponding registers;

[0020] The bus interface AXIQ unit opens / closes the bus interface AXIQ according to the calculated accurate uplink and downlink times;

[0021] A decision feedback equalizer unit, and the decision feedback equalizer fills IQ data for 40 time slots according to the configured timing.

[0022] A transceiver unit, which receives and transmits according to the configured timing of multiple frame structures.

[0023] According to another aspect of the present application, a base station applying the above-mentioned multiple frame structure configuration method or device is provided.

[0024] The present invention adopts the above scheme and has the following advantages:

[0025] 1. It is proposed that multiple completely different frame structure timings can be supported, such as 4 frame structure timings, with each 5 ms as a frame timing ratio, and the 20 ms frame structure time window is composed of four different frame timings;

[0026] 2. A mechanism for simultaneously supporting four different frame structure timings for terminals to communicate simultaneously is proposed;

[0027] 3. Compared with communicating with terminals of four different frame structures, three sets of communication devices are saved; the terminal access ability is improved, which is equivalent to saving the construction cost of three sets of base stations, and greatly reducing the construction cost of the communication system. Compared with communicating with terminals of four different frame structures, three sets of communication devices are saved; the terminal access ability is improved, which is equivalent to saving the construction cost of three sets of base stations, and greatly reducing the construction cost of the communication system. Description of the Drawings

[0028] The present invention can be better understood by referring to the description given below in conjunction with the accompanying drawings, in which the same or similar reference numerals are used in all the drawings to denote the same or similar components. The accompanying drawings, together with the following detailed description, are included in this specification and form a part of this specification, and are used to further illustrate the preferred embodiments of the present invention and explain the principles and advantages of the present invention. In the drawings:

[0029] Figure 1 is a flowchart of the multiple frame structure configuration method according to an embodiment of the present invention;

[0030] Figure 2 is a flowchart of configuring four frame structure timings according to an embodiment of the present invention;

[0031] Figure 3 is a diagram of four frame structure timings of 20 ms according to an embodiment of the present invention;

[0032] Figure 4 is a diagram of the frame structure timing of each 5 ms according to an embodiment of the present invention;

[0033] Figure 5 is a diagram of the timing of each special time slot according to an embodiment of the present invention. Detailed implementation manners

[0034] Embodiments of the present invention will be described below with reference to the accompanying drawings. Elements and features described in one drawing or one embodiment of the present invention may be combined with elements and features shown in one or more other drawings or embodiments. It should be noted that for the sake of clarity, representations and descriptions of components and processes that are irrelevant to the present invention and are known to those of ordinary skill in the art are omitted in the drawings and the description.

[0035] As a specific embodiment, the present invention provides a timing implementation scheme in which a base station supports four frame structure timing configurations and simultaneously supports communication with terminals of four different frame structures. Taking the subcarrier interval of 30 kHz as an example, each 5 ms is a frame structure, and the 20 ms transceiver timing can be used to transmit and receive data of terminal devices with four different frame structures.

[0036] See Figure 1 , and the method for configuring multiple frame structures specifically includes the following processes:

[0037] (1). Configure the timing of four frame structures; the configuration flow chart is as Figure 2 shown

[0038] (2). Calculate the uplink and downlink times of each frame mode;

[0039] (3). Configure the uplink and downlink times of each mode into the corresponding registers;

[0040] ((4). Open / close the bus interface AXIQ according to the calculated accurate uplink and downlink times;

[0041] (5). The decision feedback equalizer VSPA fills the IQ data of 40 time slots according to the configured timing;

[0042] (6). Transmit and receive according to the configured timing of the four frame structures.

[0043] [[ID=?]]The decision feedback equalizer VSPA is equivalent to the DFE module in a general-purpose chip.

[0044] The working principle is introduced as follows: The overall architecture is a software architecture that relies on the system's API to build a comprehensive basic application as the backbone of the L1 application, realizing the general function processing of the architecture. The key difference between different participants in the architecture lies in their priorities: The agent has the highest priority, and the process has a lower priority. In addition, the agent tends to a specific field, namely radio control, timing control, and VSPA control, while the process is an application that connects all participants together. The timing control module configures 4 frame modes as needed, calculates the accurate uplink and downlink times for each frame mode, writes them into the timing configuration register, and then opens / closes the bus interface AXIQ enable switch according to the accurate uplink and downlink times. The VPSA fills 40 time slots according to the mode given by the timing control module and performs IQ data transceiver corresponding to a 20ms wireless frame window.

[0045] In this embodiment, the 4-frame structure timings include a frame structure combination timing formed by arranging 4 frame structures in sequence. The 4-frame structure timings of 20ms are as Figure 3 shown, where d_slot is the downlink frame time slot, s is the special time slot, and u_slot is the number of uplink time slots. A frame structure contains 10 time slots, and each time slot contains 14 symbols. The frame structure timing of every 5ms (taking the frame structure timing P1 as an example, P2 / P3 / P4 can be the same as or different from it) is as Figure 4 shown. The 7-bit D in the figure corresponds to the downlink frame time slot d_slot, the S in the figure corresponds to the special time slot s (the physical meanings of S and s are the same), and the two-bit U in the figure corresponds to the number of uplink time slots u_slot. The timing of each special time slot is as Figure 5 shown, where d_symbols: the number of downlink symbols, Guard: the number of idle symbols, u_symbols: the number of uplink symbols.

[0046] The base station side of the traditional communication system only supports one frame structure timing ratio; the base station side of the traditional communication system only supports communication with one type of frame structure terminal. If the traditional communication system needs to communicate with terminals with four different frame structure timings, four sets of communication systems are required. By adopting the above solution, this application proposes that it can support the configuration of 4 completely different frame structure timings, with each 5ms being a frame timing ratio, and the 20ms frame structure time window is composed of four different frame timings; it proposes a mechanism to support the simultaneous communication of terminals with four different frame structure timings; 3. It proposes that communicating with terminals with four different frame structures saves three sets of communication equipment. In summary, the configuration method of this solution can improve the adaptability of the product to various environments, enable one device to support the simultaneous communication of multiple terminals, improve the terminal access ability, which is equivalent to saving the construction costs of three base stations and greatly reducing the construction cost of the communication system.

[0047] AXIQ is a bus interface. The physical meaning and its composition of the bus interface AXIQ are as follows:

[0048] AXIQ module as implemented on the chip:

[0049] The following table describes the AXIQ module integration into the chip:

[0050] This chapter describes AXIQ_LS and AXIQ_HS. The chip supports one AXII / Q high-speed bridge (AXIQ_H) and two AXI I / Q

[0051] low-speed bridges (AXIQ_L0, L1).

[0052] AXIQ_LS Overview:

[0053] The AXI I / Q interface block (AXIQ_LS) provides a DMA-based, AXI-slave interface to auxiliary devices. The AXIQ_LS can receive

[0054] data (data transfer from the DCS devices to VSPA DMEM) and transmit data (data transfer from VSPA DMEM to the DCS devices).

[0055] The AXIQ_LS includes two receive channels and two transmit channels which can operate simultaneously. Each channel has a

[0056] Built-in independent FIFO. The AXIQ_LS provides FIFO buffering of real samples or complex I / Q samples, with buffer accesses

[0057] Optimized for the AMBA AXI bus protocol and DMA side bus control and status signals.

[0058] On the receive side, AXIQ_LS receives data samples from on-chip ADC modules, internally stores the samples in a FIFO, and

[0059] Triggers the VSPA DMA to read the samples from the FIFO via the AXI bus.

[0060] On the transmit side, the VSPA DMA writes on-chip data samples into the internal FIFOs through the AXI bus. The AXIQ_LS

[0061] Communicates the samples to DAC modules. The AXIQ_LS triggers the DMA to write the samples to the FIFO through the system

[0062] AXI bus.

[0063] The AXIQ_LS includes the following key features:

[0064] ·AXI3 bus interface with 512-bit data bus

[0065] ·Maximum 614.4 MHz AXI bus clock frequency

[0066] ·Side bus signaling to DMA

[0067] —Hardware DMA triggers are supported on each FIFO

[0068] —DMA reads(Rx Channels)and writes(Tx Channels)the FIFO in burst modethrough the AXI bus

[0069] ·AXIQ_LS has both receive and transmit functionality.

[0070] —In receive channels,data is written into the AXIQ_LS FIFO from ADCthrough the rx_data ports,and then data is read

[0071] from the FIFO through the AXI bus and stored in VSPA data memory.

[0072] —In transmit channels,data is written into the AXIQ_LS FIFO throughthe AXI bus from VSPA data memory,and then data

[0073] is read from the FIFO and sent to the DAC through the tx_data ports.

[0074] οFour FIFOs are implemented.Each FIFO has 32-entries of 512-bitwide.Each FIFO is connected to an external

[0075] DAC or ADC module.

[0076] —Two receive channels are connected to two ADC modules.

[0077] —Two transmit channels are connected to two DAC modules.

[0078] ·Two receive channels and two transmit channels. Each channel has a separate FIFO.

[0079] —Two Rx channels operate only in low speed mode, each is connected to 2x 12-bit input rx_data.

[0080] οEach channel can support several modes of packing operation.

[0081] —Two Tx channels operate only in low speed mode, each is connected to 2x 12-bit output tx_data.

[0082] οEach channel can support several modes of unpacking operation.

[0083] ·No internal AXIQ configuration registers. Controlled through VSPA's GPI and GPO signals

[0084] —64-bit AXIQ_configuration bus connected to two VSPA GPO registers

[0085] —96-bit AXIQ_status bus connected to two VSPA GPI registers

[0086] · Each channel is configured independently, and operates independently of other channels

[0087] · Configurable mode of operation (for example, complex mode, interleaved mode)

[0088] · Configurable subword swap

[0089] — Swaps I and Q in the low - speed

[0090] The method of the present invention is not limited to being executed in the chronological order described in the specification, and can also be executed in other chronological orders, in parallel, or independently. Therefore, the execution order of the method described in this specification does not limit the technical scope of the present invention.

[0091] Although the present invention has been disclosed above through the description of specific embodiments of the present invention, it should be understood that all the above embodiments and examples are exemplary, not restrictive. Those skilled in the art can design various modifications, improvements, or equivalents to the present invention within the spirit and scope of the appended claims. These modifications, improvements, or equivalents should also be considered to be included within the protection scope of the present invention.

Claims

1. A method for configuring multiple frame structures, characterized in that: including: Configure N kinds of frame structure timings. Among them, the parameters of each frame structure include the downlink frame time slot d_slot, the special symbol s, and the number of uplink time slots u_slot. The special symbol s includes the number of downlink symbols, the number of idle symbols, and the number of uplink symbols; Calculate the uplink and downlink times of each frame mode; Configure the uplink and downlink times of each frame mode into the corresponding registers; Open or close the bus interface AXIQ according to the calculated accurate uplink and downlink times; The decision feedback equalizer fills the IQ data of N*10 time slots according to the configured timing; Receive and transmit according to the configured multiple frame structure timings.

2. The method for configuring multiple frame structures according to claim 1, characterized in that: The multiple frame structure timings include a frame structure combination timing formed by arranging multiple frame structures in sequence.

3. A device for configuring multiple frame structures, characterized in that: including: A configuration unit for configuring N kinds of frame structure timings. Among them, the parameters of each frame structure include the downlink frame time slot d_slot, the special symbol s, and the number of uplink time slots u_slot. The special symbol s includes the number of downlink symbols, the number of idle symbols, and the number of uplink symbols; An uplink and downlink time calculation unit for calculating the uplink and downlink times of each frame mode; An uplink and downlink time configuration unit for configuring the uplink and downlink times of each frame mode into the corresponding registers; A bus interface AXIQ unit for opening / closing the bus interface AXIQ according to the calculated accurate uplink and downlink times; A decision feedback equalizer, and the decision feedback equalizer fills the IQ data of N*10 time slots according to the configured timing; A transceiver unit for receiving and transmitting according to the configured multiple frame structure timings.

4. The multi-frame structure configuration device according to claim 3, wherein: The multiple frame structure timings include a frame structure combination timing formed by arranging multiple frame structures in sequence.

5. The multi-frame structure configuration device according to claim 4, wherein: The parameters of each frame structure include the downlink frame time slot d_slot, the special symbol s, and the number of uplink time slots u_slot.

6. A base station applying the multiple frame structure configuration method according to claim 1 or 2 or applying the multiple frame structure configuration device according to claims 3-5.

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