Package including a substrate having via walls configured to be shielded

Abstract

A package includes a substrate having a routed region and a non-routed region along a periphery of the substrate. The non-routed region includes a plurality of vias configured as a shield. The package includes an integrated device coupled to the substrate and an encapsulation layer positioned on the substrate such that the encapsulation layer encapsulates the integrated device.

Description

[0001] Priority requirements

[0002] This patent application claims priority to application number 16 / 704,789, filed on December 5, 2019, entitled “PACKAGE COMPRISING A SUBSTRATEHAVING A VIA WALL CONFIGURED AS A SHIELD”, which is assigned to the assignee of this application and is hereby expressly incorporated herein by reference. Technical Field

[0003] Various features relate to packages that include integrated devices, and more specifically, to packages that include integrated devices and a substrate, the substrate including through-hole walls configured to be shielded. Background Technology

[0004] Figure 1 A package 100 is shown, comprising a substrate 102, an integrated device 104, and an encapsulation layer 108. The substrate 102 includes multiple dielectric layers 120, multiple interconnects 122, and multiple solder interconnects 124. Multiple solder interconnects 144 are coupled to the substrate 102 and the integrated device 104. The encapsulation layer 108 encapsulates the integrated device 104 and the multiple solder interconnects 144. Components within the package can be sensitive and susceptible to interference, affecting the performance of both the component and the package. There is a ongoing need for packages with better performance. Summary of the Invention

[0005] Various features relate to packages that include integrated devices, and more specifically, to packages that include integrated devices and a substrate, the substrate including through-hole walls configured to be shielded.

[0006] One example provides a package including a substrate with wiring and non-wiring regions along its periphery. The non-wiring regions include a plurality of vias configured to be shielded. The package includes an integrated device coupled to the substrate and an encapsulation layer located on the substrate such that the encapsulation layer encapsulates the integrated device.

[0007] Another example provides an apparatus including a substrate with wiring and non-wiring regions along its periphery. The non-wiring regions include components for via shielding. The apparatus includes an integrated device coupled to the substrate and encapsulation components located on the substrate, such that the encapsulation components encapsulate the integrated device.

[0008] Another example provides a method for manufacturing a package. The method provides a substrate. The substrate includes wiring regions and non-wiring regions along its periphery. The non-wiring regions include a plurality of vias configured to shield. The method couples an integrated device to the substrate. The method forms an encapsulation layer on the substrate such that the encapsulation layer encapsulates the integrated device. Attached Figure Description

[0009] Various features, properties and advantages will become apparent from the detailed description below, taken in conjunction with the accompanying drawings, in which the same reference numerals denote the same contents.

[0010] Figure 1 A side view of the package, including the integrated devices and the substrate, is shown.

[0011] Figure 2 A side view of a package including a substrate having through-hole walls configured to be shielded is shown.

[0012] Figure 3 A side view of another package including a substrate is shown, which has through-hole walls configured to be shielded.

[0013] Figure 4 A plan view of a substrate with via walls and fin structures configured to be shielded is shown.

[0014] Figure 5 A plan view of a substrate with via walls and fin structures configured to be shielded is shown.

[0015] Figure 6 An assembly diagram of a substrate with through-hole walls and fin structures configured to be shielded is shown.

[0016] Figure 7 A view of the through-hole walls and fin structure configured as shields is shown.

[0017] Figure 8 A plan view of the through-hole walls and fin structure configured as shields is shown.

[0018] Figure 9 A plan view of the through-hole walls and fin structure configured as shields is shown.

[0019] Figure 10 A view of the through-hole walls and fin structure configured as shields is shown.

[0020] Figure 11 (including) Figure 11A-11C This illustrates an exemplary sequence for manufacturing a substrate that includes through-hole walls and fin structures configured to be shielded.

[0021] Figure 12 An exemplary flowchart of a method for manufacturing a substrate including via walls and fin structures configured to be shielded is shown.

[0022] Figure 13 (including) Figures 13A-13B This illustrates an exemplary sequence for manufacturing a package including a substrate comprising through-hole walls and fin structures configured to be shielded.

[0023] Figure 14 An exemplary flowchart of a method for manufacturing a package including a substrate comprising through-hole walls and fin structures configured to be shielded is shown.

[0024] Figure 15 Various electronic devices are shown that can integrate the dies, integrated devices, integrated passive devices (IPDs), passive components, packages and / or device packages described herein. Detailed Implementation

[0025] In the following description, specific details are set forth to provide a thorough understanding of various aspects of this disclosure. However, those skilled in the art will understand that these aspects can be implemented without these specific details. For example, circuits may be shown as block diagrams to avoid obscuring these aspects with unnecessarily detailed information. In other instances, well-known circuits, structures, and techniques may not be shown in detail in order not to obscure aspects of this disclosure.

[0026] This disclosure describes a package including a substrate having (i) a wiring region and (ii) a non-wiring region along its periphery. The non-wiring region includes a plurality of vias configured for shielding (e.g., electromagnetic interference (EMI) shielding). The package includes an integrated device coupled to the substrate and an encapsulation layer located on the substrate such that the encapsulation layer encapsulates the integrated device. The plurality of vias are configured not to be electrically connected to the integrated device. The non-wiring region may also include fin structures coupled to the plurality of vias. The package may include a metal layer located on a side of the substrate such that the metal layer is coupled to the fin structures and / or the plurality of vias located in the non-wiring region of the substrate. The metal layer, fin structures, and / or the plurality of vias can be configured for shielding the package. This configuration utilizes previously unused space and / or areas of the package to provide more effective shielding for the package without increasing the overall size and / or footprint of the package.

[0027] An exemplary package includes a substrate having through-hole walls and fin structures configured to be shielded.

[0028] Figure 2A side view of a package 200 including a substrate having through-hole walls and fin structures configured as shielding (e.g., electromagnetic interference (EMI) shielding) for the package 200 is shown. The package 200 is coupled to a board 290 (e.g., a printed circuit board (PCB)) via multiple solder interconnects 250. The package 200 may include a metal layer (e.g., an outer metal layer) situated above the sides of the substrate and above the surface of the encapsulation layer. The metal layer may also be configured for shielding (e.g., EMI shielding) of the package 200.

[0029] like Figure 2 As shown, the package 200 includes a substrate 202, an integrated device 204, an encapsulation layer 208, and a metal layer 210. The substrate 202 includes at least one dielectric layer 220, a plurality of interconnects 222, a first solder resist layer 224, and a second solder resist layer 226.

[0030] Substrate 202 includes wiring regions 270 and non-wiring regions 275. The non-wiring regions 275 are positioned along the periphery of substrate 202. The non-wiring regions 275 of substrate 202 include a plurality of vias 280 configured for shielding (e.g., EMI shielding). The non-wiring regions 275 of substrate 202 also include fin structures 285 coupled to the plurality of vias 280. The wiring regions 270 of substrate 202 include a plurality of interconnects 222. The plurality of vias 280 are configured not to be electrically connected to integrated device 204. The plurality of vias 280 may be configured not to be electrically connected to the plurality of interconnects 222. The plurality of vias 280 may be configured as via walls. The plurality of vias 280 may be components for via shielding (e.g., via EMI shielding). The fin structures 285 may be configured for shielding. The fin structures 285 may be components for fin shielding (e.g., fin EMI shielding). As will be further described below, the fin structures 285 may be formed on one or more metal layers of substrate 202. At least below... Figure 6-10 The text further describes an example of the fin structure.

[0031] Substrate 202 may be a laminated substrate. Substrate 202 includes at least one dielectric layer 220 located in wiring region 270 and non-wiring region 275. Wiring region 270 of substrate 202 may include one or more continuous and / or adjacent regions of substrate 202 comprising a plurality of interconnects 222. The plurality of interconnects 222 are configured to be electrically coupled to integrated device 204. Non-wiring region 275 may include one or more continuous and / or adjacent regions located along the periphery of substrate 202, wherein the one or more continuous and / or adjacent regions do not have interconnects configured to be electrically coupled to integrated device 204. Non-wiring region 275 may laterally surround wiring region 270. Various examples of the design and / or configuration of the plurality of vias 280 and fin structures 285 located in non-wiring region 275 will be further described in detail below.

[0032] Integrated device 204 is coupled to substrate 202. Specifically, integrated device 204 can be coupled to substrate 202 via multiple solder interconnects 240. In some embodiments, pillars (e.g., copper pillars) may be used in conjunction with or in place of the multiple solder interconnects 240 to couple integrated device 204 to substrate 202. Multiple solder interconnects 240 may be coupled to multiple interconnects 222 of substrate 202. Integrated device 204 may include a die (e.g., a bare die). Integrated device 204 may include radio frequency (RF) devices, passive devices, filters, capacitors, inductors, antennas, transmitters, receivers, GaA-based integrated devices, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light-emitting diode (LED) integrated devices, silicon carbide (SiC)-based integrated devices, and / or combinations thereof.

[0033] Encapsulation layer 208 is located on substrate 202 such that encapsulation layer 208 encapsulates integrated device 204. Encapsulation layer 208 may be a component for encapsulation. Encapsulation layer 208 may include mold, resin, epoxy resin and / or polymer.

[0034] A metal layer 210 is located on the sides of the substrate 202 and on the surface of the encapsulation layer 208. The metal layer 210 may include a conductive material. The metal layer 210 may be formed on the sides of the substrate 202 and on the surface (e.g., the outer surface) of the encapsulation layer 208 by a sputtering process. The metal layer 210 may be coupled to at least one dielectric layer 220, a plurality of vias 280, and / or a fin structure 285. The metal layer 210, the plurality of vias 280, and / or the fin structure 285 may be configured for shielding the package 200 (e.g., EMI shielding). In some embodiments, the metal layer 210, the plurality of vias 280, and / or the fin structure 285 may be configured to be coupled to ground. In some embodiments, the metal layer 210, the plurality of vias 280, and / or the fin structure 285 may help provide at least -34 dB of isolation for the package 200. The package 200 may include an antenna within the package.

[0035] As described above, by utilizing previously unused space and / or areas of the package, package 200 (or any package with a substrate having through-hole walls and / or fin structures) provides an improved package that provides more effective shielding for package 200 without increasing the overall size and / or footprint of package 200.

[0036] Figure 3 Another package is shown, including a substrate having through-hole walls and fin structures configured to be shielded. Figure 2 The package 300 is similar to Figure 2 The package 200, and includes components similar to the package 200.

[0037] like Figure 3 As shown, the package 300 includes a substrate 302, an integrated device 204, an encapsulation layer 208, and a metal layer 210. The substrate 302 includes at least one dielectric layer 320, a plurality of interconnects 322, a first solder resist layer 224, and a second solder resist layer 226.

[0038] Substrate 302 includes a wiring region 270 and a non-wiring region 275. The non-wiring region 275 is positioned along the periphery of substrate 302. The non-wiring region 275 of substrate 302 includes a plurality of vias 380 configured for shielding (e.g., EMI shielding). The non-wiring region 275 of substrate 302 also includes fin structures 385 coupled to the plurality of vias 380. The wiring region 270 of substrate 302 includes a plurality of interconnects 322. The plurality of vias 380 are configured not to be electrically connected to integrated device 204. The plurality of vias 380 may be configured not to be electrically connected to the plurality of interconnects 322. The plurality of vias 380 may be via walls. The plurality of vias 380 may be components for via shielding (e.g., via EMI shielding). The plurality of vias 380 are shown as having diagonal walls, which differs from the walls of the plurality of vias 280 having substantially vertical walls. The fin structures 385 may be configured for shielding. As will be further described below, the fin structure 385 may be formed on one or more metal layers of the substrate 302.

[0039] The substrate 302 also includes at least one dielectric layer 320 located in the wiring region 270 and the non-wiring region 275. The wiring region 270 of the substrate 302 may include one or more continuous and / or adjacent regions of the substrate 302 comprising a plurality of interconnects 322. The plurality of interconnects 322 are configured to be electrically coupled to the integrated device 204. The non-wiring region 275 may include one or more continuous and / or adjacent regions located along the periphery of the substrate 302, wherein the one or more continuous and / or adjacent regions do not have interconnects configured to be electrically coupled to the integrated device 204.

[0040] Integrated device 204 is coupled to substrate 302. Specifically, integrated device 204 can be coupled to substrate 302 via a plurality of solder interconnects 240. In some embodiments, pillars (e.g., copper pillars) may be used in conjunction with or in place of the plurality of solder interconnects 240 to couple integrated device 204 to substrate 302. The plurality of solder interconnects 240 may be coupled to a plurality of interconnects 322 of substrate 302. Encapsulation layer 208 is located on substrate 302 such that encapsulation layer 208 encapsulates integrated device 204.

[0041] A metal layer 210 is located on the side of the substrate 302 and on the surface of the encapsulation layer 208. The metal layer 210 may include a conductive material. The metal layer 210 may be formed on the side of the substrate 302 and on the surface of the encapsulation layer 208 by a sputtering process. The metal layer 210 may be coupled to at least one dielectric layer 320, a plurality of vias 380, and / or a fin structure 285. The metal layer 210, the plurality of vias 380, and / or the fin structure 385 may be configured for shielding the package 300 (e.g., EMI shielding). In some embodiments, the metal layer 210, the plurality of vias 380, and / or the fin structure 385 may be configured to be coupled to ground. The package 300 may include an antenna within the package.

[0042] Different implementations may utilize different substrates with through-hole walls and / or fin structures. The substrate may include laminated substrates, coreless substrates, and substrates including a core layer. Different implementations may have different numbers of integrated devices. Note that the figures in this disclosure are not necessarily drawn to scale.

[0043] Figure 2 and Figure 3 Packages 200 and 300 are shown configured to be electrically coupled to board 290 via a plurality of solder interconnects 250. In some embodiments, packages 200 and 300 may include one or more antennas that allow packages 200 and 300 to send (e.g., radiate signals) to and receive signals from board 290 and / or other devices and components. Therefore, in some embodiments, some or all signals (e.g., I / O signals) between packages (e.g., 200, 300) and board 290 (or other devices and packages) may bypass the solder interconnects 250. Therefore, in some embodiments, the solder interconnects 250 may be optional.

[0044] Figure 4 A plan view of substrate 202 is shown. Substrate 202 includes wiring regions 270 and non-wiring regions 275. Non-wiring regions 275 are positioned along the periphery of substrate 202. Non-wiring regions 275 of substrate 202 include a plurality of vias 280 configured for shielding (e.g., EMI shielding). Non-wiring regions 275 of substrate 202 also include fin structures 285 coupled to the plurality of vias 280. Fin structures 285 include a plurality of spaced-apart fins 485 (e.g., repeating fins). The plurality of fins 485 may have different shapes and / or different sizes. The plurality of fins 485 may be located on one or more metal layers of substrate 202. The plurality of fins 485 may include a conductive material (e.g., metal, copper). Note that some sides of substrate 202 may not include fins.

[0045] As described above, the wiring region 270 of substrate 202 may include one or more continuous and / or adjacent regions, which include interconnects configured to be electrically coupled to integrated devices. The wiring region 270 may include an inner region, a central region, and / or an intermediate region of substrate 202. As described above, the non-wiring region 275 of the substrate (e.g., 202, 302) may be defined as one or more regions along the periphery of the substrate that do not have interconnects configured to be electrically coupled to integrated devices. For example, the non-wiring region 275 may be one or more regions without interconnects configured to be electrical paths for power and / or signals (e.g., I / O signals). In some embodiments, the non-wiring region 275 of the substrate (e.g., 202, 302) may be defined as a region 250 micrometers (μm) or less from one or more outer edges of substrate 202. For example, the non-wiring region 275 of the substrate may be defined as including (i) a first region 250 micrometers (μm) or less from a first outer edge of the substrate, (ii) a second region 250 micrometers (μm) or less from a second outer edge of the substrate, (iii) a third region 250 micrometers (μm) or less from a third outer edge of the substrate, and / or (iv) a fourth region 250 micrometers (μm) or less from a fourth outer edge of the substrate. However, different embodiments may define the non-wiring region 275 of the substrate differently. The size and / or shape of the non-wiring region 275 may vary with different embodiments. In some embodiments, the non-wiring region 275 may be defined during package fabrication as one or more regions designated as not having wiring (e.g., wiring interconnects) during IC design (e.g., during IC wiring design and / or IC layout design). Therefore, during IC wiring design and / or IC layout design, wiring coupled to integrated devices is not allowed to be specified in the regions designated as non-wiring regions. The non-wiring region 275 may be located on one or more metal layers of the substrate. Non-routing region 275 may include interconnects not configured to be electrically coupled to integrated devices and / or passive devices. In one aspect, all interconnects (e.g., pads, traces, vias) in non-routing region 275 are not connected to power, input / output signals, and integrated devices. The meaning of non-routing region for substrate may combine some or all of the definitions provided in this disclosure. Routing region (e.g., 270) may be defined as one or more regions (e.g., internal regions) that allow wiring (e.g., interconnects) coupled to integrated devices. Note that a portion of a wiring region may not have interconnects, even if interconnects are specified and / or formed herein.

[0046] Figure 5A plan view of substrate 502 is shown. Substrate 502 includes wiring regions 270 and non-wiring regions 275. Non-wiring regions 275 are positioned along the periphery of substrate 502. Non-wiring regions 275 of substrate 502 include a plurality of vias 280. The plurality of vias 280 may have different shapes and / or sizes. Non-wiring regions 275 of substrate 502 also include fin structures 285 coupled to the plurality of vias 280. Fin structures 285 include a plurality of spaced-apart fins 485.

[0047] Figure 6 An assembly diagram of substrate 602 is shown. Substrate 602 includes a first metal layer (M1) 610, a second metal layer (M2) 620, and a third metal layer (M3) 630. Substrate 602 includes a first wiring region 670a on the first metal layer 610, a second wiring region 670b on the second metal layer 620, and a third wiring region 670c on the third metal layer 630. Substrate 602 also includes a first non-wiring region 675a ​​on the first metal layer 610, a second non-wiring region 675b on the second metal layer 620, and a third non-wiring region 675c on the third metal layer 630. The first non-wiring region 675a ​​on the first metal layer 610, the second non-wiring region 675b on the second metal layer 620, and the third non-wiring region 675c on the third metal layer 630 are located at the periphery of substrate 602.

[0048] The first non-wiring region 675a ​​includes a first fin structure 685a, the second non-wiring region 675b includes a second fin structure 685b, and the third non-wiring region 675c includes a third fin structure 685c. The first fin structure 685a includes multiple repeating first fins, the second fin structure 685b includes multiple repeating second fins, and the third fin structure 685c includes multiple repeating third fins. The size, shape, and / or position of the fins may be the same for all fins, or may be different for at least some fins.

[0049] Multiple first through holes 680a are coupled to a first fin structure 685a and a second fin structure 685b. Multiple second through holes 680b are coupled to a second fin structure 685b and a third fin structure 685c.

[0050] Figure 7 It shows Figure 6 A close-up view of the fin structure of substrate 602 shown. Figure 7As shown, vias from multiple first vias 680a are coupled to a first fin structure 685a and a second fin structure 685b. Vias from multiple second vias 680b are coupled to a second fin structure 685b and a third fin structure 685c. The first fin structure 685a, the second fin structure 685b, the third fin structure 685c, the multiple first vias 680a, and the multiple second vias 680b are located in a non-wiring region of the substrate 602, wherein the non-wiring region is positioned along the periphery of the substrate 602.

[0051] Figure 8 and Figure 9 This illustrates how different fin structures on different metal layers of a substrate overlap vertically. Figure 8 A first fin structure 885a on a first metal layer of the substrate and a second fin structure 885b on a second metal layer of the substrate are shown. The first fin structure 885a and the second fin structure 885b can be located in a non-wiring region of the substrate.

[0052] The first fin structure 885a includes a plurality of first repeating fins. For example, the first fin structure 885a includes first fins 886a and first fins 887a. The second fin structure 885b includes a plurality of second repeating fins. For example, the second fin structure 885b includes second fins 886b and second fins 887b. The first fin structure 885a and the second fin structure 885b are formed such that the fins on different metal layers are offset from each other.

[0053] like Figure 8 As shown, the first fin 886a and the second fin 886b partially overlap vertically, and the first fin 887a and the second fin 887b partially overlap vertically. Through-hole 880a is coupled to the first fin 886a and the second fin 886b. Through-hole 882a is coupled to the first fin 887a and the second fin 886b. Through-hole 884a is coupled to the first fin 887a and the second fin 887b. Through-holes 880b and 882b are coupled to the second fin 886b. Through-hole 884b is coupled to the second through-hole 887b.

[0054] In some implementations... Figure 8 The fins are approximately 245 micrometers or less in length and approximately 200 micrometers or less in width. Figure 8 The spacing between the fins can be approximately 100 micrometers or less. Figure 8 The spacing between the through holes can be approximately 300 micrometers.

[0055] Figure 9 A first fin structure 985a on a first metal layer of the substrate and a second fin structure 985b on a second metal layer of the substrate are shown. The first fin structure 985a and the second fin structure 985b can be located in a non-wiring region of the substrate.

[0056] The first fin structure 985a includes a plurality of first repeating fins. For example, the first fin structure 985a includes first fins 986a and first fins 987a. The second fin structure 985b includes a plurality of second repeating fins. For example, the second fin structure 985b includes second fins 986b and second fins 987b. The first fin structure 985a and the second fin structure 985b are formed such that the fins on different metal layers are offset from each other.

[0057] like Figure 9 As shown, the first fin 986a and the second fin 986b partially overlap vertically, and the first fin 987a and the second fin 987b partially overlap vertically. Through-hole 980a is coupled to the first fin 986a and the second fin 986b. Through-hole 982a is coupled to the first fin 987a and the second fin 987b. Through-hole 980b is coupled to the second fin 986b. Through-hole 982b is coupled to the second through-hole 987b.

[0058] In some implementations... Figure 9 The fins are approximately 245 micrometers or less in length and approximately 300 micrometers or less in width. Figure 9 The spacing between the fins can be approximately 100 micrometers or less. Figure 9 The spacing between the through holes can be approximately 200 micrometers.

[0059] Figure 10 A view of a non-wiring region 1000 of a substrate (e.g., 202, 302) is shown. This wiring region 1000 includes a plurality of vias 1080 and fin structures 1085 configured for shielding (e.g., EMI shielding). The plurality of vias 1080 and fin structures 1085 can be implemented in any substrate described in this disclosure. The non-wiring region 1000 is positioned along the periphery of the substrate (e.g., 202, 302). The non-wiring region 1000 includes a first metal layer (M1) 1010, a second metal layer (M2) 1020, a third metal layer (M3) 1030, a fourth metal layer (M4) 1040, and a fifth metal layer (M5) 1050. Different embodiments may have different numbers of metal layers in the non-wiring region 1000 of the substrate.

[0060] like Figure 10 As shown, the plurality of through holes 1080 include a plurality of first through holes 1080a, a plurality of second through holes 1080b, a plurality of third through holes 1080c, and a plurality of fourth through holes 1080d. The fin structure 285 includes a plurality of first fins 1085a located on the first metal layer 1010, a plurality of second fins 1085b located on the second metal layer 1020, a plurality of third fins 1085c located on the third metal layer 1030, a plurality of fourth fins 1085d located on the first metal layer 1040, and a plurality of fifth fins 1085e located on the fifth metal layer 1050.

[0061] Multiple first through-holes 1080a are coupled to multiple first fins 1085a and multiple second fins 1085b. Multiple second through-holes 1080b are coupled to multiple second fins 1085b and multiple third fins 1085c. Multiple third through-holes 1080c are coupled to multiple third fins 1085c and multiple fourth fins 1085d. Multiple fourth through-holes 1080d are coupled to multiple fourth fins 1085d and multiple fifth fins 1085e.

[0062] Different implementations may arrange the through-holes and / or fins differently. In some implementations, the through-holes may be stacked and / or staggered. Figure 7 and Figure 10 In this configuration, vias are approximately stacked on top of each other. However, in some embodiments, the vias may be staggered and / or offset. The shape, size, and / or number of fins can vary with different embodiments. For example, in some embodiments, a single fin may occupy the entire metal layer of a non-wiring area of ​​the substrate, rather than multiple fins. In some embodiments, different metal layers may have different fin designs, different configurations, and / or different numbers of fins. The fin structure can be a structure defined on one or more metal layers. Thus, a fin structure can be defined by fins on one metal layer or fins on two or more metal layers. A fin structure can be defined by several fin structures.

[0063] An exemplary substrate having via walls and fin structures configured as shields

[0064] In some embodiments, fabricating the substrate includes several processes. Figure 11 (including...) Figure 11A-11C This illustrates an exemplary sequence for providing or manufacturing a substrate including through-hole walls and fin structures. In some embodiments, Figure 11A-11C The order can be used to provide or manufacture with Figure 3 The substrate 302 has through-hole walls and fin structures. However, the process of FIG11 can be used to manufacture any substrate described in this disclosure.

[0065] It should be noted that Figure 11A-11C The sequence of processes can be combined with one or more stages to simplify and / or clarify the sequence used to provide or manufacture the substrate. In some embodiments, the sequence of processes can be changed or modified. In some embodiments, one or more processes can be substituted or replaced without departing from the spirit of this disclosure.

[0066] like Figure 11A As shown, stage 1 illustrates the state after a carrier 1100 is provided and a metal layer is formed on the carrier 1100. The metal layer can be patterned to form interconnects 1102. Electroplating and etching processes can be used to form the metal layer and the interconnects.

[0067] Phase 2 illustrates the state after the dielectric layer 1120 is formed over the carrier 1100 and interconnect 1102. The dielectric layer 1120 may comprise polyimide. However, different embodiments may use different dielectric layer materials. The dielectric layer may be formed using a deposition process or a coating process.

[0068] Stage 3 illustrates the state after multiple cavities 1110 are formed in the dielectric layer 1120. The multiple cavities 1110 can be formed using an etching process (e.g., photolithography) or a laser process.

[0069] Stage 4 illustrates the state after interconnects 1112 are formed in and on the dielectric layer 1120. For example, vias, pads, and / or traces can be formed. Electroplating processes can be used to form the interconnects.

[0070] Stage 5 illustrates the state after another dielectric layer 1122 is formed on top of dielectric layer 1120. Dielectric layer 1122 can be made of the same material as dielectric layer 1120. However, different implementations may use different dielectric layer materials. Dielectric layers may be formed using deposition or coating processes.

[0071] like Figure 11B As shown, stage 6 illustrates the state after multiple cavities 1130 are formed in the dielectric layer 1122. The cavities 1130 can be formed using an etching process or a laser process.

[0072] Stage 7 illustrates the state after interconnects 1114 are formed in and on the dielectric layer 1122. For example, vias, pads, and / or traces can be formed. Electroplating processes can be used to form the interconnects.

[0073] Stage 8 illustrates the state after another dielectric layer 1124 is formed on top of dielectric layer 1122. Dielectric layer 1124 can be made of the same material as dielectric layer 1120. However, different embodiments may use different dielectric layer materials. Dielectric layers may be formed using deposition or coating processes.

[0074] Stage 9 shows the state after multiple cavities 1140 are formed in the dielectric layer 1124. The cavities 1140 can be formed using an etching process or a laser process.

[0075] like Figure 11C As shown, stage 10 illustrates the state after interconnects 1116 have been formed in and on the dielectric layer 1124. For example, vias, pads, and / or traces may be formed. Electroplating processes may be used to form the interconnects.

[0076] Some of the interconnects 1102, 1112, 1114 and / or 1116 may define a plurality of vias 280 and / or fin structures 285 located in a non-wiring region along the periphery of the substrate. Other interconnects from interconnects 1102, 1112, 1114 and / or 1116 may define a plurality of interconnects 322 in a wiring region of the substrate.

[0077] Phase 11 illustrates the state after the carrier 1100 has been separated from the dielectric layer 1120 (e.g., removed, polished), leaving the substrate 302 (e.g., a coreless substrate). In some embodiments, the coreless substrate is an embedded trace substrate (ETS). Phase 11 illustrates the substrate 302 having at least one dielectric layer 320, which may represent dielectric layers 1120, 1122, and 1124. In some embodiments, dielectric layers 1120, 1122, and 1124 may be considered as a single dielectric layer (e.g., a single dielectric layer). The substrate 302 includes a plurality of vias 280 and fin structures 285, each via and fin structure being formed by interconnects from interconnects (e.g., 1102, 1112, 1114, 1116). The plurality of vias 280 and / or fin structures 285 may be configured for shielding (e.g., EMI shielding).

[0078] Phase 12 shows the state after the first solder resist layer 224 and the second solder resist layer 226 are formed on the substrate 302.

[0079] Different implementations may use different processes to form the metal layer. In some implementations, chemical vapor deposition (CVD) and / or physical vapor deposition (PVD) processes are used to form the metal layer. For example, sputtering, spraying, and / or electroplating processes may be used to form the metal layer.

[0080] An exemplary flowchart of a method for manufacturing a substrate having through-hole walls and fin structures configured to be shielded.

[0081] In some implementations, the fabrication of the substrate includes several processes. Figure 12 An exemplary flowchart of a method 1200 for providing or manufacturing a substrate having through-hole walls and / or fin structures is shown. In some embodiments, Figure 12 Method 1200 can be used to provide or manufacture Figure 3 The substrate. For example. Figure 12 The method can be used to manufacture substrate 302. However, method 1300 can be used to manufacture any substrate including through-hole walls and / or fin structures.

[0082] It should be noted that Figure 12The sequence of processes can be combined to simplify and / or clarify the methods for providing or manufacturing substrates with through-hole walls and / or fin structures. In some embodiments, the sequence of processes can be changed or modified.

[0083] This method provides a carrier 1100 (at 1205). Different implementations may use different carrier materials. The carrier may include a substrate, glass, quartz, and / or a carrier tape. Figure 11A Phase 1 shows the state after the carrier is provided.

[0084] This method involves forming a metal layer (at 1210) on a carrier 1100. The metal layer can be patterned to form interconnects. An electroplating process can be used to form the metal layer and the interconnects. Figure 11A Stage 1 illustrates the state after the formation of the metal layer and interconnect 1102. The metal layer may include fin structures formed and positioned along a region that is, or will become, the periphery of the substrate. This region may be a non-wiring area of ​​the substrate.

[0085] The method involves forming a dielectric layer 1120 (at 1215) over a carrier 1100 and an interconnect 1102. The dielectric layer 1120 may comprise polyimide. A deposition process or a coating process can be used to form the dielectric layer. Forming the dielectric layer may also include forming a plurality of cavities (e.g., 1110) within the dielectric layer 1120. An etching process (e.g., photolithography) or a laser process can be used to form the plurality of cavities. Figure 11A Stages 2-3 show the formation of the dielectric layer and cavities within the dielectric layer.

[0086] This method forms interconnects (at 1220) in and on the dielectric layer. For example, interconnect 1112 can be formed in and on the dielectric layer 1120. Electroplating processes can be used to form the interconnects. Forming the interconnects may include providing a patterned metal layer on and / or in the dielectric layer. Forming the interconnects may include forming a plurality of vias 280 and / or fin structures 285 along a region that is or will become the periphery of a substrate. This region may be a non-wiring area of ​​the substrate. Figure 11A Phase 4 shows an example of forming interconnects in and on top of the dielectric layer.

[0087] The method involves forming a dielectric layer 1122 (at 1225) over a dielectric layer 1120 and an interconnect. The dielectric layer 1122 may comprise polyimide. A deposition process or a coating process can be used to form the dielectric layer. Forming the dielectric layer may also include forming a plurality of cavities (e.g., 1130) within the dielectric layer 1122. An etching process or a laser process can be used to form the plurality of cavities. Figure 11A-11B Stages 5-6 show the formation of the dielectric layer and cavities within the dielectric layer.

[0088] This method forms interconnects (at 1230) in and / or on the dielectric layer. For example, interconnect 1114 can be formed. Electroplating processes can be used to form the interconnects. Forming the interconnects may include providing a patterned metal layer on and in the dielectric layer. Forming the interconnects may include forming a plurality of vias 280 and / or fin structures 285 along a region that is or will become the periphery of a substrate. This region may be a non-wiring area of ​​the substrate. Figure 11B Phase 7 shows an example of forming interconnects in and on top of the dielectric layer.

[0089] The method may form additional dielectric layers and additional interconnects, as described in 1225 and 1230. At least some of the interconnects formed in the substrate may define a plurality of vias 280 and / or fin structures 285 configured for shielding (e.g., EMI shielding). Figure 11B-11C Stages 8-10 show examples of forming interconnects in and on the dielectric layer, wherein multiple vias 280 and / or fin structures 285 may be formed along the periphery of the substrate.

[0090] Once all dielectric layers and additional interconnects are formed, the method can separate the carrier (e.g., 1100) from the dielectric layer 1120 (e.g., remove, grind), leaving a substrate with via walls and / or fin structures. In some embodiments, the method can form a solder resist layer (e.g., 224, 226) on the substrate.

[0091] Different implementations may use different processes to form the metal layer. In some implementations, chemical vapor deposition (CVD) and / or physical vapor deposition (PVD) processes are used to form the metal layer. For example, sputtering, spraying, and / or electroplating processes may be used to form the metal layer.

[0092] An exemplary sequence for manufacturing a package including a substrate having through-hole walls and fin structures configured to be shielded.

[0093] Figure 13 (including) Figures 13A-13B This illustrates an exemplary sequence for providing or manufacturing a package including a substrate comprising through-hole walls and / or fin structures. The through-hole walls and / or fin structures can be configured for shielding (e.g., EMI shielding). In some embodiments, Figures 13A-13B The order can be used to provide or manufacture including Figure 3 The substrate 302 is a package 300 or any package described in this disclosure.

[0094] It should be noted that Figures 13A-13BThe sequence of processes can be combined in one or more steps to simplify and / or clarify the sequence for providing or manufacturing a package including a substrate comprising via walls and / or fin structures. In some embodiments, the sequence of processes can be changed or modified. In some embodiments, one or more processes can be substituted or replaced without departing from the spirit of this disclosure. Figures 13A-13B The sequence can be used to manufacture one package or several packages (as part of a wafer) at a time.

[0095] like Figure 13A As shown, stage 1 illustrates the state after substrate 302 is provided. Substrate 302 can be supplied or manufactured by a supplier. The substrate may include via walls and / or fin structures. Figure 11A-11C The process shown is similar to that used to fabricate substrate 302. However, different embodiments may use different processes to fabricate substrate 302. Examples of processes that may be used to fabricate substrate 302 include semi-additive process (SAP) and modified semi-additive process (mSAP). Substrate 302 includes at least one dielectric layer 320, multiple interconnects 322, multiple vias 280, and fin structures 285.

[0096] Phase 2 illustrates the state after the integrated device 204 is coupled to the substrate 302. The integrated device 204 is coupled to the substrate 302 via a plurality of solder interconnects 240. The plurality of solder interconnects 240 can be coupled to interconnects of a plurality of interconnects 322 from the substrate 202. The integrated device 204 can be coupled to the substrate 302 such that the front side (e.g., the active side) of the integrated device 204 faces the substrate 302.

[0097] Stage 3 illustrates the state after an encapsulation layer 208 has been disposed (e.g., formed) on substrate 302, such that the encapsulation layer 208 encapsulates integrated device 204. The encapsulation layer 208 laterally surrounds integrated device 204. The process of forming and / or disposing of the encapsulation layer 208 may include using compression and transfer molding processes, sheet molding processes, or liquid molding processes. The encapsulation layer 208 may include a mold, resin, epoxy resin, and / or polymer.

[0098] Stage 3 may show the diced state, where the wafer, comprising several substrates 302, integrated devices 204, and encapsulation layer 208, is cut (e.g., sliced) into individual packages. Dividing can be performed using mechanical processes (e.g., sawing).

[0099] like Figure 13BAs shown, Stage 4 illustrates the state after the metal layer 210 has been formed on the sides of the substrate 302 and the surface of the encapsulation layer 208. The metal layer 210 can be formed using a sputtering process. The metal layer 210 can be an external metal layer and / or an external metal wall. The metal layer 210 may include a conductive material. The metal layer 210 can be formed such that it is coupled to a plurality of vias 280 and / or fin structures 285. The metal layer 210, the plurality of vias 280, and / or fin structures 285 can be configured for shielding (e.g., EMI shielding). Stage 4 may illustrate the package 300.

[0100] Phase 5 illustrates the state after multiple solder interconnects 250 are coupled to the substrate 302. The multiple solder interconnects 250 can be coupled to multiple interconnects 322.

[0101] The packages described in this disclosure may be manufactured one at a time (e.g., 200, 300), or may be manufactured together as part of one or more wafers and then split into individual packages.

[0102] An exemplary flowchart of a method for manufacturing a package including a substrate having through-hole walls and fin structures configured to be shielded.

[0103] In some embodiments, a package is fabricated including a substrate that includes via walls and / or fin structures. The via walls and / or fin structures can be configured for shielding (e.g., EMI shielding) and involve several processes. Figure 14 An exemplary flowchart of a method 1400 for providing or manufacturing a package including a substrate, the substrate including via walls and / or fin structures, is shown. The via walls and / or fin structures can be configured for shielding (e.g., EMI shielding). In some embodiments, Figure 14 Method 1400 can be used to provide or manufacture the invention described in this disclosure. Figure 3 Package 300. However, method 1400 can be used to provide or manufacture any package described in this disclosure.

[0104] It should be noted that Figure 14 The sequence of processes can be combined to simplify and / or clarify the methods for providing or manufacturing a package including a substrate comprising via walls and / or fin structures. The via walls and / or fin structures can be configured for shielding (e.g., EMI shielding). In some embodiments, the sequence of processes can be changed or modified.

[0105] The method (at 1405) provides a substrate (e.g., 302). Substrate 302 may be supplied or manufactured by a vendor. The substrate includes wiring and non-wiring regions along its periphery, wherein the non-wiring regions include a plurality of vias configured for shielding. The substrate may include via walls (e.g., a plurality of vias 280) and / or fin structures (e.g., 285). The via walls and / or fin structures may be configured for shielding (e.g., EMI shielding). Different embodiments may provide different substrates. Figure 11A-11C The process shown is similar to that used to fabricate substrate 302. However, different embodiments may use different processes to fabricate substrate 302. Substrate 302 includes at least one dielectric layer 320 and a plurality of interconnects 322. Figure 13A Phase 1 shows and describes an example of a substrate with via walls and fin structures provided in the non-wiring area of ​​the substrate.

[0106] This method couples an integrated device (e.g., 204) to a substrate (e.g., 302) at 1410. The integrated device 204 can be coupled to the substrate 302 via a plurality of solder interconnects 240. The plurality of solder interconnects 240 can be coupled to interconnects of a plurality of interconnects 322 from the substrate 302. The integrated device 204 can be coupled to the substrate 302 such that the front side (e.g., the active side) of the integrated device 204 faces the substrate 302. Figure 13B Phase 2 shows and describes an example of an integrated device coupled to a substrate.

[0107] The method provides an encapsulation layer (e.g., 208) on a substrate (e.g., 302) such that the encapsulation layer 208 encapsulates the integrated device 204. The encapsulation layer 208 may laterally surround the integrated device 204. Figure 13A Phase 3 shows and describes an example of an encapsulation layer located on a substrate and encapsulating an integrated device.

[0108] This method forms (at 1420) a metal layer (e.g., 210) on the sides of a substrate (e.g., 302) and the surface of an encapsulation layer (e.g., 208). The metal layer 210 can be formed using a sputtering process. The metal layer 210 can be an external metal layer. The metal layer 210 can include a conductive material. The metal layer 210 can be formed such that it is coupled to a plurality of vias 280 and / or fin structures 285. The metal layer 210, the plurality of vias 280, and / or fin structures 285 can be configured for shielding (e.g., EMI shielding). Figure 13B Stage 4 can be shown as the state after a metal layer is formed on the sides of the substrate and on the surface of the encapsulation layer.

[0109] This method couples (e.g., 250) solder interconnects (at 1425) to a substrate 302. The solder interconnects 250 may be coupled to a plurality of interconnects 322. Figure 13B Phase 5 shows an example of solder interconnects coupled to the substrate.

[0110] Exemplary electronic devices

[0111] Figure 15 Various electronic devices that can be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, stacked packages (PoP), system-in-packages (SiP), or systems-on-chips (SoCs) are shown. For example, mobile phone device 1502, laptop computer device 1504, fixed-location terminal device 1506, wearable device 1508, or motor vehicle 1510 may include the device 1500 described herein. Device 1500 can be any device and / or integrated circuit (IC) package described herein, for example. Figure 15 The devices 1502, 1504, 1506, and 1508 shown, as well as vehicle 1510, are merely exemplary. Other electronic devices may also feature device 1500, including, but not limited to, a group of devices (e.g., electronic devices) including mobile devices, handheld personal communication system (PCS) units, portable data units (e.g., personal digital assistants), devices supporting Global Positioning System (GPS), navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (e.g., instrument reading devices), communication devices, smartphones, tablets, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0112] Figure 2-10 One or more components, processes, features, and / or functions shown in 11A-11C, 12, 13A-13B, and / or 14-15 may be rearranged and / or combined into a single component, process, feature, or function, or embodied in several components, processes, or functions. Additional elements, components, processes, and / or functions may be added without departing from this disclosure. It should also be noted that... Figure 2-10 11A-11C, 12, 13A-13B and / or 14-15 and their corresponding descriptions in this disclosure are not limited to dies and / or ICs. In some embodiments, Figure 2-1011A-11C, 12, 13A-13B and / or 14-15 and their corresponding descriptions can be used to manufacture, create, provide and / or produce devices and / or integrated devices. In some embodiments, the device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a stacked package (PoP) device, a thermal device and / or an interposer.

[0113] It should be noted that the accompanying drawings in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some cases, the drawings may not be drawn to scale. In some cases, not all parts and / or components may be shown for clarity. In some cases, the location, size, and / or shape of various parts and / or components in the drawings may be exemplary. In some embodiments, the various parts and / or components in the drawings may be optional.

[0114] The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as being more preferred or advantageous than other aspects of this disclosure. Similarly, the term “aspect” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. The term “coupled” as used herein refers to direct or indirect coupling between two objects. For example, if object A is in physical contact with object B, and object B is in contact with object C, objects A and C can still be considered coupled to each other, even if they are not in direct physical contact. The term “electrically coupled” can mean that two objects are directly or indirectly coupled together such that current (e.g., signal, power, ground) can flow between the two objects. Electrically coupled objects may or may not have current flowing between them. The term “encapsulation” means that an object may partially or completely encapsulate another object. It should also be noted that the term “above” as used in this application in the context of one component being above another component can be used to mean that one component is on and / or in another component (e.g., on the surface of a component or embedded in a component). Therefore, for example, "first component on second component" can mean (1) the first component is on the second component but does not directly contact the second component, (2) the first component is on the second component (e.g., on its surface), and / or (3) the first component is within the second component (e.g., embedded therein). The terms "approximately 'value X'" or "approximately value X" as used in this disclosure mean within 10% of 'value X'. For example, a value of approximately 1 or approximately 1 represents a value in the range of 0.9–1.1.

[0115] In some embodiments, an interconnect is an element or component of a device or package that allows or facilitates an electrical connection between two points, elements, and / or components. In some embodiments, an interconnect may include traces, vias, pads, pillars, redistributed metal layers, and / or under-bump metallization (UBM) layers. An interconnect may include one or more metal components (e.g., a seed layer + metal layer). In some embodiments, an interconnect is a conductive material that can be configured to provide an electrical path for a signal (e.g., a data signal, ground, or power). An interconnect may be part of a circuit. An interconnect may include more than one element or component. An interconnect may be defined by one or more interconnects. Different embodiments may use similar or different processes to form interconnects. In some embodiments, chemical vapor deposition (CVD) processes and / or physical vapor deposition (PVD) processes are used to form interconnects. For example, sputtering, spraying, and / or electroplating processes may be used to form interconnects.

[0116] It should also be noted that the various disclosures contained herein may be described as processes represented by flowcharts, work diagrams, structural diagrams, or block diagrams. Although flowcharts may describe operations as sequential processes, many operations may be performed in parallel or simultaneously. Furthermore, the order of operations may be rearranged. A process terminates when the operations of a process are completed.

[0117] Various features of this disclosure described herein may be implemented in different systems without departing from this disclosure. It should be noted that the foregoing aspects of this disclosure are merely illustrative and should not be construed as limiting the scope of this disclosure. The description of aspects of this disclosure is intended to be illustrative, not to limit the scope of the claims. Thus, this teaching can be readily applied to other types of devices, and many substitutions, modifications, and variations will be apparent to those skilled in the art.

Claims

1. A package comprising: A substrate, the substrate including a wiring region and a non-wiring region along the periphery of the substrate, wherein the non-wiring region includes a plurality of vias configured to be shielded, the substrate further comprising: A first metal layer, the first metal layer including a first fin structure in the non-wiring region; and The second metal layer includes a second fin structure in the non-wiring region. The plurality of through-holes are coupled to the first fin structure and the second fin structure; A metal layer located above the side of the substrate, such that the metal layer is coupled to the first fin structure and the second fin structure; An integrated device coupled to the substrate; and An encapsulation layer is located on the substrate such that the encapsulation layer encapsulates the integrated device.

2. The package of claim 1, wherein the plurality of through-holes are configured not to be electrically connected to the integrated device.

3. The packaging component according to claim 1, The wiring region of the substrate includes a plurality of interconnects configured to be electrically coupled to the integrated device, and The non-wiring region along the periphery of the substrate is a region of the substrate that does not have interconnects electrically coupled to the integrated device.

4. The package of claim 1, wherein the substrate further comprises a third metal layer, the third metal layer comprising a third fin structure in the non-wiring region, wherein the plurality of vias are coupled to the third fin structure.

5. The packaging component according to claim 1, The first fin structure includes a plurality of repeating first fins in the non-wiring area. The second fin structure includes a plurality of repeating second fins in the non-wiring area, and The plurality of repeated second fins are offset from the plurality of repeated first fins.

6. The package according to claim 5, wherein the metal layer is further located on the surface of the encapsulation layer.

7. The package of claim 1, wherein the package is incorporated into a device selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, and devices in motor vehicles.

8. An apparatus comprising: A substrate, the substrate including a wiring region and a non-wiring region along the periphery of the substrate, wherein the non-wiring region includes components for via shielding; The substrate further comprises: A first metal layer, the first metal layer including a first fin structure in the non-wiring region; and The second metal layer includes a second fin structure in the non-wiring region. Multiple through-holes are coupled to the first fin structure and the second fin structure; A metal layer located above the side of the substrate, such that the metal layer is coupled to the first fin structure and the second fin structure; An integrated device coupled to the substrate; and Encapsulation components, located on the substrate, such that the encapsulation components encapsulate the integrated device.

9. The apparatus of claim 8, wherein the component for via shielding is configured not to be electrically connected to the integrated device.

10. The apparatus according to claim 8, The wiring region of the substrate includes a plurality of interconnects configured to be electrically coupled to the integrated device, and The non-wiring region along the periphery of the substrate is a region of the substrate that does not have interconnects electrically coupled to the integrated device.

11. The apparatus of claim 10, wherein the substrate further comprises a third metal layer, the third metal layer including a third fin shielding component in the non-wiring region, wherein the via shielding component is coupled to the third fin shielding component.

12. The apparatus according to claim 10, The first component used for fin shielding includes multiple repeating first fins in the non-wiring area. The second component for fin shielding includes multiple repeating second fins in the non-wiring area, and The plurality of repeated second fins are offset from the plurality of repeated first fins.

13. The apparatus of claim 8, wherein the metal layer is further situated on the surface of the encapsulated component.

14. The apparatus of claim 8, wherein the apparatus is incorporated into a device selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, and devices in motor vehicles.

15. A method of manufacturing a package, comprising: A substrate is provided, the substrate including a wiring region and a non-wiring region along the periphery of the substrate, wherein the non-wiring region includes a plurality of vias configured to be shielded; the substrate further includes: A first metal layer, the first metal layer including a first fin structure in the non-wiring region; and The second metal layer includes a second fin structure in the non-wiring region. The plurality of through-holes are coupled to the first fin structure and the second fin structure; A metal layer is formed on the side of the substrate, such that the metal layer is coupled to the first fin structure and the second fin structure; Couple the integrated device to the substrate; and An encapsulation layer is formed on the substrate such that the encapsulation layer encapsulates the integrated device.

16. The method of claim 15, wherein the plurality of vias are configured not to be electrically connected to the integrated device.

17. The method according to claim 15, The wiring region of the substrate includes a plurality of interconnects configured to be electrically coupled to the integrated device, and The non-wiring region along the periphery of the substrate is a region of the substrate that does not have interconnects electrically coupled to the integrated device.

18. The method of claim 15, wherein forming the metal layer further comprises forming the metal layer above the surface of the encapsulation layer.

19. A package comprising: A substrate, the substrate including a wiring region and a non-wiring region along the periphery of the substrate, wherein the non-wiring region includes a plurality of vias configured to be shielded, the substrate further comprising: A first metal layer, the first metal layer including a first fin structure in the non-wiring region; and The second metal layer includes a second fin structure in the non-wiring region. The plurality of through-holes are coupled to the first fin structure and the second fin structure; The first fin structure includes a plurality of repeating first fins in the non-wiring area. The second fin structure includes a plurality of repeating second fins in the non-wiring area, and The plurality of repeated second fins are offset from the plurality of repeated first fins; An integrated device coupled to the substrate; and An encapsulation layer is located on the substrate such that the encapsulation layer encapsulates the integrated device.

20. The package of claim 19, wherein the substrate further comprises a third metal layer, the third metal layer comprising a third fin structure in the non-wiring region, wherein the plurality of vias are coupled to the third fin structure.

21. The package of claim 19, further comprising a metal layer located above a side portion of the substrate, such that the metal layer is coupled to the first fin structure.

22. The package of claim 19, wherein the metal layer is further located on the surface of the encapsulation layer.

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