semiconductor element

Abstract

This invention discloses a semiconductor device comprising: a semiconductor stack including a first reflective structure, a second reflective structure, and a resonant cavity region located between the first reflective structure and the second reflective structure, wherein the resonant cavity region includes a first surface, a second surface on the first surface, and a sidewall located on the first surface and the second surface, the first surface being closer to the first reflective structure than the second reflective structure; a first electrode electrically connected to the first reflective structure; and a second electrode electrically connected to the second reflective structure, wherein the second electrode includes an electrode pad portion and a side portion extending from the electrode pad portion; wherein the electrode pad portions of the first electrode and the second electrode are located on the first surface, and the side portion of the second electrode covers the sidewall of the resonant cavity region.

Description

[0001] This application is a divisional application of Chinese invention patent application (application number: 201810436344.5, application date: May 9, 2018, invention title: semiconductor element). Technical Field

[0002] This invention relates to a semiconductor device, and more particularly to a semiconductor device comprising a resonant cavity region. Background Technology

[0003] A vertical cavity surface emitting laser (VCSEL) emits light perpendicular to an active region. A VCSEL comprises a structure including a pair of mirror stacks and an active region located between the mirror stacks. A first electrode and a second electrode are respectively disposed above and below the mirror stacks. Current is injected into the active region through the first and second electrodes to cause the active region to emit light, which is emitted from the structure. Summary of the Invention

[0004] The present invention provides a semiconductor device comprising: a semiconductor stack including a first reflective structure, a second reflective structure, and a resonant cavity region located between the first reflective structure and the second reflective structure, wherein the resonant cavity region includes a first surface, a second surface on the first surface, and a sidewall located on the first surface and the second surface, the first surface being closer to the first reflective structure than the second reflective structure; a first electrode electrically connected to the first reflective structure; and a second electrode electrically connected to the second reflective structure, wherein the second electrode includes an electrode pad portion and a side portion extending from the electrode pad portion; wherein the electrode pad portions of the first electrode and the second electrode are located on the first surface, and the side portion of the second electrode covers the sidewall of the resonant cavity region.

[0005] The present invention also provides a semiconductor device comprising: a semiconductor stack including a first reflective structure, a second reflective structure, and a resonant cavity region located between the first reflective structure and the second reflective structure, wherein the resonant cavity region includes a first surface, a second surface on the first surface, and a sidewall located on the first surface and the second surface, the first surface being closer to the first reflective structure than the second reflective structure; a first electrode electrically connected to the first reflective structure; a second electrode electrically connected to the second reflective structure; and a first conductive layer located on the second surface of the resonant cavity region, the first electrode and the second electrode being located on the same side of the first conductive layer. Attached Figure Description

[0006] Figure 1This is a top view of a semiconductor element according to a first embodiment of the present invention;

[0007] Figure 2 The semiconductor element of the first embodiment of the present invention follows the path described above. Figure 1 A sectional view of line A-A';

[0008] Figures 3A to 3F To manufacture such Figure 1 as well as Figure 2 A schematic diagram of the method using the semiconductor device shown;

[0009] Figure 4A A cross-sectional view of a semiconductor element according to a second embodiment of the present invention;

[0010] Figure 4B A top view after the formation of the first conductive layer in the method for manufacturing a semiconductor element according to the second embodiment of the present invention;

[0011] Figure 5 A cross-sectional view of a semiconductor element according to a third embodiment of the present invention;

[0012] Figures 6A to 6F To manufacture such Figure 5 A schematic diagram of the method using the semiconductor device shown;

[0013] Figure 7 A cross-sectional view of a semiconductor element according to the fourth embodiment of the present invention;

[0014] Figures 8A to 8I To manufacture such Figure 7 A schematic diagram of the method for using a semiconductor device according to the fourth embodiment is shown;

[0015] Figure 9 This is a cross-sectional view of a semiconductor element according to the fifth embodiment of the present invention;

[0016] Figure 10 This is a cross-sectional view of a semiconductor element according to the sixth embodiment of the present invention;

[0017] Figure 11A This is a cross-sectional view of a semiconductor element according to the seventh embodiment of the present invention.

[0018] Figure 11B A cross-sectional view of a semiconductor element according to the eighth embodiment of the present invention;

[0019] Figure 11C A cross-sectional view of a semiconductor element according to the ninth embodiment of the present invention;

[0020] Figure 12A This is a cross-sectional view of a semiconductor element according to the tenth embodiment of the present invention;

[0021] Figure 12B This is a cross-sectional view of a semiconductor element according to the eleventh embodiment of the present invention;

[0022] Figure 12C This is a cross-sectional view of a semiconductor element according to the twelfth embodiment of the present invention;

[0023] Figure 13A This is a cross-sectional view of a semiconductor element according to the thirteenth embodiment of the present invention;

[0024] Figure 13B This is a cross-sectional view of a semiconductor element according to the fourteenth embodiment of the present invention;

[0025] Figure 13C This is a cross-sectional view of a semiconductor element according to the fifteenth embodiment of the present invention;

[0026] Figure 14 A cross-sectional view of a semiconductor element according to the sixteenth embodiment of the present invention; and

[0027] Figure 15 This is a cross-sectional view of a semiconductor element according to the seventeenth embodiment of the present invention.

[0028] Symbol Explanation

[0029] 10: Semiconductor stack 101: First reflective structure

[0030] 102: Second reflection structure; 103: Resonance cavity region

[0031] 104: First semiconductor contact layer; 105: Second semiconductor contact layer

[0032] 106: Etching barrier layer; 107: Conductive area

[0033] 108: Columnar structure; 1031: First surface

[0034] 1032: Second surface; 1033: Sidewall

[0035] 20: First electrode; 21: First outer surface

[0036] 30: Second electrode; 31: Electrode pad portion

[0037] 32: Side portion; 33: Second outer surface

[0038] 40: Substrate; 41: Top surface

[0039] 42: First page 43: Second page

[0040] 44: Third page 45: Fourth page

[0041] 46: First side 47: Second side

[0042] 50: First conductive layer; 51: Hole

[0043] 60: Adhesive layer; 70: Second conductive layer

[0044] 80: First insulating layer; 801: First region

[0045] 802: Second Region; 90: Metal Contact Layer

[0046] 100: Growth substrate; 110: Insulating area

[0047] 120: Groove; 1201: Third semiconductor layer

[0048] 130: Second insulation layer; 1301: Third region

[0049] 1302: Fourth District

[0050] 1303: Opening 140: Current limiting layer

[0051] 1401: Conductive part; 1402: Insulating part

[0052] 150: Optical structure; 1501: Convex part

[0053] 1502: Recessed portion 160: Optical element

[0054] 1601: Third side 1602: Fourth side

[0055] W1: First width W2: Second width

[0056] W3: Third width W4: Fourth width

[0057] D1: First distance; D2: Second distance

[0058] D3: Third distance 1033a: First part

[0059] 1033b: Second part Detailed Implementation

[0060] The following embodiments will illustrate the concept of the invention with accompanying drawings. In the drawings or description, similar or identical parts are referred to by the same reference numerals, and the shape or thickness of elements may be enlarged or reduced in the drawings. It should be particularly noted that elements not shown in the drawings or described in the specification may be in forms known to those skilled in the art.

[0061] In this specification, unless otherwise specified, the same element symbols in different drawings have the same or substantially the same structure, material, material composition and / or manufacturing method as described anywhere in the content of this invention.

[0062] In this invention, unless otherwise specified, the general formula AlGaAs represents Al x1 Ga (1-x1) As, where 0≤x1≤1; the general formula AlInP represents Al x2 In (1-x2) P, where 0 ≤ x² ≤ 1; the general formula AlGaInP represents (Al y1 Ga (1-y1) ) 1-x3 In x3 P, where 0 ≤ x³ ≤ 1, 0 ≤ y¹ ≤ 1; the general formula AlAsSb represents AlAs (1-x5) Sb x5 Where 0 ≤ x5 ≤ 1; the general formula InGaP represents In x6 Ga 1-x6 P, where 0 ≤ x6 ≤ 1; the general formula InGaAsP represents In x7 Ga 1-x7 As 1-y2 P y2 Where 0≤x7≤1, 0≤y2≤1; the general formula AlGaAsP represents Al x9 Ga 1-x9 As 1-y4 P y4 Where 0≤x9≤1, 0≤y4≤1; the general formula InGaAs represents In x10 Ga 1- x10 As, where 0 ≤ x 10 ≤ 1; Adjusting the content of elements can achieve different purposes, such as, but not limited to, adjusting the energy level, or, when the semiconductor element is a light-emitting element, adjusting the main emission wavelength of the light-emitting element.

[0063] Figure 1 This is a top view of a semiconductor element according to a first embodiment of the present invention. Figure 2 The semiconductor element of the first embodiment of the present invention follows the path described above. Figure 1 A sectional view of line A-A'. See also Figure 1 as well as Figure 2The semiconductor element includes a semiconductor stack 10, a first electrode 20 electrically connected to the semiconductor stack 10, and a second electrode 30 electrically connected to the semiconductor stack 10. The semiconductor stack 10 includes a first reflective structure 101, a second reflective structure 102, and a resonant cavity region 103 located between the first reflective structure 101 and the second reflective structure 102. The first electrode 20 is electrically connected to the first reflective structure 101. The second electrode 30 is electrically connected to the second reflective structure 102. In this embodiment, the first reflective structure 101 includes an n-type distributed Bragg reflector (DBR). The second reflective structure 102 includes a p-type distributed Bragg reflector (DBR). In one embodiment, the first reflective structure 101 includes a p-type DBR. The second reflective structure 102 includes an n-type DBR. The resonant cavity region 103 can emit radiation. Preferably, the resonant cavity region 103 can emit coherent radiation. Preferably, the coherent radiation has a far-field angle of less than 50 degrees, and more preferably, less than 40 degrees. The resonant cavity region 103 includes an active region (not shown), which contains a multi-quantumwell (MQW) structure. To clarify the beam divergence, the far-field angle of the radiation from the light-emitting element of this invention is a divergence angle of half a wavelength.

[0064] Please see Figure 2The resonant cavity region 103 includes a first surface 1031, a second surface 1032 opposite to the first surface 1031, and a sidewall 1033 located between the first surface 1031 and the second surface 1032. The first surface 1031 is closer to the first reflective structure 101 than to the second reflective structure 102. The sidewall 1033 has a first portion 1033a and a second portion 1033b opposite to the first portion 1033a. The first portion 1033a of the sidewall 1033 is closer to the second electrode 30 than to the first electrode 20. The second portion 1033b of the sidewall 1033 is closer to the first electrode 20 than to the second electrode 30. The second electrode 30 includes an electrode pad portion 31 and a side portion 32. The electrode pad portion 31 is on the first surface 1031 of the resonant cavity region 103, and the side portion 32 extends from the electrode pad portion 31 and covers the sidewall 1033 of the resonant cavity region 103. Specifically, compared to the first electrode 20, the first portion 1033a of the sidewall 1033 is closer to the side portion 32 of the second electrode 30. Preferably, the side portion 32 covers the first portion 1033a of the sidewall 1033. The electrode pad portions 31 of the first electrode 20 and the second electrode 30 are located on the same side of the resonant cavity region 103. Preferably, the first electrode 20 does not overlap with the second electrode 30 in the thickness direction T1 of the resonant cavity region 103. The thickness direction T1 of the resonant cavity region 103 is as follows: Figure 1 As shown.

[0065] In this embodiment, the electrode pad portions 31 of both the first electrode 20 and the second electrode 30 are located on the first surface 1031. In other words, compared to the second surface 1032 of the resonant cavity region 103, the electrode pad portions 31 of both the first electrode 20 and the second electrode 30 are closer to the first surface 1031 of the resonant cavity region 103. Specifically, the first electrode 20 includes a first outer surface 21, which is substantially parallel to the first surface 1031 of the resonant cavity region 103. The electrode pad portion 31 of the second electrode 30 includes a second outer surface 33, which is substantially parallel to the first surface 1031 of the resonant cavity region 103. The first outer surface 21 and the second outer surface 33 are both located on the same side of the resonant cavity region 103. In this embodiment, the first outer surface 21 and the second outer surface 33 are both located on the first surface 1031. In other words, compared to the second surface 1032 of the resonant cavity region 103, the first outer surface 21 and the second outer surface 33 are closer to the first surface 1031 of the resonant cavity region 103. The height difference between the first outer surface 21 and the second outer surface 33 is no greater than 5 micrometers (μm), and preferably no greater than 3 μm.

[0066] The first reflective structure 101 and the second reflective structure 102 each comprise a plurality of overlapping first semiconductor layers (not shown) and second semiconductor layers (not shown). Each first semiconductor layer has a first refractive index, and each second semiconductor layer has a second refractive index smaller than the first refractive index. The materials of the first and second semiconductor layers comprise group III-V semiconductor materials. In one embodiment, each first semiconductor layer has a first aluminum content, and each second semiconductor layer has a second aluminum content. The second aluminum content of each second semiconductor layer is different from the first aluminum content of each first semiconductor layer, and preferably is greater than the first aluminum content of each first semiconductor layer. In one embodiment, the first reflective structure 101 comprises a first group (not shown) and a second group (not shown) located on the first group. The first group has a first doping concentration of a dopant, and the second group has a second doping concentration of a dopant. Preferably, the first doping concentration and the second doping concentration are different. In one embodiment, the first doping concentration is higher than the second doping concentration. Preferably, the ratio of the first doping concentration to the second doping concentration is between 1.1 and 3 (both inclusive), and more preferably, between 1.1 and 1.5 (both inclusive). In one embodiment, the second doping concentration is higher than the first doping concentration. Preferably, the ratio of the second doping concentration to the first doping concentration is between 1.1 and 3 (both inclusive), and more preferably, between 1.1 and 1.5 (both inclusive). In one embodiment, the dopants in the first group are the same as those in the second group. In this embodiment, the first semiconductor layer comprises Al. n Ga (1-n) As, the second semiconductor layer contains Al m Ga (1-m) As, where n is different from m, and preferably, m is greater than n. The predetermined reflection band range can be achieved by adjusting the aluminum and gallium content in the first and second semiconductor layers. Each first semiconductor layer has a thickness substantially equal to λ / 4n, and each second semiconductor layer has a thickness substantially equal to λ / 4n, where λ is the peak wavelength of the radiation emitted from the resonant cavity region 103, and n is the refractive index of each layer. The first reflective structure 101 has a reflectivity exceeding 99% at the peak wavelength. The second reflective structure 102 has a reflectivity exceeding 98% at the peak wavelength. Preferably, the reflectivity of the first reflective structure 101 at the peak wavelength is greater than that of the second reflective structure 102 at the peak wavelength.

[0067] In the first reflective structure 101, the number of pairs of the first semiconductor layer and the second semiconductor layer is greater than that in the second reflective structure 102, wherein a first semiconductor layer and an adjacent second semiconductor layer are considered a pair. Preferably, the number of pairs of the first reflective structure 101 is greater than 15, and more preferably, greater than 30 and less than 80. The number of pairs of the second reflective structure 102 is greater than 15, and more preferably, greater than 20 and less than 80.

[0068] Please see Figure 1 as well as Figure 2 In this embodiment, the semiconductor device further includes a substrate 40 located on the semiconductor stack 10. Radiation emitted from the resonant cavity region 103 dissipates outside the semiconductor device in a direction from the first surface 1031 to the second surface 1032 of the resonant cavity region 103. The substrate 40 includes a top surface 41 having a first area. The first outer surface 21 of the first electrode 20 includes a second area, which is not less than 10% of the first area, and preferably not greater than 40% of the first area, and more preferably between 13% and 30% of the first area (both inclusive). The second outer surface 33 of the second electrode 30 includes a third area, which is not less than 10% of the first area, and preferably not greater than 40% of the first area, and more preferably between 13% and 30% of the first area (both inclusive). The first area, the second area, and the third area are viewed from a top view of the semiconductor device.

[0069] Please see Figure 2 In this embodiment, the semiconductor element further includes a first conductive layer 50 and an adhesive layer 60. The first conductive layer 50 is located between the substrate 40 and the semiconductor stack 10, and the adhesive layer 60 covers the first conductive layer and is located between the substrate 40 and the semiconductor stack 10. In this embodiment, the semiconductor element includes a plurality of holes 51 penetrating the first conductive layer 50, and the plurality of holes 51 are arranged in a one-dimensional array or a two-dimensional array. The adhesive layer 60 surrounds the first conductive layer 50, and a portion of the adhesive layer 60 is located within the plurality of holes. The adhesive layer 60 is used to connect the substrate 40 and the semiconductor stack 10, and radiation emitted from the resonant cavity region 103 can substantially penetrate the adhesive layer 60. In one embodiment, the semiconductor element includes a hole penetrating the first conductive layer 50. The adhesive layer 60 surrounds the first conductive layer 50, and a portion of the adhesive layer 60 is located within the hole.

[0070] In this embodiment, the first conductive layer 50 has a first width W1, and the resonant cavity region 103 has a second width W2, wherein the first width W1 is greater than the second width W2. Specifically, a portion of the first conductive layer is not covered by the resonant cavity region 103, thus a portion of the first conductive layer is exposed. The second electrode 30 is in direct contact with the exposed portion of the first conductive layer 50. Specifically, the side portion 32 of the second electrode 30 is in direct contact with the exposed portion of the first conductive layer 50. The first conductive layer 50 has a thickness of not less than 500 nanometers (nm), preferably not more than 3000 nm, and more preferably not more than 2000 nm. In this embodiment, the first electrode 20 and the second electrode 30 are located on the same side of the first conductive layer 50.

[0071] Please see Figure 1 In this embodiment, the substrate 40 includes a first surface 42, a second surface 43 opposite to the first surface 42, and a third surface 44 and a fourth surface 45 located between the first surface 42 and the second surface 43. The top surface 41 of the substrate 40 is located between the first surface 42, the second surface 43, the third surface 44, and the fourth surface 45. In this embodiment, the first surface 42 has a first edge (not shown), the second surface 43 has a second edge (not shown), the third surface 44 has a third edge (not shown), and the fourth surface 45 has a fourth edge (not shown). In this embodiment, the length of the first edge is less than the length of the third edge or the length of the fourth edge, and the length of the second edge is less than the length of the third edge or the length of the fourth edge. In another embodiment, the lengths of the first edge, the second edge, the third edge, and the fourth edge are substantially the same.

[0072] Please see Figure 2 In a cross-sectional view of a semiconductor device, the first distance D1 between the first surface 42 of the substrate 40 and the first portion 1033a of the sidewall 1033 of the resonant cavity region 103 is different from the second distance D2 between the second surface 43 of the substrate 40 and the second portion 1033b of the sidewall 1033 of the resonant cavity region 103. Preferably, the first distance is at least 15 micrometers (μm) greater than the second distance, and more preferably, not more than 50 μm. The first distance D1 is not less than 20 μm, and preferably, not more than 60 μm. The second distance D2 is not less than 5 μm, and preferably, not more than 40 μm.

[0073] Please see Figure 2In this embodiment, the semiconductor element further includes a first semiconductor contact layer 104 and a second semiconductor contact layer 105. The first semiconductor contact layer 104 is located between the first electrode 20 and the first reflective structure 101, and the second semiconductor contact layer 105 is located between the second reflective structure 102 and the first conductive layer 50. In this embodiment, the second semiconductor contact layer 105 includes a plurality of separate contact regions 1051, which are arranged in a one-dimensional array or a two-dimensional array. Specifically, each contact region 1051 is located directly below a hole 51 penetrating the first conductive layer 50. Preferably, the contact regions 1051 and the holes 51 correspond one-to-one. In other words, the first conductive layer 50 does not overlap with the plurality of contact regions 1051 in the thickness direction T1 of the resonant cavity region 103.

[0074] In this embodiment, the second electrode 30 overlaps with one or more contact areas 1051 in the thickness direction T1 of the resonant cavity region 103. Specifically, the electrode pad portion 31 of the second electrode 30 overlaps with one or more contact areas 1051 in the thickness direction T1 of the resonant cavity region 103. Each contact area 1051 has a third width W3. Each hole 51 penetrating the first conductive layer 50 has a fourth width W4. The third width W3 of a contact area 1051 is smaller than the fourth width W4 of its corresponding hole 51. Specifically, the third width W3 of a contact area 1051 is smaller than the fourth width W4 of the hole 51 located directly above it. Preferably, the third width W3 of each contact area 1051 is smaller than the fourth width W4 of its corresponding hole 51. Therefore, the problem of the first conductive layer 50 blocking light emitted from the resonant cavity region 103 can be avoided or mitigated. In this embodiment, each hole 51 has a circular shape. Each contact area 1051 has a circular shape. The fourth width W4 of one of the holes 51 is the diameter of a circle. The third width W3 of one of the contact areas 1051 is the diameter of a circle. The shapes of the contact area 1051 and the hole 51 are not limited to this embodiment. The shapes of the hole 51 and the contact area 1051 can be elliptical, rectangular, square, rhomboid, or any other suitable shape. The third width W3 is, for example, but not limited to, between 15 μm and 40 μm (both inclusive). The fourth width W4 is, for example, but not limited to, between 20 μm and 50 μm (both inclusive).

[0075] In one embodiment, the semiconductor element further includes a hole penetrating the first conductive layer 50, with the second semiconductor contact layer 105 located directly below the hole. In other words, the first conductive layer 50 does not overlap with the second semiconductor contact layer 105 in the thickness direction T1 of the resonant cavity region 103. The second semiconductor contact layer 105 has a third width, and the hole penetrating the first conductive layer 50 has a fourth width. Preferably, the third width is smaller than the fourth width.

[0076] Please see Figure 2 In this embodiment, the semiconductor stack 10 further includes an etch stop layer 106 located between the second electrode 30 and the first semiconductor contact layer 104. The semiconductor element also includes a second conductive layer 70 located between the second reflective structure 102 and the first conductive layer 50. The second conductive layer 70 covers and surrounds a plurality of contact regions 1051. The contact resistance between the contact regions 1051 and the second reflective structure 102 is lower than the contact resistance between the second conductive layer 70 and the second reflective structure 102. In this embodiment, the material of the first conductive layer 50 is different from the material of the second conductive layer 70.

[0077] Please see Figure 1 as well as Figure 2 In this embodiment, the semiconductor element further includes a first insulating layer 80 located between the semiconductor stack 10 and the second electrode 30. Furthermore, the first insulating layer 80 is located between the first electrode 20 and the semiconductor stack 10. The first insulating layer 80 overlaps with the first reflective structure 101 and the second reflective structure 102 in the thickness direction T1 of the resonant cavity region 103. In this embodiment, the first insulating layer 80 covers a bottom surface of the etch stop layer 106, covers the sidewalls of the etch stop layer 106, covers the sidewalls of the first semiconductor contact layer 104, covers the sidewalls of the first reflective structure 101, covers the sidewalls 1033 of the resonant cavity region 103, covers the sidewalls of the second reflective structure 102, covers the sidewalls of the second conductive layer 70, and is in direct contact with the exposed portion of the first conductive layer 50. The first insulating layer 80 is partially covered by the second electrode 30. Therefore, the first insulating layer 80 is located between the first surface 1031 of the resonant cavity region 103 and the electrode pad portion 31 of the second electrode 30, and between the side wall 1033 of the resonant cavity region 103 and the side portion 32 of the second electrode 30. The first electrode 20 covers another portion of the first insulating layer 80, so the first insulating layer 80 is also located between the first surface 1031 of the resonant cavity region 103 and the first electrode 20.

[0078] Please see Figure 2In this embodiment, in a cross-sectional view of the semiconductor element, the first insulating layer 80 includes a first region 801 and a second region 802. A second electrode 30 is located between the first region 801 and the second region 802. Specifically, a side portion 32 of the second electrode 30 separates the second region 802 and the first region 801. The first region 801 is located between the semiconductor stack 10 and the side portion 32 of the second electrode 30. The second region 802 is in direct contact with the adhesive layer 60. In this embodiment, the second region 802 is in direct contact with both the adhesive layer 60 and the first conductive layer 50. The first insulating layer 80 has a thickness of less than 500 nm, and preferably, no greater than 3 μm.

[0079] Please see Figure 1 as well as Figure 2 In this embodiment, the first electrode 20 and the second electrode 30 are separated, and the first insulating layer 80 located between the first electrode 20 and the semiconductor stack 10 is exposed. A third distance D3 between the first electrode 20 and the second electrode 30 is not less than 50 μm, and preferably not more than 300 μm, and more preferably between 90 μm and 200 μm (both inclusive). In other words, a third distance D3 between the electrode pad portions 31 of the first electrode 20 and the second electrode 30 is not less than 50 μm, and preferably not more than 300 μm, and more preferably between 90 μm and 200 μm (both inclusive).

[0080] Please see Figure 2 The semiconductor device further includes a metal contact layer 90 located between the first electrode 20 and the first reflective structure 101. The metal contact layer 90 penetrates the etch barrier layer 106 and thus directly contacts the first semiconductor contact layer 104. In other words, the etch barrier layer 106 surrounds the metal contact layer 90. In this embodiment, the metal contact layer 90 does not overlap with the second electrode 30 in the thickness direction T1 of the resonant cavity region 103. Specifically, the metal contact layer 90 does not overlap with the electrode pad portion 31 of the second electrode 30 in the thickness direction T1 of the resonant cavity region 103. Preferably, the metal contact layer 90 has a maximum width that is smaller than the maximum width of the first electrode 20. The direction in which the maximum width of the metal contact layer 90 and the maximum width of the first electrode 20 are measured is substantially perpendicular to the thickness direction T1 of the resonant cavity region 103.

[0081] When current flows from the first electrode 20 and the second electrode 30 into the resonant cavity region 103, because the contact resistance between the second semiconductor contact layer 105 and the second conductive layer 70 is relatively lower than the contact resistance between the second conductive layer 70 and the second reflective structure 10, most of the current flows from the second conductive layer 70 to the contact region 1051 of the second semiconductor contact layer 105, and then mainly flows into the resonant cavity region 103 via the contact region 1051. That is, the current density at the location of the second reflective structure 102 directly below the contact region 1051 is higher than the current density at the location of the second reflective structure 102 not covered by the contact region 1051. In this embodiment, the resonant cavity region 103 located directly below the contact region 1051 serves as the main radiation emission region I, and the radiation emitted by the main radiation emission region I dissipates from the substrate 40 to the outside of the semiconductor element through the holes 51 formed in the first conductive layer 50.

[0082] In this embodiment, the semiconductor element has a forward voltage V f A laser threshold current I th and a saturation current I sat A semiconductor device under a forward voltage V f A significant positive current begins to conduct, the laser threshold current I. th It is the minimum current at which stimulated emission exceeds spontaneous emission in the radiation emitted by the radiative emission region of a semiconductor device, and therefore the laser threshold current I. th The downward radiation is homogeneous. The saturation current I... sat This refers to the current whose radiation output no longer increases with increasing forward current. The semiconductor element operates when its forward voltage V is greater than the semiconductor element's forward voltage V. f Operating voltage V op And when the forward current is less than the laser threshold current I th When operating under these conditions, the radiation emitted by the radiation emission region I of the semiconductor element described in this invention is non-homogeneous light. When the semiconductor element is in a forward current greater than the laser threshold current I... th and less than the saturation current I sat When operating under these conditions, the radiation emitted by the radiation emission region I of the semiconductor element is homogeneous light.

[0083] Figures 3A to 3F To manufacture such Figure 1 as well as Figure 2 The method for using the semiconductor device shown. Figure 3A This is a top view after the contact area 1051 has been formed. Figure 3B For along such Figure 3A A sectional view of line A-A'. See also Figure 3A as well as Figure 3B Manufacturing such Figure 1 as well as Figure 2 The method of creating the semiconductor device includes providing a growth substrate 100; forming a semiconductor stack 10 on the growth substrate 100 by epitaxial growth, wherein the semiconductor stack 10 sequentially includes an etch stop layer 106, a first semiconductor contact layer 104, a first reflective structure 101, a resonant cavity region 103, a second reflective structure 102 and a semiconductor layer (not shown); and patterning the semiconductor layer to form a second semiconductor contact layer 105 including a plurality of contact regions 1051.

[0084] Figure 3C This is a top view after the contact area 1051 has been formed. Figure 3D For along such Figure 3C A sectional view of line A-A'. See also Figure 3C as well as Figure 3D The method for manufacturing a semiconductor device further includes forming a second conductive layer 70 on a semiconductor stack 10, wherein the second conductive layer 70 covers a plurality of contact regions 1051; forming a current-conducting layer (not shown) on the second conductive layer 70; and patterning the current-conducting layer using a photolithography mask to form a first conductive layer 50. After patterning the current-conducting layer, the semiconductor device includes a plurality of holes 51 penetrating the first conductive layer 50, the positions of which correspond to the positions of the contact regions 1051. In other words, the first conductive layer 500 does not overlap with the contact regions 1051 in the thickness direction T1 of the resonant cavity region 103, and the plurality of holes 51 are exposed beneath the second conductive layer 70.

[0085] Figure 3E This is a cross-sectional view after connecting substrate 40. Please refer to [link / reference]. Figure 3E The method of manufacturing a semiconductor device further includes providing a substrate 40; connecting the substrate 40 and an adhesive layer 60. Figure 3D The structure shown; and the removal of the growth substrate 100 by any suitable method. A portion of the adhesive layer 60 is located within the holes 51 formed in the first conductive layer 50.

[0086] Figure 3F This is a cross-sectional view after the first insulating layer 80 has been formed. See also... Figure 3FThe method of manufacturing a semiconductor device further includes removing a portion of the semiconductor stack 10 and a portion of the second conductive layer 70 by any suitable method, such as inductively coupled plasma (ICP) or wet etching, to expose a portion of the first conductive layer 50 and a portion of the adhesive layer 60; removing a portion of the etch barrier layer 106 to expose a portion of the first semiconductor contact layer 104; forming a metal contact layer 90 in direct contact with the exposed portion of the first semiconductor contact layer 104, wherein in this embodiment, the metal contact layer 90 comprises an alloy, such as germanium-gold-nickel; and forming a first insulating layer 80, which covers the sidewalls of the semiconductor stack 10, covers the sidewalls of the second conductive layer 70, and is in direct contact with the exposed portion of the first conductive layer 50.

[0087] The method of manufacturing a semiconductor device further includes removing a portion of a first insulating layer 80 located on a first conductive layer 50 and forming a first electrode 20 and a second electrode 30 to achieve, for example... Figure 2 The semiconductor element shown.

[0088] Please see Figure 2 A portion of the first insulating layer 80 located on the first conductive layer 50 is removed to form a trench (not shown) exposing a portion of the first conductive layer 50, and a portion of the first insulating layer 80 located on the first semiconductor contact layer 104 is also removed to simultaneously expose the etch stop layer 106 and the metal contact layer 90. In another embodiment, after removing the first insulating layer 80, the etch stop layer 106 may not be exposed, only the metal contact layer 90 may be exposed. In an incomplete cross-sectional view of the semiconductor device, the trench divides the first insulating layer 80 into a first region 801 and a second region 802. The first region 801 covers the sidewalls of the semiconductor stack 10.

[0089] The first electrode 20 is in direct contact with the exposed portion of the metal contact layer 90, and preferably, the first electrode 20 is in direct contact with the exposed portion of the metal contact layer 90, the exposed portion of the etch barrier layer 106, and a portion of the first insulating layer 80 simultaneously. The second electrode 30 is separated from the first electrode 20 and located on the first insulating layer 80. Specifically, the second electrode 30 covers the first region 801. A portion of the side portion 32 is located within a trench to directly contact the exposed portion of the first conductive layer 50.

[0090] Figure 4A This is a cross-sectional view of a semiconductor element according to a second embodiment of the present invention. Figure 4BThis is a top view after the first conductive layer 50 has been formed in the method of manufacturing a semiconductor element according to the second embodiment of the present invention. The semiconductor element of the second embodiment of the present invention includes a structure substantially the same as that of the first embodiment, and the method of manufacturing the semiconductor element of the second embodiment includes steps substantially the same as those of the semiconductor element of the first embodiment. The difference between the semiconductor element of the second embodiment and the semiconductor element of the first embodiment is that the second semiconductor contact layer 105 does not overlap with the second electrode 30 in the thickness direction T1 of the resonant cavity region 103. In other words, the second semiconductor contact layer 105 does not overlap with the electrode pad portion 31 of the second electrode 30 in the thickness direction T1 of the resonant cavity region 103. Specifically, the hole 51 penetrating the first conductive layer 50 does not overlap with the electrode pad portion 31 of the second electrode 30 in the thickness direction T1 of the resonant cavity region 103.

[0091] Figure 5 This is a cross-sectional view of a semiconductor element according to a third embodiment of the present invention. The semiconductor element of the third embodiment of the present invention comprises a structure substantially the same as that of the first embodiment, with the differences described below. In this embodiment, the second semiconductor contact layer 105 does not include the plurality of separate contact regions 1051 as in the first embodiment. The first conductive layer 50 is directly located on the second semiconductor contact layer 105. The semiconductor element of this embodiment does not include the second conductive layer 70 located between the second reflective structure 102 and the adhesive layer 60 as in the first embodiment. The semiconductor element also includes an insulating region 110 formed within the semiconductor stack 10 for defining one or more conductive regions 107 within the semiconductor stack 10. The insulating region 110 contains ions, such as argon (Ar) ions, helium (He) ions, or hydrogen (H) ions, for reducing the conductivity of the semiconductor stack 10. Figure 6A As shown, the insulating region 110 surrounds multiple conductive regions 107.

[0092] In this embodiment, the insulating region 110 is located on the first semiconductor contact layer 104. Preferably, the insulating region 110 is located on the resonant cavity region 103. The conductive region 107 includes the portion of the second semiconductor contact layer 105 that does not contain ions that reduce conductivity and the portion of the second reflective structure 102 that does not contain ions that reduce conductivity. Each conductive region 107 is directly located under one of the holes 51. In this embodiment, the insulating region 110 is located within the second semiconductor contact layer 105 and within the second reflective structure 102. In another embodiment, the insulating region 110 is located only within the second reflective structure 102. Specifically, the insulating region 110 is not directly located under the plurality of holes 51 penetrating the first conductive layer 50. In other words, the insulating region 110 overlaps with the first conductive layer 50 in the thickness direction T1 of the resonant cavity region 103. However, the insulating region 110 does not overlap with the plurality of holes 51 penetrating the first conductive layer 50 in the thickness direction T1 of the resonant cavity region 103.

[0093] In this embodiment, the pattern of the insulating region 110 is substantially identical to the pattern of the first conductive layer 50. In other words, the conductive regions 107, surrounded by and separated from each other by the insulating region 110, are arranged in a one-dimensional or two-dimensional array. Preferably, the arrangement of the conductive regions 107 is substantially the same as the arrangement of the holes 51 penetrating the first conductive layer 50. Furthermore, each conductive region 107 is located directly beneath one of the holes 51. In this embodiment, in a top view of the conductive region 107, the shape of the conductive region 107 can be elliptical, rectangular, square, rhomboid, or any other suitable shape. Each conductive region 107 has a conductivity higher than that of the insulating region 110. Preferably, the conductivity of the conductive region 107 is at least three orders of magnitude higher than that of the insulating region 110, and more preferably, at least five orders of magnitude higher.

[0094] The exposed portions of the second semiconductor contact layer 105 are located beneath the plurality of holes 51 penetrating the first conductive layer 50. In this embodiment, when current flows into the resonant cavity region 103 from the first electrode 20 and the second electrode 30, most of the current flows into the resonant cavity region 103 from the conductive region 107 directly below the holes 51 because the conductivity of the conductive region 107 directly below the holes 51 is higher than that of the insulating region 110. In this embodiment, the portion of the resonant cavity region 103 directly below the holes 51 serves as the main radiation emission region I, and the radiation emitted from the main radiation emission region I dissipates from the substrate 40 to the outside of the semiconductor device via the holes 51 penetrating the first conductive layer 50. In this embodiment, in a cross-sectional view of the semiconductor device, the width of a conductive region 107 is greater than the fourth width W4 of the corresponding hole 51. Preferably, the width of each conductive region 107 is greater than the fourth width W4 of its corresponding hole 51. In other words, the first conductive layer 50 overlaps with both the conductive region 107 and the insulating region 110 in the thickness direction T1 of the resonant cavity region 103.

[0095] Figures 6A to 6F To manufacture such Figure 5 The method for using the semiconductor device shown. Figure 6A This is a top view after the insulation region 110 has been formed. Figure 6B For along such Figure 6A A sectional view of line A-A'. See also Figure 6A as well as Figure 6B Manufacturing such Figure 5 The method for creating a semiconductor device includes providing a growth substrate 100; forming a semiconductor stack 10 on the growth substrate 100 via epitaxial growth; and implanting ions into a portion of the semiconductor stack 10 to reduce conductivity and form an insulating region 110. The ion implantation does not substantially affect the conductivity of another portion of the semiconductor stack 10; the ions may be, for example, argon (Ar) ions, helium (He) ions, or hydrogen (H) ions. In this embodiment, ions are implanted into a portion of the second semiconductor contact layer 105 and a portion of the second reflective structure 102 to form the insulating region 110 and define a conductive region 107 surrounded by the insulating region 110. Preferably, ions are not implanted into the resonant cavity region 103. In another embodiment, ions are implanted only into a portion of the second reflective structure 102. The portions of the second semiconductor contact layer 105 and the second reflective structure 102 that do not contain ions that reduce conductivity constitute the conductive region 107. In this embodiment, the conductive regions 107 are arranged in a one-dimensional or two-dimensional array.

[0096] Figure 6C This is a top view after the first conductive layer 50 has been formed. Figure 6D For along Figure 6CA sectional view of line A-A'. See also Figure 6C as well as Figure 6D Manufacturing such Figure 5 The method for creating the semiconductor device further includes forming a current-conducting layer (not shown) on the semiconductor stack 10; and patterning the current-conducting layer using a photolithographic mask to form a first conductive layer 50. After patterning the current-conducting layer, the semiconductor device includes a plurality of holes 51 penetrating the first conductive layer 50 to expose portions of a second semiconductor contact layer 105 located thereunder and not containing implanted ions. In other words, the holes 51 penetrating the first conductive layer 50 expose conductive regions 107 thereunder. In this embodiment, in a cross-sectional view of the semiconductor stack 10, the width of each conductive region 107 is greater than the fourth width W4 of the corresponding hole 51. In other words, the first conductive layer 50 overlaps with both the conductive region 107 and the insulating region 110 in the thickness direction T1 of the resonant cavity region 103.

[0097] Figure 6E This is a cross-sectional view after connecting substrate 40. Please refer to [link / reference]. Figure 6E Manufacturing such Figure 5 The method for creating a semiconductor device further includes providing a substrate 40; connecting the substrate 40 and the substrate 40 via an adhesive layer 60. Figure 6D The structure shown; and the removal of the growth substrate 100 by any suitable method. A portion of the adhesive layer 60 is located within a plurality of holes 51 penetrating the first conductive layer 50.

[0098] Figure 6F This is a cross-sectional view after the first insulating layer 80 has been formed. See also... Figure 6F Manufacturing such Figure 5 The method for creating the semiconductor device further includes removing a portion of the semiconductor stack 10 by any suitable method, such as inductively coupled plasma (ICP) or wet etching, to expose a portion of the first conductive layer 50 and a portion of the adhesive layer 60; removing a portion of the etch stop layer 106 to expose a portion of the first semiconductor contact layer 104; forming a metal contact layer 90 in direct contact with the exposed portion of the first semiconductor contact layer 104, the metal contact layer 90 comprising an alloy, such as germanium-gold-nickel; and forming a first insulating layer 80 that covers the sidewalls of the etch stop layer 106 relative to the substrate 40, covers the sidewalls of the first reflective structure 101, covers the sidewalls 1033 of the resonant cavity region 103, covers the sidewalls of the insulating region 110, and is in direct contact with the exposed portion of the first conductive layer 50. In this embodiment, the first insulating layer 80 is also in direct contact with the adhesive layer 60.

[0099] The method of manufacturing a semiconductor device further includes removing a portion of a first insulating layer 80 located on a first conductive layer 50 and forming a first electrode 20 and a second electrode 30 to achieve the following: Figure 5 The semiconductor element shown. Please refer to [link / reference]. Figure 5 A portion of the first insulating layer 80 located on the first conductive layer 50 is removed to form a trench (not shown) exposing a portion of the first conductive layer 50, and a portion of the first insulating layer 80 located on the first semiconductor contact layer 104 is also removed to simultaneously expose the etch stop layer 106 and the metal contact layer 90. In another embodiment, after removing the first insulating layer 80, the etch stop layer 106 may not be exposed, only the metal contact layer 90 may be exposed. In an incomplete cross-sectional view of the semiconductor device, the trench divides the first insulating layer 80 into a first region 801 and a second region 802. The first region 801 covers the sidewalls of the semiconductor stack 10.

[0100] The first electrode 20 is in direct contact with the exposed portion of the metal contact layer 90, and preferably, the first electrode 20 is in direct contact with the exposed portion of the metal contact layer 90, the exposed portion of the etch barrier layer 106, and a portion of the first insulating layer 80 simultaneously. The second electrode 30 is separated from the first electrode 20 and located on the first insulating layer 80. Specifically, the second electrode 30 covers the first region 801. A portion of the side portion 32 is located within a trench to directly contact the exposed portion of the first conductive layer 50.

[0101] Figure 7 This is a cross-sectional view of a semiconductor element according to a fourth embodiment of the present invention. The semiconductor element of the fourth embodiment of the present invention comprises substantially the same structure as that of the first embodiment, with the differences described below. Please refer to... Figure 7 The semiconductor stack 10 includes a plurality of columnar structures 108 separated from each other by a groove 120. Each columnar structure 108 includes the same structure, that is, in this embodiment, each columnar structure 108 sequentially includes a first reflective structure 101, a resonant cavity region 103, a second reflective structure 102 and a second semiconductor contact layer 105 as mentioned in the first embodiment.

[0102] Each columnar structure 108 includes an outer wall 1081, with a groove 120 exposing the outer wall 1081. Specifically, the groove 120 penetrates the second semiconductor contact layer 105, and preferably, the groove 120 also penetrates the second reflective structure 102 and penetrates the resonant cavity region 103 to expose the first reflective structure 101. Therefore, the outer wall 1081 of the columnar structure 108 is exposed. Compared to the sidewall 1033 of the resonant cavity region 103, the outer wall 1081 is further away from the first surface 42, second surface 43, third surface 44, and fourth surface 45 of the substrate 40. In a top view of the columnar structure 108, the shape of the columnar structure 108 can be, but is not limited to, circular, rectangular, square, rhomboid, or any other suitable shape.

[0103] The semiconductor device further includes a second insulating layer 130 covering the columnar structure 108 along its contour. Specifically, the second insulating layer 130 covers one top surface of the second semiconductor contact layer 105 facing the substrate 40, covers the outer wall 1081 of the columnar structure 108, and covers an upper surface of the first reflective structure 101 exposed by the recess 120. Specifically, the second insulating layer 130 is located between the first conductive layer 5 and the first electrode 20. The second insulating layer 130 overlaps with the first insulating layer 80 in the thickness direction T1 of the resonant cavity region 103. In other words, the second insulating layer 130 overlaps with both the second electrode 30 and the first insulating layer 80 in the thickness direction T1 of the resonant cavity region 103. Specifically, the second insulating layer 130 overlaps with both the electrode pad portion 31 of the second electrode 30 and the first insulating layer 80 in the thickness direction T1 of the resonant cavity region 103.

[0104] In this embodiment, the second insulating layer 130 is located between the second region 802 of the first insulating layer 80 and the adhesive layer 60. The second insulating layer 130 is in direct contact with both the first conductive layer 50 and the adhesive layer 60. Specifically, the second insulating layer 130 includes a third region 1301 and a fourth region 1302. The side portion 32 of the second electrode 30 separates the third region 1301 and the fourth region 1302. The third region 1301 of the second insulating layer 130 overlaps with both the semiconductor stack 10 and the first conductive layer 50 in the thickness direction T1 of the resonant cavity region 103. The fourth region 1302 of the second insulating layer 130 overlaps with both the second region 802 of the first insulating layer 80 and the first insulating layer 80 in the thickness direction T1 of the resonant cavity region 103.

[0105] Please see Figure 7In this embodiment, the second insulating layer 130 has an optical thickness substantially equal to Nλ / 4, where λ is the peak wavelength of the radiation emitted by the resonant cavity region 103, and N is an odd positive integer. In this embodiment, λ is 940±10 nm. In another embodiment, λ is 905±10 nm. In another embodiment, λ is 850±10 nm. In another embodiment, the thickness of the second insulating layer 130 is between 300 nm and 400 nm (both inclusive). The semiconductor element includes a plurality of openings 1303 penetrating the second insulating layer 130. Each opening 1303 is directly located on one of the columnar structures 108. Each opening 1303 exposes a portion of the second semiconductor contact layer 105 of the corresponding columnar structure 108 below it. Specifically, in a top view of the second insulating layer 130, the shape of one or each opening 1303 is, but not limited to, annular.

[0106] Please see Figure 7 The first conductive layer 50 covers the second insulating layer 130 along the contour of the second insulating layer 130. Specifically, a portion of the first conductive layer 50 is located within an opening 1303 penetrating the second insulating layer 130 to directly contact the second semiconductor contact layer 105 of one or more pillar structures 108. The semiconductor element in this embodiment does not include the second conductive layer 70 located between the second reflective structure 102 and the adhesive layer 60 as in the first embodiment.

[0107] Please see Figure 7 In this embodiment, the semiconductor element includes a current-limiting layer 140 located in each pillar structure 108. Preferably, the current-limiting layer 140 is located within the second reflective structure 102. The current-limiting layer 140 includes a conductive portion 1401 and an insulating portion 1402, with the insulating portion 1402 surrounding the conductive portion 1401. The portion of the resonant cavity region 103 located directly below the conductive portion 1401 serves as the primary radiation emission region I, and the radiation emitted from the primary radiation emission region I dissipates from the substrate 40 to the outside of the semiconductor element through the hole 51 penetrating the first conductive layer 50.

[0108] The conductive portion 1401 contains a group III-V semiconductor material, which includes aluminum, such as Al. a Ga (1-a) As, where 0.9 ≤ a ≤ 1.0. The aluminum content in the conductive portion 1401 is higher than the aluminum content n of the first semiconductor layer and the aluminum content m of the second semiconductor layer in the first reflective structure 101 and the second reflective structure 102. For example, the conductive portion 1401 contains Al. a Ga 1-a As, where 0.9 ≤ a ≤ 0.99. The insulating portion 1402 comprises an oxide. Preferably, the insulating portion 1402 comprises aluminum oxide, which has an Al content.a O b The experimental formula is given, where a and b are natural numbers not containing zero. In this embodiment, the current limiting layer 140 is inserted into the second reflective structure 102 to be located between one of the first semiconductor layers and an adjacent second semiconductor layer. In another embodiment, in each columnar structure 108, one of the first semiconductor layers or one of the second semiconductor layers in the second reflective structure 102 is replaced by the current limiting layer 140. A plurality of holes 51 penetrating the first conductive layer 50 are located directly above the conductive portions 1401 of the corresponding current limiting layer 140. Preferably, the electrode pad portion 31 of the second electrode 30 does not overlap with the conductive portions 1401 of the columnar structure 108 in the thickness direction T1 of the resonant cavity region 103. In one embodiment, the electrode pad portion 31 of the second electrode 30 does not overlap with the plurality of holes 51 penetrating the first conductive layer 50 in the thickness direction T1 of the resonant cavity region 103. Each conductive portion 1401 has a width. Preferably, the width of one conductive portion 1401 is less than the fourth width W4 of the corresponding hole 51. Preferably, the width of one conductive portion 1401 is not less than 3 μm, and more preferably, not greater than 20 μm.

[0109] Figures 8A to 8I To manufacture such Figure 7 The method for using a semiconductor device according to the fourth embodiment shown. Figure 8A This is a top view after the formation of the second semiconductor contact layer 105. (See also...) Figure 8A Manufacturing such Figure 7 The method of creating a semiconductor device includes providing a growth substrate 100; and forming a semiconductor stack 10 as described in the first embodiment on the growth substrate 100 by epitaxial growth. The semiconductor stack 10 includes a second reflective structure 102, which includes a plurality of overlapping first semiconductor layers and second semiconductor layers as described in the first embodiment. This embodiment differs from the first embodiment in that, in this embodiment, the second reflective structure 102 includes a third semiconductor layer 1201 located between one of the first semiconductor layers and an adjacent second semiconductor layer. The third semiconductor layer 1201 has a third refractive index, which is less than the second refractive index of each of the second semiconductor layers. In one embodiment, the third semiconductor layer 1201 has a third aluminum content, which is higher than the second aluminum content of each of the second semiconductor layers. In this embodiment, the plurality of first semiconductor layers contain Al. n Ga (1-n) As, multiple second semiconductor layers contain Al m Ga (1-m) As, the third semiconductor layer 1201 contains Al f Ga (1-f) As, and f>m>n.

[0110] Figure 8B This is a top view after multiple columnar structures 108 have been formed. Figure 8C For along Figure 8B A sectional view of line A-A'. See also Figure 8B as well as Figure 8C Manufacturing such Figure 7 The method for creating the semiconductor device also includes removing portions of the semiconductor stack 10 by any suitable method to form a recess 120 and a plurality of columnar structures 108. The plurality of columnar structures 108 are separated from each other by the recess 120, each columnar structure 108 including an outer wall 1081, and preferably, the recess 120 exposes an upper surface of the first reflective structure 101.

[0111] Figure 8D A top view after the second insulating layer 130 has been formed. Figure 8E For along Figure 8D A sectional view of line A-A'. See also Figure 8D as well as Figure 8E Manufacturing such Figure 7 The method of the semiconductor device shown further includes oxidizing a third semiconductor layer 1201 to form a current limiting layer 140, the current limiting layer 140 including a conductive portion 1401 and an insulating portion 1402 surrounding the conductive portion 1401, the third semiconductor layer 1201 having a third aluminum content being oxidized starting from the outer wall 1081 exposed by the recess 120 to form the insulating portion 1402; forming a second insulating layer 130, the second insulating layer 130 covering one top surface of the second semiconductor contact layer 105 facing the substrate 40, covering the outer wall 1081 of the columnar structure 108 and covering an upper surface of the first reflective structure 101 exposed by the recess 120; and removing a portion of the second insulating layer 130 located on the columnar structure 108 to form a plurality of openings 1303, wherein the plurality of openings 1303 expose portions of the second semiconductor contact layer 105 thereunder.

[0112] Figure 8F This is a top view after the first conductive layer 50 has been formed. Figure 8G For along Figure 8F A sectional view of line A-A'. See also Figure 8F as well as Figure 8G Manufacturing such Figure 7The method for creating the semiconductor device further includes forming a current-conducting layer (not shown) on the second insulating layer 130 and within the opening 1303, the current-conducting layer directly contacting the second semiconductor contact layer 105; and patterning the current-conducting layer using a photolithographic mask to form a first conductive layer 50. After patterning the current-conducting layer, the semiconductor device includes a plurality of holes 51 penetrating the first conductive layer 50. Each hole 51 is located directly above a conductive portion 1401 of a current-limiting layer 140 of one of the columnar structures 108, and the exposed portion of the hole 51 is located beneath the second semiconductor contact layer 105.

[0113] Figure 8H This is a cross-sectional view after connecting substrate 40. Please refer to [link / reference]. Figure 8H Manufacturing such Figure 7 The method for creating a semiconductor device further includes providing a substrate 40; connecting the substrate 40 and the substrate 40 via an adhesive layer 60. Figure 8G The structure shown. A portion of the adhesive layer 60 is located within a plurality of holes 51 penetrating the first conductive layer 50.

[0114] Figure 8I This is a cross-sectional view after the first insulating layer 80 has been formed. See also... Figure 8I Manufacturing such Figure 7 The method of creating the semiconductor device further includes removing the growth substrate 100 by any suitable method; removing a peripheral portion of the semiconductor stack 10 to expose a portion of the second insulating layer 130 by any suitable method, such as inductively coupled plasma (ICP) or wet etching; removing a portion of the etch barrier layer 106 to expose a portion of the first semiconductor contact layer 104; forming a metal contact layer 90 in direct contact with the exposed portion of the first semiconductor contact layer 104, the metal contact layer 90 comprising an alloy, such as germanium-gold-nickel; and forming a first insulating layer 80 located on a top surface of the etch barrier layer 106 relative to the substrate 40, covering the sidewalls of the semiconductor stack 10 and covering the second insulating layer 130.

[0115] Manufacturing such as Figure 7 The method for creating a semiconductor device further includes simultaneously removing portions of a first insulating layer 80 and a portion of a second insulating layer 130, forming a first electrode 20, and forming a second electrode 30, for completing, as shown. Figure 7 The semiconductor element shown. Please refer to [link / reference]. Figure 7A portion of the first insulating layer 80 and a portion of the second insulating layer 130 are simultaneously removed to form a trench (not shown) exposing a portion of the first conductive layer 50, and a portion of the first insulating layer 80 located on the first semiconductor contact layer 104 is removed to simultaneously expose the etch stop layer 106 and the metal contact layer 90. In another embodiment, after removing the first insulating layer 80, the etch stop layer 106 may not be exposed, only the metal contact layer 90 may be exposed. In an incomplete cross-sectional view of the semiconductor device, the trench divides the first insulating layer 80 into a first region 801 and a second region 802, and divides the second insulating layer 130 into a third region 1301 and a fourth region 1302.

[0116] The first electrode 20 is in direct contact with the exposed portion of the metal contact layer 90. Preferably, the first electrode 20 is in direct contact with the exposed portion of the metal contact layer 90, the exposed portion of the etch stop layer 106, and a portion of the first insulating layer 80. The second electrode 30 is separated from the first electrode 20 and located on the first insulating layer 80. Specifically, the second electrode 30 covers the first region 801 of the first insulating layer 80, and a portion of its side portion 32 is located within a trench to directly contact the exposed portion of the first conductive layer 50. In other words, in a cross-sectional view of the semiconductor device, the side portion 32 of the second electrode 30 is located between the first region 801 and the second region 802 of the first insulating layer 80, and between the third region 1301 and a fourth region 1302 of the second insulating layer 130 to directly contact the exposed portion of the first conductive layer 50.

[0117] Figure 9 This is a cross-sectional view of a semiconductor device according to a fifth embodiment of the present invention. The semiconductor device of the fifth embodiment of the present invention comprises a structure substantially the same as that of the first embodiment, except that the metal contact layer 90 is located between the first insulating layer 80 and the semiconductor stack 10. Specifically, in a cross-sectional view of a semiconductor device, the metal contact layer 90 overlaps with all contact regions 1051 and holes 51 in the thickness direction T1 of the resonant cavity region 103.

[0118] Figure 10 This is a cross-sectional view of a semiconductor element according to a sixth embodiment of the present invention. The semiconductor element of the sixth embodiment of the present invention includes a structure substantially the same as that of the first embodiment, except that the second reflective structure 102 includes a platform structure 1021. Specifically, the second reflective structure 102 includes two different widths, one width being substantially equal to the second width W2 of the resonant cavity region 103, and the other width being greater than the second width W2 of the resonant cavity region 103.

[0119] Manufacturing such as Figure 10 The method for manufacturing a semiconductor device according to the sixth embodiment shown includes the following: Figure 1 as well as Figure 2 The methods for forming semiconductor devices are largely the same. The differences are described below. Figure 3E After the structure shown, manufacture as follows Figure 10 The method for creating a semiconductor device according to the sixth embodiment further includes removing the surrounding portion of the etch barrier layer 106, removing the surrounding portion of the first semiconductor contact layer 104, removing the surrounding portion of the first reflective structure 10, removing the surrounding portion of the resonant cavity region 103, and removing the bottom surrounding portion of the second reflective structure 102 to form a platform structure 1021; protecting the sidewalls 10331 of the resonant cavity region 103 with a protective layer; and further removing the top surrounding portion of the second reflective structure 102 and the surrounding portion of the second conductive layer 70 to expose the first conductive layer 50. In the step of removing the surrounding portion of the second conductive layer 70, a portion of the exposed first conductive layer 50 may be removed, causing the conductive material of the first conductive layer 50 to sputter, thereby leading to leakage current. By protecting the sidewalls 10331 of the resonant cavity region 103, the sputtering of the conductive material of the first conductive layer 50 to the sidewalls 1033 of the resonant cavity region 103 due to the removal of a portion of the exposed first conductive layer 50 can be mitigated or avoided, further mitigating or avoiding the leakage current problem of the semiconductor device.

[0120] Next, a portion of the etch barrier layer 106 is removed to form the first insulating layer 80, the first electrode 20, and the second electrode 30. See the preceding paragraphs for a related description.

[0121] Figure 11A This is a cross-sectional view of a semiconductor device according to a seventh embodiment of the present invention. The semiconductor device of the seventh embodiment of the present invention includes a structure substantially the same as that of the first embodiment, except that the semiconductor device of this embodiment includes an optical structure 150. The radiation emitted from the resonant cavity region 103 has a radiation pattern. The optical structure 150 can modify the radiation pattern. In one embodiment, the optical structure 150 can enlarge or reduce the size of the radiation pattern. In one embodiment, the optical structure 150 can modify the direction or shape of the radiation pattern. For example, the shape of the radiation pattern can be changed from circular to linear by the optical structure 150. In a cross-sectional view of the semiconductor device, the optical structure 150 includes a plurality of alternately arranged protrusions 1501 and a plurality of recesses 1502. In a cross-sectional view of the semiconductor device, the shape of one protrusion 1501 includes a rectangle, a triangle, or a semicircle. The shapes of the plurality of protrusions 1501 can be the same or different. In one embodiment, the optical structure 150 includes a Fresnel lens.

[0122] In one embodiment, from a top view of the optical structure 150, a plurality of protrusions 1501 and a plurality of recesses 1502 may be configured as a regular pattern with repeating units. In another embodiment, from a top view of the optical structure 150, a plurality of protrusions 1501 and a plurality of recesses 1502 may be configured as an irregular pattern. In this embodiment, in a cross-sectional view of the semiconductor element, the shape of each protrusion 1501 of the optical structure 150 includes a rectangle. In one embodiment, the height of one of the protrusions 1501 of the optical structure 150 is between 0.3 μm and 5 μm. In this embodiment, the height of one of the protrusions 1501 of the optical structure 150 is between 0.5 μm and 1.5 μm. The heights of the plurality of protrusions 1501 may be the same or different. In this embodiment, the heights of the plurality of protrusions 1501 are substantially the same.

[0123] Please see Figure 11A Specifically, substrate 40 includes a first side 46 and a second side 47 opposite to the first side 46. The first side 46 is closer to the semiconductor stack 10 than the second side 47. The first side 46 and the second side 47 are close to the first surface 42, the second surface 43, the third surface (not shown), and the fourth surface (not shown). The second side 47 includes a top surface 41. In this embodiment, optical structure 150 is located on the second side 47. Specifically, a portion of substrate 40 is removed to form optical structure 150. The optical structure overlaps with one or more principal radiation emission regions I in the thickness direction T1 of the resonant cavity region 103. In this embodiment, optical structure 150 overlaps with all principal radiation emission regions I in the thickness direction T1 of the resonant cavity region 103. In this embodiment, radiation escapes from substrate 40 to outside the semiconductor element through optical structure 150.

[0124] Figure 11B This is a cross-sectional view of a semiconductor element according to the eighth embodiment of the present invention. The semiconductor element of the eighth embodiment of the present invention includes a structure substantially the same as that of the seventh embodiment, except that the optical structure 150 is located on the first side 46. In this embodiment, the optical structure 150 is in direct contact with the adhesive layer 60. Specifically, a plurality of protrusions 1501 of the optical structure 150 are in direct contact with the adhesive layer 60. In one embodiment, a plurality of recesses 1502 may be filled with air or other materials different from the substrate 40. Preferably, radiation emitted from the resonant cavity region 103 can penetrate the material filling the plurality of recesses 1502. In one embodiment, the material filling the plurality of recesses 1502 is the same as the material of the adhesive layer 60. If the material filling the plurality of recesses 1502 is the same as the material of the adhesive layer 60, there is no boundary between the plurality of recesses 1502 and the adhesive layer 60.

[0125] Figure 11CThis is a cross-sectional view of a semiconductor element according to the ninth embodiment of the present invention. The semiconductor element of the ninth embodiment of the present invention comprises a structure substantially the same as that of the seventh embodiment, except that the semiconductor element in this embodiment includes two optical structures 150. One optical structure 150 is located on a first side 46, and the other optical structure 150 is located on a second side 47. In a cross-sectional view of the semiconductor element, the shapes of the two optical structures 150 may be the same or different. Specifically, in a cross-sectional view of the semiconductor element, the shape of any protrusion 1501 of one optical structure 150 may be the same or different from the shape of any protrusion 1501 of the other optical structure 150. In this embodiment, in a cross-sectional view of the semiconductor element, the shape of any protrusion 1501 of the optical structure 150 located on the first side 46 is rectangular. In a cross-sectional view of the semiconductor element, the shape of each protrusion 1501 of the optical structure 150 located on the second side 47 is rectangular. The radiation emitted from the resonant cavity region 103 has a radiation pattern. Radiation escapes from the substrate 40 to the outside of the semiconductor device, and the radiation pattern can be changed by the optical structure 150 located on the first side 46, and then by the optical structure 150 located on the second side 47.

[0126] Figure 12A This is a cross-sectional view of a semiconductor element according to the tenth embodiment of the present invention. The semiconductor element of the tenth embodiment of the present invention comprises a structure substantially the same as that of the seventh embodiment, except that, in a cross-sectional view of the semiconductor element, the shape of the plurality of protrusions 1501 differs from that of the seventh embodiment. Figure 11A The shape shown is shown in the figure. In this embodiment, in a cross-sectional view of the semiconductor element, each protrusion 1501 is triangular in shape.

[0127] Figure 12B This is a cross-sectional view of a semiconductor element according to the eleventh embodiment of the present invention. The semiconductor element of the eleventh embodiment of the present invention comprises a structure substantially the same as that of the eighth embodiment, except that, in a cross-sectional view of the semiconductor element, the shape of the plurality of protrusions 1501 differs from that of the eighth embodiment. Figure 11B The shape shown is shown in the figure. In this embodiment, in a cross-sectional view of the semiconductor element, each protrusion 1501 is triangular in shape.

[0128] Figure 12C This is a cross-sectional view of a semiconductor device according to the twelfth embodiment of the present invention. The semiconductor device of the twelfth embodiment of the present invention comprises a structure substantially the same as that of the ninth embodiment, except that, in a cross-sectional view of the semiconductor device, the shape of the plurality of protrusions 1501 differs from that of the previous embodiment. Figure 11CThe shapes shown are as follows. In this embodiment, in a cross-sectional view of the semiconductor element, each protrusion 1501 of the optical structure 150 located on the second side 47 is triangular in shape. In a cross-sectional view of the semiconductor element, each protrusion 1501 of the optical structure 150 located on the first side 46 is triangular in shape.

[0129] Figure 13A This is a cross-sectional view of a semiconductor device according to the thirteenth embodiment of the present invention. The semiconductor device of the thirteenth embodiment of the present invention comprises a structure substantially the same as that of the seventh embodiment, with the differences described below. The second side 47 of the substrate 40 includes a top surface 41. An optical structure 150 is formed on the top surface 41. In this embodiment, in a cross-sectional view of the semiconductor device, the optical structure 150 includes a plurality of protrusions 1501 protruding from the top surface 41. In a cross-sectional view of the semiconductor device, the shapes of the plurality of protrusions 1501 differ from... Figure 11A The shape shown is illustrated. In this embodiment, each protrusion 1501 is semi-circular. In one embodiment, the material of the optical structure 150 is different from the material of the substrate 40. The material of the optical structure 150 includes silicon, quartz, silicon dioxide, or calcium fluoride (CaF2).

[0130] Figure 13B This is a cross-sectional view of a semiconductor element according to the fourteenth embodiment of the present invention. The semiconductor element of the fourteenth embodiment of the present invention comprises a structure substantially the same as that of the eighth embodiment, except that, in a cross-sectional view of the semiconductor element, the shape of the plurality of recesses 1502 differs from that of the previous embodiment. Figure 11B The shape shown is shown in the figure. In this embodiment, in a cross-sectional view of the semiconductor element, each recess 1502 is semi-circular in shape.

[0131] Figure 13C This is a cross-sectional view of a semiconductor element according to the fifteenth embodiment of the present invention. The semiconductor element of the fifteenth embodiment of the present invention comprises a structure substantially the same as that of the thirteenth embodiment, except that the semiconductor element of this embodiment includes two optical structures 150. One semiconductor element 150 is located on a first side 46, and the other optical structure 150 is located on the top surface 41 of a second side 47. In this embodiment, in a cross-sectional view of the semiconductor element, each protrusion 1501 of the optical structure 150 located on the first side 46 is semi-circular in shape. In a cross-sectional view of the semiconductor element, each recess 1502 of the optical structure 150 located on the top surface 41 of the second side 47 is semi-circular in shape.

[0132] Figure 14This is a cross-sectional view of a semiconductor element according to the sixteenth embodiment of the present invention. The semiconductor element of the sixteenth embodiment of the present invention comprises a structure substantially the same as that of the fourteenth embodiment, with the differences described below. The semiconductor element further includes an optical element 160 connected to a second side 47 of a substrate 40. In this embodiment, the second side 47 of the substrate 40 includes a top surface 41 relative to the semiconductor stack 10. The optical element 160 is located on the top surface 41 of the second side 47 of the substrate 40. The optical element 160 includes a third side 1601, a fourth side 1602, and an optical structure 150 as previously disclosed. The third side 1601 is closer to the substrate 40 than the fourth side 1602. The optical structure 150 is located on the fourth side 1602. In this embodiment, the material of the optical element 160 is different from the material of the substrate 40. Preferably, radiation emitted from the resonant cavity region 103 is substantially permeable to the material of the optical element 160. In one embodiment, the material of the optical element 160 includes silicon, quartz, silicon dioxide, or calcium fluoride (CaF2). Radiation escapes from the substrate 40 to the semiconductor element through the optical element 160, and the radiation pattern can be altered by the optical element 160 and the optical structure 150 of the substrate 40. In another embodiment, the optical element 160 is located between the substrate 40 and the semiconductor stack 10.

[0133] Figure 15 This is a cross-sectional view of a semiconductor element according to the seventeenth embodiment of the present invention. The semiconductor element of the seventeenth embodiment of the present invention includes a structure substantially the same as that of the first embodiment, except that the second electrode 30 does not contain the electrode pad portion 31 disclosed in the first embodiment. In this embodiment, the first electrode 20 and the second electrode 30 are located on the same side of the first conductive layer 50.

[0134] The present invention also provides a semiconductor package (not shown). The semiconductor package includes one of the semiconductor elements as disclosed in the first to sixth embodiments. The semiconductor package further includes an optical element 160 as disclosed in the sixteenth embodiment. The optical element 160 is separated from the semiconductor element, and the distance between the two is not less than 200 μm. In one embodiment, the semiconductor package further includes a first lens (not shown) located between the optical element 160 and the semiconductor package. In another embodiment, the optical element 160 is located between the first lens and the semiconductor package. In one embodiment, the semiconductor package further includes a second lens (not shown). The first lens and the second lens are located on opposite sides of the optical element 160, and the first lens or the second lens is located between the optical element 160 and the semiconductor element.

[0135] Another embodiment of the present invention is based on a combination or modification of the structures in the foregoing embodiments. For example, in one embodiment, Figure 7The semiconductor device shown may include, for example: Figure 10 The platform structure shown is 1021.

[0136] In another embodiment of the present invention, the adhesive layer 60 comprises a transparent conductive oxide, a metal, an insulating oxide, or a polymer. The transparent conductive oxide comprises indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), zinc aluminum oxide (AZO), zinc tin oxide (ZTO), zinc gallium oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO), or indium zinc oxide (IZO). The metal comprises indium, tin, gold, platinum, tungsten, titanium, aluminum, nickel, or alloys thereof. The insulating oxide comprises aluminum oxide (AlO). x ), silicon dioxide (SiO) x ) or silicon oxynitride (SiO) x N y The polymeric materials include epoxy resin, polyimide, perfluorocyclobutane, benzocyclobutene (BCB), or silicone. In one embodiment, if the adhesive layer 60 is made of a metal, its thickness can be thin enough for radiation emitted from the resonant cavity region 103 to penetrate. In one embodiment, if the adhesive layer 60 is made of a transparent conductive oxide, the adhesive layer 60 has a thickness between 400 nanometers and 5000 nanometers.

[0137] According to another embodiment of the present invention, the second conductive layer 70 has an optical thickness substantially equal to Nλ / 4, where λ is the peak wavelength of the radiation emitted from the resonant cavity region 103, and N is an odd positive integer. In one embodiment, the second conductive layer 70 comprises a transparent conductive oxide, including indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), zinc aluminum oxide (AZO), zinc tin oxide (ZTO), zinc gallium oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO), or indium zinc oxide (IZO). In one embodiment, the second conductive layer 70 comprises graphene. The radiation emitted from the resonant cavity region 103 can penetrate the second conductive layer 70.

[0138] In another embodiment of the present invention, the substrate 40 has a sufficient thickness to support layers or structures on the substrate 40. The thickness of the substrate 40 is, for example, not less than 50 μm, and preferably not more than 250 μm, and more preferably not more than 200 μm. In this embodiment, the thickness of the substrate 40 is between 80 μm and 120 μm. In one embodiment, the substrate 40 comprises a conductive material, such as silicon. In another embodiment, radiation emitted from the resonant cavity region 103 can penetrate the substrate 40. In one embodiment, the substrate 40 comprises aluminum oxide or aluminum nitride.

[0139] In another embodiment of the present invention, the growth substrate 100 provides an upper surface for epitaxially growing a semiconductor stack 10. The growth substrate 100 has a sufficient thickness to support layers or structures subsequently grown on it. Preferably, the thickness of the growth substrate 100 is not less than 100 micrometers, and more preferably, not more than 250 micrometers. The growth substrate 100 is a single crystal and contains a semiconductor material, for example, a group III-V semiconductor material or a group IV semiconductor material. In one embodiment, the growth substrate 100 contains a group III-V semiconductor material having an n-type or p-type structure. In this embodiment, the group III-V semiconductor material contains n-type gallium arsenide (GaAs), and the n-type dopant is silicon (Si).

[0140] According to another embodiment of the present invention, the multiple quantum well structure includes overlapping well layers and barrier layers. The energy level of each barrier layer is greater than the energy level of one of the well layers. The peak wavelength of the radiation emitted by the resonant cavity region 103 can be changed by altering the thickness or material of the well layers. Preferably, the material of the well layers comprises a group III-V semiconductor material, such as aluminum gallium arsenide (AlGaAs). The material of the barrier layers comprises a group III-V semiconductor material, such as aluminum gallium arsenide (AlGaAs). The resonant cavity region 103 may further include a spacer layer located between the multiple quantum well structure and the first reflective structure 101 and / or between the multiple quantum well structure and the second reflective structure 102, for adjusting the thickness of the resonant cavity region 103 to approximately approach or equal to a thickness of N'λ / 2, where λ is the peak wavelength of the radiation emitted by the resonant cavity region 103, and N' is a positive integer. The spacer layer material comprises a group III-V semiconductor material, such as aluminum gallium arsenide (AlGaAs).

[0141] According to another embodiment of the present invention, the second semiconductor contact layer 105 is p-type. The second semiconductor contact layer 105 has a dopant with a doping concentration of not less than 10. 18 / cm 3 And preferably, not less than 10 19 / cm 3 And more preferably, between 1×10 19 / cm 3 and 5×1022 / cm 3 Between (both). The material of the second semiconductor contact layer 105 comprises a group III-V semiconductor material, such as gallium arsenide (GaAs) or aluminum gallium arsenide (AlGaAs). The P-type dopant is magnesium (Mg), carbon (C), or zinc (Zn).

[0142] In another embodiment of the present invention, the first semiconductor contact layer 104 is n-type. The first semiconductor contact layer 104 has dopants with a doping concentration of not less than 10. 18 / cm 3 And preferably, not less than 10 19 / cm 3 And more preferably, between 1×10 19 / cm 3 and 5×10 22 / cm 3 Between (both). The material of the first semiconductor contact layer 104 comprises a group III-V semiconductor material, such as gallium arsenide (GaAs) or aluminum gallium arsenide (AlGaAs). The n-type dopant is silicon (Si) or antimony (Te).

[0143] According to another embodiment of the present invention, the first insulating layer 80 and the second insulating layer 130 comprise an insulating material, the insulating material comprising aluminum oxide (Al₂O₃). x ), silicon dioxide (SiO) x Silicon nitride (Si) x N y ), silicon oxynitride (SiO) x N y The materials used are epoxy resin, polyimide, perfluorocyclobutane, benzocyclobutene (BCB), or silicone. In one embodiment, the material of the first insulating layer 80 may be the same as the material of the second insulating layer 130. In another embodiment, the material of the first insulating layer 80 may be different from the material of the second insulating layer 130.

[0144] In another embodiment of the present invention, the etch barrier layer 106 comprises a group III-V semiconductor material. The etch barrier layer 106 can be removed by an etchant. The etchant has a first etch rate for the material of the etch barrier layer 106 and a second etch rate for the material of the first semiconductor contact layer 104. The first etch rate differs from the second etch rate. Preferably, the second etch rate is greater than the first etch rate. For example, the first semiconductor contact layer 104 comprises GaAs, and the etch barrier layer 106 comprises InGaP. The etch barrier layer 106 has a dopant with a doping concentration, the doping concentration of the dopant in the etch barrier layer 106 being less than the doping concentration of the dopant in the first semiconductor contact layer 104. Specifically, the doping concentration of the dopant in the first semiconductor contact layer 104 is at least twice the doping concentration of the dopant in the etch barrier layer 106.

[0145] According to another embodiment of the present invention, the first electrode 20 and the second electrode 30 are used to connect to an external power source and conduct current between them. The materials of the first electrode 20, the first conductive layer 50, and the second electrode 30 comprise transparent conductive oxides or metals. Transparent conductive oxides include indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO), or indium zinc oxide (IZO). Metals include indium, tin, gold, platinum, tungsten, titanium, aluminum, nickel, or alloys thereof. Preferably, the first conductive layer 50 comprises a metal.

[0146] According to another embodiment of the present invention, the measurement directions of the first width W1, the second width W2, the third width W3, the fourth width W4, the first distance D1, the second distance D2, the third distance D3, the maximum width of the metal contact layer, the maximum width of the first electrode 20, and the width of each conductive region 107 are generally perpendicular to the thickness direction T1 of the resonant cavity region 103. The measurement directions of the heights of the plurality of protrusions 1501 of the optical structure 150 are generally parallel to the thickness direction T1 of the resonant cavity region 103.

[0147] According to another embodiment of the present invention, the radiation comprises light. In one embodiment, the light may be visible light. Preferably, the light has a peak wavelength between 580 nm and 730 nm. In another embodiment, the light may be invisible light. Preferably, the light has a peak wavelength between 730 nm and 1600 nm, and more preferably, a peak wavelength between 800 nm and 1000 nm.

[0148] In one embodiment, the current-limiting layer 140 is separated from the resonant cavity region 103 by a pair of first semiconductor layers and an adjacent second semiconductor layer. In another embodiment, the current-limiting layer 140 is separated from the resonant cavity region 103 by two pairs of first semiconductor layers and an adjacent second semiconductor layer. In yet another embodiment, the current-limiting layer 140 is in direct contact with the resonant cavity region 103.

[0149] In one embodiment, the resonant cavity region 103 further includes a first conductivity layer and a second conductivity layer. The first conductivity layer and the second conductivity layer are located on both sides of the active region. Each of the first conductivity layer and the second conductivity layer has an energy level that is greater than the energy level of one of the barrier layers. Specifically, the energy levels of the first conductivity layer and the second conductivity layer are lower than the energy level of the conductive portion 1401 of the current limiting layer 140.

[0150] In this embodiment, the semiconductor element can be flip-chip bonded to a support substrate containing circuitry, and most of the light will escape from the semiconductor element through the substrate 40.

[0151] Semiconductor components can be used in applications such as proximity sensors, night vision systems, blood oxygen detectors, or data transmission.

[0152] Epitaxial methods include, but are not limited to, metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), or liquid-phase epitaxy (LPE).

[0153] It should be noted that the embodiments listed in this invention are only illustrative and not intended to limit the scope of the invention. Any obvious modifications or alterations made to this invention do not depart from its spirit and scope. Components that are the same or similar in different embodiments, or components with the same reference numerals in different embodiments, have the same physical or chemical properties. Furthermore, the embodiments described above can be combined or substituted with each other where appropriate, and are not limited to the specific embodiments described. The connection relationships between specific components and other components described in detail in one embodiment can also be applied to other embodiments, and all fall within the scope of protection of the appended claims of this invention.

Claims

1. A semiconductor element comprising: substrate; A semiconductor stack is located on the substrate and includes a first reflective structure, a second reflective structure, and a resonant cavity region located between the first reflective structure and the second reflective structure, wherein the semiconductor stack includes a first surface and a second surface opposite to the first surface; The first electrode is located on the first surface and is electrically connected to the first reflective structure; The second electrode includes an electrode pad portion and a side portion extending from the electrode pad portion. The electrode pad portion is located on the first surface and the side portion covers the sidewall of the resonant cavity region. The second electrode is electrically connected to the second reflective structure. A conductive layer is located on the second surface and between the substrate and the semiconductor stack; Conductive regions are formed within the semiconductor stack; as well as An insulating region is formed within the semiconductor stack and surrounds the conductive region; A hole, penetrating the conductive layer; Wherein, the insulating region overlaps with the conductive layer in the thickness direction of the resonant cavity region but not with the hole; and The resonant cavity region can emit radiation, and the radiation escapes from the substrate to the outside of the semiconductor device through the hole.

2. The semiconductor element according to claim 1, wherein The substrate includes a first side surface, and the first electrode or the second electrode does not cover the first side surface.

3. The semiconductor device according to claim 1, wherein The electrode pad overlaps with the first and second reflective structures in the thickness direction of the resonant cavity region.

4. The semiconductor device as claimed in claim 3, wherein, The first reflective structure has a side surface, and the side portion covers the side surface.

5. The semiconductor device of claim 3, further comprising an insulating layer located between the second electrode and the sidewall of the resonant cavity region, wherein in a cross-sectional view, the insulating layer comprises a first region and a second region separated from the first region, and the side portion of the second electrode is located between the first region and the second region.

6. The semiconductor device as claimed in claim 5, wherein, The conductive layer overlaps with the insulating layer in the thickness direction of the resonant cavity region.

7. The semiconductor device as claimed in claim 1, wherein, The conductive layer has a surface facing the semiconductor stack, and the second electrode is in direct contact with the surface.

8. The semiconductor device as claimed in claim 1, wherein, The substrate includes a first side surface and a second side surface relative to the first side surface, and a sidewall of the resonant cavity region. The sidewall has a first portion and a second portion relative to the first portion. The first portion of the sidewall is closer to the second electrode and is a first distance away from the first side surface of the substrate. The second portion of the sidewall is closer to the first electrode and is a second distance away from the second side surface of the substrate. The first distance is different from the second distance.

9. The semiconductor device of claim 1, wherein the first reflective structure and the second reflective structure comprise a distributed Bragg reflector.

10. The semiconductor device of claim 1, wherein, The conductive layer extends beyond the sidewall of the resonant cavity region.

11. The semiconductor device as claimed in claim 1, wherein, The semiconductor stack also includes a semiconductor contact layer located between the first electrode and the first reflective structure.

12. The semiconductor device of claim 1, wherein the first electrode includes a first outer surface, the electrode pad portion of the second electrode includes a second outer surface, and the height difference between the first outer surface and the second outer surface is not greater than 5 micrometers.

13. The semiconductor element of claim 1, further comprising an optical structure, wherein the optical structure is located on one side of the substrate.

14. The semiconductor device of claim 13, wherein, The optical structure includes multiple alternating protrusions and multiple recesses.

15. The semiconductor device of claim 14, wherein, The height of one of the multiple protrusions is between 0.3 micrometers and 5 micrometers.

16. The semiconductor device of claim 1, further comprising: Grooves are formed within the semiconductor stack to create multiple columnar structures that are separated from each other.

17. The semiconductor element of claim 16, further comprising an insulating layer covering the groove and the columnar structures, the insulating layer having an opening that overlaps with the insulating region in the thickness direction of the resonant cavity region.

18. The semiconductor device of claim 17, wherein, The width of the opening is smaller than the width of the insulating area.

19. The semiconductor device of claim 13, wherein, In the thickness direction of the resonant cavity region, the optical structure overlaps with the hole.

20. The semiconductor device of claim 1, further comprising an adhesive layer filled within the cavity.

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