Impedance control circuit

Abstract

The impedance control circuit includes a configuration channel interface, a first resistor, a first transistor, a second transistor, a second resistor, and a third resistor. The configuration channel interface is coupled to a universal serial bus device. A first end of the first resistor is coupled to the configuration channel interface. A first end of the first transistor is coupled to a second end of the first resistor, and a second end of the first transistor is coupled to a system voltage terminal. A first end of the second transistor is coupled to the second end of the first resistor, and a second end of the second transistor is coupled to the system voltage terminal. A first end of the second resistor is coupled to the second end of the first resistor, and a second end of the second resistor is coupled to a control terminal of the second transistor. A first end of the third resistor is coupled to the second end of the second resistor, and a second end of the third resistor is coupled to the system voltage terminal.

Description

Technical Field

[0001] This invention relates to an impedance control circuit, and more particularly to an impedance control circuit capable of controlling impedance to enable Universal Serial Bus devices to confirm connection status. Background Technology

[0002] The Type-C Universal Serial Bus (USB) has been widely used in various electronic devices due to its symmetrical, foolproof structure and ability to support a variety of data transmission applications. Figure 1 This is a schematic diagram of the configuration channel (CC) connection when electronic devices A1 and A2 are connected via a C-type universal serial bus in the prior art.

[0003] exist Figure 1 In this configuration, electronic device A1 acts as a Downstream Face Port (DFP) on the Universal Serial Bus (USB), while electronic device A2 acts as an Upstream Face Port (UFP). In this setup, electronic device A1 couples resistor Rp1 to its configuration channel interface CCP1, while electronic device A2 couples resistor Rd2 to its configuration channel interface CCP2. Furthermore, electronic device A1 applies an operating voltage VDD (e.g., 3.3V) to one end of resistor Rp1 and monitors the voltage at configuration channel interface CCP1. If configuration channel interface CCP2 provides a matching impedance, the voltage drop across resistors Rp1 and Rd2 will cause the voltage at configuration channel interface CCP1 to fall within a predetermined range. At this point, electronic device A1 determines that electronic device A2 is coupled to it via the USB and begins supplying power to electronic device A2 through the USB.

[0004] However, since both electronic devices A1 and A2 may be used as downlink or uplink data connection ports, the configuration channel interface CCP1 of electronic device A1 may also be coupled to resistor Rd1, and the configuration channel interface CCP2 may be coupled to resistor Rp2. In the prior art, since electronic device A1 only supplies power to electronic device A2 after confirming that electronic device A2 is coupled to electronic device A1, if electronic device A2 previously did not couple resistor Rd2 to configuration channel interface CCP2, but instead coupled resistor Rp2 to configuration channel interface CCP2, then electronic device A2 will not be able to switch resistors without receiving power. As a result, electronic device A1 will determine that electronic device A2 is not coupled to electronic device A1, making electronic device A2 undetectable and creating a system deadlock. Summary of the Invention

[0005] One embodiment of the present invention provides an impedance control circuit, the impedance control circuit including a configuration channel interface, a first resistor, a first transistor, a second transistor, a second resistor, and a third resistor.

[0006] The configuration channel interface is coupled to a Universal Serial Bus (USB) device. A first resistor has a first terminal and a second terminal, with the first terminal coupled to the configuration channel interface. A first transistor has a first terminal, a second terminal, and a control terminal; the first terminal of the first transistor is coupled to the second terminal of the first resistor, and the second terminal of the first transistor is coupled to a system voltage terminal. A second transistor has a first terminal, a second terminal, and a control terminal; the first terminal of the second transistor is coupled to the second terminal of the first resistor, and the second terminal of the second transistor is coupled to a system voltage terminal. A second resistor has a first terminal and a second terminal; the first terminal of the second resistor is coupled to the second terminal of the first resistor, and the second terminal of the second resistor is coupled to the control terminal of the second transistor. A third resistor has a first terminal and a second terminal; the first terminal of the third resistor is coupled to the second terminal of the second resistor, and the second terminal of the third resistor is coupled to a system voltage terminal. Attached Figure Description

[0007] Figure 1 This is a connection diagram of the configuration channel when connected via a C-type universal serial bus in the prior art.

[0008] Figure 2 This is a schematic diagram of an impedance control circuit according to an embodiment of the present invention.

[0009] Figure 3 This is a schematic diagram of a negative pressure generating circuit according to an embodiment of the present invention. Detailed Implementation

[0010] Figure 2This is a schematic diagram of an impedance control circuit 100 according to an embodiment of the present invention. The impedance control circuit 100 includes a configuration channel interface 110, a resistor R1, a transistor M1, a transistor M2, a resistor R2, and a resistor R3. In some embodiments, the impedance control circuit 100 may be disposed in a Universal Serial Bus (USB) device U2. When USB device U2 is coupled to USB device U1, the configuration channel interface 110 may be coupled to the configuration channel interface of USB device U1 and may provide a matching impedance, enabling USB device U1 to confirm that USB device U2 is connected to USB device U1 and perform subsequent operations.

[0011] exist Figure 2 In the configuration, resistor R1 has a first terminal and a second terminal, and the first terminal of resistor R1 can be coupled to the configuration channel interface 110. Transistor M1 has a first terminal, a second terminal, and a control terminal, and the first terminal of transistor M1 can be coupled to the second terminal of resistor R1, while the second terminal of transistor M1 can be coupled to the system voltage terminal VSS. Transistor M2 has a first terminal, a second terminal, and a control terminal, and the first terminal of transistor M2 can be coupled to the second terminal of resistor R1, while the second terminal of transistor M2 can be coupled to the control terminal of transistor M2. Resistor R3 has a first terminal and a second terminal, and the first terminal of resistor R3 can be coupled to the second terminal of resistor R2, while the second terminal of resistor R3 can be coupled to the system voltage terminal VSS.

[0012] Furthermore, in some embodiments, the threshold voltage of transistor M1 can be negative, while the threshold voltage of transistor M2 can be positive. That is, transistor M1 can be turned on even when no specific voltage is received at the control terminal, while transistor M2 will remain off when no specific voltage is received at the control terminal. Thus, when the Universal Serial Bus device U1 is coupled to the resistive channel interface 110 of the impedance control circuit 100, if the Universal Serial Bus device U1 has applied an operating voltage VDD to one end of its internal resistor Rp1, the configuration channel interface 110 of the impedance control circuit 100 will be in a corresponding voltage division state, such as a first voltage V1, based on the resistor Rp1 and its own internal impedance. In some embodiments, the operating voltage VDD can be, for example, but not limited to, 3.3 volts (V), the resistance of resistor R1 can be, for example, but not limited to, 5.1 kΩ, and the resistance of resistor Rp1 can be, for example, but not limited to, 36 kΩ. In this case, the first voltage V1 is approximately 0.4 volts. At this time, transistor M1 will be turned on while transistor M2 will be turned off. Therefore, through resistor R1 and transistor M1, the channel interface 110 can provide an impedance close to that of resistor R1.

[0013] However, in some embodiments, Universal Serial Bus (USB) device U1 may use different pull-up resistors to determine whether USB device U2 is matched in order to provide different power supply modes. For example, according to the USB Association, when providing a preset power supply mode, USB device U1 can use a 36K ohm resistor, and if the voltage of the configuration channel interface 110 is detected to be between 0.25 volts and 1.5 volts, then USB device U2 is considered a matched device. When the provided power supply mode is 5 volts and 1.5 amps (A), USB device U1 may use a 12K ohm resistor Rp1, and if the voltage of the configuration channel interface 110 is detected to be between 0.45V and 1.5V, then USB device U2 is considered a matched device. In addition, when the provided power mode is 5 volts and 3 amps, Universal Serial Bus device U1 may use a 4.7K ohm resistor Rp1, while if the voltage of the configuration channel interface 110 is detected to be between 0.85V and 2.45V, it indicates that Universal Serial Bus device U2 is a matched device.

[0014] In this scenario, when the Universal Serial Bus device U1 uses a smaller resistor Rp1, such as 12K ohms or 4.7K ohms, the configuration channel interface 110 will be at a higher second voltage V2 because the resistance values ​​of Rp1 and R1 are relatively close. At this time, transistor M1 will enter reverse saturation or be close to cutoff. However, because the second voltage V2 is higher, the voltage divider VD1 provided between resistors R2 and R3 can turn on transistor M2. Thus, through resistor R1 and transistor M2, the configuration channel interface 110 can still provide an impedance close to that of resistor R1.

[0015] In some embodiments, to avoid resistors R2 and R3 affecting the impedance provided by the configuration channel interface 110, resistors R2 and R3 with relatively large resistance values ​​can be selected. For example, the resistance values ​​of resistors R2 and R3 can be more than ten times greater than the resistance value of resistor R1. In some embodiments, resistors R2 and R3 can be, but are not limited to, 500K ohms.

[0016] Through the impedance control circuit 100, when the Universal Serial Bus (USB) device U2 has not yet received power, it can automatically turn on transistor M1 or transistor M2 to provide a stable impedance based on the voltage at the configuration channel interface 110, allowing USB device U1 to successfully confirm its connection status with USB device U2. For example, when USB device U1 detects that the voltage at the configuration channel interface 110 is within a predetermined range specified by the USB device, USB device U1 can confirm the connection relationship and provide power to USB device U2 via the bus power interface.

[0017] In some embodiments, after the Universal Serial Bus device U1 begins supplying power to the Universal Serial Bus device U2, the impedance control circuit 100 must switch to providing a high impedance to facilitate subsequent operations. Figure 2 In some embodiments, the impedance control circuit 100 may further include a negative voltage generating circuit 120 and a transistor M3. The negative voltage generating circuit 120 may be coupled to the control terminal of transistor M1 and may generate a negative voltage to the control terminal of transistor M1 according to the first enable signal EN1 to turn off transistor M1. Transistor M3 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor M3 may be coupled to the control terminal of transistor M2, the second terminal of transistor M3 may be coupled to the system voltage terminal VSS, and the control terminal of transistor M3 may receive a second enable signal EN2. In some embodiments, when the control terminal of transistor M3 receives the second enable signal EN2, transistor M3 will be turned on, and at this time the control terminal of transistor M2 will be coupled to the system voltage terminal VSS, so that transistor M2 is turned off.

[0018] In other words, when the Universal Serial Bus (USB) device U2 receives power from the USB device U1, it generates a first enable signal EN1 and a second enable signal EN2 to turn off transistors M1 and M2. Thus, after the USB device U2 receives power from the USB device U1, the impedance control circuit 100 can provide high impedance at the configuration channel interface 110 to facilitate subsequent operations. In some embodiments, the first enable signal EN1 and the second enable signal EN2 can be different signals generated by the same circuit, the same signal, or different signals generated by different circuits.

[0019] Figure 3 This is a schematic diagram of a negative pressure generating circuit 120 according to an embodiment of the present invention. Figure 3 In the circuit, the negative voltage generating circuit 120 may include an oscillator 122, a capacitor C1, a diode D1, a capacitor C2, and a diode D2. The oscillator 122 generates a clock signal CLK according to a first enable signal EN1. Capacitor C1 has a first terminal and a second terminal; the first terminal of capacitor C1 can receive the clock signal CLK. Diode D1 has an anode and a cathode; the anode of diode D1 can be coupled to the second terminal of capacitor C1, and the cathode of diode D1 can be coupled to the system voltage terminal VSS. Diode D2 has an anode and a cathode; the anode of diode D2 can be coupled to the control terminal of transistor M1, and the cathode of diode D2 can be coupled to the second terminal of capacitor C1. Capacitor C2 has a first terminal and a second terminal; the first terminal of capacitor C2 can be coupled to the anode of diode D2, and the second terminal of capacitor C2 can be coupled to the system voltage terminal VSS.

[0020] In this scenario, when the clock signal CLK is high, capacitor C1 is charged, causing its first terminal to be at a high potential, while the second terminal is held at a voltage close to the system voltage VSS due to diode D1. Then, when the clock signal CLK goes low, the second terminal of capacitor C1 becomes negative, at which point diode D2 conducts, pulling the first terminal of capacitor C2 down to a negative voltage. Thus, as the clock signal CLK continuously alternates between high and low potentials, a negative voltage is generated at the control terminal of transistor M1, causing transistor M1 to turn off.

[0021] In addition, Figure 3 In some embodiments, the negative voltage generating circuit 120 may further include a signal buffer 124. The signal buffer 124 may be coupled between the oscillator 122 and the capacitor C1, and may receive and output a clock signal CLK. However, in some embodiments, if the oscillator 122 can provide a clock signal CLK with sufficient driving capability, the signal buffer 124 may be omitted. Furthermore, the present invention is not limited to using... Figure 3The structure shown is used to implement the negative pressure generating circuit 120. In some other embodiments, the negative pressure generating circuit 120 may also be implemented with other structures or including other components, depending on the needs of the system.

[0022] In summary, the impedance control circuit provided by the embodiments of the present invention can provide a stable impedance at the configured channel interface without receiving an external power supply. In this way, regardless of the power configuration used by the Universal Serial Bus (USB) device coupled to the impedance control circuit, the USB device can successfully confirm the connection and begin providing power.

[0023] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the scope of the claims of the present invention shall fall within the scope of the present invention.

[0024] Explanation of reference numerals in the attached figures:

[0025] A1, A2, U1, U2: Universal Serial Bus devices

[0026] VDD: Operating voltage

[0027] Rp1, Rp2, Rd2, R1, R2, R3: Resistors

[0028] 100: Impedance control circuit

[0029] CCP1, CCP2, 110: Configure channel interfaces

[0030] 120: Negative voltage generating circuit

[0031] M1, M2, M3: Transistors

[0032] 122: Oscillator

[0033] 124: Signal Buffer

[0034] VSS: System voltage terminal

[0035] V1: First voltage

[0036] V2: Second voltage; VD1: Voltage divider

[0037] C1, C2: Capacitors

[0038] D1, D2: Diodes

[0039] CLK: Clock signal

[0040] EN1: First enable signal

[0041] EN2: Second enable signal

Claims

1. An impedance control circuit, comprising: Configure the channel interface for coupling with the first universal serial bus device; A first resistor has a first end coupled to the configured channel interface and a second end; The first transistor has a first terminal coupled to the second terminal of the first resistor, a second terminal coupled to the system voltage terminal, and a control terminal; The second transistor has a first terminal coupled to the second terminal of the first resistor, a second terminal coupled to the system voltage terminal, and a control terminal; The second resistor has a first end coupled to the second end of the first resistor and a second end coupled to the control terminal of the second transistor; as well as The third resistor has a first end coupled to the second end of the second resistor and a second end coupled to the system voltage terminal; The threshold voltage of the first transistor is negative, and the threshold voltage of the second transistor is positive; when the configuration channel interface is at the first voltage, the first transistor is turned on and the second transistor is turned off; when the configuration channel interface is at the second voltage, the second transistor is turned on. And the second voltage is greater than the first voltage.

2. The impedance control circuit as described in claim 1, wherein the resistance of the first resistor is 5.1 kΩ.

3. The impedance control circuit as described in claim 1, wherein the resistance values ​​of the second resistor and the third resistor are greater than ten times the resistance value of the first resistor.

4. The impedance control circuit of claim 1 further includes a negative voltage generating circuit coupled to the control terminal of the first transistor, for generating a negative voltage to the control terminal of the first transistor according to a first enable signal to turn off the first transistor.

5. The impedance control circuit as described in claim 4, wherein the negative voltage generating circuit comprises: An oscillator for generating a clock signal according to the first enable signal; The first capacitor has a first terminal for receiving the clock signal and a second terminal; The first diode has an anode coupled to the second terminal of the first capacitor and a cathode coupled to the system voltage terminal; The second diode has an anode coupled to the control terminal of the first transistor and a cathode coupled to the second terminal of the first capacitor; as well as The second capacitor has a first end coupled to the anode of the second diode and a second end coupled to the system voltage terminal.

6. The impedance control circuit as described in claim 5, wherein the negative voltage generating circuit further comprises: A signal buffer, coupled between the oscillator and the first capacitor, is used to receive and output the clock signal.

7. The impedance control circuit according to any one of claims 1, 4 to 6, further comprising a third transistor having a first terminal coupled to the control terminal of the second transistor, a second terminal coupled to the system voltage terminal, and a control terminal for receiving a second enable signal.

8. The impedance control circuit as described in claim 1, wherein: The impedance control circuit is located in the second universal serial bus device; as well as When the first Universal Serial Bus (USB) device detects that the voltage of the configuration channel interface is within a predetermined range, the first USB device provides power to the second USB device via the bus power interface.

Images