Digitally controlled oscillator, signal generation method and electronic device

Abstract

The application provides a digital control oscillator for a reconfigurable computing array, comprising a configuration module connected with a Cordic operation array, an output control module and an output cache module, and used for setting configuration information of the Cordic operation array, configuration information of the output control module and configuration information of the output cache module; the Cordic operation array is connected with the output control module, and used for generating a down-converted signal according to the configuration information of the Cordic operation array, and sending the down-converted signal to the output control module; the output control module is connected with the output cache module, and used for outputting the down-converted signal to the output cache module according to the configuration information of the output control module; and the output cache module is used for outputting a quadrature signal based on the down-converted signal according to the configuration information of the output cache module. The application further provides a signal generation method and electronic equipment, which can improve the NCO performance and reduce the NCO energy consumption.

Description

Technical Field

[0001] This invention relates to the field of routing technology, and more particularly to a digitally controlled oscillator, signal generation method, and electronic device for a reconfigurable computing array. Background Technology

[0002] Reconfigurable communication computing arrays are hardware architectures for software-defined communication chips developed using coarse-grained reconfigurable computing technology. They represent a new form between Field-Programmable Gate Arrays (FPGAs) and Application-Specific Integrated Circuits (ASICs). This array structure boasts excellent energy efficiency, addressing the bottlenecks of high power consumption and low clock frequency inherent in FPGAs while compensating for the lack of development flexibility in ASICs for diverse requirements. Consequently, it has found widespread application in communication and other fields. The Digitally Controlled Oscillator (NCO) is a crucial component in reconfigurable design.

[0003] Existing digitally controlled oscillator designs suffer from problems such as unadjustable precision, inability to achieve parallel mixing, and complex and cumbersome numerical information configuration. Summary of the Invention

[0004] The main objective of this invention is to provide a digitally controlled oscillator, a signal generation method, and an electronic device for reconfigurable computing arrays.

[0005] To achieve the above objectives, a first aspect of the present invention provides a digitally controlled oscillator for a reconfigurable computing array, the digitally controlled oscillator comprising:

[0006] Configuration module, Cordic computing array, output control module, and output buffer module;

[0007] The configuration module is connected to the Cordic computing array, the output control module, and the output buffer module, and is used to set the configuration information of the Cordic computing array, the configuration information of the output control module, and the configuration information of the output buffer module.

[0008] The Cordic computing array is connected to the output control module and is used to generate a down-conversion signal according to the configuration information of the Cordic computing array, and send the down-conversion signal to the output control module.

[0009] The output control module is connected to the output buffer module and is used to output the down-conversion signal to the output buffer module according to the configuration information of the output control module;

[0010] The output buffer module is used to output an orthogonal signal based on the down-converted signal according to the configuration information of the output buffer module.

[0011] In one embodiment of this disclosure, the Cordic arithmetic array includes N columns of arithmetic unit groups, each column of the arithmetic unit group being used to output one down-converted signal, where N is an integer greater than 0;

[0012] The N columns of the operational unit group can be partially or completely connected in series.

[0013] In one embodiment of this disclosure, the configuration information of the Cordic computing array includes N columns of configuration information for the computing unit groups, and each column of configuration information for the computing unit groups includes column enable information, phase control word information, and frequency control word information;

[0014] The column enable information is used to control whether the computing unit group in this column is in a working state or an idle state;

[0015] The phase control word information is used to control the initial phase of the output down-conversion signal;

[0016] The frequency control word information is used to control the output step size of the down-conversion signal when outputting serially.

[0017] In one embodiment of this disclosure, the configuration information of the Cordic computing array further includes column configuration control information;

[0018] The column configuration control information for each column of the computational unit group is used to control the configuration information of the current column of the computational unit group to be the configuration information of the previous column of the computational unit group, or the configuration information of the current column of the computational unit group set by the configuration module;

[0019] Wherein, when the operation unit group in this column is connected in series with the operation unit group in the previous column, the column configuration control information of each operation unit group is used to control the configuration information of the operation unit group in this column to be the configuration information of the operation unit group in the previous column. Where the operation unit group in this column is not connected in series with the operation unit group in the previous column, the column configuration control information of each operation unit group is used to control the configuration information of the operation unit group in this column to be the configuration information of the operation unit group in this column set by the configuration module.

[0020] In one embodiment of this disclosure, the configuration information of the output control module is used to control the down-conversion signal to be output serially or in parallel.

[0021] In one embodiment of this disclosure, the configuration information of the output buffer module is used to select the first target port of the output buffer module that outputs the quadrature signal in the case of serial output;

[0022] The configuration information of the output buffer module is also used to control the buffer depth of the down-converted signal in the case of parallel output, and to select the second target port of the output buffer module that outputs the quadrature signal.

[0023] In one embodiment of this disclosure, the output control module includes N serial output interfaces and a counter;

[0024] The N serial output interfaces are used to buffer the down-converted signal into the first target port of the output buffer module in the case of serial output;

[0025] The counter is used to control the output buffer module to buffer the down-converted signal to the second target port of the output buffer module according to the buffer depth in the case of parallel output.

[0026] In one embodiment of this disclosure, the output buffer module is specifically used to output the quadrature signal through the first target port in the case of serial output, and to output the quadrature signal through the second target port in the case of parallel output, according to the configuration information of the output buffer module.

[0027] A second aspect of this invention provides a signal generation method for a reconfigurable computing array, comprising:

[0028] Configure the configuration information for the Cordic computing array, the output control module, and the output cache module;

[0029] The Cordic computing array generates a down-conversion signal according to its configuration information and sends the down-conversion signal to the output control module.

[0030] The output control module outputs the down-conversion signal to the output buffer module according to the configuration information of the output control module;

[0031] The output buffer module outputs an orthogonal signal based on the down-converted signal according to its configuration information.

[0032] A third aspect of the present invention provides an electronic device comprising the digitally controlled oscillator for a reconfigurable computing array described in the first aspect.

[0033] According to an embodiment of the present invention, the digitally controlled oscillator for a reconfigurable computing array (NCO) includes: a configuration module, a Cordic arithmetic array, an output control module, and an output buffer module. The configuration module, connected to the Cordic arithmetic array, the output control module, and the output buffer module, is used to set configuration information for the Cordic arithmetic array, the output control module, and the output buffer module. The Cordic arithmetic array, connected to the output control module, is used to generate a down-converted signal according to the configuration information of the Cordic arithmetic array and send the down-converted signal to the output control module. The output control module, connected to the output buffer module, is used to output the down-converted signal to the output buffer module according to the configuration information of the output control module. The output buffer module is used to output an orthogonal signal based on the down-converted signal according to the configuration information of the output buffer module, thereby improving NCO performance and reducing NCO energy consumption. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a schematic diagram of a digitally controlled oscillator for a reconfigurable computing array provided in an embodiment of the present invention;

[0036] Figure 2 This is a schematic diagram of a digitally controlled oscillator for a reconfigurable computing array provided in an embodiment of the present invention;

[0037] Figure 3 This is a flowchart illustrating a signal generation method for a reconfigurable computing array according to an embodiment of the present invention.

[0038] Figure 4 A schematic diagram of the hardware structure of an electronic device is shown. Detailed Implementation

[0039] To make the objectives, features, and advantages of this invention more apparent and understandable, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0040] Reconfigurable computing arrays are a coarse-grained reconfigurable cryptographic multi-core architecture. Their structure is arranged in an array, and due to the real-time characteristics of the system, the system array adopts a pipelined layout. In this invention, the NCO is designed as a coarse-grained operator in the array. Its position can generally be preceded by a decimation filter. The data sampled by the analog-to-digital converter is filtered and then input to the mixer and NCO for down-conversion processing. The NCO can be followed by a low-pass filter to filter out high-frequency signals generated in the mixing operation.

[0041] NCOs are typically used to generate controllable sine or cosine waves. Their function is to perform multiplication (mixing) with signals to achieve down-conversion in communication systems. Down-conversion can generally be divided into serial mixing for narrow-bandwidth signals and parallel mixing for wide-bandwidth signals. Serial mixing involves the NCO generating one oscillation value per clock cycle and mixing it with one signal. Parallel mixing involves the NCO generating a set of oscillation values ​​per clock cycle and mixing them with a set of signals.

[0042] For NCOs of reconfigurable computing arrays, in a typical application scenario, they can be used as oscillation signal generators for mixers. The front end is a digital signal acquired by an analog-to-digital converter or a filtered digital signal. The signal is down-converted by the mixer and then output to a low-pass filter. The low-pass filter then filters out the high-frequency signal noise generated by the mixer and further processes the communication signal.

[0043] This invention provides a digitally controlled oscillator (DCO) for a reconfigurable computing array (NCO). The DCO includes a configuration module, a Cordic arithmetic array, an output control module, and an output buffer module. The configuration module, connected to the Cordic arithmetic array, the output control module, and the output buffer module, is used to set configuration information for the Cordic arithmetic array, the output control module, and the output buffer module. The Cordic arithmetic array, connected to the output control module, generates a down-converted signal based on its configuration information and sends the down-converted signal to the output control module. The output control module, connected to the output buffer module, outputs the down-converted signal to the output buffer module according to its configuration information. The output buffer module outputs an orthogonal signal based on the down-converted signal according to its configuration information, thereby improving NCO performance and reducing NCO energy consumption.

[0044] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Where there is no conflict between the embodiments, the following embodiments and features thereof can be combined with each other.

[0045] Please see Figure 1 , Figure 1This is a schematic diagram of a digitally controlled oscillator (NCO) for a reconfigurable computing array according to an embodiment of the present invention. The NCO mainly includes:

[0046] Configuration module 1010, Cordic arithmetic array 20, output control module 30 and output buffer module 40.

[0047] The configuration module 10 is connected to the Cordic computing array 20, the output control module 30, and the output buffer module 40, and is used to set the configuration information of the Cordic computing array 20, the output control module 30, and the output buffer module 40.

[0048] The Cordic computing array 20 is connected to the output control module 30 and is used to generate a down-conversion signal according to the configuration information of the Cordic computing array 20, and send the down-conversion signal to the output control module 30.

[0049] The output control module 30 is connected to the output buffer module 40 and is used to output the down-conversion signal to the output buffer module 40 according to the configuration information of the output control module 30.

[0050] The output buffer module 40 is used to output an orthogonal signal based on the down-converted signal according to the configuration information of the output buffer module 40.

[0051] In one embodiment of the present invention, the Cordic arithmetic array 20 includes N columns of arithmetic unit groups, each column of which is used to output one down-converted signal, where N is an integer greater than 0. The N columns of arithmetic units can be partially or entirely connected in series. With a fixed structure for the Cordic arithmetic array 20, the output accuracy of the NCO can be adjusted by connecting them in series, thus solving the problem of accuracy redundancy and reasonably reducing power consumption.

[0052] In this invention, the number of operational units within each column of operational units is not specifically limited and can be 2, 3, 4, 10, etc. The number of operational unit groups and the number of operational units within each column of operational units together characterize the computational accuracy. Those skilled in the art can adjust the size of the Cordic operational array 20, that is, adjust the number of operational unit groups and the number of operational units within each column of operational units, according to the actual computational accuracy requirements. Specifically, a larger Cordic operational array 20 results in higher accuracy, while a smaller Cordic operational array 20 results in lower accuracy.

[0053] like Figure 2As shown in the example, taking N=4 and the number of arithmetic units in each column of arithmetic units as 4, the present invention is illustrated. That is, the size of the Cordic arithmetic array 20 is 4×4. The 4 columns of arithmetic units can be partially or fully connected in series to form 4 low-precision NCO outputs with 4 stages, or 2 medium-precision NCO outputs with 8 stages of pipeline, or a high-precision NCO output with 12 stages of pipeline and a low-precision NCO output with 4 stages, or a high-precision NCO output with 16 stages of pipeline. Furthermore, depending on actual needs, the enable of unnecessary arithmetic unit groups can be turned off to reduce power consumption. For example, if only a high-precision NCO output with 12 stages of pipeline is needed, the column enable information of the remaining column of arithmetic units (4-stage low-precision NCO output) can be configured to be in an idle state to turn off the enable of the arithmetic units in that column, effectively reducing the power consumption of the Cordic arithmetic array 20.

[0054] In one embodiment of the present invention, the configuration information of the Cordic arithmetic array 20 includes N columns of configuration information for the arithmetic unit groups. Each column of configuration information for the arithmetic unit group includes column enable information, phase control word information, and frequency control word information. The column enable information controls whether the arithmetic unit group in that column is in an active or idle state. The phase control word information controls the initial phase of the output down-converted signal. The frequency control word information controls the output step size of the down-converted signal in the case of serial output. Through the configuration information of the N columns of arithmetic unit groups and the Cordic arithmetic array 20, N-channel phase-adjustable Cordic operators (NCOs) can be generated, addressing the need for multi-channel, multi-band serial mixing.

[0055] In this invention, a configuration interface can be provided for each column of the arithmetic unit group, through which the configuration information of the N columns of the arithmetic unit group can be input. For column enable information, as exemplified above, configuring the column enable information allows disabling the enable of unnecessary arithmetic unit groups according to actual needs, reducing power consumption. For phase control word information, orthogonal signals conforming to phase requirements can be output. For example, the initial phase of the first column of arithmetic unit groups can be configured as 0°, the initial phase of the second column as 90°, the initial phase of the third column as 180°, and the initial phase of the fourth column as 270°. For frequency control word information, orthogonal signals conforming to frequency requirements can be output. The frequency control word information controls the output step size of the NCO in serial mode. With a fixed main frequency, what is actually controlled is the frequency output by the NCO in serial mode.

[0056] In one embodiment of the present invention, the configuration information of the Cordic operation array 20 further includes column configuration control information. The column configuration control information of each column of the operation unit group is used to control the configuration information of the current column of the operation unit group to be the configuration information of the previous column of the operation unit group, or the configuration information of the current column of the operation unit group set by the configuration module 10.

[0057] Wherein, when the current column of the operation unit group is connected in series with the previous column of the operation unit group, the column configuration control information of each column of the operation unit group is used to control the configuration information of the current column of the operation unit group to be the configuration information of the previous column of the operation unit group. Where the current column of the operation unit group is not connected in series with the previous column of the operation unit group, the column configuration control information of each column of the operation unit group is used to control the configuration information of the current column of the operation unit group to be the configuration information of the current column of the operation unit group set by the configuration module 10.

[0058] In this embodiment, the main function of the column configuration control information is to select whether the configuration information of each column comes from the configuration module 10 or inherits from the previous level's configuration (the leftmost column's operation unit group has no inherited columns and defaults to coming from the configuration module 10). In one example, the column configuration control information, such as... Figure 2 As shown, the 4×4 Cordic arithmetic array 20 can be combined into four 4-level NCO outputs, or two 8-level NCO outputs, or one 16-level NCO output, or a mixed output of 4 and 12 levels. The higher the number of levels in the Cordic arithmetic array 20, the higher the data precision of the NCO output. Therefore, the precision of the NCO output value can be controlled by configuring the control information through the configuration column.

[0059] In one embodiment of the present invention, the configuration information of the output control module 30 is used to control whether the down-converted signal is output serially or in parallel. This satisfies both serial and parallel mixing requirements. Furthermore, the N-column arithmetic unit array can output N different frequency serial NCO oscillation values, enabling simultaneous demodulation of signals across different frequency bands.

[0060] In one embodiment of the present invention, the configuration information of the output buffer module 40 is used to select a first target port of the output buffer module 40 that outputs the quadrature signal in the case of serial output. The configuration information of the output buffer module 40 is also used to control the buffer depth of the downconverted signal in the case of parallel output, and to select a second target port of the output buffer module 40 that outputs the quadrature signal. It is compatible with both serial mixing and parallel mixing application requirements.

[0061] In one example, such as Figure 2As shown, the 4×4 Cordic operational array 20 outputs four down-converted signals. If the configuration information of the output control module 30 is to control the down-converted signals to be output serially, then the configuration information of the output buffer module 40 can select any four ports for the first target port of the output buffer module 40 that outputs the quadrature signals, such as ports 0 to 3. If the configuration information of the output control module 30 is to control the down-converted signals to be output in parallel, then the configuration information of the output buffer module 40 controls the buffer depth of the down-converted signals to a maximum depth of 16, and selects ports 0-15 as the second target ports of the output buffer module 40 that outputs the quadrature signals.

[0062] In one embodiment of the present invention, the output control module 30 includes N serial output interfaces and a counter. The N serial output interfaces are used to buffer the down-converted signal to the first target port of the output buffer module 40 in the case of serial output. The counter is used to control the output buffer module 40 to buffer the down-converted signal to the second target port of the output buffer module 40 according to the buffer depth in the case of parallel output.

[0063] In this embodiment, the output control module 30 is mainly used to control all output ports to output normally according to a predetermined configuration. Figure 2 In the example shown, the 4×4 Cordic arithmetic array 20 and the output buffer module 40 include 16 output ports. The inputs of the N serial output interfaces are the outputs of the four columns of arithmetic units, and the outputs of the N serial output interfaces can be output ports 0-3, meaning output ports 0-3 output, while ports 4-15 do not output. The counter mainly controls the NCO buffer to cache to the output ports corresponding to the configured buffer depth in the case of parallel output. For example, if the buffer depth is 16, the corresponding output ports are 0-15. Once the buffer is complete, i.e., the counter equals the buffer depth, a parallel NCO output enable signal is generated. The configured buffer depth does not exceed the total number of output ports of the output buffer module 40, the number of second target ports is equal to the buffer depth, and serial output and parallel output configurations are mutually exclusive; they cannot coexist.

[0064] In one embodiment of the present invention, the output buffer module 40 is specifically used to output the quadrature signal through the first target port in the case of serial output, and to output the quadrature signal through the second target port in the case of parallel output, according to the configuration information of the output buffer module 40.

[0065] exist Figure 2In the example shown, the 4×4 Cordic arithmetic array 20 and the output buffer module 40 include 16 output ports. In the case of serial output, only output ports 0-3 will be used, that is, the first target ports are 0-3. In the case of parallel output, the corresponding effective output is generated according to the configured buffer depth, and the configured effective depth does not exceed 16.

[0066] Please see Figure 3 , Figure 3 This is a flowchart illustrating a signal generation method for a reconfigurable computing array according to an embodiment of the present invention. The signal generation method can be achieved through methods such as... Figure 1 and Figure 2 The digitally controlled oscillator generation method shown for a reconfigurable computing array includes:

[0067] S301. Configure the configuration information of the Cordic computing array, the output control module, and the output buffer module;

[0068] S302. The Cordic computing array generates a down-conversion signal according to the configuration information of the Cordic computing array, and sends the down-conversion signal to the output control module;

[0069] S303. The output control module outputs the down-conversion signal to the output buffer module according to the configuration information of the output control module;

[0070] S304. The output buffer module outputs an orthogonal signal based on the down-converted signal according to the configuration information of the output buffer module.

[0071] In one embodiment of the present invention, the Cordic arithmetic array includes N columns of arithmetic units, each column of which is used to output one down-converted signal, where N is an integer greater than 0. The N columns of arithmetic units can be partially or completely connected in series.

[0072] In one embodiment of the present invention, the configuration information of the Cordic computing array includes N columns of configuration information of the computing unit group, and each column of configuration information of the computing unit group includes column enable information, phase control word information and frequency control word information;

[0073] The method further includes: configuring column enable information, which is used to control whether the column's operation unit group is in a working state or an idle state;

[0074] Configure the phase control word information, which is used to control the initial phase of the output down-converter signal;

[0075] Configure the frequency control word information, which is used to control the output step size of the down-converted signal in the case of serial output.

[0076] In one embodiment of the present invention, the configuration information of the Cordic computing array further includes column configuration control information;

[0077] The method further includes: configuring column configuration control information for each column of the operation unit group, wherein the column configuration control information for each column of the operation unit group is used to control the configuration information of the current column of the operation unit group to be the configuration information of the previous column of the operation unit group, or the configuration information of the current column of the operation unit group set by the configuration module;

[0078] Specifically, when the current column of the computational unit group is connected in series with the previous column of the computational unit group, the column configuration control information of each column of the computational unit group is used to control the configuration information of the current column of the computational unit group to be the configuration information of the previous column of the computational unit group. When the current column of the computational unit group is not connected in series with the previous column of the computational unit group, the column configuration control information of each column of the computational unit group is used to control the configuration information of the current column of the computational unit group to be the configuration information of the current column of the computational unit group set by the configuration module.

[0079] In one embodiment of the present invention, the configuration information of the output control module is used to control the downconversion signal to be output serially or in parallel.

[0080] In one embodiment of the present invention, the configuration information of the output buffer module is used to select the first target port of the output buffer module that outputs the quadrature signal in the case of serial output;

[0081] The configuration information of the output buffer module is also used to control the buffer depth of the downconverted signal in the case of parallel output, and to select the second target port of the output buffer module that outputs the quadrature signal.

[0082] In one embodiment of the present invention, the output control module includes N serial output interfaces and a counter;

[0083] The method also includes: using the N serial output interfaces to buffer the down-converted signal into the first target port of the output buffer module in the case of serial output;

[0084] Using this counter in the case of parallel output, the output buffer module is controlled to buffer the down-converted signal to the second target port of the output buffer module according to the buffer depth.

[0085] In one embodiment of the present invention, the method further includes: the output buffer module outputs the quadrature signal through the first target port in the case of serial output, and outputs the quadrature signal through the second target port in the case of parallel output, according to the configuration information of the output buffer module.

[0086] In one example, downconversion of four signals is required to obtain a 40MHz effective signal from a 50MHz quadrature signal. The system frequency is 100MHz. The input needs to generate four NCO output frequencies of 10MHz, with initial phase differences of 90° between columns 1 and 2 and 90° between columns 3 and 4, and configuration information needs to be sent to the configuration module.

[0087] First, the configuration module parses the configuration information into the CORDIC arithmetic array, output control module, and output buffer module. The configuration information of the CORDIC arithmetic array after parsing by the configuration module is as follows: the column enable information of the four arithmetic unit groups is all in the working state; the phase control word information of the four arithmetic unit groups is that the phase configuration words of columns 1 and 2 are 0 and 90° respectively, and the phase configuration words of columns 3 and 4 are 180° and 270° respectively; the frequency control word information of the four arithmetic unit groups is all in a step size of 10; the column configuration control information of the four arithmetic unit groups is all from the configuration module.

[0088] Then, initialize and configure the down-conversion signals (serial output) corresponding to the four columns of arithmetic units at output ports 0-3. Configure the CORDIC arithmetic array configuration information parsed by the configuration module: enable the four columns of CORDIC modules, putting the four-column CORDIC array into working state. Configure the output control module and output buffer module configuration information parsed by the configuration module: the output control module operates in serial output mode, meaning it will remain operational after the CORDIC arithmetic array is enabled; configure the second target port 0-3 in the output buffer module, meaning data does not need to be buffered, and the four columns of arithmetic units output four orthogonal signals with two sets of 10MHz frequencies from left to right, corresponding to ports 0-3.

[0089] Furthermore, the four input signals are multiplied (mixed) with the signals output from NCO output ports 0-3. For example, two quadrature input signals of 50MHz are mixed with the NCO to produce an effective signal containing a high-frequency signal (60MHz) and a low-frequency signal (40MHz). Ultimately, two sets of quadrature mixed signals are generated.

[0090] This disclosure also provides an electronic device, the electronic device including... Figure 1 or Figure 2 The digitally controlled oscillator shown is used for a reconfigurable computing array.

[0091] Figure 4 A block diagram of an electronic device for a signal generation method for a reconfigurable computing array according to an embodiment of the present disclosure is shown schematically.

[0092] like Figure 4As shown, an electronic device 400 according to an embodiment of the present disclosure includes a processor 401, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 402 or a program loaded from a storage portion 408 into a random access memory (RAM) 403. The processor 401 may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor and / or an associated chipset and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 401 may also include onboard memory for caching purposes. The processor 401 may include a single processing unit or multiple processing units for performing different actions of the method flow according to an embodiment of the present disclosure.

[0093] RAM 403 stores various programs and data required for the operation of electronic device 400. Processor 401, ROM 402, and RAM 403 are interconnected via bus 404. Processor 401 performs various operations of the method flow according to embodiments of the present disclosure by executing programs in ROM 402 and / or RAM 403. It should be noted that the programs may also be stored in one or more memories other than ROM 402 and RAM 403. Processor 401 may also perform various operations of the method flow according to embodiments of the present disclosure by executing programs stored in said one or more memories.

[0094] According to embodiments of this disclosure, the electronic device 400 may further include an input / output (I / O) interface 405, which is also connected to a bus 404. The electronic device 400 may also include one or more of the following components connected to the I / O interface 405: an input section 406 including a keyboard, mouse, etc.; an output section 407 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 408 including a hard disk, etc.; and a communication section 409 including a network interface card such as a LAN card, modem, etc. The communication section 409 performs communication processing via a network such as the Internet. A drive 410 is also connected to the I / O interface 405 as needed. A removable medium 411, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on the drive 410 as needed so that computer programs read from it can be installed into the storage section 408 as needed.

[0095] This disclosure also provides a computer-readable storage medium, which may be included in the device / apparatus / system described in the above embodiments; or it may exist independently and not assembled into the device / apparatus / system. The computer-readable storage medium carries one or more programs that, when executed, implement the method according to the embodiments of this disclosure.

[0096] According to embodiments of this disclosure, the computer-readable storage medium may be a non-volatile computer-readable storage medium, such as, but not limited to: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In this disclosure, the computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. For example, according to embodiments of this disclosure, the computer-readable storage medium may include ROM 402 and / or RAM 403 and / or one or more memories other than ROM 402 and RAM 403 described above.

[0097] Embodiments of this disclosure also include a computer program product comprising a computer program containing program code for performing the methods shown in the flowchart. When the computer program product is run on a computer system, the program code is used to cause the computer system to implement the item recommendation method provided in the embodiments of this disclosure.

[0098] When the computer program is executed by the processor 401, it performs the functions defined in the system / apparatus of this disclosure embodiments. According to embodiments of this disclosure, the systems, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0099] In one embodiment, the computer program may rely on a tangible storage medium such as an optical storage device or a magnetic storage device. In another embodiment, the computer program may also be transmitted and distributed in the form of signals over a network medium, and downloaded and installed via communication section 409, and / or installed from removable medium 411. The program code contained in the computer program can be transmitted using any suitable network medium, including but not limited to: wireless, wired, etc., or any suitable combination thereof.

[0100] In such an embodiment, the computer program can be downloaded and installed from a network via communication section 409, and / or installed from removable medium 411. When the computer program is executed by processor 401, it performs the functions defined in the system of this disclosure embodiment. According to embodiments of this disclosure, the systems, devices, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0101] According to embodiments of this disclosure, program code for executing the computer programs provided in embodiments of this disclosure can be written in any combination of one or more programming languages. Specifically, these computational programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages ​​include, but are not limited to, languages ​​such as Java, C++, Python, "C", or similar programming languages. The program code can execute entirely on the user's computing device, partially on the user's device, partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0102] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0103] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure can be combined or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0104] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A digitally controlled oscillator for a reconfigurable computing array, characterized in that, The digitally controlled oscillator includes: Configuration module, Cordic computing array, output control module, and output buffer module; The configuration module is connected to the Cordic computing array, the output control module, and the output buffer module, and is used to set the configuration information of the Cordic computing array, the configuration information of the output control module, and the configuration information of the output buffer module. The Cordic computing array is connected to the output control module and is used to generate a down-conversion signal according to the configuration information of the Cordic computing array, and send the down-conversion signal to the output control module. The output control module is connected to the output buffer module and is used to output the down-conversion signal to the output buffer module according to the configuration information of the output control module; The output buffer module is used to output an orthogonal signal based on the down-converted signal according to the configuration information of the output buffer module; The Cordic arithmetic array includes N columns of arithmetic units, each column of which is used to output one down-converted signal, where N is an integer greater than 0; wherein, the N columns of arithmetic units can be partially or completely connected in series. The configuration information of the Cordic computing array includes N columns of configuration information for the computing unit groups. Each column of configuration information for the computing unit groups includes column enable information, phase control word information, and frequency control word information. The column enable information is used to control whether the computation unit group in this column is in a working state or an idle state; The phase control word information is used to control the initial phase of the output down-conversion signal; The frequency control word information is used to control the output step size of the down-conversion signal when outputting serially.

2. The digitally controlled oscillator according to claim 1, characterized in that, The configuration information of the Cordic computing array also includes column configuration control information; The column configuration control information for each column of the computational unit group is used to control the configuration information of the computational unit group in this column to be the configuration information of the previous column of the computational unit group, or the configuration information of the computational unit group in this column set by the configuration module; Wherein, when the operation unit group in this column is connected in series with the operation unit group in the previous column, the column configuration control information of each operation unit group is used to control the configuration information of the operation unit group in this column to be the configuration information of the operation unit group in the previous column. Where the operation unit group in this column is not connected in series with the operation unit group in the previous column, the column configuration control information of each operation unit group is used to control the configuration information of the operation unit group in this column to be the configuration information of the operation unit group in this column set by the configuration module.

3. The digitally controlled oscillator according to claim 1, characterized in that, The configuration information of the output control module is used to control whether the down-conversion signal is output serially or in parallel.

4. The digitally controlled oscillator according to claim 1, characterized in that, The configuration information of the output buffer module is used to select the first target port of the output buffer module that outputs the quadrature signal in the case of serial output; The configuration information of the output buffer module is also used to control the buffer depth of the down-converted signal in the case of parallel output, and to select the second target port of the output buffer module that outputs the quadrature signal.

5. The digitally controlled oscillator according to claim 4, characterized in that, The output control module includes N serial output interfaces and a counter; The N serial output interfaces are used to buffer the down-converted signal into the first target port of the output buffer module in the case of serial output; The counter is used to control the output buffer module to buffer the down-converted signal to the second target port of the output buffer module according to the buffer depth in the case of parallel output.

6. The digitally controlled oscillator according to claim 1, characterized in that, The output buffer module is specifically used to output the quadrature signal through the first target port in the case of serial output, and to output the quadrature signal through the second target port in the case of parallel output, according to the configuration information of the output buffer module.

7. A signal generation method for a reconfigurable computing array, characterized in that, include: Configure the configuration information for the Cordic computing array, the output control module, and the output cache module; The Cordic computing array generates a down-conversion signal according to its configuration information and sends the down-conversion signal to the output control module. The output control module outputs the down-conversion signal to the output buffer module according to the configuration information of the output control module; The output buffer module outputs an orthogonal signal based on the down-converted signal according to the configuration information of the output buffer module. The Cordic arithmetic array includes N columns of arithmetic units, each column of which is used to output one down-converted signal, where N is an integer greater than 0; wherein, the N columns of arithmetic units can be partially or completely connected in series. The configuration information of the Cordic computing array includes N columns of configuration information for the computing unit groups. Each column of configuration information for the computing unit groups includes column enable information, phase control word information, and frequency control word information. The column enable information is used to control whether the computation unit group in this column is in a working state or an idle state; The phase control word information is used to control the initial phase of the output down-conversion signal; The frequency control word information is used to control the output step size of the down-conversion signal when outputting serially.

8. An electronic device, characterized in that, The electronic device includes a digitally controlled oscillator for a reconfigurable computing array as described in any one of claims 1 to 6.

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