Memory and data writing method thereof, and storage system
By introducing detection control circuits and switching circuits into the static random access memory, the control bit line is connected after the data level jump is detected. Power consumption is reduced by utilizing charge redistribution, which solves the problem of high power consumption in adjacent write operations and achieves effective energy saving.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- YANGTZE MEMORY TECH CO LTD
- Filing Date
- 2022-08-24
- Publication Date
- 2026-06-16
Smart Images
Figure CN115331716B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of storage technology, and in particular to a memory and its data writing method and storage system. Background Technology
[0002] Static random-access memory (SRAM) is a type of random access memory characterized by high read and write speeds, often used as a cache. An SRAM cell typically includes six transistors: four transistors form a latch, and the other two act as control switches. One of these control switches is connected to the word line (WL), the first bit line (BL), and the first latch node in the latch; the other is connected to the WL, the second bit line, and the second latch node in the latch. The second bit line is also called BL NOT, i.e.
[0003] When performing a write operation on an SRAM cell, the data to be written can be loaded onto the first bit line, and the inverted data obtained from the inverted data can be loaded onto the second bit line. Furthermore, both control switches can be turned on via WL, connecting the first bit line to the first latch node in the latch and the second bit line to the second latch node in the latch. Thus, the data loaded on the first bit line can be written to the latch. Specifically, if the data to be written is 1, a high level is applied to the first bit line and a low level is applied to the second bit line. If the data to be written is 0, a low level is applied to the first bit line and a high level is applied to the second bit line.
[0004] However, if the data to be written in two consecutive write operations are different, the level on the first or second bit line needs to be changed from low to high, resulting in high power consumption when driving the bit line. Summary of the Invention
[0005] This application provides a memory, a data writing method therewith, and a storage system, which can solve the technical problem of high power consumption when driving bit lines. The technical solution is as follows:
[0006] In a first aspect, a memory is provided, the memory comprising: a memory cell array, a write control circuit, a detection control circuit, and a switching circuit;
[0007] The memory cell array includes multiple static random access memory (SRAM) cells coupled to different word lines, and each of the multiple SRAM cells is also connected to the first bit line and the second bit line.
[0008] The write control circuit is connected to the first bit line and the second bit line respectively. When the write control circuit is in the working state, it loads the first data to be written onto the first bit line and loads the second data obtained by inverting the first data onto the second bit line.
[0009] The detection control circuit is connected to the write control circuit and the switch circuit respectively. The switch circuit is also connected to the first bit line and the second bit line respectively. If the level of the first data is detected to change, the detection control circuit controls the switch circuit to connect the first bit line and the second bit line and controls the write control circuit to stop working.
[0010] Optionally, the detection control circuit includes: a detection sub-circuit and a control sub-circuit;
[0011] The input terminal of the detection sub-circuit is used to receive the first data, and the output terminal of the detection sub-circuit is connected to the first input terminal of the control sub-circuit and the first control terminal of the switch circuit respectively. The detection sub-circuit is used to output a pulse signal if a level change of the first data is detected.
[0012] The second input terminal of the control sub-circuit is used to receive a write enable signal. The output terminal of the control sub-circuit is connected to the control terminal of the write control circuit. The control sub-circuit is used to output a de-enable signal to stop the write control circuit from working when the pulse signal is at the first level, and to output the write enable signal when the pulse signal is at the second level.
[0013] The first terminal of the switching circuit is connected to the first bit line, and the second terminal of the switching circuit is connected to the second bit line. The switching circuit is used to turn on the first terminal and the second terminal when the pulse signal is at a first level, and to turn off the first terminal and the second terminal when the pulse signal is at a second level.
[0014] Optionally, the detection sub-circuit includes: a delay sub-circuit and a comparison sub-circuit;
[0015] The input terminal of the delay sub-circuit is used to receive the first data, and the output terminal of the delay sub-circuit is connected to the first input terminal of the comparison sub-circuit. The delay sub-circuit is used to output the first data after delaying it.
[0016] The second input terminal of the comparator sub-circuit is used to receive the first data. The output terminal of the comparator sub-circuit is connected to the first input terminal of the control sub-circuit and the first control terminal of the switch circuit, respectively. The comparator sub-circuit is used to output a pulse signal if it detects that the levels of the two input terminals of the comparator sub-circuit are different.
[0017] Optionally, the comparator sub-circuit includes: a first NOT gate, a first NOR gate, a NAND gate, a second NOT gate, a second NOR gate, and a third NOT gate;
[0018] The input terminal of the first NOT gate is connected to the output terminal of the delay sub-circuit, and the output terminal of the first NOT gate is connected to the first input terminal of the first NOR gate and the first input terminal of the NAND gate, respectively.
[0019] The second input terminals of the first NOR gate and the second input terminal of the NAND gate are both used to receive the first data. The output terminal of the first NOR gate is connected to the first input terminal of the second NOR gate, the output terminal of the NAND gate is connected to the input terminal of the second NOT gate, and the output terminal of the second NOT gate is connected to the second input terminal of the second NOR gate.
[0020] The output of the second NOR gate is connected to the input of the third NOT gate, and the output of the third NOT gate is connected to the first input of the control sub-circuit and the first control terminal of the switching circuit.
[0021] Optionally, the switching circuit further has a second control terminal; the detection control circuit further includes an inverting sub-circuit.
[0022] The input terminal of the inverting sub-circuit is connected to the output terminal of the comparator sub-circuit, and the output terminal of the inverting sub-circuit is connected to the second control terminal of the switching circuit. The inverting sub-circuit is used to invert the pulse signal and output it.
[0023] The switching circuit is used to connect the first terminal and the second terminal when the first control terminal is at the first level and the second control terminal is at the second level, and to disconnect the first terminal and the second terminal when the first control terminal is at the second level and the first control terminal is at the first level.
[0024] Optionally, the inverting sub-circuit includes a fourth NOT gate.
[0025] Optionally, the control sub-circuit includes a fifth NOT gate and a third NOR gate;
[0026] The input terminal of the fifth NOT gate is used to receive a write enable signal, and the output terminal of the fifth NOT gate is connected to the first input terminal of the third NOR gate.
[0027] The second input terminal of the third NOR gate is connected to the output terminal of the detection sub-circuit, and the output terminal of the third NOR gate is connected to the control terminal of the write control circuit.
[0028] Optionally, the switching circuit includes: a first transistor;
[0029] The gate of the first transistor is connected to the output terminal of the detection sub-circuit or the output terminal of the inverting sub-circuit. The first terminal of the first transistor is connected to the first bit line, and the second terminal of the first transistor is connected to the second bit line. The first transistor is either an N-type transistor or a P-type transistor.
[0030] Optionally, in the scenario where the gate of the first transistor is connected to the output terminal of the inverting sub-circuit, the switching circuit further includes: a second transistor, the polarity of which is opposite to that of the first transistor;
[0031] Furthermore, the gate of the second transistor is connected to the output terminal of the detection sub-circuit, the first electrode of the second transistor is connected to the first bit line, and the second electrode of the second transistor is connected to the second bit line.
[0032] Optionally, the write control circuit includes: a sixth NOT gate, a first tri-state gate, and a second tri-state gate;
[0033] The input terminals of the sixth NOT gate and the first tri-state gate are both used to receive the first data, and the output terminal of the sixth NOT gate is connected to the input terminal of the second tri-state gate.
[0034] The control terminal of the first tri-state gate is connected to the output terminal of the detection control circuit, and the output terminal of the first tri-state gate is connected to the first bit line;
[0035] The control terminal of the second tri-state gate is connected to the output terminal of the detection control circuit, and the output terminal of the second tri-state gate is connected to the second bit line.
[0036] Secondly, a data writing method for a memory is provided, the memory including a memory cell array, the memory cell array including a plurality of static random access memory (SRAM) cells coupled to different word lines, the plurality of SRAM cells also being connected to a first bit line and a second bit line; the method includes:
[0037] Load the first data to be written onto the first bit line, and load the second data obtained by inverting the first data onto the second bit line;
[0038] If a level change in the first data is detected, the first bit line is connected to the second bit line, and data loading to the first bit line and the second bit line is stopped.
[0039] Optionally, the method further includes:
[0040] After the level of the first bit line is equal to the level of the second bit line, the connection between the first bit line and the second bit line is turned off, and the first data is continued to be loaded onto the first bit line, and the second data is continued to be loaded onto the second bit line.
[0041] Optionally, before loading the first data to be written onto the first bit line, the method further includes: loading a valid level write enable signal onto the detection control circuit in the memory.
[0042] Optionally, the method further includes: during the process of loading the first data to be written onto the first bit line, loading an effective level onto the word line coupled to the SRAM cell to which the first data is to be written.
[0043] Thirdly, a storage system is provided, the storage system comprising: a memory controller, and at least one memory as provided in the above aspects.
[0044] The technical solution provided in this application can include at least the following beneficial effects:
[0045] This application provides a memory and its data writing method and storage system. The memory provided by this application includes: a memory cell array, a write control circuit, a detection control circuit, and a switching circuit. The switching circuit is connected to a first bit line and a second bit line respectively. When the detection control circuit detects a level change in the first data to be written to the memory cell array, it controls the switching circuit to connect the first bit line and the second bit line, and controls the write control circuit to stop operating. Therefore, the bit line at a high level between the first and second bit lines can pull the level of the other bit line high through charge redistribution. This charge redistribution process does not require driving by the write control circuit, thus effectively reducing the power consumption required to drive the bit lines. Attached Figure Description
[0046] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0047] Figure 1 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;
[0048] Figure 2 This is a schematic diagram of an SRAM structure provided in an embodiment of this application;
[0049] Figure 3This is a schematic diagram of the structure of an SRAM cell provided in an embodiment of this application;
[0050] Figure 4 This is a signal timing diagram provided in an embodiment of the present application when writing data into a storage cell array;
[0051] Figure 5 This is a schematic diagram of the structure of a memory provided in an embodiment of this application;
[0052] Figure 6 This is a schematic diagram of the structure of a detection control circuit provided in an embodiment of this application;
[0053] Figure 7 This is a schematic diagram of the structure of a detection sub-circuit provided in an embodiment of this application;
[0054] Figure 8 This is a schematic diagram of a switching circuit provided in an embodiment of this application;
[0055] Figure 9 This is a schematic diagram of another switching circuit provided in an embodiment of this application;
[0056] Figure 10 This is a schematic diagram of a write control circuit provided in an embodiment of this application;
[0057] Figure 11 This is a flowchart of a data writing method for a memory provided in an embodiment of this application;
[0058] Figure 12 This is another signal timing diagram provided in an embodiment of this application when writing data into a storage cell array. Detailed Implementation
[0059] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.
[0060] The solutions provided in this application can be applied to electronic devices. These electronic devices can be mobile terminals, desktop computers, laptop computers, tablet computers, vehicle computers, game consoles, printers, positioning devices, wearable electronic devices, smart sensors, virtual reality devices, augmented reality devices, or any other suitable electronic device having memory.
[0061] Figure 1 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application, such as... Figure 1As shown, the electronic device includes a storage system 10 and a host 20. The host 20 can be a central processing unit (CPU) or a system-on-chip (SOC) of the electronic device. The host 20 is used to send data to the storage system 10 for storage or to read data from the storage system 10.
[0062] refer to Figure 1 The storage system 10 includes a memory controller 200 and at least one SRAM 100, for example... Figure 1 Multiple SRAM 100s are shown. For example... Figure 1 As shown, the storage system 10 may also include at least one NAND gate memory 300, for example... Figure 1 The diagram shows multiple NAND memories 300. Each NAND memory 300 can be a three-dimensional (3D) memory, such as 3D NAND flash memory. A memory controller 200 is connected to at least one SRAM 100, at least one NAND memory 300, and a host 20, respectively. The memory controller 200 is used to manage the data stored in the SRAM 100 and the NAND memory 300, and to communicate with the host 20.
[0063] Figure 2 This is a schematic diagram of an SRAM structure provided in an embodiment of this application. Figure 2 As shown, the SRAM 100 may include a memory cell array 101 and a write control circuit 102. The memory cell array 101 includes n SRAM cells, where n is an integer greater than 1. These n SRAM cells can be connected one-to-one with n write queues (WLs), for example, an SRAM cell m can be connected to a write queue m, where m is a positive integer not greater than n. Figure 2 It can also be seen that each of the n SRAM cells can be connected to the first bit line BT and the second bit line BB. Under the control of the write enable signal W0_en, the write control circuit 102 can write data into the SRAM cells through the first bit line BT and the second bit line BB.
[0064] Figure 3 This is a schematic diagram of the structure of an SRAM cell provided in an embodiment of this application. Figure 3As shown, this SRAM cell can include two P-type transistors, MP0 and MP1, and four N-type transistors, MN0 to MN3. MP0 and MN0 can form an inverter, and MP1 and MN1 can form another inverter. These two inverters form an interlock structure (i.e., a latch) to store data. MN2 and MN3 are two control switches used, under the control of WL, to control the on / off state between the first bit line BT and the latch node d in the latch, and to control the on / off state between the second bit line BB and the latch node d_n in the latch.
[0065] It is understandable that each SRAM cell can store 1 bit of data. Furthermore, when node d in the SRAM cell is high and node d_n is low (i.e., d = 1, d_n = 0), it indicates that the stored data is 1; when node d is low and node d_n is high (i.e., d = 0, d_n = 1), it indicates that the stored data is 0.
[0066] Figure 4 This is a signal timing diagram provided in an embodiment of this application for writing data into a memory cell array. For example... Figure 4 As shown, when performing a write operation on the memory cell array 101, the write enable signal W0_en is at a high level. Under the control of this write enable signal W0_en, the write control circuit 102 can load the first data DATA to be written onto the first bit line BT and load the second data DATA_n onto the second bit line BB. The second data DATA_n is obtained by inverting the first data DATA. Inverting the first data DATA means that if the level of the first data DATA is high, then the high level is converted to a low level; if the level of the first data DATA is low, then the low level is converted to a high level.
[0067] If data needs to be written to any SRAM cell in the memory cell array 101, the WL connected to that SRAM cell can be set to a high level. The two control switches in the SRAM cell can then be turned on under the control of WL, and the first data loaded on the first bit line BT is written to the latch in the SRAM cell.
[0068] For example, refer to Figure 4When WL1 is set to high, the first data DATA is 0. At this time, the write control circuit 102 can pull down the level of node d1 in SRAM cell 1 to low and pull up the level of node d1_n to high, thereby writing the first data 0 into SRAM cell 1. When WL2 is set to high, the first data DATA is 1. At this time, the write control circuit 102 can pull up the level of node d2 in SRAM cell 2 to high and pull down the level of node d2_n to low, thereby writing the first data 1 into SRAM cell 2.
[0069] As the storage capacity of SRAM 100 increases, the number of SRAM cells included in the memory cell array 101 also increases, leading to a larger capacitive load on the first bit line BT and the second bit line BB. Since each write operation to an SRAM cell requires setting either the first bit line BT or the second bit line BB to a high level, if the data to be written in two adjacent write operations is different, the level on either the first bit line BT or the second bit line BB needs to be changed from low to high. When the capacitive load on the first bit line BT and the second bit line BB is large, a significant amount of power is required to pull the level on a bit line from low to high.
[0070] Figure 5 This is a schematic diagram of a memory structure provided in an embodiment of this application. The memory is an SRAM, and the application addresses the technical problem of high power consumption required when driving bit lines during data writing. (Reference) Figure 5 The SRAM 100 includes: a memory cell array 101, a write control circuit 102, a detection control circuit 103, and a switching circuit 104.
[0071] refer to Figure 2 The memory cell array 101 includes multiple SRAM cells coupled to different word lines, and each of the multiple SRAM cells is also connected to the first bit line BT and the second bit line BB.
[0072] The write control circuit 102 is connected to the first bit line BT and the second bit line BB respectively. When the write control circuit 102 is in the working state, it loads the first data DATA to be written to the first bit line BT and loads the second data DATA_n obtained by inverting the first data to the second bit line BB.
[0073] The detection control circuit 103 is connected to the write control circuit 102 and the switch circuit 104, respectively. The switch circuit 104 is also connected to the first bit line BT and the second bit line BB, respectively. The detection control circuit 103 is used to control the switch circuit 104 to connect the first bit line BT and the second bit line BB, and to control the write control circuit 102 to stop working if a level change of the first data DATA is detected.
[0074] Understandably, during a write operation to an SRAM cell in the memory cell array 101, one of the levels of the first data DATA loaded on the first bit line BT and the second data DATA_n loaded on the second bit line BB is high, while the other is low. If the detection control circuit 103 detects a change in the level of the first data DATA, it can determine that the level on one of the bit lines, the first bit line BT and the second bit line BB, needs to change from low to high.
[0075] In the solution provided in this application embodiment, when the detection control circuit 103 detects a level change in the first data DATA, it can control the switching circuit 104 to connect the first bit line BT and the second bit line BB. Therefore, the charge on these two bit lines will shift until their levels are equal. For example, assuming a high level is VDD and a low level is 0, after the first bit line BT and the second bit line BB are connected, the levels on the two bit lines will eventually stabilize at VDD / 2. Furthermore, since the detection control circuit 103 can control the write control circuit 102 to stop working during the connection of the first bit line BT and the second bit line BB, the write control circuit 102 does not need to drive the first bit line BT and the second bit line BB.
[0076] It is also understandable that after the level of the first bit line BT equals the level of the second bit line BB, the detection control circuit 103 can also control the switching circuit 104 to disconnect the connection between the first bit line BT and the second bit line BB, and control the write control circuit 102 to return to the working state. After the write control circuit 102 returns to the working state, it can continue to drive the first bit line BT and the second bit line BB. For example, the write control circuit 102 can pull up the level of one bit line, the first bit line BT, to VDD from VDD / 2, and pull down the level of the other bit line from VDD / 2 to 0.
[0077] Based on the above analysis, when the level of the first data DATA changes, the detection control circuit 103 controls the switching circuit 104 to connect the first bit line BT and the second bit line BB. This allows the bit line that is at a high level between the first bit line BT and the second bit line BB to pull up the level of the other bit line through charge redistribution. For example, the level of the other bit line can be pulled up from 0 to VDD / 2. Then, the write control circuit 102 continues to drive the other bit line to pull up the level of the other bit line to VDD. This effectively reduces the power consumption required by the write control circuit 102 when driving the bit line.
[0078] In summary, this application provides a memory comprising a memory cell array, a write control circuit, a detection control circuit, and a switching circuit. The switching circuit is connected to a first bit line and a second bit line, respectively. When the detection control circuit detects a level change in the first data to be written to the memory cell array, it controls the switching circuit to connect the first bit line and the second bit line, and controls the write control circuit to stop operating. Therefore, a high-level bit line can pull up the level of the other bit line through charge redistribution. This charge redistribution process does not require driving by the write control circuit, thus effectively reducing the power consumption required to drive the bit lines.
[0079] Figure 6 This is a schematic diagram of a detection control circuit provided in an embodiment of this application. Figure 6 As shown, the detection control circuit 103 may include a detection sub-circuit 1031 and a control sub-circuit 1032.
[0080] The input terminal of the detection sub-circuit 1031 is used to receive the first data DATA, and the output terminal of the detection sub-circuit 1031 is connected to the first input terminal of the control sub-circuit 1032 and the switch circuit 104, respectively. Figure 6 The first control terminal (not shown) is connected. The detection sub-circuit 1031 is used to output a pulse signal eq_en if a level change of the first data DATA is detected. Since the detection sub-circuit 1031 can detect whether the level of the first data DATA has changed, that is, whether a changing edge has occurred, it can also be called an edge detection circuit.
[0081] The second input terminal of the control sub-circuit 1032 is used to receive the write enable signal W0_en, and the output terminal of the control sub-circuit 1032 is connected to the write control circuit 102. Figure 6The control terminal (not shown) is connected. The control sub-circuit 1032 is used to output a de-enable signal to stop the write control circuit 102 from working when the pulse signal eq_en is at the first level, and to output the write enable signal W0_en when the pulse signal eq_en is at the second level.
[0082] refer to Figure 6 In this embodiment, the signal output by the control sub-circuit 1032 is represented as W1_en. Based on the above analysis, it can be seen that when the pulse signal eq_en is at the first level, the level of the signal W1_en output by the control sub-circuit 1032 is an invalid level, for example, it can be a low level. This invalid level signal W1_en can stop the write control circuit 102 from working, and therefore can be called a de-enable signal.
[0083] When the pulse signal eq_en is at the second level, the level of the signal W1_en output by the control sub-circuit 1032 is equal to the level of the write enable signal W0_en. This second level can be either low or high relative to the first level.
[0084] The first terminal of the switching circuit 104 is connected to the first bit line BT, and the second terminal of the switching circuit 104 is connected to the second bit line BB. The switching circuit 104 is used to turn on its first terminal and the second terminal when the pulse signal eq_en is at the first level, and to turn off its first terminal and the second terminal when the pulse signal eq_en is at the second level.
[0085] Understandably, the switching circuit 104, based on the pulse signal eq_en at the first level, connects its first and second terminals, thus connecting the first bit line BT and the second bit line BB. At this time, the bit line BT at a high level among the first and second bit lines BB can pull the level of the other bit line high through charge redistribution. Furthermore, since the signal W1_en output by the control sub-circuit 1032 is a de-enable signal during this charge redistribution process, it can stop the write control circuit 102 from operating, thereby effectively reducing the power consumption of the write control circuit 102 when driving the bit lines.
[0086] It is also understandable that after the switching circuit 104 turns off its first and second terminals based on the pulse signal eq_en at the second level, the connection between the first bit line BT and the second bit line BB is broken. At this time, since the signal W1_en output by the control sub-circuit 1032 is the write enable signal W0_en, the write control circuit 102 can be restarted to continue pulling up the level on the other bit line to the target level.
[0087] For example, assuming that during the first stage of the pulse signal eq_en, a high-level bit line can pull up the level of another bit line from 0 to VDD / 2 through charge redistribution, then during the second stage of the pulse signal eq_en, the write control circuit 102 only needs to continue pulling up the level of that other bit line from VDD / 2 to the target level VDD. This saves approximately half of the drive power consumption.
[0088] In this embodiment, the duration of the pulse signal eq_en at the first level, i.e., the pulse width of the pulse signal eq_en, can be flexibly adjusted according to the needs of the application scenario. It is only necessary to ensure that the pulse width is sufficient to balance the charge on the first bit line BT and the second bit line BB (i.e., the levels on the two bit lines are equal).
[0089] Figure 7 This is a schematic diagram of a detection sub-circuit provided in an embodiment of this application. For example... Figure 7 As shown, the detection sub-circuit 1031 may include a delay sub-circuit 31a and a comparison sub-circuit 31b.
[0090] The input terminal of the delay sub-circuit 31a is used to receive the first data DATA, and the output terminal of the delay sub-circuit 31a is connected to the first input terminal of the comparison sub-circuit 31b. The delay sub-circuit 31a is used to delay the first data DATA before outputting it.
[0091] The second input terminal of the comparator circuit 31b is used to receive the first data DATA. The output terminal of the comparator circuit 31b is connected to the first input terminal of the control circuit 1032 and the first control terminal of the switch circuit 104, respectively. If the level of the two input terminals of the comparator circuit 31b is detected to be different, the comparator circuit 31b outputs a pulse signal eq_en.
[0092] Understandably, if the levels at the two input terminals of the comparator circuit 31b are different, it indicates that the level of the first data DATA has changed. Therefore, the comparator circuit 31b can output a pulse signal eq_en to indicate this level change. Furthermore, if the levels at the two input terminals of the comparator circuit 31b are the same, the level at the output terminal of the comparator circuit 31b can remain at the second level.
[0093] It is also understandable that the pulse width of the pulse signal eq_en can be related to the delay duration of the delay sub-circuit 31a. Accordingly, the delay duration of the delay sub-circuit 31a can be adjusted according to the requirements of the application scenario, thereby achieving flexible adjustment of the pulse width of the pulse signal eq_en.
[0094] In this embodiment, the delay sub-circuit 31a can be a resistor-capacitance (RC) delay circuit or a transistor delay circuit, etc.
[0095] Optionally, such as Figure 7 As shown, the comparator sub-circuit 31b may include: a first NOT gate NOT1, a first NOR gate NOR1, a NAND gate NAND1, a second NOT gate NOT2, a second NOR gate NOR2, and a third NOT gate NOT3.
[0096] The input terminal of the first NOT gate NOT1 is connected to the output terminal of the delay sub-circuit 31a, and the output terminal of the first NOT gate NOT1 is connected to the first input terminal of the first NOR gate NOR1 and the first input terminal of the NAND gate NAND1.
[0097] The second input of the first NOR gate NOR1 and the second input of the NAND gate NAND1 are both used to receive the first data DATA. The output of the first NOR gate NOR1 is connected to the first input of the second NOR gate NOR2, the output of the NAND gate NAND1 is connected to the input of the second NOT gate NOT2, and the output of the second NOT gate NOT2 is connected to the second input of the second NOR gate NOR2.
[0098] The output of the second NOR gate NOR2 is connected to the input of the third NOT gate NOT3, and the output of the third NOT gate NOT3 is connected to the first input of the control sub-circuit 1032 and the first control terminal of the switch circuit 104. The output of the third NOT gate NOT3 is used to output a pulse signal eq_en to the control sub-circuit 1032 and the switch circuit 104.
[0099] Table 1 is the truth table of comparator circuit 31b, where a value of 1 represents a high level and a value of 0 represents a low level. IN1 and IN2 represent the levels of the two input terminals of comparator circuit 31b. Referring to Table 1, when both input terminals of comparator circuit 31b are either low (0) or both are high (1), the output of the third NOT gate is low (0). When the level of the first data DATA changes, causing a difference in the levels of the two input terminals of comparator circuit 31b, the output of the third NOT gate is high (1), meaning the third NOT gate can output the pulse signal eq_en.
[0100] Table 1
[0101] IN1 IN2 NOT1 NAND1 NOT2 NOR1 NOR2 NOT3 0 0 1 1 0 0 1 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0
[0102] Understandable, Figure 7The comparator circuit 31b shown is merely an illustration. It can also be implemented using combinations of other logic devices, as long as it ensures that a pulse signal is output when the levels of the two input terminals are different. For example, the comparator circuit 31b may also omit the first NOT gate (NOT1) and the third NOT gate (MOT3).
[0103] Figure 8 This is a schematic diagram of a switching circuit provided in an embodiment of this application. Figure 8 As shown, the switching circuit 104 may include a first transistor T1. The gate of the first transistor T1 may be connected to the output terminal of the detection sub-circuit 1031. For example, the gate of the first transistor T1 may be connected to the output terminal of the comparator sub-circuit 31b in the detection sub-circuit 1031, and may receive the pulse signal eq_en output by the detection sub-circuit 1031. The first terminal of the first transistor T1 is connected to the first bit line BT, and the second terminal of the first transistor T1 is connected to the second bit line BB. The first terminal of the first transistor T1 may be one of the source and drain terminals, and the second terminal may be the other of the source and drain terminals.
[0104] Optionally, refer to Figure 8 In (a) of the above, the first transistor T1 can be an N-type transistor. Correspondingly, the first level of the pulse signal eq_en output by the detection sub-circuit 1031 can be high relative to the second level. The first transistor T1 can be turned on under the drive of this high level, thereby connecting the first bit line BT and the second bit line BB. Alternatively, the first transistor T1 can be a P-type transistor. Correspondingly, the first level of the pulse signal eq_en output by the detection sub-circuit 1031 can be low relative to the second level. The first transistor T1 can be turned on under the drive of this low level, thereby connecting the first bit line BT and the second bit line BB.
[0105] Optionally, the switching circuit 104 may also have a second control terminal. When the first control terminal is at a first level and the second control terminal is at a second level, the switching circuit 104 can connect its first and second terminals. Furthermore, the switching circuit 104 can disconnect its first and second terminals when the first control terminal is at a second level and the second control terminal is at a first level. (Continue to refer to...) Figure 6 The detection control circuit 103 may also include an inverting sub-circuit 1033.
[0106] The input terminal of the inverting sub-circuit 1033 is connected to the output terminal of the comparator sub-circuit 31b, and the output terminal of the inverting sub-circuit 1033 is connected to the second control terminal of the switching circuit 104. The inverting sub-circuit 1033 is used to invert the pulse signal eq_en and then output it.
[0107] Optionally, such as Figure 6 As shown, the inverter sub-circuit 1033 may include a fourth NOT gate, NOT4. Of course, the inverter sub-circuit 1033 may also be implemented in other ways, such as including multiple NOT gates connected in series, which is not limited in this embodiment.
[0108] Understandably, when the pulse signal eq_en output by the comparator circuit 31b is at the first level, the signal eq_en_n output by the inverting circuit 1033 to the second control terminal of the switching circuit 104 is at the second level. Conversely, when the pulse signal eq_en output by the comparator circuit 31b is at the second level, the signal eq_en_n output by the inverting circuit 103 to the second control terminal of the switching circuit 104 is at the first level. This ensures that the levels applied by the detection control circuit 103 to the two control terminals of the switching circuit 104 are opposite.
[0109] It is also understandable that the detection control circuit 103 may not need to include the inverter sub-circuit 1033. Furthermore, as... Figure 7 As shown, the output of the second NOR gate NOR2 in the comparator circuit 31b of the detection control circuit 103 can also be connected to the second control terminal of the switching circuit 104, and can output the signal eq_en_n to the second control terminal.
[0110] Optionally, refer to Figure 8 In (b), the gate of the first transistor T1 can be connected to the output of the inverter sub-circuit 1033 and can receive the signal eq_en_n output by the inverter sub-circuit 1033. For example, the first transistor T1 can be a P-type transistor, which can be turned on when the signal eq_en_n output by the inverter sub-circuit 1033 is low, thereby connecting the first bit line BT and the second bit line BB.
[0111] For the case where the switching circuit 104 also has a second control terminal, refer to... Figure 9 The switching circuit 104 may further include a second transistor T2. The polarity of the second transistor T2 is opposite to that of the first transistor T1, for example, Figure 9 In the switch circuit 104 shown, the first transistor T1 is a P-type transistor and the second transistor T2 is an N-type transistor.
[0112] In this circuit, the gate of the first transistor T1 is connected to the output terminal of the inverting sub-circuit 1033 in the detection and control circuit 103, and the gate of the second transistor T2 is connected to the output terminal of the comparator sub-circuit 31b in the detection and control circuit 103. The first terminal of the second transistor T2 is connected to the first bit line BT, and the second terminal of the second transistor T2 is connected to the second bit line BB.
[0113] When the pulse signal eq_en output by the comparator circuit 31b is at the first level and the signal eq_en_n output by the inverter circuit 1033 is at the second level, both the first transistor T1 and the second transistor T2 are turned on, thereby connecting the first bit line BT and the second bit line BB. When the pulse signal eq_en output by the comparator circuit 31b is at the second level and the signal eq_en_n output by the inverter circuit 1033 is at the first level, both the first transistor T1 and the second transistor T2 are turned off, thereby disconnecting the first bit line BT from the second bit line BB.
[0114] based on Figure 9 The implementation shown can effectively improve the reliability of the switching circuit 104 during operation because the switching circuit 104 includes two transistors.
[0115] It is understandable that both the first transistor T1 and the second transistor T2 mentioned above can be metal-oxide-semiconductor field-effect transistors (MOSFETs). It is also understandable that the switching circuit 104 can, in addition to using… Figure 8 or Figure 9 The method shown can be used to implement this, but other methods can also be employed. For example, the switching circuit 104 may include multiple transistors connected in series or in parallel.
[0116] Optionally, such as Figure 6 As shown, the control sub-circuit 1032 may include: a fifth NOT gate (NOT5) and a third NOR gate (NOR3).
[0117] The input of the fifth NOT gate (NOT5) is used to receive the write enable signal W0_en, and the output of the fifth NOT gate (NOT5) is connected to the first input of the third NOR gate (NOR3).
[0118] The second input terminal of the third NOR gate NOR3 is connected to the output terminal of the detection sub-circuit 1031 and is used to receive the pulse signal eq_en. The output terminal of the third NOR gate NOR3 is connected to the control terminal of the write control circuit 102.
[0119] Table 2 is the truth table of control sub-circuit 1032. Table 2 illustrates the case where the pulse signal eq_en has a high level (i.e., value 1) and a low level (i.e., value 0) at its first level, and the de-enable signal written to control circuit 102 is a low level. Referring to Table 2, when the pulse signal eq_en is high, regardless of whether the write enable signal W0_en is high or low, the signal W1_en output by control sub-circuit 1032 is low. That is, when the pulse signal eq_en is high, control sub-circuit 1032 can output a de-enable signal. When the pulse signal eq_en is low, the level of the signal W1_en output by control sub-circuit 1032 is the same as the level of the write enable signal W0_en. That is, when the pulse signal eq_en is high, the signal W1_en output by control sub-circuit 1032 is the write enable signal W0_en.
[0120] Table 2
[0121]
[0122]
[0123] Figure 10 This is a schematic diagram of a write control circuit provided in an embodiment of this application. For example... Figure 10 As shown, the write control circuit 102 may include: a sixth NOT gate (NOT6), a first tri-state gate (Tr1), and a second tri-state gate (Tr2). The tri-state gate can also be called a tri-state buffer.
[0124] The inputs of the sixth NOT gate (NOT6) and the first tri-state gate (Tr1) are both used to receive the first data DATA. The output of the sixth NOT gate (NOT6) is connected to the input of the second tri-state gate (Tr2). The sixth NOT gate (NOT6) is used to invert the level of the first data DATA to obtain the second data DATA_n, and then outputs the second data DATA_n to the second tri-state gate (Tr2).
[0125] The control terminals of the first tri-state gate Tr1 and the second tri-state gate Tr2 are both connected to the output terminal of the detection control circuit 103 and are used to receive the signal W1_en output by the detection control circuit 103. The output terminal of the first tri-state gate Tr is connected to the first bit line BT, and the output terminal of the second tri-state gate Tr2 is connected to the second bit line BB.
[0126] In this embodiment, when the signal W1_en output by the detection control circuit 103 is a de-enable signal, both the first tri-state gate Tr1 and the second tri-state gate Tr2 are closed. At this time, the first data DATA cannot be loaded onto the first bit line BT through the first tri-state gate Tr1, and the second data DATA_n cannot be loaded onto the second bit line BB through the second tri-state gate Tr2. When the signal W1_en output by the detection control circuit 103 is a write enable signal W0_en, and the level of the write enable signal W0_en is an active level (e.g., high level), both the first tri-state gate Tr1 and the second tri-state gate Tr2 are turned on. At this time, the first data DATA can be loaded onto the first bit line BT through the first tri-state gate Tr1, and the second data DATA_n can be loaded onto the second bit line BB through the second tri-state gate Tr2.
[0127] It is understood that the first data DATA and the write enable signal W0_en mentioned above can both be provided by the peripheral circuitry of the memory. For example, they can be provided by the memory controller 200.
[0128] In summary, this application provides a memory comprising a memory cell array, a write control circuit, a detection control circuit, and a switching circuit. The switching circuit is connected to a first bit line and a second bit line, respectively. When the detection control circuit detects a level change in the first data to be written to the memory cell array, it controls the switching circuit to connect the first bit line and the second bit line, and controls the write control circuit to stop operating. Therefore, a high-level bit line can pull up the level of the other bit line through charge redistribution. This charge redistribution process does not require driving by the write control circuit, thus effectively reducing the power consumption required to drive the bit lines.
[0129] Figure 11 This is a flowchart illustrating a data writing method for a memory according to an embodiment of this application. This method can be applied to the memory provided in the above embodiment. Figure 11 As shown, the method includes:
[0130] Step 201: Load the first data to be written onto the first bit line, and load the second data obtained by inverting the first data onto the second bit line.
[0131] In this embodiment of the application, if the signal W1_en received by the write control circuit 102 is at an active level, the write control circuit 102 can load the first data DATA to be written onto the first bit line BT, and load the second data DATA_n obtained by inverting the first data DATA onto the second bit line BB.
[0132] Step 202: If a level change in the first data is detected, connect the first bit line to the second bit line and stop loading data onto the first bit line and the second bit line.
[0133] In this embodiment, the detection control circuit 103 can detect the level of the first data DATA. If a level change in the first data DATA is detected, the detection control circuit 103 can control the first and second terminals of the switching circuit 104 to be turned on, thereby connecting the first bit line BT and the second bit line BB. At the same time, the signal W1_en output by the detection control circuit 103 to the write control circuit 102 is an invalid level (i.e., a de-enable signal), and the write control circuit 102 stops working and cannot continue to load data onto the first bit line BT and the second bit line BB.
[0134] Continue to refer to Figure 11 The method may also include:
[0135] Step 203: After the level of the first bit line is equal to the level of the second bit line, disconnect the connection between the first bit line and the second bit line, and continue to load the first data onto the first bit line and continue to load the second data onto the second bit line.
[0136] After the first bit line BT and the second bit line BB are connected, the bit line that is at a high level in the first bit line BT and the second bit line BB can pull up the level of the other bit line through charge redistribution until the levels on the two bit lines are equal. After the levels on the two bit lines are equal, the detection control circuit 103 can control the first and second terminals of the switching circuit 104 to turn off, thereby disconnecting the connection between the first bit line BT and the second bit line BB. At the same time, the signal W1_en output by the detection control circuit 103 to the write control circuit 102 can be a write enable signal W0_en. The write control circuit 102 can restart under the drive of the write enable signal W0_en and continue to load data onto the first bit line BT and the second bit line BB.
[0137] For example, in this embodiment of the application, the detection control circuit 103 can control the first and second terminals of the switch circuit 104 to turn off after the connection duration of the first bit line BT and the second bit line BB reaches a target duration. The target duration can be a pre-configured duration in the detection control circuit 103, and the target duration can be greater than or equal to the duration required for the charges on the first bit line BT and the second bit line BB to reach equilibrium.
[0138] It is understood that, prior to step 201 above, the method may further include: loading a valid level write enable signal W0_en onto the detection control circuit 103 in the memory.
[0139] During the execution of step 201 above, the method may further include: applying an effective level (e.g., a high level) to the word line coupled to the SRAM cell to which the first data is to be written. This enables two control switches in the SRAM cell to be turned on, thereby writing the first data loaded on the first bit line BT to the latch in the SRAM cell.
[0140] The following text is incomplete and cannot be translated. Figure 12 Taking the timing diagram shown as an example, and using a high level for valid logic and a low level for invalid logic as an example, the flow of the data writing method provided in this application embodiment will be described. (Reference) Figure 12 Assuming that at time t1, the level of the first data DATA changes from high to low (i.e., the first data to be written is 0), the detection control circuit 103 can output a high-level pulse signal eq_en to the switching circuit 104 and a low-level signal W1_en to the write control circuit 102. At this time, the switching circuit 104 connects the first bit line BT and the second bit line BB. The first bit line BT pulls the level on the second bit line BB from 0 to VDD / 2 through charge redistribution. Furthermore, during this process, the write control circuit 102 stops working, thus consuming no power.
[0141] After the pulse signal eq_en output by the detection control circuit 103 remains high for a target duration Δt, the level of the pulse signal eq_en transitions to a low level. Correspondingly, the signal W1_en output by the detection control circuit 103 to the write control circuit 102 transitions to a high level. At this time, the switching circuit 104 disconnects the first bit line BT and the second bit line BB, and the write control circuit 102 is in operation, capable of pulling the level of the second bit line BB up from VDD / 2 to VDD, and pulling the level of the first bit line BT down from VDD / 2 to 0.
[0142] refer to Figure 12 Assuming that at time t2, the word line WL1 coupled to SRAM cell 1 in memory cell array 101 is at a high level, then the two control switches in SRAM cell 1 can be turned on. At this time, the first bit line BT can pull down the level of node d1 in SRAM cell 1 to a low level, thereby writing the first data 0 into SRAM cell 1.
[0143] Assuming that at time t3, the level of the first data DATA changes from low to high again (i.e., the first data to be written is 1), the detection control circuit 103 can again output a high-level pulse signal eq_en to the switching circuit 104, and can again output a low-level signal W1_en to the write control circuit 102. At this time, the switching circuit 104 connects the first bit line BT and the second bit line BB. The second bit line BB pulls the level on the first bit line BT from 0 to VDD / 2 through charge redistribution. Furthermore, during this process, the write control circuit 102 stops working, so it does not consume power.
[0144] Subsequently, when the level of the pulse signal eq_en jumps to low and the signal W1_en is high, the switching circuit 104 can disconnect the first bit line BT and the second bit line BB, the write control circuit 102 can resume its working state, and can pull up the level of the first bit line BT from VDD / 2 to VDD, and pull down the level of the second bit line BB from VDD / 2 to 0.
[0145] Continue to refer to Figure 12 Assuming that at time t4, the word line WL2 coupled to SRAM cell 2 in memory cell array 101 is at a high level, then the two control switches in SRAM cell 2 can be turned on. At this time, the first bit line BT can pull up the level of node d2 in SRAM cell 2 to a high level, thereby writing the first data 1 into SRAM cell 2. Assuming that at time t5, the word line WL3 coupled to SRAM cell 3 in memory cell array 101 is at a high level, then the two control switches in SRAM cell 3 can be turned on. At this time, the first bit line BT can pull up the level of node d3 in SRAM cell 3 to a high level, thereby writing the first data 1 into SRAM cell 3.
[0146] It is understood that the implementation process of the data writing method of the memory provided in the embodiments of this application can refer to the relevant description in the above-described memory embodiments, and will not be repeated here.
[0147] It is also understood that the order of steps in the data writing method for the memory provided in this application embodiment can be appropriately adjusted, and steps can be added or removed as needed. For example, after step 203 above, step 202 can be executed again as needed.
[0148] In summary, this application provides a data writing method for a memory. This method can connect the first bit line and the second bit line when a level transition of the first data to be written to the memory cell array is detected, and stop loading data onto the first and second bit lines. Therefore, the bit line at a high level in the first and second bit lines can pull the level of the other bit line high through charge redistribution. This charge redistribution process does not require a write control circuit to drive the bit lines, thus effectively reducing the power consumption required to drive the bit lines.
[0149] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "at least one" means one or more, and the term "multiple" means two or more, unless otherwise expressly defined.
[0150] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. The scope of protection of this application should be determined by the scope of the claims.
Claims
1. A memory (100), characterized in that, The memory (100) includes: a memory cell array (101), a write control circuit (102), a detection control circuit (103), and a switch circuit (104); The memory cell array (101) includes multiple static random access memory (100) SRAM cells coupled to different word lines, and each of the multiple SRAM cells is also connected to the first bit line (BT) and the second bit line (BB). The write control circuit (102) is connected to the first bit line (BT) and the second bit line (BB) respectively. When the write control circuit (102) is in the working state, it loads the first data (DATA) to be written to the first bit line (BT) and loads the second data (DATA_n) obtained by inverting the first data (DATA) to the second bit line (BB). The detection control circuit (103) is connected to the write control circuit (102) and the switch circuit (104) respectively. The switch circuit (104) is also connected to the first bit line (BT) and the second bit line (BB) respectively. The detection control circuit (103) is used to control the switch circuit (104) to connect the first bit line (BT) and the second bit line (BB) and control the write control circuit (102) to stop working if a level change of the first data (DATA) is detected.
2. The memory (100) according to claim 1, characterized in that, The detection control circuit (103) includes: a detection sub-circuit (1031) and a control sub-circuit (1032); The input terminal of the detection sub-circuit (1031) is used to receive the first data (DATA), and the output terminal of the detection sub-circuit (1031) is connected to the first input terminal of the control sub-circuit (1032) and the first control terminal of the switch circuit (104) respectively. The detection sub-circuit (1031) is used to output a pulse signal (eq_en) if a level change of the first data (DATA) is detected. The second input terminal of the control sub-circuit (1032) is used to receive the write enable signal (W0_en). The output terminal of the control sub-circuit (1032) is connected to the control terminal of the write control circuit (102). The control sub-circuit (1032) is used to output a de-enable signal to stop the write control circuit (102) from working when the pulse signal (eq_en) is at the first level, and to output the write enable signal (W0_en) when the pulse signal (eq_en) is at the second level. The first terminal of the switching circuit (104) is connected to the first bit line (BT), and the second terminal of the switching circuit (104) is connected to the second bit line (BB). The switching circuit (104) is used to turn on the first terminal and the second terminal when the pulse signal (eq_en) is at the first level, and to turn off the first terminal and the second terminal when the pulse signal (eq_en) is at the second level.
3. The memory (100) according to claim 2, characterized in that, The detection sub-circuit (1031) includes: a delay sub-circuit (31a) and a comparison sub-circuit (31b); The input terminal of the delay sub-circuit (31a) is used to receive the first data (DATA), and the output terminal of the delay sub-circuit (31a) is connected to the first input terminal of the comparison sub-circuit (31b). The delay sub-circuit (31a) is used to output the first data (DATA) after delaying it. The second input terminal of the comparator sub-circuit (31b) is used to receive the first data (DATA). The output terminal of the comparator sub-circuit (31b) is connected to the first input terminal of the control sub-circuit (1032) and the first control terminal of the switch circuit (104), respectively. If the level of the two input terminals of the comparator sub-circuit (31b) is detected to be different, the comparator sub-circuit (31b) outputs a pulse signal (eq_en).
4. The memory (100) according to claim 3, characterized in that, The comparator sub-circuit (31b) includes: a first NOT gate (NOT1), a first NOR gate (NOR1), a NAND gate (NAND1), a second NOT gate (NOT2), a second NOR gate (NOR2), and a third NOT gate (NOT3); The input terminal of the first NOT gate (NOT1) is connected to the output terminal of the delay sub-circuit (31a), and the output terminal of the first NOT gate (NOT1) is connected to the first input terminal of the first NOR gate (NOR1) and the first input terminal of the NAND gate (NAND1). The second input of the first NOR gate (NOR1) and the second input of the NAND gate (NAND1) are both used to receive the first data (DATA). The output of the first NOR gate (NOR1) is connected to the first input of the second NOR gate (NOR2). The output of the NAND gate (NAND1) is connected to the input of the second NOT gate (NOT2). The output of the second NOT gate (NOT2) is connected to the second input of the second NOR gate (NOR2). The output of the second NOR gate (NOR2) is connected to the input of the third NOT gate (NOT3), and the output of the third NOT gate (NOT3) is connected to the first input of the control sub-circuit (1032) and the first control terminal of the switch circuit (104).
5. The memory (100) according to claim 2, characterized in that, The switching circuit (104) also has a second control terminal; the detection control circuit (103) further includes: an inverting sub-circuit (1033); The input terminal of the inverting sub-circuit (1033) is connected to the output terminal of the comparator sub-circuit (31b) in the detection sub-circuit (1031), and the output terminal of the inverting sub-circuit (1033) is connected to the second control terminal of the switching circuit (104). The inverting sub-circuit (1033) is used to invert the pulse signal (eq_en) and output it. The switching circuit (104) is used to connect the first terminal and the second terminal when the first control terminal is at the first level and the second control terminal is at the second level, and to disconnect the first terminal and the second terminal when the first control terminal is at the second level and the first control terminal is at the first level.
6. The memory (100) according to claim 5, characterized in that, The inverter sub-circuit (1033) includes: a fourth NOT gate (NOT4).
7. The memory (100) according to claim 2, characterized in that, The control sub-circuit (1032) includes a fifth NOT gate (NOT5) and a third NOR gate (NOR3); The input of the fifth NOT gate (NOT5) is used to receive the write enable signal (W0_en), and the output of the fifth NOT gate (NOT5) is connected to the first input of the third NOR gate (NOR3). The second input terminal of the third NOR gate (NOR3) is connected to the output terminal of the detection sub-circuit (1031), and the output terminal of the third NOR gate (NOR3) is connected to the control terminal of the write control circuit (102).
8. The memory (100) according to claim 2, characterized in that, The switching circuit (104) includes: a first transistor (T1); The gate of the first transistor (T1) is connected to the output terminal of the detection sub-circuit (1031), the first electrode of the first transistor (T1) is connected to the first bit line (BT), and the second electrode of the first transistor (T1) is connected to the second bit line (BB).
9. The memory (100) according to claim 5, characterized in that, The switching circuit (104) includes: a first transistor (T1); The gate of the first transistor (T1) is connected to the output terminal of the inverter sub-circuit (1033), the first terminal of the first transistor (T1) is connected to the first bit line (BT), and the second terminal of the first transistor (T1) is connected to the second bit line (BB).
10. The memory (100) according to claim 9, characterized in that, The switching circuit (104) further includes: a second transistor (T2), the polarity of which is opposite to that of the first transistor (T1); The gate of the second transistor (T2) is connected to the output terminal of the detection sub-circuit (1031), the first terminal of the second transistor (T2) is connected to the first bit line (BT), and the second terminal of the second transistor (T2) is connected to the second bit line (BB).
11. The memory (100) according to any one of claims 1 to 10, characterized in that, The write control circuit (102) includes: a sixth NOT gate (NOT6), a first tri-state gate (Tr1), and a second tri-state gate (Tr2); The input terminals of the sixth NOT gate (NOT6) and the first tri-state gate (Tr1) are both used to receive the first data (DATA), and the output terminal of the sixth NOT gate (NOT6) is connected to the input terminal of the second tri-state gate (Tr2). The control terminal of the first tri-state gate (Tr1) is connected to the output terminal of the detection control circuit (103), and the output terminal of the first tri-state gate (Tr1) is connected to the first bit line (BT). The control terminal of the second tri-state gate (Tr2) is connected to the output terminal of the detection control circuit (103), and the output terminal of the second tri-state gate (Tr2) is connected to the second bit line (BB).
12. A method for writing data to a memory, characterized in that, The memory includes a memory cell array, the memory cell array including multiple static random access memory (SRAM) cells coupled to different word lines, and each of the multiple SRAM cells is also connected to a first bit line and a second bit line; the method includes: Load the first data to be written onto the first bit line, and load the second data obtained by inverting the first data onto the second bit line; If a level change in the first data is detected, the first bit line is connected to the second bit line, and data loading to the first bit line and the second bit line is stopped.
13. The method according to claim 12, characterized in that, The method further includes: After the level of the first bit line is equal to the level of the second bit line, the connection between the first bit line and the second bit line is turned off, and the first data is continued to be loaded onto the first bit line, and the second data is continued to be loaded onto the second bit line.
14. The method according to claim 12, characterized in that, Before loading the first data to be written onto the first bit line, the method further includes: A valid write enable signal is applied to the detection control circuit in the memory.
15. The method according to any one of claims 12 to 14, characterized in that, The method further includes: During the process of loading the first data to be written onto the first bit line, an effective level is applied to the word line coupled to the SRAM cell to which the first data is to be written.
16. A storage system (10), characterized in that, The storage system (10) includes: a memory controller (200), and at least one memory (100) as described in any one of claims 1 to 11.