Transceiver phase shifting for beamforming

Abstract

In a beamforming transmitter, a signal is constructed from multiple paths with defined phase shift relationships between them. A set of intermediate frequency beamforming signals is generated by introducing a phase shift based on the number of cycles of a higher frequency local oscillator signal used to upconvert the set of intermediate frequency signals. The set of intermediate frequency signals with defined phase shift relationships are then mixed with data signals such as in-phase / quadrature (I / Q) data signals and subsequently upconverted to generate a set of beamforming signals provided to an antenna array. A receiver using the same technique to generate a set of local oscillator signals is also proposed.

Description

Technical Field

[0001] The present disclosure generally relates to the architecture of a beamforming transceiver. Background Art

[0002] As the demand for mobile network data throughput increases, mobile networks can progress to higher frequencies for higher bandwidths, such as using 5G (fifth generation) frequency range 2 (FR2) from 24,250MHz to 52,600MHz or 30GHz to 300GHz or millimeter wave (mmWave) bands with wavelengths from 1mm to 10mm. Radio waves in these extremely high frequency radio bands are absorbed by gases in the atmosphere, and compared to lower frequency bands, millimeter waves have high atmospheric attenuation and relatively short propagation distances, resulting in high communication path losses in mmWave 5G mobile networks. Summary of the invention

[0003] According to one aspect of the present disclosure, a transmitter includes one or more frequency synthesizers, a plurality of intermediate frequency (IF) local oscillators, a plurality of first data signal mixers, and a plurality of up-conversion mixers. Each frequency synthesizer is configured to generate a corresponding radio frequency (RF) local oscillator signal. Each IF local oscillator is configured to: receive a first RF local oscillator signal among one or more RF local oscillator signals; receive a corresponding delay value among a plurality of delay values, each delay value specifying a delay of a plurality of cycles of the first RF local oscillator signal; and generate a first IF local oscillator signal by dividing the first RF local oscillator signal by an integer division ratio and shifting the first RF local oscillator signal by a corresponding delay value. Each first data signal mixer is configured to receive a first basic data signal and a corresponding first IF local oscillator signal among a plurality of first IF local oscillator signals, and generate a corresponding first IF data signal among a plurality of first IF data signals therefrom. Each up-conversion mixer is configured to receive a second RF local oscillator signal of the one or more RF local oscillator signals and a corresponding first IF data signal of the plurality of first IF data signals and generate therefrom a beamformed RF antenna signal of the plurality of beamformed RF antenna signals.

[0004] Optionally, in the aforementioned aspect, each of the plurality of IF local oscillators is further configured to generate a second IF local oscillator signal by dividing the second RF local oscillator signal by an integer division ratio and shifting the corresponding delay value, and the first IF local oscillator signal and the second IF local oscillator signal form an in-phase / quadrature IF local oscillator signal pair. The transmitter may further include: a plurality of second data signal mixers, each second data signal mixer configured to receive the second basic data signal and the corresponding second IF local oscillator signal in the plurality of second IF local oscillator signals, and generate therefrom a corresponding second IF data signal in the plurality of second IF data signals. The first basic data signal and the second basic data signal are an in-phase / quadrature pair, and the plurality of first IF data signals and the plurality of second IF data signals are a plurality of in-phase / quadrature IF data signal pairs. The plurality of up-conversion mixers are each further configured to receive a corresponding second signal in the plurality of first IF data signals, and a plurality of beamforming RF antenna signals are formed by the combined in-phase / quadrature IF data signal pairs.

[0005] Optionally, in any of the preceding aspects, the transmitter further comprises: one or more control circuits configured to provide a plurality of delay values ​​to the IF local oscillator.

[0006] Optionally, in any of the aforementioned aspects, the transmitter further comprises: a plurality of amplifiers connected to receive and amplify corresponding beamforming RF antenna signals among the plurality of beamforming RF antenna signals.

[0007] Optionally, in any of the foregoing aspects, the one or more control circuits are further configured to provide a plurality of delay values ​​to the IF local oscillator and provide a corresponding gain factor to each of the plurality of amplifiers, each amplifier being configured to amplify a received beamformed RF antenna signal of the plurality of beamformed RF antenna signals according to the corresponding gain factor.

[0008] Optionally, in any of the aforementioned aspects, the transmitter further comprises: a plurality of RF filters, each RF filter being configured to receive and filter a corresponding beamforming RF antenna signal among the plurality of beamforming RF antenna signals.

[0009] Optionally, in any of the aforementioned aspects, the transmitter further comprises: an array of multiple antennas, each antenna being configured to receive and transmit a corresponding beamformed RF antenna signal among the multiple beamformed RF antenna signals.

[0010] Optionally, in any of the aforementioned aspects, the number of frequency synthesizers is one, and the first RF local oscillator signal is the same as the second RF local oscillator signal.

[0011] Optionally, in any preceding aspect, the one or more frequency synthesizers include a first frequency synthesizer configured to provide a first RF local oscillator signal and a second frequency synthesizer configured to provide a second RF local oscillator signal.

[0012] Optionally, in any preceding aspect, each delay value specifies a delay of an integer number of cycles.

[0013] Optionally, in any preceding aspect, each delay value specifies a delay of half an integer number of cycles.

[0014] According to another aspect of the present disclosure, a method for transmitting a beamforming signal is provided. The method includes: receiving a first radio frequency (RF) local oscillator signal and a corresponding delay value in a plurality of delay values ​​at each of a plurality of intermediate frequency (IF) local oscillators, each delay value specifying a delay of a plurality of cycles of the first RF local oscillator signal; generating a first IF local oscillator signal by dividing the first RF local oscillator signal by an integer division ratio and shifting the first RF local oscillator signal by a corresponding delay value at each of a plurality of first data signal mixers; receiving a first base data signal and a corresponding first IF local oscillator signal in a plurality of first IF local oscillator signals at each of a plurality of first data signal mixers. Each first data signal mixer generates a first IF data signal from the first base data signal and a corresponding first IF local oscillator signal in a plurality of first IF local oscillator signals. Receiving a second RF local oscillator signal and a corresponding first IF data signal in a plurality of first IF data signals at each of a plurality of up-conversion mixers. Each upconversion mixer generates a corresponding beamforming RF antenna signal from the second RF local oscillator signal and a corresponding first IF data signal of the plurality of first IF data signals.

[0015] Optionally, in the aforementioned aspect, the method further comprises: exchanging one or more control signals between the transmitter controller and the receiver; determining, by the transmitter controller, a delay value from the exchanged control signals; and providing the determined delay value from the transmitter controller to the IF local oscillator.

[0016] Optionally, in any of the preceding aspects, the determining of the delay value comprises calculating the delay value by the transmitter controller based on the exchanged control signals.

[0017] Optionally, in any of the two aforementioned aspects, the determining of the delay value comprises receiving the delay value from the receiver in an exchanged control signal.

[0018] Optionally, in any of the three aforementioned aspects, the method further includes: receiving a corresponding beamforming RF antenna signal and a corresponding gain factor among a plurality of beamforming RF antenna signals at each amplifier among a plurality of amplifiers; amplifying a corresponding beamforming RF antenna signal among a plurality of beamforming RF antenna signals according to the gain factor at each amplifier; determining the gain factor by a transmitter controller according to an exchanged control signal; and providing the determined gain factor from the transmitter controller to an IF local oscillator.

[0019] Optionally, in any of the aforementioned aspects of the method for transmitting a beamforming signal, the method further comprises: generating a second IF local oscillator signal at each IF local oscillator by dividing the second RF local oscillator signal by an integer division ratio and shifting the second RF local oscillator signal by a corresponding delay value, the first IF local oscillator signal and the second IF local oscillator signal forming an in-phase / quadrature IF local oscillator signal pair; receiving a second basic data signal and a corresponding second IF local oscillator signal from the second basic data signal and the second IF local oscillator signal from the plurality of second data signal mixers; each second data signal mixer generates a second IF local oscillator signal from the second basic data signal and the plurality of second IF local oscillator signals; A corresponding second IF local oscillator signal among the two IF local oscillator signals generates a second IF data signal, wherein the first basic data signal and the second basic data signal are an in-phase / quadrature pair, and multiple first IF data signals and multiple second IF data signals are multiple in-phase / quadrature IF data signal pairs; and a combined in-phase / quadrature IF data signal pair is formed, wherein the generation of a corresponding beamforming RF antenna signal from the second RF local oscillator signal and the corresponding first IF data signal among the multiple first IF data signals by each up-conversion mixer includes generating a corresponding beamforming RF antenna signal from the corresponding combined in-phase / quadrature IF data signal pair among the combined in-phase / quadrature IF data signal pairs.

[0020] Optionally, in any of the aforementioned aspects of the method of transmitting a beamforming signal, the method further includes: each RF filter of a plurality of RF filters filtering a corresponding beamforming RF antenna signal of a plurality of beamforming RF antenna signals.

[0021] Optionally, in any of the aforementioned aspects of the method for transmitting a beamforming signal, the method further includes: each antenna of a plurality of antennas transmitting a corresponding beamforming RF antenna signal of a plurality of beamforming RF antenna signals.

[0022] Optionally, in any of the aforementioned aspects of the method of transmitting a beamformed signal, the first RF local oscillator signal is the same as the second RF local oscillator signal.

[0023] According to additional aspects of the present disclosure, a receiver includes: one or more frequency synthesizers; a plurality of intermediate frequency (IF) local oscillators; a plurality of down-conversion mixers; and a plurality of first data signal mixers. The frequency synthesizers are each configured to generate a corresponding radio frequency (RF) local oscillator signal. Each IF local oscillator is configured to: receive a first RF local oscillator signal from among the one or more RF local oscillator signals; receive a corresponding delay value from among a plurality of delay values, each delay value specifying a delay of a plurality of cycles of the first RF local oscillator signal; and generate a first IF local oscillator signal by dividing the first RF local oscillator signal by an integer division ratio and shifting the first RF local oscillator signal by a corresponding delay value. Each down-conversion mixer is configured to receive a second RF local oscillator signal among the one or more RF local oscillator signals and an RF antenna signal among the multiple RF antenna signals, and generate therefrom a corresponding first IF data signal among the multiple first IF data signals; and each first data signal mixer is configured to receive a corresponding first IF data signal among the multiple first IF data signals and a corresponding first IF local oscillator signal among the multiple first IF local oscillator signals, and generate therefrom a first basic data signal.

[0024] Optionally, in any of the aforementioned aspects, each IF local oscillator is further configured to generate a second IF local oscillator signal by dividing the second RF local oscillator signal by an integer division ratio and shifting a corresponding delay value, and the first IF local oscillator signal and the second IF local oscillator signal form an in-phase / quadrature IF local oscillator signal pair. The receiver further includes: a plurality of second data signal mixers, each second data signal mixer is configured to receive a corresponding second IF data signal among the plurality of second IF data signals and a corresponding first IF local oscillator signal among the plurality of first IF local oscillator signals, and generate a second basic data signal therefrom, and the first basic data signal and the second basic data signal form a plurality of in-phase / quadrature basic data signal pairs.

[0025] Optionally, in any of the aforementioned aspects of the receiver, the receiver further comprises: one or more control circuits configured to provide a plurality of delay values ​​to the IF local oscillator.

[0026] Optionally, in any of the foregoing aspects of the receiver, the receiver further comprises: a plurality of amplifiers connected to receive and amplify corresponding RF antenna signals among the plurality of RF antenna signals, and to provide each amplified RF antenna signal to a corresponding down-conversion mixer among the plurality of down-conversion mixers.

[0027] Optionally, in any of the aforementioned aspects, one or more control circuits are further configured to provide multiple delay values ​​to the IF local oscillator and provide corresponding gain factors to each of the multiple amplifiers, wherein each amplifier is configured to amplify a received RF antenna signal among the multiple RF antenna signals according to the corresponding gain factor.

[0028] Optionally, in any of the aforementioned aspects of the receiver, the receiver further comprises: a plurality of RF filters, each RF filter being configured to receive and filter a corresponding RF antenna signal among the plurality of RF antenna signals.

[0029] Optionally, in any of the aforementioned aspects of the receiver, the receiver further comprises: an array of a plurality of antennas, each antenna being configured to receive an RF signal and provide the RF signal to a plurality of down-conversion mixers.

[0030] Optionally, in any of the aforementioned aspects of the receiver, the number of frequency synthesizers is one, and the first RF local oscillator signal is the same as the second RF local oscillator signal.

[0031] Optionally, in any of the aforementioned aspects of the receiver, the one or more frequency synthesizers include a first frequency synthesizer configured to provide a first RF local oscillator signal and a second frequency synthesizer configured to provide a second RF local oscillator signal.

[0032] Optionally, in any preceding aspect of the receiver, each delay value specifies a delay of an integer number of cycles.

[0033] Optionally, in any preceding aspect of the receiver, each delay value specifies a delay of half an integer number of cycles.

[0034] According to another aspect of the present disclosure, a method for receiving a radio frequency (RF) signal is provided, comprising: receiving a first intermediate frequency (IF) local oscillator signal and a corresponding delay value among a plurality of delay values ​​at each IF local oscillator among a plurality of IF local oscillators, each delay value specifying a delay of a plurality of cycles of the first RF local oscillator signal; generating the first IF local oscillator signal by each IF local oscillator by dividing the first RF local oscillator signal by an integer division ratio and shifting the first RF local oscillator signal by a corresponding delay value; receiving a second RF local oscillator signal and a corresponding RF antenna signal among a plurality of RF antenna signals at each down-conversion mixer among a plurality of IF local oscillators; and A corresponding first IF data signal among a plurality of first IF data signals is generated at each of the plurality of down-conversion mixers from a second RF local oscillator signal and a corresponding RF antenna signal; a corresponding first IF data signal among a plurality of first IF data signals and a corresponding first IF local oscillator signal among a plurality of first IF local oscillator signals are received at each of the plurality of first data signal mixers; and a first basic data signal is generated at each of the plurality of first data signal mixers from a corresponding first IF data signal among a plurality of first IF data signals and a corresponding first IF local oscillator signal among a plurality of first IF local oscillator signals.

[0035] Optionally, in any of the foregoing aspects of the method for receiving an RF signal, the method further includes: exchanging one or more control signals between a receiver controller and a transmitter; determining, by the receiver controller, a delay value from the exchanged control signals; and providing the determined delay value from the receiver controller to an IF local oscillator.

[0036] Optionally, in any of the aforementioned aspects of the method of receiving an RF signal, the determining of the delay value comprises calculating the delay value by the receiver controller according to the exchanged control signal.

[0037] Optionally, in any of the two aforementioned aspects of the method of receiving an RF signal, the determining of the delay value comprises receiving the delay value from the transmitter in an exchanged control signal.

[0038] Optionally, in any of the aforementioned three aspects of the method for receiving an RF signal, the method further includes: receiving a corresponding RF antenna signal and a corresponding gain factor among a plurality of RF antenna signals at each amplifier among a plurality of amplifiers; amplifying a corresponding RF antenna signal among a plurality of RF antenna signals according to the gain factor at each amplifier; a receiver controller determining the gain factor according to the exchanged control signal; and providing the determined gain factor from the receiver controller to the IF local oscillator.

[0039] Optionally, in any of the aforementioned aspects of the method for receiving an RF signal, the method further includes: each IF local oscillator generates a second IF local oscillator signal by dividing the second RF local oscillator signal by an integer division ratio and shifting a corresponding delay value, the first IF local oscillator signal and the second IF local oscillator signal forming an in-phase / quadrature IF local oscillator signal pair; receiving a corresponding second IF data signal among a plurality of second IF data signals and a corresponding first IF local oscillator signal among a plurality of first IF local oscillator signals at each second data signal mixer among a plurality of second data signal mixers; and generating a corresponding second basic data signal from a corresponding second IF data signal among a plurality of second IF data signals and a corresponding first IF local oscillator signal among a plurality of first IF local oscillator signals at each second data signal mixer, the first basic data signal and the second basic data signal forming a plurality of in-phase / quadrature basic data signal pairs.

[0040] Optionally, in any of the aforementioned aspects of the method for receiving an RF signal, the method further includes: performing filtering at each RF filter among a plurality of RF filters, filtering a corresponding RF antenna signal among a plurality of RF antenna signals.

[0041] Optionally, in any of the aforementioned aspects of the method of receiving an RF signal, the number of the frequency synthesizer is one, and the first RF local oscillator signal is the same as the second RF local oscillator signal.

[0042] This summary is provided to introduce a selection of concepts in a simplified form, which are further described in the detailed description below. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. The claimed subject matter is not limited to implementations that solve any or all of the disadvantages mentioned in the background technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The aspects of the present disclosure are illustrated by way of example and not limitation in the accompanying figures, throughout which like references indicate similar elements.

[0044] Figure 1 A wireless network for communicating data is shown.

[0045] Figure 2 It is available in Figure 1 Block diagram of a wireless communication system used in a network.

[0046] Figure 3 is a block diagram of one embodiment of a beamforming transmitter that uses a high frequency local oscillator clock edge to introduce a delay value on an intermediate frequency local oscillator path.

[0047] Figure 4 Synchronous intermediate local frequency oscillators in N paths of an intermediate frequency local oscillator (IFLO) generation block 210 are shown.

[0048] Figure 5 is a block diagram of an embodiment of a beamforming transmitter that uses quadrature radio frequency local oscillators (RFLOs) for frequency up-conversion and uses high frequency local oscillator clock edges to introduce delay values ​​on an intermediate frequency local oscillator path.

[0049] Fig. 6A and Figure 6B They are shown respectively Figure 3 The non-image-rejected superheterodyne embodiment and Figure 5 The output of an image-rejected superheterodyne embodiment.

[0050] Figure 7 is a block diagram of an embodiment of a beamforming transmitter including a dedicated frequency synthesizer for generating an intermediate frequency local oscillator signal.

[0051] Figure 8 is a flow chart of an embodiment for forming a set of beamforming signals, wherein a phase shift / delay for beamforming is introduced in an IFLO generation block.

[0052] Fig. 9 is a block diagram of one embodiment of a receiver that uses high frequency local oscillator clock edges to control various intermediate frequency local oscillator clock generation blocks to introduce delay values ​​on intermediate frequency local oscillator paths.

[0053] Fig.10 is a block diagram of an embodiment of a receiver that uses a quadrature RFLO for frequency down-conversion and uses a high frequency local oscillator clock edge to introduce a predefined delay value on an intermediate frequency local oscillator path.

[0054] Fig.11 is a block diagram of an embodiment of a transmitter including a dedicated frequency synthesizer for generating an intermediate frequency local oscillator signal in an IFLO generation block.

[0055] Fig.12 It is used to receive a set of antenna signals and apply Figures 9 to 11 Flowchart of an embodiment of a phase shift / delay introduced in an IFLO generation block to extract data content. DETAILED DESCRIPTION

[0056] The present disclosure will now be described with reference to the accompanying drawings, which generally relate to techniques for improving communication signal transmission when networks progress to higher frequency ranges. As the demand for mobile network data throughput increases, mobile networks can use higher frequencies to achieve high bandwidths. For example, mobile networks can begin to communicate in 5G frequency range 2 (FR2) from 24250MHz to 52600MHz and 5G millimeter wave (mmWave) frequency ranges from 30GHz to 300Ghz. In mmWave 5G mobile networks, path losses are high, which means that beamforming capabilities can be used to provide high antenna gain in order to overcome losses. In addition, beamforming can reduce interference between different users, which is also desirable in mobile networks. In order to achieve beamforming, using a transmitter (Tx) as an example, a signal is constructed from multiple paths with a defined phase shift relationship between these paths. In the technology described below, a set of intermediate frequency beamforming signals is generated by introducing a phase shift based on the number of cycles of a higher frequency local oscillator signal used to up-convert a set of intermediate frequency signals. The set of intermediate frequency signals with a defined phase shift relationship are then mixed with data signals such as in-phase / quadrature (I / Q) data signals and then up-converted to generate a set of beamforming signals provided to the antenna array.

[0057] It should be understood that the current embodiments of the present disclosure can be implemented in many different forms, and the scope of the claims should not be interpreted as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided to make the present disclosure sufficient and complete, and to fully convey the embodiment concepts of the present invention to those skilled in the art. In fact, the present disclosure is intended to cover replacements, modifications and equivalents of these embodiments, which are included in the scope and spirit of the present disclosure as defined by the appended claims. Further, in the following detailed description of the current embodiments of the present disclosure, many specific details are set forth in order to provide a thorough understanding. However, it will be clear to those of ordinary skill in the art that the current embodiments of the present disclosure can be implemented without these specific details.

[0058] Figure 1 A wireless network for communicating data is shown. Communication system 10 includes, for example, user equipment 11A-11C, radio access networks (RAN) 12A-12B, core network 13, public switched telephone network (PSTN) 14, Internet 15, and other networks 16. Additional or alternative networks include private and public packet data networks, including corporate intranets. Although certain numbers of these components or elements are shown in the figure, any number of these components or elements may be included in system 10.

[0059] In one embodiment, the wireless network may be a fifth generation (5G) network including at least one 5G base station, wherein the at least one 5G base station uses orthogonal frequency-division multiplexing (OFDM) and / or non-OFDM and a transmission time interval (TTI) shorter than 1 millisecond (ms) (e.g., 100 or 200 microseconds) to communicate with the communication device. In general, references to base stations may refer to any of eNBs and 5G base stations (gNBs). In addition, the network may further include a network server for processing information received from the communication device via at least one eNB or gNB base station.

[0060] The system 10 enables multiple wireless users to transmit and receive data and other content. The system 10 may implement one or more channel access methods such as, but not limited to, code division multiple access (CDMA), time division multiple access (TDMA), frequency division multiple access (FDMA), orthogonal FDMA (OFDMA), or single-carrier FDMA (SC-FDMA).

[0061] User equipment (UE) 11A-11C is configured to operate and / or communicate in the system 10. For example, the user equipment 11A-11C is configured to send and / or receive wireless signals or wired signals. Each user equipment 11A-11C represents any suitable end-user device and may include such devices as (or may be referred to as) user equipment / devices, wireless transmission / reception units (UEs), mobile stations, fixed or mobile subscriber units, pagers, cellular phones, personal digital assistants (PDAs), smart phones, laptops, computers, touch pads, wireless sensors, wearable devices, or consumer electronic devices.

[0062] In the illustrated embodiment, the RAN 12A-12B includes one or more base stations 17A, 17B, respectively (collectively referred to as base stations 17). Each of the base stations 17 is configured to wirelessly interface with one or more of the UEs 11A, 11B, 11C to allow access to the core network 13, the PSTN 14, the Internet 15, and / or other networks 16. For example, the base station (BS) 17 may include one or more of several well-known devices, such as a base transceiver station (BTS), a Node-B (NodeB), an evolved NodeB (evolved NodeB, eNB), a next (fifth) generation (5G) NodeB (gNB), a home NodeB, a home eNodeB, a site controller, an access point (AP) or a wireless router, or a server, a router, a switch, or other processing entity with a wired or wireless network.

[0063] In one embodiment, base station 17A forms part of RAN 12A, which may include other base stations, elements and / or devices. Similarly, base station 17B forms part of RAN 12B, which may include other base stations, elements and / or devices. Each of base stations 17 transmits and / or receives wireless signals within a specific geographic region or area (sometimes referred to as a "cell"). In some embodiments, multiple-input multiple-output (MIMO) technology may be used, which has multiple transceivers for each cell.

[0064] The base station 17 communicates with one or more of the user equipment 11A-11C using wireless communication links over one or more air interfaces (not shown). The air interface may employ any suitable radio access technology.

[0065] It is contemplated that the system 10 may use multi-channel access functionality, including, for example, a scheme in which the base station 17 and the user equipment 11A-11C are configured to implement the Long Term Evolution wireless communication standard (LTE), LTE Advanced (LTE-A), and / or LTE Multimedia Broadcast Multicast Service (MBMS). In other embodiments, the base station 17 and the user equipment 11A-11C are configured to implement UMTS, HSPA, or HSPA+ standards and protocols. Of course, other multiple access schemes and wireless protocols may be utilized.

[0066] The RANs 12A-12B communicate with the core network 13 to provide voice, data, applications, voice over Internet Protocol (VoIP) or other services to the user devices 11A-11C. As will be appreciated, the RANs 12A-12B and / or the core network 13 may communicate directly or indirectly with one or more other RANs (not shown). The core network 13 may also serve as a gateway access to other networks such as the PSTN 14, the Internet 15, and other networks 16. In addition, some or all of the user devices 11A-11C may include functionality to communicate with different wireless networks over different wireless links using different wireless technologies and / or protocols.

[0067] The RAN 12A-12B may also include millimeter and / or microwave access points (APs). The AP may be part of the base station 17 or may be located remote from the base station 17. The AP may include, but is not limited to, a connection point (mmW CP) or a base station 17 capable of mmW communication (e.g., a mmW base station). The mmW AP may send and receive signals in a frequency range of, for example, from 24 GHz to 100 GHz, but need not operate over the entire range. As used herein, the term "base station" is used to refer to a base station and / or a wireless access point.

[0068] although Figure 1 An example of a communication system is shown, but the Figure 1 Various changes may be made. For example, the communication system 10 may include any number of user equipment, base stations, networks, or other components of any suitable configuration. It should also be understood that the term "user equipment" may refer to any type of wireless device that communicates with a radio network node in a cellular or mobile communication system. Non-limiting examples of user equipment are target devices, device-to-device (D2D) user equipment, machine-type user equipment or user equipment capable of machine-to-machine (M2M) communication, laptops, PDAs, iPads, tablet computers, mobile terminals, smart phones, laptop embedded equipment (laptop embedded equipment, LEE), laptop mounted equipment (laptop mounted equipment, LME) and USB dongles.

[0069] Figure 21 is a block diagram of a wireless communication system 100, such as a mobile phone or user equipment 11A-11C or a base station 17, with some of the elements discussed below shown. To transmit the output signals from the circuit elements of the processor 111, the transmitter (Tx) RF / analog section 101 up-converts the output signals from the intermediate frequency (IF) range to the radio frequency (RF) range, amplifies, filters, and may perform other processing before providing the transmit signals to the antenna 105. The output signals are provided to the Tx RF / analog section 101 in an in-phase / quadrature (I / Q) format as in-phase and quadrature signals I generated by the Tx digital baseband block 107. Tx and Q Tx Although the Tx digital baseband block 107 Figure 2 1 as separate blocks from the Tx RF / Analog portion 101, but depending on the embodiment, these elements may be combined differently as circuit elements and implemented in hardware, firmware, software, or a combination thereof.

[0070] The signal is received by antenna 105 and provided to a receiver (Rx) RF / analog section 102. The Rx RF / analog section 102 performs any necessary or desired signal processing, such as down-conversion from the radio frequency (RF) range to the intermediate frequency (IF) range and filtering, and then passes the signal to other components on the device represented at processor 111. Figure 2 In the embodiment of the present invention, the output of the Rx RF / analog section 102 is in I / Q format, and the Rx digital baseband section 117 converts it into a received signal provided to the processor. Figure 2 102, but depending on the embodiment, these elements may be combined differently as circuit elements and implemented in hardware, firmware, software, or a combination thereof. Figure 2 The Tx RF / analog section 101 and the Rx RF / analog section 102 are shown as separate elements, but depending on the embodiment, the transmitter and receiver paths may share many elements or be implemented as a combined transceiver. Hereinafter, "transceiver" may be used generally to refer to a combined transmitter / receiver, separate transceiver and receiver sections, or embodiments in which one or more components (e.g., a local oscillator) are shared between the transmitter and receiver.

[0071] In order to increase the data throughput of mobile networks, mobile networks can progress to higher frequency ranges, such as millimeter (mmWave) in the range of 30GHz to 300GHz. At such frequencies, the path loss is high, so beamforming capabilities may be important to provide high antenna gain to overcome the loss. In addition, beamforming can reduce interference between different users, which is also desirable in mobile networks. In order to implement beamforming, using a transmitter (Tx) mobile station as an example, it is necessary to construct signals from multiple paths with a defined phase shift relationship between these paths. Multiple signals are sent from an array of a corresponding set of antennas, and the relative phase shift or delay is selected so that the individual antenna signals produce constructive interference, thereby forming a beam at the receiver position and producing destructive interference away from the receiver position.

[0072] There are different ways to achieve the relative phase shift of the component beamforming signals, ranging from pure digital phase shift implementations to RF delay line implementations. Typically, digital phase shift implementations require N complete signal paths to form a set of N beamforming signals and result in high power consumption / large chip size; RF delay line implementations suffer from phase shift accuracy issues and have high losses, which means high power consumption. To help overcome these difficulties, alternative techniques for achieving precise phase shift control and low power consumption / small chip size are described below.

[0073] In applications with higher output (Tx) and input (Rx) frequencies such as 5G mmWave mobile applications, high frequency clock generation capability is required for both transmitter and receiver paths regardless of beamforming. The embodiments presented herein take advantage of this capability to provide fine delay control in N beamforming paths by using a high frequency clock to control a lower frequency clock. For example, in a superheterodyne architecture, a high frequency local oscillator clock (RFLO clock) is available. An intermediate frequency local oscillator (IFLO) clock can be generated by dividing the RFLO clock. By using the high frequency RFLO clock edge to control the individual IFLO clock generation blocks, delays can be achieved on the IFLO path. This IFLO path delay will be converted to the signal path through the IF mixer conversion process, so the transmitter or receiver can achieve the target signal path delay through IFLO clock edge control. The delay (τ) is determined by ω IF *τ is converted to phase shift, where ω IF is the frequency of the IF signal, and different delays between the N paths provide different phase shifts between the N paths.

[0074] To describe these techniques, a transmitter example is first used. In the first example, assume that the Tx output frequency is 50 GHz, the IFLO frequency is RFout / 25=2 GHz, and the beamforming uses a total of N paths. The choice of IFLO frequency is relevant and will be discussed later. Figure 3is a block diagram illustrating the concept.

[0075] Figure 3 is a block diagram of one embodiment of a beamforming transmitter that uses high frequency local oscillator clock edges to control various intermediate frequency local oscillator clock generation blocks to introduce defined delay values ​​on intermediate frequency local oscillator paths. Figure 3 The transmitter (Tx) 201 may correspond to Figure 2 The Tx RF / analog section 101, I data and Q data may correspond to the data from Figure 2 The in-phase / quadrature (I / Q) data I of the Tx digital baseband block 107 Tx and Q Tx data, and the antenna arrays 245-1, 245-2, ..., 245-N correspond to Figure 2 Antenna 105.

[0076] The beamforming transmitter Tx 201 includes a frequency synthesizer 203, which has an output frequency Fout=48 GHz in this example, which is also used as the up-converted RF local oscillator signal RFLO at the mixer 237-i and the input frequency Freq1 of the IFLO generation circuit 210. The input frequency Freq1 (=Fout in this embodiment) is provided to N intermediate frequency local oscillator generators IFLO Gen_i 211-i (i.e., 211-1, 211-2, ..., 211-N, where i=1, 2, ..., N), and each IFLO Gen_i 211-i divides Freq1 by a division factor of 24 to provide an intermediate frequency signal of 2 GHz. Figure 3 In the embodiments presented in the subsequent figures, the data is in I / Q format, and the output of each IFLO Gen_i 211-i is an I / Q pair - IFLO I and IFLO Q.

[0077] In order to introduce a relative delay into each IFLO signal, each IFLO Gen_i 211-i receives a delay value di. The delay is the number of cycles of the Freq1 signal, which may be an integer number of cycles or a half-integer number (i.e., 0, 1 / 2, 1, 3 / 2, 2, 5 / 2, ...) of cycles, depending on the embodiment. Based on the corresponding delay value, each intermediate frequency signal will have its leading edge locked to the corresponding edge of the high frequency signal Freq1. For example, each IFLO signal will have its leading edge locked to each of the corresponding Freq1s, where this may be the leading edge of the Freq1 signal when di is an integer value, or the leading or trailing edge for a half-integer value. This is schematically represented by the waveform at the input of each IFLO Gen_i 211-i, and the following reference is made to Figure 4 Describe in more detail.

[0078] The delay values ​​d1, d2, ..., dn are provided by the control block 207. The control block may be one or more control circuits, and depending on the embodiment, these elements may be combined differently as circuit elements and implemented in hardware, firmware, software, or a combination thereof. Return to Reference Figure 1 , control block 207 may be part of processor 111, a separate control element dedicated to beamforming in Tx RF / analog section 101, or some combination thereof. Since the delay values ​​d1, d2, ..., dn are relative delays for each path, these may be provided as N separate values; or, in other embodiments, only (n-1) delays may be provided, since, for example, the delay at IFLO Gen_1 211-1 may be fixed to 0, and another (n-1) delays may be provided from control block 207 relative to the signal. Since for evenly spaced antennas the delays will be multiples of the same basic delay, the di values ​​may be provided based solely on the basic differential delay. In addition to a set of relative delays or equivalent phases introduced into each of a set of beamforming signals for the antenna array, in some embodiments, a relative amplitude difference may be introduced into each signal. The corresponding relative amplitudes may be provided by control block 207, represented by gain values ​​g1, g2, ..., gn provided to corresponding amplifiers 241-1, 241-2, ..., 241-N as described below.

[0079] Based on the characteristics of the transmitter antenna array (245-1, 245-2, ..., 245-N), a set of relative delays and relative amplitudes for embodiments using them are selected to form a beam at the location of the receiver antenna. Therefore, when transmitting to multiple receivers, each receiver has its own set of parameters. The parameter values ​​can be determined based on the signals exchanged between the transmitter and the receiver. In some embodiments, this can be based on pilot signals exchanged between the receiver and the transmitter, which can then be used to determine the parameters on the transmitter or receiver, in which case they can be sent back to the transmitter via a control channel. Pilot signals can also be sent via a control channel, where these signals can be in-band control signals or out-of-band control signals using a specific channel. In other embodiments, the determination or update of the parameters can be determined alternatively or additionally by monitoring the data signal itself.

[0080] The in-phase and quadrature outputs IFLO I and IFLO Q of each IFLO Gen_i 211-i are provided to the corresponding in-phase data mixer 231-i and quadrature data mixer 233-i, respectively. Figure 3In the embodiment of the present invention, the I / Q basic data signals are received in digital form. The I basic data signal is received at the digital-to-analog converter DAC I 221, may pass through a low pass filter LPF I 223, and then arrive at each in-phase data mixer 231-i, where each mixer receives the same in-phase data signal I. The Q basic data signal is received at the digital-to-analog converter DAC Q 225, may pass through a low pass filter LPF Q 227, and then arrive at each orthogonal data mixer 233-i, where each mixer receives the same orthogonal data signal Q. The I / Q pairs from each data mixer pair 231-i / 233-i are combined to form an I / Q IF data signal and arrive at a corresponding buffer / driver 235-i.

[0081] In this example, the frequency of the IF data signal is Freq1 / 24=2GHz. To upconvert each IF I / Q data signal pair, the combined output of the data mixer pair 231-i / 233-i is the input of 235-i to a corresponding upconversion mixer 237-i, each of which also receives an RFLO signal from the frequency synthesizer 203 (48GHz in this example). The result of this set of RF signals is a set of I / Q beamforming RF data signals at 50GHz for the antenna array. Each upconverted I / Q data signal is then amplified by a corresponding amplifier 241-i, where, depending on the embodiment, the gain of all amplifiers can be the same, or individually set with a gain gi from the control block 207 to assist in beamforming. As discussed in more detail below, the set of I / Q beamforming RF data signals for the antenna can also be filtered at 243-i before going to the corresponding antenna 245-i of the antenna array.

[0082] For the entire operation, Figure 3In the embodiment of the present invention, baseband digital I / Q data (I data, Q data) is converted into analog signals by the DACs (221, 225, respectively) of the I path and the Q path. Low pass filters LPF 223 / 227 for the I / Q path are applied to remove any noise / distortion from the DACs 221 / 225, and the LPF output signals are fed to the IF mixers 231-i / 233-i for quadrature up-conversion. Phase shift / delay occurs in the IFLO quadrature generation block 210. After the IF up-conversion at the data mixer pair 231-i / 233-i, another RF up-conversion block of the RF up-conversion mixer 237-i is used to convert the signal into the final radio frequency of a set of beamforming antenna signals. In this example, this RF up-conversion is performed by a single mixer for each path, i.e., in a non-orthogonal form. Amplifier 241-i is used after the RF mixer 237-i. After amplifier 241-i, filter 243-i may be used depending on image (from RF non-orthogonal up-conversion) requirements. Finally, the N antenna signals are sent to N antennas 245-i for beamforming.

[0083] exist Figure 3 In the arrangement and other embodiments presented below, the critical phase shift / delay is not implemented directly in the signal path as in the prior art, but is implemented in the IFLO generation block 210. By synchronizing the N IFLO generation blocks 211-i to different edges of the input high frequency clock, the trigger edge generated by each IFLO can be delayed by a target value relative to, for example, the first path IFLO generation block 211-1. This means that the IFLO generation block 210 can achieve the target delay / phase shift in all N paths.

[0084] Figure 4 2 shows the synchronized intermediate frequency local oscillator signals in the N paths of the IFLO generation block 210. Figure 3 As shown, in Figure 4 In the example of , the RFLO also has a frequency of 48 GHz and the IFLO has a frequency of 2 GHz, so the division ratio is 24, so that 24 cycles of the RFLO clock fit into one cycle of the IFLO clock. Figure 4 The example assumes that the goal is to achieve 0*minimum delay for path 1, 1*minimum delay for path 2, 2*minimum delay for path 3, and so on. (In this example, the minimum value of the delay is the phase shift resolution, but in practice this will vary from case to case.) So, if Figure 4 As shown, the leading edge of the IFLO 1 waveform is aligned with the first RFLO leading edge, the leading edge of the IFLO 2 waveform is aligned with the second RFLO leading edge, the leading edge of the IFLO 3 waveform is aligned with the third RFLO leading edge, and so on for the remaining waveforms in the N IFLO waveforms.

[0085] exist Figure 4In the example shown, each duty cycle period (360 degrees phase shift) of the RFLO clock (48 GHz) represents a 360 / 24 = 15 degree phase shift in the IFLO clock (2 GHz) for a division ratio of 24. If both rising and falling edges are used (i.e., half-integer delay values), half of the LO domain duty cycle period (180 degrees) represents 180 / 24 = 7.5 degrees in the 2 GHz IFLO domain.

[0086] In general, the resolution of the phase shift depends on the ratio of the RFLO to the IFLO, so assuming both the rising and falling edges are used, a 48 GHz RFLO to a 2 GHz IFLO (ratio of 24) provides a phase shift resolution of 180 / 24 = 7.5 degrees. Since this scheme uses the high frequency clock (RFLO) edge to control the delay, it can achieve a more accurate delay than the RF delay line implementation, depending on the RFLO clock quality. In addition, since the delay is implemented in the IF up-conversion block, the digital / DAC / LPF circuit does not have to be repeated N times, thereby achieving lower power consumption relative to the digital delay implementation.

[0087] Regarding IFLO frequency selection, a higher RFLO to IFLO ratio is preferred from a fine phase shift resolution perspective; however, a very low IFLO may cause image distortion issues in the RFLO upconversion process. Figure 3 The example RFLO upconversion is non-orthogonal and will generate desired (RFLO+IFLO) frequencies and undesired (RFLO-IFLO) frequencies, so the image content (RFLO-IFLO) should be reduced to avoid interference with other users. Setting the IFLO frequency high enough so that the LO-IF distortion is outside the TX band, and using RF filters 243-i can reduce the undesired image level. In addition, typically the antenna array and its individual antennas 245-i will be frequency selective, thus reducing the image distortion level. Finally, beamforming itself is frequency dependent, which means that the image distortion level is filtered when it reaches the target receiver. Therefore, from the perspective of reducing image distortion, a higher IFLO frequency makes things easier. In this example, a balanced RFLO to IFLO ratio was selected.

[0088] The possibility of RFLO image distortion can be addressed in other ways. Figure 5 The embodiment of FIG. 1 shows an example of up-conversion using a quadrature RFLO.

[0089] Figure 5 is a block diagram of an embodiment of a beamforming transmitter 401 that uses quadrature RFLO up-conversion and uses high frequency local oscillator clock edges to control various IF local oscillator clock generation blocks to introduce delay values ​​on the IF local oscillator paths. Figure 5Included with Figure 3 , which are similarly numbered (i.e., control block 207 / 407, frequency synthesizer 203 / 403, IFLO generation block 210 / 410, etc.), and which may be described above with respect to Figure 3 Works as described.

[0090] Relative to Figure 3 ,exist Figure 5 In the embodiment of FIG. 4 , the frequency Fout=Freq1 of the frequency synthesizer 403 is now doubled to 96 GHz. In the IFLO generation block 410, each IFLO Gen_i 411-i now divides Freq1 by 48 and provides cos(ω IF *t), sin(ω IF *t) and -sin(ω IF *t) of 2GHz IF output. cos(ω IF *t) is separated and provided to the in-phase data signal mixer 451-i and the quadrature data signal mixer 457-i. IF *t) output is provided to the quadrature data signal mixer 453-i, and -sin(ω IF *t) is provided to the in-phase data signal mixer 455-i. In-phase cos(ω IF *t) / orthogonal sin(ω IF *t) pairs are combined and enter buffer / driver 461-i, in phase -sin(ω IF *t) / orthogonal cos(ω IF *t) pairs are combined and enter buffer / driver 463-i and then RF up-converted at corresponding RF up-conversion mixers 465-i and 467-i.

[0091] exist Figure 5 For RF up-conversion, the output of frequency synthesizer 403 at Fout = 96 GHz now enters RFLO generator 459 to generate cos(ω RF *t) and sin(ω RF *t), which are provided to RF up-conversion mixers 465-i and 467-i to be combined with the outputs of 461-i and 463-i, respectively. The outputs of the RF up-conversion mixer pairs are then provided to corresponding amplifiers 441-i. Figure 3 , the output of amplifier 441-i is provided to antenna 445-i without an intermediate filter because, as shown below with respect to Fig. 6A and Figure 6B As shown, Figure 5 Embodiments will not have undesired LO-IFLO frequencies as part of the mirror content.

[0092] Relative to Figure 3 An embodiment of Figure 5 The quadrature RFLO upconversion embodiment of FIG. 1 doubles the number of mixers (IF mixers and RF upconversion mixers) in each Tx path. Figure 5 A single-ended circuit is shown, but in actual implementation this is usually a differential circuit which will use the available -sin(ω IF *t)IFLO signal. In addition, to generate a quadrature clock, the frequency synthesizer 403 generates a clock at least twice the rate of the RFLO clock, or Figure 5 In the example, 96 GHz. Figure 5 The higher clock frequency and higher power consumption of the embodiment is to reduce Figure 3 The (RFLO-IFLO) image level compromise.

[0093] Fig. 6A and Figure 6B They are shown respectively Figure 3 The non-image-rejected superheterodyne embodiment and Figure 5 The output of an image-rejected superheterodyne embodiment. Fig. 6A and Figure 6B In both, the signal level in decibels is plotted against frequency. Fig. 6A Shows Figure 3 An example RFLO upconversion of an embodiment of is non-orthogonal and generates a desired (LO+IFLO) frequency (higher frequency peak) and an undesired (LO-IFLO) frequency (lower frequency peak). To remove the image content at (LO-IFLO), a filter 243-i may be used to reduce the peak to avoid interference with other users. Figure 6B Shows Figure 5 An example of quadrature RFLO upconversion of an embodiment of the present invention, which lacks the undesirable (LO-IFLO) image content. Since the (LO-IFLO) image content is suppressed, Figure 6B In the embodiment of FIG. 5 , no RF filter is used for the group of antenna signals.

[0094] Another variation of this architecture is to use a dedicated IFLO generation block, such as a phase locked loop (PLL), which can be Figure 3 or Figure 5 is implemented in the embodiment of. Figure 7 is similar to Figure 3 A block diagram of an embodiment of , but incorporating a dedicated frequency synthesizer.

[0095] Figure 7is a block diagram of an embodiment of a beamforming transmitter 601 including a dedicated frequency synthesizer (Frequency Synthesizer 2 605 ) for generating an intermediate frequency local oscillator signal in an IFLO generation block 610 . Figure 7 Repeated with Figure 3 607, frequency synthesizer 203 / 603, IFLO generation block 210 / 610, etc., and they may be described above with respect to Figure 3 Works as described.

[0096] Relative to Figure 3 ,exist Figure 7 The embodiment of includes a second frequency synthesizer 2 605, such as a PLL, which provides Freq1 to the IFLO generation block 610. In this example, Freq1 is again taken to be 48 GHz, and the division ratio 24 is again used to generate a 2 GHz IFLO signal. Fout from the frequency synthesizer 603 can now be set independently of Freq1, providing greater flexibility. Figure 7 In the example of , Fout = 50 GHz. Since RFLO is now at 50 GHz, up-conversion at mixer 637 - i produces a set of beamforming antenna signals at RFout = 52 GHz.

[0097] exist Figure 7 In the embodiment of , since the output of RFLO frequency synthesizer 603 is no longer used as the input of IFLO generation block 610, dedicated frequency synthesizer 2 605 allows the IFLO frequency to be set to a constant, which can help signal path design in some cases. Figure 7 In the embodiment of , Freq1 is a constant, so frequency synthesizer 2 605 can be simpler than frequency synthesizer 603: for example, frequency synthesizer 2 605 can be an integer PLL instead of a fractional-N phase-locked loop (Frac-N PLL). Figure 5 In the embodiment of the present invention, an additional dedicated frequency synthesizer may be similarly introduced for the IFLO generation block 410.

[0098] The beamforming transmitter presented above performs phase shift / delay to form a beam in the IFLO generation block 210 / 410 / 610, which is an arrangement different from previous beamforming schemes. The scheme presented here does not use a signal path for phase shift, but uses the clock generation block 210 / 410 / 610 to introduce phase shift. This means that even if the phase shift is performed in the IF domain, no signal path loss is introduced. In addition, compared with the prior art using digital phase shift or RF delay line phase shift, the phase shift based on IFLO generation is a balanced scheme. The scheme proposed here requires fewer circuit blocks than the digital phase shift implementation; and has better delay control accuracy and lower signal path loss than the RF delay line phase shift implementation.

[0099] Figure 8 is a flow chart of an embodiment for forming a set of beamforming signals, wherein phase shifts / delays for forming beams are introduced in the IFLO generation block. At 701, the control block 207 / 407 / 607 receives or determines delay values ​​(d1, d2, ..., dn). These values ​​may be determined based on signals exchanged between the transmitter 201 / 401 / 601 and the receiver, wherein these signals may be data signals or control signals, such as beacons, either in-band of a data signal channel or via an out-of-band control channel. Depending on the embodiment, the delays may be calculated in the control block 207 / 407 / 607 or sent to the control block by the receiver.

[0100] At 703, each of the IFLOs 211-i / 411-i / 611-i receives the first RFLO signal Freq1 (from the frequency synthesizer 203 / 403 or the frequency synthesizer 2 603) and the corresponding delay value di from the control block 207 / 407 / 607. At 705, each of the IFLOs 211-i / 411-i / 611-i generates an IFLO signal with a corresponding specified delay. Figure 3 and Figure 7 In the embodiment of FIG. 5 , these are the corresponding IFLO I and IFLO Q signals and are Figure 5 In the embodiment, cos(ω IF *t)、-sin(ω IF *t) is the same as sin(ω IF *t), cos(ω IF *t) orthogonal pair.

[0101] At 707, each data signal mixer (231-i / 451-i, 455-i / 631-i for I and 233-i / 453-i, 457-i / 633-i for Q) receives the IF data signal (I data from LPF 1 223 / 423 / 623 and Q data from LPF2 227 / 427 / 627) and the corresponding IFLO signal. Then, at 709, the data signal mixer generates an IF data signal.

[0102] At 711, each up-conversion mixer (237-i / 465-i, 467-i / 637-i) receives a second RFLO signal (Fout from 203 / 603, or cos(ω) from RFLO Gen 459). IF *t), sin(ω IF *t)) and the corresponding IF data signal from one of the data signal mixers. (In Figure 3 and Figure 5 In an embodiment, the second RFLO signal and the first RFLO signal at 703 both originate from the frequency synthesizer 203 / 403). At 713, each up-conversion mixer generates one of a set of beamforming RF antenna signals, which may then be amplified, filtered, and passed to the antenna arrays 245-1, 245-2, ..., 245-N, according to an embodiment.

[0103] As with the transmitter case above, similar techniques can be applied to the receiver, with much of the discussion of the transmitter also applicable to the receiver case. Fig. 9 , Fig.10 and Fig.11 The corresponding Figure 3 , Figure 5 and Figure 7 Although the receiver and transmitter embodiments are described separately, in some embodiments, components (e.g., IFLO generation block, antenna array, etc.) may be shared between the transmitter and receiver sides, or both may be implemented as transceivers. Return to Reference Figure 2 , the transceiver embodiments given below may correspond to the Rx RF / analog part 102 .

[0104] Fig. 9 is a block diagram of one embodiment of a receiver 802 that uses high frequency local oscillator clock edges to control various IFLO clock generation blocks to introduce delay values ​​on an intermediate frequency local oscillator path. Fig. 9 An example exploit similar to Figure 3 The architecture uses a single frequency synthesizer with non-orthogonal RF down-conversion, the architecture includes corresponding Figure 3807, the frequency synthesizer 203 / 803, the IFLO generation block 210 / 810, etc.). Specifically, the frequency synthesizer 803, the control block 807, and the IFLO generation block 810 may be described above with reference to Figure 3 Works as described. Fig. 9 is the receiver, not Figure 3 The transmitter in Fig. 9 The right-hand element given in is now relative to Figure 3 The arrangement is "reverse" because signals are received from the antenna arrays 845-1, 845-1, ..., 845-N and I / Q data is extracted.

[0105] More specifically, each antenna 845-i receives an RF signal from a transmitter, which may then be filtered at a corresponding RF filter 843-i and amplified in a corresponding amplifier 841-i. In some embodiments, each amplifier 841-i may individually set its differential gain gi based on a value provided by control block 807. Fig. 9 In the example of , the received RF frequency is RFin = 50 GHz. The RF antenna signals are then each down-converted at the corresponding down-conversion mixer 837-i using the RFLO signal, which is 48 GHz in this example, to produce a 2 GHz down-converted antenna signal that enters the buffer / driver 835-i in each path.

[0106] To extract I / Q data, each down-converted antenna signal enters an in-phase data signal mixer 831-i and a quadrature data signal mixer 833-i, the in-phase data signal mixer 831-i also receiving an IFLO-I signal with a corresponding delay di from IFLO GEN_i 811-i, and the quadrature data signal mixer 833-i also receiving an IFLO-Q signal with a corresponding delay di from IFLO GEN_i 811-i. The I signal and the Q signal from the I data signal mixer and the Q data signal mixer can then be filtered in LPF I 823 and LPF Q 827, respectively, and digitized in analog-to-digital converters ADC I 821 and ADC Q 825 to provide I / Q basic data signals.

[0107] Fig.10 9 is a block diagram of an embodiment of a receiver 902 that uses quadrature RFLO down-conversion and uses high frequency local oscillator clock edges to control various intermediate frequency local oscillator clock generation blocks to introduce predefined delay values ​​on the intermediate frequency local oscillator path. Fig.10 yes Figure 5 The receiver counterpart of the transmitter embodiment. On the left, as shown, Fig.10 Included with Figure 5 , which are similarly numbered (i.e., control block 407 / 907, frequency synthesizer 403 / 903, RFLO Gen 459 / 959, and IFLO generation block 410 / 910), and which may be described above with respect to Figure 5 Works as described.

[0108] like Fig. 9 As shown in Fig.10 The elements shown on the right are arranged as a receiver 902, thereby receiving signals from antenna arrays 945-1, 945-1, ..., 945-N and extracting I / Q data. More specifically, each antenna 945-i receives an RF signal from a transmitter, which can then be amplified in a corresponding amplifier 941-i. In some embodiments, each amplifier 941-i can individually set its differential gain gi based on the value provided by the control block 907. Fig.10 In the example of , the received RF frequency is RFin=50GHz. Fig.10 In the quadrature RFLO downconversion, similar to Figure 5 of the transmitter embodiment, and as regards Fig. 6A and Figure 6B The RF filter between the antenna and the amplifier is not included in the discussion. Then, at the corresponding I / Q down-conversion mixer 837-i / 965-i, a 48 GHz RFLO GEN signal (cos(ω in this example) is used RF *t) and sin(ω RF *t)) down-converts the RF antenna signals individually to produce 2 GHz down-converted antenna signals, which enter the buffer / driver pair 961-i / 963-i in each path.

[0109] To extract I / Q data, each down-converted antenna signal from 961-i enters the in-phase data signal mixer 951-i and the quadrature data signal mixer 953-i. The in-phase data signal mixer 951-i also receives the cos(ω) with corresponding delay di from IFLO GEN_i 911-i. IF *t) signal, the quadrature data signal mixer 953-i also receives the sin(ω) with corresponding delay di from IFLO GEN_i 911-i. IF *t) signal. Each down-converted antenna signal from 963-i enters the in-phase data signal mixer 955-i and the orthogonal data signal mixer 957-i. The in-phase data signal mixer 955-i also receives the -sin(ω) with the corresponding delay di from IFLO GEN_i 911-i. IF*t) signal, the quadrature data signal mixer 957-i also receives the cos(ω) with corresponding delay di from IFLOGEN_i 911-i. IF The I signal and the Q signal from the I data signal mixer and the Q data signal mixer may then be filtered at LPF I 923 and LPF Q 927, respectively, and digitized in analog-to-digital converters ADC I 921 and ADC Q 925 to provide I / Q data.

[0110] Fig.11 is a block diagram of an embodiment of a transmitter 1002 including a dedicated frequency synthesizer 1005 for generating an intermediate frequency local oscillator signal in an IFLO generation block 1010, similar to Figure 7 Transmitter 601. Fig.11 Repeated with Fig. 9 807 / 1007, frequency synthesizer 803 / 1003, IFLO generation block 810 / 1010, etc., and they may be described above with respect to Fig. 9 Works as described.

[0111] Relative to Fig. 9 , Fig.11 In the embodiment of , a second frequency synthesizer 2 1005 is included, such as a PLL, which provides Freq1 to the IFLO generation block 1010. In this example, Freq1 is again taken to be 48 GHz, and the division ratio 24 is again used to generate a 2 GHz IFLO signal. Fout from the frequency synthesizer 1003 can now be set independently of Freq1, providing greater flexibility. Fig.11 In the example of , Fout = 50 GHz, and the signal from antenna 1045 - i is now at RFin = 52 GHz, so that the down-conversion at mixer 1037 - i produces a down-converted antenna signal at 2 GHz.

[0112] exist Fig.11 In the embodiment of FIG. 1 , instead of using the RFLO frequency synthesizer 1003 output as the input to the IFLO generation block 1010, a dedicated frequency synthesizer 2 1005 allows the IFLO frequency to be set to a constant, which may help in signal path design in some cases. Fig.11 In the embodiment of , Freq1 is a constant, so frequency synthesizer 2 1005 can be simpler than frequency synthesizer 1003: for example, an integer PLL can be used instead of a Frac-N PLL. Fig.10 In an embodiment of the present invention, an additional dedicated frequency synthesizer may be similarly introduced for the IFLO generation block 910.

[0113] Fig.12 It is used to receive a set of antenna signals and apply Figures 9 to 11 Flowchart of an embodiment of a phase shift / delay introduced in an IFLO generation block to extract data content. At 1101, the control block 807 / 907 / 1007 receives or determines delay values ​​(d1, d2, ..., dn). These values ​​can be determined based on signals exchanged between the transmitter 802 / 902 / 1002 and the receiver, where these signals can be data signals or control signals, such as beacons, which are either in-band of the data signal channel or through an out-of-band control channel. Depending on the embodiment, the delay can be calculated in the control block 802 / 902 / 1002 or sent to the control block by the transmitter.

[0114] At 1103, each of the IFLOs 811-i / 911-i / 1011-i receives the first RFLO signal Freq1 (from frequency synthesizer 803 / 1003 or frequency synthesizer 2 903) and the corresponding delay value di from the control block 807 / 907 / 1007. At 1105, each of the IFLOs 811-i / 911-i / 1011-i generates an IFLO signal with a corresponding specified delay. Fig. 9 and Fig.11 In the embodiment of FIG. 5 , these are the corresponding IFLO I and IFLO Q signals and are Fig.10 In the embodiment, cos(ω IF *t)、-sin(ω IF *t) is the same as sin(ω IF *t), cos(ω IF *t) orthogonal pair.

[0115] At 1107, each down-conversion mixer (837-i / 965-i, 967-i / 1037-i) receives a second RFLO signal (also from Fig. 9 and Fig.11 Fout of 803 / 1003 in, or from Fig.10 The cos(ω IF *t), sin(ω IF *t)) and the corresponding RF antenna signals from the antenna array, which may be amplified and filtered before being provided to the down-mixer. (In Fig. 9 and Fig.11 In the embodiment of the present invention, the second RFLO signal and the first RFLO signal at 1103 both originate from the frequency synthesizer 803 / 1003). Each down-conversion mixer generates an IF data signal at 1109, which can then be passed to the data signal mixer.

[0116] At 1111, each data signal mixer (831-i / 951-i, 955-i / 1031-i for I and 833-i / 953-i, 957-i / 1033-i for Q) receives a corresponding down-converted IF antenna signal and a corresponding IFLO signal. The data signal mixer then generates an I / Q data signal at 1113. The extracted I / Q data signal may then be filtered and converted to digital form.

[0117] The techniques described herein may be implemented using hardware, firmware, software, or a combination thereof. The software or firmware used may be stored on one or more processor-readable storage devices to be used for Figures 3 to 12 One or more blocks of the computer programmable memory device may be programmed to perform the functions described herein. The processor readable storage device may include computer readable media, such as volatile and non-volatile media, removable and non-removable media. As an example and not limitation, the computer readable medium may include computer readable storage media and communication media. The computer readable storage medium may be implemented in any method or technology for storing information (such as computer readable instructions, data structures, program modules or other data). Examples of computer readable storage media include RAM, ROM, EEPROM, flash memory or other storage technology, CD-ROM, digital versatile disk (digital versatile disk, DVD) or other optical disk storage, cassette, magnetic tape, disk storage or other magnetic storage device, or any other medium that can be used to store the required information and can be accessed by the above components. One or more computer readable media do not include propagated, modulated or transient signals.

[0118] Communication media typically contain computer readable instructions, data structures, program modules, or other data in a propagated, modulated or transient data signal such as a carrier wave or other transport mechanism, and include any information delivery media. The term "modulated data signal" refers to a signal that has one or more characteristics set or changed in a manner that encodes information in the signal. By way of example and not limitation, communication media include wired media such as a wired network or a direct wired connection, and wireless media such as RF and other wireless media. Any combination of the above is also included within the scope of computer readable media.

[0119] In alternative embodiments, some or all of the software or firmware may be replaced by dedicated hardware logic components. For example, but not limited to, exemplary types of hardware logic components that can be used include field programmable gate arrays (Field-programmable Gate Array, FPGA), application-specific integrated circuits (Application-specific Integrated Circuit, ASIC), application-specific standard products (Application-specific Standard Products, ASSP), system-on-a-chip (System-on-a-chip, SOC), complex programmable logic devices (Complex Programmable Logic Device, CPLD), special computers, etc. In one embodiment, software (stored on a storage device) that implements one or more embodiments is used to program one or more processors. One or more processors can communicate with one or more computer-readable media / storage devices, peripheral devices, and / or communication interfaces.

[0120] It should be understood that the present subject matter can be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided to make the present subject matter thorough and complete and to fully convey the disclosure to those skilled in the art. In fact, the present subject matter is intended to cover the replacements, modifications and equivalents of these embodiments, which are included in the scope and spirit of the present subject matter defined by the appended claims. Further, in the following detailed description of the present subject matter, many specific details are set forth to provide a thorough understanding of the present subject matter. However, it is apparent to one of ordinary skill in the art that the present subject matter can be implemented without these specific details.

[0121] Various aspects of the present disclosure are described herein with reference to the flowchart and / or block diagram of the method, device (system) and computer program product according to the embodiments of the present disclosure. It will be understood that each block of the flowchart and / or block diagram and the combination of the blocks in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer or other programmable data processing device to produce such a machine, that is, so that the instructions executed by the processor of the computer or other programmable instruction execution device create a mechanism for implementing the function / action specified in the flowchart and / or block diagram.

[0122] The description of the present disclosure has been given for the purpose of illustration and description, but is not intended to be exhaustive or to limit the present disclosure to the disclosed forms. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the present disclosure. Various aspects of the present disclosure are selected and described herein in order to best explain the principles and practical applications of the present disclosure and to enable other persons of ordinary skill in the art to understand that the present disclosure has various modifications suitable for the intended specific use.

[0123] For the purposes of this document, each process associated with the disclosed technology can be performed serially by one or more computing devices. Each step in the process can be performed by the same or different computing devices used in other steps, and each step does not have to be performed by a single computing device.

[0124] Although the subject matter has been described in language specific to structural features and / or methodological acts, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims

1. A transmitter, comprising: one or more frequency synthesizers, each frequency synthesizer configured to generate a corresponding radio frequency (RF) local oscillator signal; A plurality of intermediate frequency (IF) local oscillators, each IF local oscillator being configured as: receiving a first RF local oscillator signal of one or more RF local oscillator signals; receiving a corresponding delay value of a plurality of delay values, each of the delay values ​​specifying a delay of a plurality of cycles of the first RF local oscillator signal; as well as generating a first IF local oscillator signal by dividing the first RF local oscillator signal by an integer division ratio and shifting the first RF local oscillator signal by a corresponding delay value; a plurality of first data signal mixers, each first data signal mixer configured to receive the first base data signal and a corresponding first IF local oscillator signal of the plurality of first IF local oscillator signals and generate therefrom a corresponding first IF data signal of the plurality of first IF data signals; as well as A plurality of up-conversion mixers, each up-conversion mixer being configured to receive a second RF local oscillator signal among the one or more RF local oscillator signals and a corresponding first IF data signal among the plurality of first IF data signals and to generate therefrom a beamformed RF antenna signal among a plurality of beamformed RF antenna signals.

2. The transmitter according to claim 1, wherein: Each of the plurality of IF local oscillators is further configured to generate a second IF local oscillator signal by dividing the second RF local oscillator signal by the integer division ratio and shifting a corresponding delay value, the first IF local oscillator signal and the second IF local oscillator signal forming an in-phase / quadrature IF local oscillator signal pair, the transmitter further comprising: a plurality of second data signal mixers, each second data signal mixer being configured to receive a second primary data signal and a corresponding second IF local oscillator signal of a plurality of second IF local oscillator signals and generate therefrom a corresponding second IF data signal of a plurality of second IF data signals, wherein the first primary data signal and the second primary data signal are an in-phase / quadrature pair, and the plurality of first IF data signals and the plurality of second IF data signals are a plurality of in-phase / quadrature IF data signal pairs, The plurality of up-conversion mixers are each further configured to receive a corresponding second IF data signal among the plurality of second IF data signals, and the plurality of beamforming RF antenna signals are formed by a plurality of combined in-phase / quadrature IF data signal pairs.

3. The transmitter according to claim 1, further comprising: One or more control circuits are configured to provide the plurality of delay values ​​to the plurality of IF local oscillators.

4. The transmitter according to claim 3, further comprising: A plurality of amplifiers are connected to receive and amplify corresponding beamformed RF antenna signals among the plurality of beamformed RF antenna signals.

5. The transmitter of claim 4, the one or more control circuits further configured to provide the plurality of delay values ​​to the plurality of IF local oscillators and to provide a corresponding gain factor to each of the plurality of amplifiers, Each of the amplifiers is configured to amplify a received beamformed RF antenna signal among the plurality of beamformed RF antenna signals according to the corresponding gain factor.

6. The transmitter according to any one of claims 1 to 5, further comprising: A plurality of RF filters, each RF filter being configured to receive and filter a corresponding beamformed RF antenna signal of the plurality of beamformed RF antenna signals.

7. The transmitter according to any one of claims 1 to 5, further comprising: An array of multiple antennas, each antenna configured to receive and transmit a corresponding beamformed RF antenna signal of the plurality of beamformed RF antenna signals.

8. A transmitter according to any one of claims 1 to 5, wherein: The number of frequency synthesizers is one, and the first RF local oscillator signal is identical to the second RF local oscillator signal.

9. A transmitter according to any one of claims 1 to 5, wherein: The one or more frequency synthesizers include a first frequency synthesizer configured to provide the first RF local oscillator signal and a second frequency synthesizer configured to provide the second RF local oscillator signal.

10. A transmitter according to any one of claims 1 to 5, wherein: Each of the delay values ​​specifies a delay of an integer number of cycles.

11. A transmitter according to any one of claims 1 to 5, wherein: Each of the delay values ​​specifies a delay of half an integer number of cycles.

12. A method for transmitting a beamforming signal, comprising: receiving, at each of a plurality of intermediate frequency (IF) local oscillators, a first radio frequency (RF) local oscillator signal and a corresponding delay value of a plurality of delay values, each of the delay values ​​specifying a delay of a plurality of cycles of the first RF local oscillator signal; generating, at each of the IF local oscillators, a first IF local oscillator signal by dividing the first RF local oscillator signal by an integer division ratio and shifting the first RF local oscillator signal by a corresponding delay value; receiving, at each of the plurality of first data signal mixers, a first base data signal and a corresponding first IF local oscillator signal of the plurality of first IF local oscillator signals; generating, by each of the first data signal mixers, a first IF data signal from the first base data signal and a corresponding first IF local oscillator signal of the plurality of first IF local oscillator signals; receiving, at each of the plurality of up-conversion mixers, a second RF local oscillator signal and a corresponding first IF data signal of the plurality of first IF data signals; as well as A corresponding beamforming RF antenna signal is generated by each of the up-converting mixers from the second RF local oscillator signal and a corresponding first IF data signal of the plurality of first IF data signals.

13. The method according to claim 12, further comprising: exchanging one or more control signals between the transmitter controller and the receiver; determining, by the transmitter controller, the delay value from the exchanged control signals; as well as A determined delay value is provided from the transmitter controller to the IF local oscillator.

14. The method according to claim 13, wherein: The determining of the delay value includes calculating, by the transmitter controller, the delay value based on the exchanged control signals.

15. The method of claim 13, wherein: The determination of the delay value includes receiving the delay value from the receiver in a control signal of the exchange.

16. The method according to claim 13, further comprising: receiving, at each amplifier of the plurality of amplifiers, a corresponding beamformed RF antenna signal of the plurality of beamformed RF antenna signals and a corresponding gain factor; at each of the amplifiers, amplifying a corresponding beamformed RF antenna signal among the plurality of beamformed RF antenna signals according to the gain factor; determining, by the transmitter controller, the gain factor based on the exchanged control signal; as well as The determined gain factor is provided from the transmitter controller to the IF local oscillator.

17. The method according to any one of claims 12 to 16, further comprising: generating a second IF local oscillator signal at each of the IF local oscillators by dividing the second RF local oscillator signal by the integer division ratio and shifting the second RF local oscillator signal by a corresponding delay value, the first IF local oscillator signal and the second IF local oscillator signal forming an in-phase / quadrature IF local oscillator signal pair; receiving, at each of the plurality of second data signal mixers, a second base data signal and a corresponding second IF local oscillator signal of the plurality of second IF local oscillator signals; generating, by each of the second data signal mixers, a second IF data signal from the second primary data signal and a corresponding second IF local oscillator signal of the plurality of second IF local oscillator signals, wherein the first primary data signal and the second primary data signal are an in-phase / quadrature pair, and the plurality of first IF data signals and the plurality of second IF data signals are a plurality of in-phase / quadrature IF data signal pairs; as well as Forming a combined in-phase / quadrature IF data signal pair, wherein said generating a corresponding beamforming RF antenna signal from said second RF local oscillator signal and a corresponding first IF data signal from said plurality of first IF data signals by each of said up-conversion mixers includes generating said corresponding beamforming RF antenna signal from a corresponding combined in-phase / quadrature IF data signal pair from a plurality of combined in-phase / quadrature IF data signal pairs.

18. The method according to any one of claims 12 to 16, further comprising: Each RF filter of the plurality of RF filters filters a corresponding beamformed RF antenna signal of the plurality of beamformed RF antenna signals.

19. The method according to any one of claims 12 to 16, further comprising: Each antenna of the plurality of antennas transmits a corresponding beamformed RF antenna signal of the plurality of beamformed RF antenna signals.

20. The method according to any one of claims 12 to 16, wherein: The first RF local oscillator signal is identical to the second RF local oscillator signal.

21. A receiver, comprising: one or more frequency synthesizers, each frequency synthesizer configured to generate a corresponding radio frequency (RF) local oscillator signal; A plurality of intermediate frequency (IF) local oscillators, each IF local oscillator being configured as: receiving a first RF local oscillator signal of one or more RF local oscillator signals; receiving a corresponding delay value of a plurality of delay values, each of the delay values ​​specifying a delay of a plurality of cycles of the first RF local oscillator signal; as well as generating a first IF local oscillator signal by dividing the first RF local oscillator signal by an integer division ratio and shifting the first RF local oscillator signal by a corresponding delay value; a plurality of down-conversion mixers, each down-conversion mixer configured to receive a second RF local oscillator signal of the one or more RF local oscillator signals and an RF antenna signal of the plurality of RF antenna signals and generate therefrom a corresponding first IF data signal of the plurality of first IF data signals; as well as A plurality of first data signal mixers, each of the first data signal mixers is configured to receive a corresponding first IF data signal among the plurality of first IF data signals and a corresponding first IF local oscillator signal among the plurality of first IF local oscillator signals, and generate a first basic data signal therefrom.

22. The receiver of claim 21, wherein: Each of the plurality of IF local oscillators is further configured to generate a second IF local oscillator signal by dividing the second RF local oscillator signal by the integer division ratio and shifting a corresponding delay value, the first IF local oscillator signal and the second IF local oscillator signal forming an in-phase / quadrature IF local oscillator signal pair, the receiver further comprising: A plurality of second data signal mixers, each second data signal mixer is configured to receive a corresponding second IF data signal among the plurality of second IF data signals and a corresponding first IF local oscillator signal among the plurality of first IF local oscillator signals, and generate a second basic data signal therefrom, the first basic data signal and the second basic data signal forming an in-phase / quadrature basic data signal pair.

23. The receiver of claim 21, further comprising: One or more control circuits are configured to provide the plurality of delay values ​​to the plurality of IF local oscillators.

24. The receiver of claim 23, further comprising: A plurality of amplifiers are connected to receive and amplify corresponding ones of the plurality of RF antenna signals and provide each amplified RF antenna signal to a corresponding one of the plurality of down-conversion mixers.

25. The receiver of claim 24, the one or more control circuits further configured to provide the plurality of delay values ​​to the plurality of IF local oscillators and to provide a corresponding gain factor to each of the plurality of amplifiers, Each of the amplifiers is configured to amplify a received RF antenna signal among the plurality of RF antenna signals according to the corresponding gain factor.

26. The receiver according to any one of claims 21 to 25, further comprising: A plurality of RF filters, each RF filter being configured to receive and filter a corresponding RF antenna signal of the plurality of RF antenna signals.

27. The receiver according to any one of claims 21 to 25, further comprising: An array of multiple antennas, each antenna configured to receive an RF signal and provide the RF signal to the multiple down-conversion mixers.

28. A receiver according to any one of claims 21 to 25, wherein: The number of frequency synthesizers is one, and the first RF local oscillator signal is identical to the second RF local oscillator signal.

29. A receiver according to any one of claims 21 to 25, wherein: The one or more frequency synthesizers include a first frequency synthesizer configured to provide the first RF local oscillator signal and a second frequency synthesizer configured to provide the second RF local oscillator signal.

30. A receiver according to any one of claims 21 to 25, wherein: Each of the delay values ​​specifies a delay of an integer number of cycles.

31. A receiver according to any one of claims 21 to 25, wherein: Each of the delay values ​​specifies a delay of half an integer number of cycles.

32. A method for receiving a radio frequency (RF) signal, comprising: receiving, at each of a plurality of intermediate frequency (IF) local oscillators, a first RF local oscillator signal and a corresponding delay value of a plurality of delay values, each of the delay values ​​specifying a delay of a plurality of cycles of the first RF local oscillator signal; generating a first IF local oscillator signal by each of the IF local oscillators by dividing the first RF local oscillator signal by an integer division ratio and shifting the first RF local oscillator signal by a corresponding delay value; receiving, at each of the plurality of down-conversion mixers, a second RF local oscillator signal and a corresponding RF antenna signal of the plurality of RF antenna signals; generating, at each of the plurality of down-conversion mixers, a corresponding first IF data signal of a plurality of first IF data signals from the second RF local oscillator signal and the corresponding RF antenna signal; receiving, at each of the plurality of first data signal mixers, a corresponding first IF data signal of the plurality of first IF data signals and a corresponding first IF local oscillator signal of the plurality of first IF local oscillator signals; as well as At each of the plurality of first data signal mixers, a first base data signal is generated from a corresponding first IF data signal of the plurality of first IF data signals and a corresponding first IF local oscillator signal of the plurality of first IF local oscillator signals.

33. The method of claim 32, further comprising: exchanging one or more control signals between the receiver controller and the transmitter; determining, by the receiver controller, the delay value from the exchanged control signals; as well as A determined delay value is provided from the receiver controller to the IF local oscillator.

34. The method of claim 33, wherein: The determining of the delay value includes calculating, by the receiver controller, the delay value based on the exchanged control signal.

35. The method of claim 33, wherein: The determination of the delay value includes receiving the delay value from the transmitter in a control signal of the exchange.

36. The method of claim 33, further comprising: receiving, at each amplifier of the plurality of amplifiers, a corresponding RF antenna signal of the plurality of RF antenna signals and a corresponding gain factor; amplifying, at each amplifier of the plurality of amplifiers, a corresponding RF antenna signal of the plurality of RF antenna signals according to the gain factor; The receiver controller determines the gain factor based on the exchanged control signal; as well as The determined gain factor is provided from the receiver controller to the IF local oscillator.

37. The method according to any one of claims 32 to 36, further comprising: generating a second IF local oscillator signal by each of the IF local oscillators by dividing the second RF local oscillator signal by the integer division ratio and shifting a corresponding delay value, the first IF local oscillator signal and the second IF local oscillator signal forming an in-phase / quadrature IF local oscillator signal pair; receiving, at each of the plurality of second data signal mixers, a corresponding second IF data signal of the plurality of second IF data signals and a corresponding first IF local oscillator signal of the plurality of first IF local oscillator signals; as well as At each of the second data signal mixers, a corresponding second basic data signal is generated from a corresponding second IF data signal among the plurality of second IF data signals and a corresponding first IF local oscillator signal among the plurality of first IF local oscillator signals, the first basic data signal and the second basic data signal forming an in-phase / quadrature basic data signal pair.

38. The method according to any one of claims 32 to 36, further comprising: Filtering is performed at each of the plurality of RF filters to filter a corresponding RF antenna signal of the plurality of RF antenna signals.

39. A method according to any one of claims 32 to 36, wherein: The number of frequency synthesizers is one, and the first RF local oscillator signal is identical to the second RF local oscillator signal.

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