System, method, and apparatus for memory failure prediction

Abstract

The present disclosure relates to systems, methods, and apparatuses for memory failure prediction through image analysis using artificial neural networks. A sequence of images indicative of progression of memory failure in a region of an integrated circuit die can be generated from a physical layout of memory cells in the region. The artificial neural network can be trained to recognize graphical features in early images in the sequence and predict memory failure exhibited in subsequent images in the sequence based on the recognized graphical features. A computing device can use the artificial neural network to analyze an input image exhibiting current memory failure in the region and identify one or more memory cells in the region that are likely to have subsequent memory failure.

Description

[0001] Related applications

[0002] This application claims priority to provisional U.S. patent application serial number 63 / 185,275, filed May 6, 2021, the entire disclosure of which is hereby incorporated herein by reference. Technical Field

[0003] At least some of the embodiments disclosed herein generally relate to the prediction of memory failures, and more specifically, but not limited to, predictions using artificial neural networks (ANNs). Background Technology

[0004] Artificial neural networks (ANNs) use a network of neurons to process the inputs to the network and produce outputs from the network.

[0005] Deep learning has been applied to many fields, such as computer vision, speech / audio recognition, natural language processing, machine translation, bioinformatics, drug design, medical image processing, and games. Summary of the Invention

[0006] In one aspect, this disclosure relates to a method comprising: generating, in a computing device and according to a physical layout of a plurality of memory cells in a region of an integrated circuit die, an image sequence indicating the progression of memory faults in the region of the integrated circuit die; training an artificial neural network in the computing device using machine learning techniques to identify graphic features in the images, and predicting, based on the identified graphic features in a first image in the sequence, one or more memory faults displayed in a second image appearing after the first image in the sequence; receiving, in the computing device, a third image indicating one or more memory faults in the region of the integrated circuit die; analyzing, by the computing device, the third image using the artificial neural network; and identifying, based on the analysis, one or more memory cells in the region, the one or more memory cells being identified as having memory faults after the time of the third image.

[0007] In another aspect, this disclosure relates to an apparatus comprising: a memory storing instructions; and at least one processor configured via the instructions to: receive a sequence of images generated according to the physical layout of a plurality of memory cells in a region of an integrated circuit die to demonstrate the progression of memory faults in the region of the integrated circuit die; train an artificial neural network using machine learning techniques to identify graphic features in the images, and predict, based on the identified graphic features in a first image in the sequence, one or more memory faults displayed in a second image appearing after the first image in the sequence; receive a third image indicating one or more memory faults in the region of the integrated circuit die; and identify one or more memory cells in the region based on analysis of the third image using the artificial neural network, the one or more memory cells being identified as having memory faults after the time of the third image.

[0008] In another aspect, this disclosure relates to a non-transitory computer-readable storage medium for storing instructions that, when executed by a microprocessor in a computing device, cause the computing device to perform a method comprising: receiving, during a time period, first data identifying memory faults in areas of an integrated circuit die; receiving second data identifying the physical layout of a plurality of memory cells in the areas; generating, based on the first data and the second data, an image sequence indicating the progression of memory faults in the areas of the integrated circuit die; training an artificial neural network using machine learning techniques to identify graphic features in the images, and predicting, based on the identified graphic features in the first images in the sequence, one or more memory faults displayed in a second image appearing after the first images in the sequence; receiving third data identifying one or more memory faults in the areas of the integrated circuit die; generating, according to the physical layout, a third image displaying the one or more memory faults in the areas of the integrated circuit die; analyzing the third image using the artificial neural network; and identifying, based on the analysis, one or more memory cells in the areas, the one or more memory cells being identified as having memory faults after the time period of the third image. Attached Figure Description

[0009] The embodiments are illustrated by way of example and are not limited to the figures in the accompanying drawings, wherein similar element symbols indicate similar elements.

[0010] Figure 1 This describes a technique for predicting memory failures via image analysis using an artificial neural network (ANN) according to one embodiment.

[0011] Figures 2 to 5 This describes a memory state image for memory fault prediction according to some embodiments.

[0012] Figure 6 A memory failure prediction method according to one embodiment is demonstrated.

[0013] Figure 7 This is a block diagram of an example computer system in which embodiments of this disclosure may be operated. Detailed Implementation

[0014] At least some aspects of this disclosure are for memory fault prediction using image analysis performed by artificial neural networks.

[0015] An integrated circuit memory device may have one or more integrated circuit dies on which memory cells are formed. The memory cells fabricated on the integrated circuit dies may be programmed to store data by means of their states under voltages applied across the memory cells.

[0016] For example, if a memory cell is configured or programmed to be in a state that allows substantial current to flow through the memory cell at a voltage in a predefined voltage region, then the memory cell is considered to be configured or programmed to store a first bit value (e.g., 1 or 0); otherwise, the memory cell is storing a second bit value (e.g., 0 or 1).

[0017] Optionally, some types of memory cells can be configured or programmed to store more than one bit of data by having a threshold voltage in one of more than two separate voltage regions. The threshold voltage of a memory cell causes it to rapidly or abruptly change, snap, or jump from a non-conductive state to a conductive state when the voltage applied across the memory cell increases above the threshold voltage. The non-conductive state allows a small leakage current to pass through the memory cell; in contrast, the conductive state allows current exceeding the threshold amount to pass through. Therefore, memory devices can use sensors to detect changes or determine the conductive / non-conductive state of the memory device under one or more applied voltages to assess the level of the threshold voltage of the memory cell and thus its stored data or to classify it.

[0018] Threshold voltages of memory cells configured / programmed to be in different voltage regions can be used to represent different data values ​​stored in the memory cell. For example, the threshold voltage of a memory cell can be programmed to be in any of four predefined voltage regions; and each of these regions can be used to represent the bit value of a different two-bit data item. Therefore, given a two-bit data item, one of the four voltage regions can be selected based on the mapping between the two-bit data item and the voltage regions; and the threshold voltage of the memory cell can be adjusted, programmed, or configured to be in the selected voltage region to represent or store the given two-bit data item. To retrieve, identify, or read a data item from a memory cell, one or more read voltages can be applied across the memory cell to determine which of the four voltage regions contains the threshold voltage of the memory cell. Identification of the voltage regions containing the threshold voltage of the memory cell provides information about two-bit data items that have been stored, programmed, or written into the memory cell.

[0019] For example, a flash memory or crosspoint memory type memory cell can be configured or programmed to store one data item in single-level cell (SLC) mode, two data items in multi-level cell (MLC) mode, three data items in three-level cell (TLC) mode, four data items in four-level cell (QLC) mode, or five data items in five-level cell (PLC) mode.

[0020] The threshold voltage of a memory cell can vary or drift over a period of time, during use and / or read operations, and in response to specific environmental factors such as temperature changes. The rate of variation or drift can increase as the memory cell ages. Variation or drift can lead to errors when retrieving, accessing, or reading data items from the memory cell.

[0021] Some memory cells store electrical charge to represent state data stored in the memory cell. Charge leakage can cause state changes and therefore errors when reading the memory cell.

[0022] Random errors during memory cell reads can be detected and corrected using redundant information. Data stored in memory cells can be encoded to include redundant information to facilitate error detection and recovery. When data encoded with redundant information is stored in the memory subsystem, the subsystem can detect errors in the data represented by the voltage region of the threshold voltage of the memory cell, and / or recover the original data used to generate data for programming the threshold voltage of the memory cell. Recovery operations can be successful (or have a high probability of success) when the data represented by the threshold voltage of the memory cell and therefore retrieved directly from the memory cell in the memory subsystem contains few errors, or when the bit error rate in the retrieved data is low and / or when the amount of redundant information is high. For example, error detection and data recovery can be performed using techniques such as error correction codes (ECC), low-density parity-check (LDPC) codes, etc. However, recovery operations may fail (or have a high probability of failure) when the bit error rate is high and / or when the amount of redundant information is insufficient.

[0023] At least some aspects of this disclosure address the above and other disadvantages and / or challenges by generating images representing the health and usage of memory cells in a memory device, and by using image analysis techniques implemented with artificial neural networks to perform memory fault prediction.

[0024] For example, the spatial correlation of faults during memory cell reads can exhibit patterns visible in an image representing the state of memory cells formed on an integrated circuit die. Faults in localized areas on the integrated circuit die may grow over a period of time beyond the error recovery capability of error correction codes (ECCs). Fault growth can be visualized in an image and analyzed via artificial neural networks (e.g., using computer vision techniques) to predict subsequent memory faults. When fault progression can be predicted by observing a small number of recoverable errors, preemptive measures can be scheduled and deployed to avoid unrecoverable errors.

[0025] Figure 1 This describes a technique for predicting memory failures using an artificial neural network (ANN) via image analysis, according to one embodiment.

[0026] exist Figure 1 In this computing system, there is a host system 101 and a memory device 103. The host system 101 can send commands to access the memory device 103, such as commands to write data to the memory device 103, commands to read data from the memory device 103, commands to erase data from the memory device 103, etc.

[0027] The memory device 103 may have memory cells formed on an integrated circuit die. The memory cell physical layout 107 specifies the location where the memory cells are individually disposed on the integrated circuit die in the memory device 103. Optionally, the memory cell physical layout 107 may further identify structures, elements, or features in the integrated circuit die that may be related to memory failure, such as the location of voltage drivers configured to apply voltage to the memory cells, wires connecting the voltage drivers to the memory cells, etc.

[0028] During the operation of the computing system, the host system 101 may generate health and usage data 105 for memory cells at various memory addresses. For example, health and usage data 105 may indicate when a memory failure occurred at the memory cell identified by the memory address. For example, health and usage data 105 may identify the time of the last refresh or write to the memory cell. For example, health and usage data 105 may identify the age of the memory cell based on the programming / erase cycles the memory cell has undergone.

[0029] The memory status image 109 can be generated from health and usage data 105 and the physical layout of memory cells 107. For example, in the image 109 corresponding to the physical layout of memory cells 107, the areas or locations of memory cells in the physical layout 107 can be identified by color and / or shape markings to identify the health and usage data 105 of memory cells at a given time.

[0030] For example, a memory cell may be shown in memory state image 109 at a location corresponding to its physical location in a page, block, array, layer, or region on an integrated circuit die.

[0031] For example, a memory cell may be shown as a pixel or a group of pixels in the memory status image 109.

[0032] For example, whether a read error has occurred in a memory cell can be indicated by the color of one or more pixels representing the memory cell.

[0033] For example, usage data related to the prediction of memory failures (e.g., read errors, write errors) can be colored as a background color in the relevant area or presented as a symbol or shape at a relevant location on the memory status image 109. For example, the time of the last write to a memory cell area, the age of the memory cell in the area, etc., can be graphically represented in the memory status image 109.

[0034] The memory status image 109 graphically displays the progression of memory faults over time at various locations on the integrated circuit die. The graphical representation of health and usage data 105 on the physical layout 107 of the memory cells, presented in the form of the memory status image 109, can be visually inspected to predict fault patterns.

[0035] exist Figure 1 In this context, the artificial neural network 111 is trained using machine learning techniques. For example, computer vision, image segmentation, and image pattern recognition techniques can be applied to the memory status image 109 to identify identified image segments 113 and predicted faults 115 exhibiting memory fault progression patterns. Machine learning techniques reduce the discrepancy between the predicted fault 115 and the memory faults identified in the health and usage data 105 and reflected in the corresponding graphical features in the memory status image 109.

[0036] For example, memory failure patterns that evolve from several early errors to subsequent errors in a local region of the memory state image 109 can be identified by the artificial neural network 111 and used to train predictions of subsequent errors. Subsequently, when a pattern of early errors is discovered in another local region and identified by the artificial neural network 111, the artificial neural network 111 can predict subsequent errors that have been observed and thus trained from similar subsequent errors in other regions.

[0037] Figures 2 to 5 This describes a memory state image for memory fault prediction according to some embodiments. For example, Figures 2 to 5 The images described herein can be used for implementation Figure 1 The technology.

[0038] Figure 2 A memory state image 121 is shown, in which a typical memory cell 119 on an integrated circuit die is displayed in the memory state image 121 at its location according to its layout on the integrated circuit die. Therefore, the spatial relationship between memory cells in the memory state image 121 represents the spatial relationship of corresponding memory cells on the integrated circuit die.

[0039] Memory cells with memory faults (e.g., read errors) (e.g., 133 and 135) are presented in memory status image 121 in a way that is visually different from other memory cells (e.g., 137) that do not yet have memory faults.

[0040] Figure 3 The image shows subsequent memory status images 123, which are in Figure 2 The memory cell 137 near the memory error clusters at memory cells 133 and 135, as shown in the earlier memory state image 121, has a new memory fault.

[0041] When a memory fault grows in a localized area on an integrated circuit die, the graphic features of image segment 131 are identifiable in memory status images 121 and 123.

[0042] The artificial neural network 111 can be trained to recognize the identified image segment 131 (e.g., using image segmentation techniques in computer vision and / or image processing).

[0043] In addition, the artificial neural network 111 is trained to predict subsequent errors in the memory unit 137 based on the graphic image features in the image segment 131.

[0044] Figure 2 and 3 An example of a graphical representation illustrating the progression of a memory fault in the memory region represented by image segment 131. Generally, health and usage data 105 from the computing system provides several observed cases, which can be used to train an artificial neural network 111 to identify image segment 113 and to predict fault 115 in a manner consistent with the observed fault cases identified in the health and usage data 105.

[0045] Figure 4 Examples illustrating the predictive power of artificial neural networks 111. Figure 4 In this context, artificial neural networks (111) possess the ability to recognize and... Figure 2 Image segment 141 shows a pattern of similar graphic features to image segment 131. Because... Figure 3 The previously processed memory state image 123 is used to train an artificial neural network 111 to predict memory failures in memory cells 137 within image segment 131. Therefore, the artificial neural network 111 can predict that a memory failure is likely to occur in memory cell 147 within image segment 141. This prediction can be used by the host system 101 to take actions to prevent data loss and / or interruption. For example, the host system 101 can generate a command to refresh the data in the memory area corresponding to image segment 141. For example, the host system 101 can generate a command to create a redundant copy of the data in the memory area corresponding to image segment 141. For example, the host system 101 can generate a command to move data from the memory area corresponding to image segment 141 to another memory area.

[0046] In one implementation, each memory cell with a memory fault (e.g., 133, 135) is represented by a pixel with a predetermined color (e.g., black). The spatial relationship between pixels is proportional to the distance between corresponding memory cells in the integrated circuit die. Furthermore, pixels with other colors can be used to indicate the usage status of corresponding memory cells without memory faults. For example, a grayscale level of brightness can be used to indicate the time elapsed since the last write, the age of the memory cell, the number of erase operations applied to the memory cell, or another parameter related to the prediction of a memory fault. For example, the red, green, and blue channels of a pixel's color can be used to represent three health and / or usage parameters of the memory cell.

[0047] In another embodiment, each memory cell (e.g., 119) is represented by a set of pixels having a shape (e.g., a square or a circle). Health and usage data 105 of the memory cell (e.g., 119) may be presented via the shape and / or color of at least some of the pixels representing the memory cell (e.g., 119).

[0048] Figure 5 The memory status image 125 illustrates that a shape (e.g., a circle) with a color (e.g., black) is used to represent memory cells with memory faults (e.g., 133, 135, 137, 143, 145), while another shape (e.g., a square) with a different color (e.g., white) is used to represent memory cells without memory faults (e.g., 147).

[0049] The shape of a memory cell can be superimposed on the area representing one or more parameters common to memory cells in the area representing the background color.

[0050] Furthermore, some features or parameters of the memory cells, as specified in the physical arrangement 107, can be displayed on the memory status image 109. For example, the electrical distance to the voltage driver can be represented by the background color of the memory cell.

[0051] When health and usage data 105 and memory physical layout 107 are visually presented in memory status image 109, artificial neural network 111 can be used to learn the development pattern of memory faults in local memory regions and predict faults 115.

[0052] Figure 6 A memory failure prediction method according to one embodiment is illustrated. For example, Figure 6 The operation can be used Figure 1 technology and Figures 2 to 5 The memory state image described herein is used for implementation.

[0053] In box 181, the computing device receives first data over a period of time to identify memory faults in a region of the integrated circuit die.

[0054] For example, the first data may be provided by a computing device having a host system 101 and a memory device 103 having memory cells on an integrated circuit die during the use of the memory device 103. The first data may include health and usage data 105 about the memory cells at memory addresses used by the host system 101 and / or the memory device 103.

[0055] In one embodiment, the computing device having host system 101 and memory device 103 may be part of a computing device. In another embodiment, the computing device operates independently of the computing device having host system 101. For example, the computing device may receive first data from the computing device via a wired or wireless computer connection. For example, the computing device may be a server computer connected to host system 101.

[0056] In box 183, the computing device receives second data of the physical layout 107 of multiple memory cells in the area that identifies the integrated circuit die.

[0057] In box 185, the computing device generates an image sequence 109 based on first data and second data, indicating the progression of a memory fault in a region of an integrated circuit die.

[0058] For example, pixels representing multiple memory cells in an area can be configured in image 109 to be located at positions corresponding to the multiple memory cells in an area of ​​an integrated circuit die. Therefore, the spatial relationship between memory cells is represented by the spatial relationship between groups of pixels representing the respective memory cells.

[0059] In box 187, the computing device uses machine learning techniques to train an artificial neural network 111 to identify graphic features in an image and predict one or more memory faults in a second image 123 that appears after the first image in the sequence based on the identified graphic features in the first image 121 in the sequence.

[0060] For example, each corresponding memory cell with a memory fault in the region is represented in the first image by at least one pixel at a location corresponding to the location of the corresponding memory cell in the region on the integrated circuit die.

[0061] For example, a corresponding memory cell with a memory fault can be represented in the first image 121 by a plurality of pixels with predefined shapes. The shapes can be the same as or different from the shapes of the pixels representing memory cells without memory faults.

[0062] For example, multiple pixels in the first image representing corresponding memory cells with memory faults may have one or more predefined colors that are different from those representing memory cells without memory faults.

[0063] Optionally, the first image 121 may include pixels representing structural features associated with a plurality of memory cells in the region, such as the electrical distance from a memory cell to its driver.

[0064] Optionally, the first image 121 may include pixels with attributes that represent the use of multiple memory cells in the indication area, such as the time since the last write / refresh operation, the age of the memory cell, etc.

[0065] For example, the artificial neural network 111 can be configured to perform image segmentation to identify portions of the first image 131 (e.g., image segment 131) to recognize graphic features in those portions. Therefore, the development of patterns of graphic features in local areas of the memory state image 121 can be identified and used to train the artificial neural network 111 to make predictions in other local areas of the memory state image 121.

[0066] In box 189, the computing device receives third data that identifies one or more memory faults in the area of ​​the integrated circuit die.

[0067] In frame 191, the computing device generates a third image 125 based on physical layout 107, showing one or more memory faults in an area of ​​the integrated circuit die.

[0068] In box 193, the computing device uses an artificial neural network 111 to analyze the third image 125.

[0069] In box 195, the computing device identifies / predicts one or more memory cells (e.g., 147) in the region that are identified as having memory faults after the time of the third image 125, based on analysis of the third image 125 using an artificial neural network 111.

[0070] An identified / predicted memory failure in one or more memory cells (e.g., 147) can cause the computing device and / or host system 101 to determine whether to perform operations to prevent data loss and / or interruption. For example, a data refresh operation may be performed in an area of ​​an integrated circuit die in response to one or more memory cells being identified as having a memory failure. For example, redundant copies of data in an area may be stored in response to one or more memory cells being identified as having a memory failure. For example, data in an area may be moved to a different area in response to one or more memory cells being identified as having a memory failure.

[0071] Figure 7The computer system 200 is described as an example machine within which a set of instructions can be executed to cause the machine to perform any or more of the methodologies discussed herein. In some embodiments, the computer system 200 may correspond to a host system that includes, is coupled to, or utilizes a memory subsystem or is available for performing operations of the memory failure predictor 206 (e.g., executing instructions to perform operations corresponding to...). Figures 1 to 6 (The described operation of memory fault prediction). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0072] A machine can be a server, a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network facility, a network router, a switch, or a bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) specifying actions to be taken by said machine. Furthermore, while describing a single machine, the term "machine" should also be considered as any collection of machines that individually or jointly execute a set (or more) of instructions to perform any or more of the methodologies discussed herein.

[0073] The example computer system 200 includes a processing device 202, a main memory 204 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), static random access memory (SRAM), etc.) and a data storage system 218, which communicate with each other via a bus 230 (which may include multiple buses).

[0074] Processing device 202 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or multiple processors implementing combinations of instruction sets. Processing device 202 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 202 is configured to execute instructions 226 for performing the operations and steps discussed herein. Computer system 200 may further include a network interface device 208 for communication via network 220.

[0075] Data storage system 218 may include one or more sets of instructions 226 or software embodying any or more of the methodologies or functions described herein, stored thereon on machine-readable medium 224 (also referred to as computer-readable medium). Instructions 226 may also reside wholly or at least partially in main memory 204 and / or processing device 202 during execution by computer system 200, which also constitute machine-readable storage medium. Machine-readable medium 224, data storage system 218, and / or main memory 204 may correspond to a memory subsystem.

[0076] In one embodiment, instruction 226 includes functionality for implementing the memory fault predictor 206 (e.g., regarding...). Figures 1 to 6 The instructions (described in the memory fault prediction operation) are described. Although machine-readable medium 224 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered as a single medium or multiple media containing one or more sets of instructions. The term "machine-readable storage medium" should also be considered as any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any or more of the methodologies of this disclosure. Therefore, the term "machine-readable storage medium" should be considered as including, but not limited to, solid-state memory, optical media, and magnetic media.

[0077] Some parts of the aforementioned specific embodiments have been presented based on algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are methods used by those skilled in the art of data processing to most effectively communicate the main points of their work to others skilled in the art. Algorithms are, and generally are, conceived herein as self-consistent sequences of operations that lead to desired results. Operations are operations that require the physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been shown that, primarily for general reasons, it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc.

[0078] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient labels for application to those quantities. This disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulate and convert data representing physical (electronic) quantities in the registers and memories of a computer system into other data representing physical quantities similarly represented in the memory or registers of a computer system or other such information storage systems.

[0079] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for its intended purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each of which is coupled to a computer system bus.

[0080] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to execute the methods. The structures of various such systems will appear as described below. Furthermore, this disclosure is not described with reference to any particular programming language. It should be understood that a wide variety of programming languages ​​can be used to implement the teachings of this disclosure as described herein.

[0081] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being usable to program a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any means for storing information in a form readable by a machine (e.g., a computer). In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0082] In this description, various functions and operations are described as being executed or caused by computer instructions for the sake of simplicity. However, those skilled in the art will recognize that such expressions mean that the function arises from the execution of computer instructions by one or more controllers or processors, such as microprocessors. Alternatively or in combination, functions and operations may be implemented using dedicated circuit systems with or without software instructions, such as application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs). Embodiments may be implemented using hardwired circuit systems with or without software instructions. Therefore, the technology is neither limited to any particular combination of hardware circuit systems and software, nor to any particular source of instructions executed by a data processing system.

[0083] In the foregoing description, embodiments thereof have been described with reference to specific examples of this disclosure. It is apparent that various modifications may be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the specification and drawings should be viewed in an illustrative rather than restrictive manner.

Claims

1. A method comprising: In a computing device, an image sequence is generated that indicates the progression of a memory fault in the region of the integrated circuit die, based on the physical layout of multiple memory cells in a region of the integrated circuit die. The computing device uses machine learning techniques to train an artificial neural network to identify graphic features in the image, and predicts one or more memory faults in a second image that appears after the first image in the sequence based on the identified graphic features in the first image in the sequence. Receive in the computing device a third image indicating one or more memory faults in the region of the integrated circuit die; The computing device analyzes the third image using the artificial neural network; and Based on the analysis, one or more memory cells in the region are identified, and the one or more memory cells are identified as having a memory fault after the time of the third image.

2. The method of claim 1, wherein each corresponding memory cell with a memory fault in the region is represented in the first image by at least one pixel at a position corresponding to the location of the corresponding memory cell in the region on the integrated circuit die.

3. The method of claim 2, wherein the corresponding memory unit in the first image is represented by a plurality of pixels having a predefined shape.

4. The method of claim 3, wherein the plurality of pixels in the first image representing the corresponding memory cells have a predefined color that is different from the color of the pixels representing memory cells without memory faults.

5. The method of claim 4, wherein the first image comprises pixels representing structural features associated with the plurality of memory cells in the region.

6. The method of claim 4, wherein the first image comprises pixels having attributes representing data indicating the use of the plurality of memory units in the region.

7. The method of claim 4, wherein the artificial neural network is configured to perform image segmentation to identify portions of the first image to identify graphic features in the portions.

8. The method of claim 4, further comprising: In response to one or more memory cells being identified as having a memory fault, a data refresh operation is performed in the region.

9. The method of claim 4, further comprising: In response to one or more memory cells being identified as having a memory fault, a redundant copy of the data in the area is stored.

10. The method of claim 4, further comprising: In response to one or more memory cells being identified as having a memory fault, data is moved from the area to a different area.

11. An apparatus comprising: Memory, which stores instructions; and At least one processor configured via the instructions to: Receive a sequence of images generated based on the physical layout of multiple memory cells in a region of an integrated circuit die to demonstrate the progression of a memory fault in the region of the integrated circuit die; The artificial neural network is trained using machine learning techniques to identify graphic features in the images, and one or more memory faults are predicted in a second image that appears after the first image in the sequence based on the identified graphic features in the first image in the sequence. Receive a third image indicating one or more memory faults in the region of the integrated circuit die; and Based on the analysis of the third image using the artificial neural network, one or more memory cells in the region are identified, and the one or more memory cells are identified as having a memory fault after the time of the third image.

12. The device of claim 11, wherein each corresponding memory cell with a memory fault in the region is represented in the corresponding image of the sequence by at least one pixel at a position corresponding to the location of the corresponding memory cell in the region on the integrated circuit die.

13. The device of claim 12, wherein the respective memory cell in the respective image is represented by a plurality of pixels having a shape different from that representing a memory cell without a memory fault.

14. The device of claim 13, wherein the plurality of pixels representing the memory cells in the corresponding image have a predefined color that is different from one or more colors of the pixels representing memory cells without memory faults.

15. The device of claim 14, wherein the first image comprises pixels representing structural features associated with the plurality of memory cells in the region.

16. The device of claim 14, wherein the first image comprises pixels having attributes representing data indicating the use of the plurality of memory units in the region.

17. The apparatus of claim 14, wherein the artificial neural network is configured to perform image segmentation to identify portions of the first image to identify graphic features in the portions.

18. A non-transitory computer-readable storage medium storing instructions, said instructions, when executed by a microprocessor in a computing device, causing the computing device to perform a method, said method comprising: Receive the first data within a certain time period to identify memory faults in the area of ​​the integrated circuit die; Receive second data identifying the physical layout of multiple memory cells in the region; Based on the first data and the second data, an image sequence is generated indicating the progression of a memory fault in the region of the integrated circuit die; The artificial neural network is trained using machine learning techniques to identify graphic features in the images, and one or more memory faults are predicted in a second image that appears after the first image in the sequence based on the identified graphic features in the first image in the sequence. Receive third data that identifies one or more memory faults in the region of the integrated circuit die; A third image is generated based on the physical layout, showing one or more memory faults in the area of ​​the integrated circuit die; The third image is analyzed using the artificial neural network. and Based on the analysis, one or more memory cells in the region are identified, and the one or more memory cells are identified as having a memory fault after the time of the third image.

19. The non-transitory computer-readable storage medium of claim 18, wherein the pixels representing the plurality of memory cells in the region are configured to be located at positions corresponding to the positions of the plurality of memory cells in the region of the integrated circuit die.

20. The non-transitory computer-readable storage medium of claim 19, wherein the first data includes health and usage information of the plurality of memory cells in the area; and indicates that the pixels of the plurality of memory cells in the area are configured to have attributes representing the health and usage information.

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