Display panel and display device

Abstract

The present application provides a display panel and a display device, relating to the field of display technology. The display panel includes: a first substrate and a second substrate stacked together; a first conductive layer located between the first substrate and the second substrate, including a signal connection line; a second conductive layer located on a side of the second substrate away from the first conductive layer, including a first bonding line, the first bonding line being connected to the signal connection line via a first via; and a third conductive layer located on a side of the second conductive layer away from the first conductive layer, including a data signal line, the data signal line being electrically connected to the first bonding line. The data signal line is electrically connected to the signal connection line located between the first substrate and the second substrate.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Organic Light-Emitting Diode (OLED) displays are widely used in mobile phones, tablets, televisions, and other applications due to their excellent performance, such as self-luminescence and high color saturation. However, in the application process, it has been found that in order to increase the screen-to-body ratio of OLED displays, the structure of the display panel becomes complex. Summary of the Invention

[0003] The embodiments of the present application provide a display panel and a display device, and provide a display panel with a new structural form.

[0004] In one aspect, an embodiment of the present application provides a display panel, comprising:

[0005] A first substrate and a second substrate are stacked;

[0006] a first conductive layer, located between the first substrate and the second substrate, comprising signal connection lines;

[0007] a second conductive layer, located on a side of the second substrate away from the first conductive layer, comprising a first bonding wire connected to the signal connection wire through a first via;

[0008] The third conductive layer is located on a side of the second conductive layer away from the first conductive layer, and includes a data signal line, and the data signal line is electrically connected to the first bonding line.

[0009] In some embodiments, the display panel further includes a fourth conductive layer, where the fourth conductive layer is located on a side of the third conductive layer away from the first conductive layer;

[0010] The fourth conductive layer includes a power line, the third conductive layer also includes a third bonding line, the second conductive layer also includes a second bonding line, and the first conductive layer also includes a power connection line;

[0011] The second bonding wire is connected to the power connection wire through a second via hole; the power line is electrically connected to the power connection wire through a third bonding wire and a second bonding wire in sequence.

[0012] In some embodiments, the display panel further includes an anode layer and a cathode layer, wherein the cathode layer is located on a side of the anode layer away from the fourth conductive layer;

[0013] The anode layer includes an anode and a fourth bonding wire that are not connected to each other; the first conductive layer also includes a cathode connection wire; the second conductive layer also includes a fifth bonding wire, the third conductive layer also includes a sixth bonding wire, and the fourth conductive layer also includes a seventh bonding wire;

[0014] The fifth bonding wire is connected to the cathode connection wire through a third via hole, and the cathode layer is electrically connected to the cathode connection wire through the fourth bonding wire, the seventh bonding wire, the sixth bonding wire, and the fifth bonding wire in sequence.

[0015] In some embodiments, the display panel includes a display area and a non-display area located around the display area, the signal connection line, the power connection line and the cathode connection line are located in the display area, and at least one of the first via hole, the second via hole and the third via hole is located in the non-display area.

[0016] In some embodiments, the first via hole, the second via hole, and the third via hole are all located in the non-display area.

[0017] In some embodiments, the second via hole and the third via hole are located in the non-display area, and the first via hole is located in the display area.

[0018] In some embodiments, an insulating layer is further provided between the second substrate and the second conductive layer, and the first via penetrates the insulating layer and the second substrate;

[0019] The sidewall of the first via located on the insulating layer includes a first sidewall, a second sidewall, and a step surface connecting the first sidewall and the second sidewall; the projection of the step surface on the first conductive layer is located within the projection of the second substrate on the first conductive layer.

[0020] In some embodiments, the insulating layer includes a first sublayer and a second sublayer, the second sublayer is located on a side of the first sublayer away from the second substrate, and the step surface and the second sidewall are located on the first sublayer.

[0021] In some embodiments, the first sublayer is an inorganic layer, and the second substrate is a polyimide film.

[0022] In some embodiments, the distance between the step surface and the second substrate is less than or equal to

[0023] In some embodiments, a fifth conductive layer is further provided between the first conductive layer and the second conductive layer, and the fifth conductive layer includes a gate.

[0024] On the other hand, an embodiment of the present application provides a display device including the display panel.

[0025] The display panel and display device provided by the embodiments of the present application have a signal connection line arranged between the first substrate and the second substrate, the first jumper line is electrically connected to the signal connection line through the first via hole, and the data signal line in the third conductive layer is electrically connected to the first jumper line, thereby electrically connecting the data signal line to the signal connection line located between the first substrate and the second substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0027] Figure 1 A schematic diagram of a mobile phone display module in the related art;

[0028] Figures 2 to 4 A cross-sectional view of a display panel provided in an embodiment of the present application;

[0029] Figures 5 to 7 A wiring diagram of a display panel provided in an embodiment of the present application;

[0030] Figures 8 to 12 is a schematic diagram of a first via hole in the related art;

[0031] Figure 13 Schematic diagram of a first via hole in an embodiment of the present application;

[0032] Figure 14 16 are schematic diagrams of preparing the first via hole in an embodiment of the present application.

[0033] Reference numerals:

[0034] 100-display panel;

[0035] 110 - substrate; 120 - first substrate; 130 - buffer layer; 140 - first conductive layer; 150 - second substrate; 160 - insulating layer;

[0036] 171-first lap joint; 172-second lap joint; 173-fifth lap joint;

[0037] 181 - data signal line; 182 - third bonding line; 183 - sixth bonding line;

[0038] 191-power line; 192-seventh bonding line;

[0039] 211 - fourth bonding wire; 212 - anode;

[0040] 220- cathode layer; 230- fifth conductive layer;

[0041] 161-pointed structure; 162-first via hole; 163-step surface;

[0042] 300-Photoresist. DETAILED DESCRIPTION

[0043] The present application provides a display device. The display device may be a mobile phone, a laptop computer, an ultra-mobile personal computer (UMPC), a netbook, a personal digital assistant (PDA), a wearable device, a virtual reality device, a mobile computing device, or other device having a display module, although the present application is not limited thereto. For ease of description, the present application uses a mobile phone as an example for the display device.

[0044] like Figure 2 As shown, the present application provides a display panel 100 , which includes a first conductive layer 140 , a second conductive layer, a third conductive layer, and a first substrate 120 and a second substrate 150 that are stacked.

[0045] The first substrate 120 and the second substrate 150 may be flexible substrates, such as polyimide film (PI film), so that the display panel 100 can be bent. The first substrate 120 and the second substrate 150 may also be rigid substrates, which is not limited in this application.

[0046] When the first substrate 120 and the second substrate 150 are flexible substrates and the display panel 100 does not need to be bent, a substrate 110 (eg, a glass substrate) may be provided on a side of the first substrate 120 away from the second substrate 150 to support the first substrate 120 and the second substrate 150 .

[0047] The first conductive layer 140 is located between the first substrate 120 and the second substrate 150. The first conductive layer 140 is formed with a plurality of connection lines, wherein the plurality of connection lines include signal connection lines. The signal connection lines are used to electrically connect to the driver chip of the display panel 100, so as to transmit the data signal of the driver chip to the data signal line through the signal connection line, and then write the data signal into the data write transistor.

[0048] In order to prevent conductive particles in the plurality of connection lines between the first substrate 120 and the second substrate 150 from entering the first substrate 120 , a buffer layer 130 may be further disposed between the first conductive layer 140 and the first substrate 120 .

[0049] The second conductive layer is located on a side of the second substrate 150 away from the first conductive layer 140 and includes a first bonding wire 171. In practical applications, the second conductive layer may include multiple first bonding wires 171, each of which is not connected to another. For example, each signal connection line corresponds to a first bonding wire 171.

[0050] A first via 162 may be provided between the first conductive layer 140 and the second conductive layer. The first via 162 penetrates the structure between the second conductive layer and the first conductive layer 140 , so that the first bonding wire 171 may be connected to the signal connection wire through the first via 162 .

[0051] For example, the first bonding line 171 may include a connection structure extending along the sidewall of the first via hole 162 toward the first conductive layer 140 , and the first bonding line 171 is connected to the signal connection line through the connection structure.

[0052] In actual application, an insulating layer 160 may be further provided on the side of the second substrate 150 facing away from the first substrate 120. The insulating layer 160 and the second substrate 150 are etched through an etching process to form a first via 162 that penetrates the insulating layer 160 and the second substrate 150. The signal connection line between the first substrate 120 and the second substrate 150 is exposed through the first via 162. A conductive layer (i.e., a connection structure) is formed on the sidewalls of the first via 162 and on the signal connection line exposed through the first via 162 through a deposition process, thereby electrically connecting the first bonding line 171 on the insulating layer 160 to the signal connection line through the connection structure.

[0053] Of course, the connection structure may also be filled in the first via hole 162 , thereby achieving electrical connection between the first bonding wire 171 and the signal connection wire.

[0054] The third conductive layer is located on a side of the second conductive layer away from the first conductive layer 140, and the third conductive layer includes a data signal line 181. The data signal line 181 refers to a line electrically connected to the data write transistor. In actual application, the display panel 100 is provided with a plurality of sub-pixels arranged in an array, and each sub-pixel is provided with a data write transistor and a drive transistor. Among them, each column of sub-pixels is provided with a data signal line 181, and the data signal line 181 is electrically connected to the data write transistor of the sub-pixel in this column. That is, a plurality of data signal lines 181 are provided on the third conductive layer, and each data signal line 181 corresponds to a column of sub-pixels.

[0055] The data signal line 181 is electrically connected to the first bonding line 171. For example, an insulating layer 160 may be provided between the third conductive layer and the second conductive layer, and the data signal line 181 may be electrically connected to the first bonding line 171 through a via structure.

[0056] In the embodiments of the present application, each conductive layer can be a metal layer or a non-metal layer such as a semiconductor, as long as it can achieve conductivity. The insulating layer 160 can be an organic insulating layer or an inorganic insulating layer. The present application does not limit the materials of the conductive layer and the insulating layer 160.

[0057] The display panel 100 and the display device provided in the embodiment of the present application are provided with a signal connection line between the first substrate 120 and the second substrate 150, the first bonding line 171 is electrically connected to the signal connection line through the first via 162, and the data signal line 181 in the third conductive layer is electrically connected to the first bonding line 171, so that the data signal line 181 is electrically connected to the signal connection line located between the first substrate 120 and the second substrate 150.

[0058] Figure 1 Schematic diagram of a mobile phone display module in the related art, in which VDD refers to the power connection line and Vss refers to the cathode connection line. Figure 1 As shown, since fan-out wiring is required at the two chamfers at the lower end of the display panel 100 to lead out the data signal line, power connection line, and cathode connection line of the display panel 100 and bend them to the back of the display panel 100, the non-display area at the lower end of the display panel 100 is increased, reducing the screen-to-body ratio of the display device. Moreover, when the power connection line and the cathode connection line are arranged on the same layer, the bending area of ​​the power connection line and the cathode connection line is increased, further reducing the screen-to-body ratio of the display device. In the embodiment of the present application, it is not necessary to lead out the data signal line through the fan-out wiring at the lower end of the display panel, which reduces the area of ​​the non-display area of ​​the display panel and improves the screen-to-body ratio of the display device.

[0059] like Figure 3 As shown, the display panel 100 further includes a fourth conductive layer, which is located on a side of the third conductive layer away from the first conductive layer 140 , and an insulating layer may be further provided between the fourth conductive layer and the third conductive layer.

[0060] The fourth conductive layer includes a power line 191 , which is electrically connected to one electrode of the driving transistor, and the other electrode of the driving transistor is electrically connected to the anode of the light emitting unit.

[0061] The first conductive layer 140 further includes a power connection line, and the power connection line and the signal connection line are not connected to each other.

[0062] The second conductive layer further includes a second bonding line 172 . The second bonding line 172 is not connected to the first bonding line 171 . The second bonding line 172 is electrically connected to the power connection line through a second via hole.

[0063] In actual application, an insulating layer 160 may be further provided on the side of the second substrate 150 facing away from the first substrate 120. An etching process is performed on the insulating layer 160 and the second substrate 150 to form a second via hole, through which the power connection line between the first substrate 120 and the second substrate 150 is exposed. A conductive layer is formed on the sidewalls of the second via hole and on the power connection line exposed through the second via hole through a deposition process, thereby electrically connecting the second bonding line 172 located on the insulating layer 160 to the power connection line through the conductive layer.

[0064] The structure of the second via hole can be the same as or different from that of the first via hole 162. Correspondingly, the structure of the second bonding wire 172 can be the same as or different from that of the first bonding wire 171. When the structures of the first via hole 162 and the second via hole, and the structures of the first bonding wire 171 and the second bonding wire 172 are the same, the processing difficulty can be reduced.

[0065] The third conductive layer further includes a third bonding line 182, which is not connected to the data signal line 181. The power line 191 is electrically connected to the power connection line via the third bonding line 182 and the second bonding line 172 in sequence.

[0066] A power connection line is set between the first substrate 120 and the second substrate 150, the second bonding line 172 is electrically connected to the power connection line through the second via, the third bonding line 182 in the third conductive layer is electrically connected to the second bonding line 172, and the power line 191 in the fourth conductive layer is electrically connected to the third bonding line 182, so that the power line 191 is electrically connected to the power connection line located between the first substrate 120 and the second substrate 150.

[0067] like Figure 4 As shown, the display panel 100 further includes an anode layer and a cathode layer 220. The cathode layer 220 is located on the side of the anode layer away from the fourth conductive layer. The anode layer includes the anode 212 of the light-emitting unit, and the cathode layer 220 includes the cathode of the light-emitting unit. An organic light-emitting layer is disposed between the anode 212 and the cathode. During operation, when the anode 212 and the cathode are energized, the organic light-emitting layer emits light.

[0068] The first conductive layer 140 further includes a cathode connection line, which is not connected to the power connection line or the signal connection line and is used to connect to the ground line.

[0069] The second conductive layer further includes a fifth bonding line 173, which is not connected to the first bonding line 171 or the second bonding line 172. The fifth bonding line 173 is electrically connected to the cathode connection line through a third via hole.

[0070] In actual application, an insulating layer 160 may be further provided on the side of the second substrate 150 facing away from the first substrate 120. An etching process is performed on the insulating layer 160 and the second substrate 150 to form a third via hole, through which the cathode connection line located between the first substrate 120 and the second substrate 150 is exposed. A conductive layer is formed on the sidewalls of the third via hole and on the power connection line exposed through the third via hole through a deposition process, thereby electrically connecting the fifth bonding line 173 located on the insulating layer 160 to the cathode connection line through the conductive layer.

[0071] The structure of the third via can be the same as or different from that of the first and second vias 162. Accordingly, the structure of the fifth bonding wire 173 can be the same as or different from that of the first and second bonding wires 171 and 172. When the structures of the third via, the first and second vias 162 and 172 are the same, and when the structures of the fifth bonding wire 173, the first and second bonding wires 171 and 172 are the same, processing difficulty can be reduced.

[0072] The third conductive layer further includes a sixth bonding line 183, which is electrically connected to the fifth bonding line 173. The sixth bonding line 183 is not connected to the third bonding line 182 and the data signal line 181, which are also located in the third conductive layer.

[0073] The anode layer also includes a fourth bonding wire 211, which is not connected to the anode 212. The fourth conductive layer also includes a seventh bonding wire 192, which is electrically connected to the fourth bonding wire 211 and the seventh bonding wire 192. The cathode layer 220 is electrically connected to the fourth bonding wire 211. The cathode layer 220 is electrically connected to the cathode connection line via the fourth bonding wire 211, the seventh bonding wire 192, the sixth bonding wire 183, and the fifth bonding wire 173, in sequence. The seventh bonding wire 192 is not connected to the power connection line 191, which is also located in the fourth conductive layer.

[0074] A cathode connection line is provided between the first substrate 120 and the second substrate 150. The fifth bonding line 173 in the second conductive layer is electrically connected to the cathode connection line through a third via. The sixth bonding line 183 in the third conductive layer is electrically connected to the fifth bonding line 173. The seventh bonding line 192 in the fourth conductive layer is electrically connected to the sixth bonding line 183. This electrically connects the cathode to the cathode connection line located between the first substrate 120 and the second substrate 150. Therefore, there is no need to lead the cathode connection line out from the lower end of the display panel 100 via a fan-out routing, which reduces the area of ​​the non-display region of the display panel 100 and improves the screen-to-body ratio of the display device.

[0075] A fifth conductive layer 230 is further provided between the first conductive layer 140 and the second conductive layer. The fifth conductive layer 230 includes a gate.

[0076] For example, Figure 4 As shown, an inorganic insulating layer is provided on the side of the second substrate 150 facing away from the first substrate 120. An active layer is provided on the side of the inorganic insulating layer facing away from the second substrate 150. An active layer insulating layer is provided on the side of the active layer facing away from the first substrate 120. A fifth conductive layer 230 is provided on the side of the active layer insulating layer facing away from the first substrate 120. The fifth conductive layer 230 includes a gate at a position corresponding to the active layer. A gate insulating layer is provided on the side of the gate facing away from the first substrate 120. A second conductive layer is provided on the side of the gate insulating layer facing away from the first substrate 120.

[0077] like Figure 5 As shown, the display panel 100 includes a display area and a non-display area located around the display area. The signal connection line, power connection line, and cathode connection line are located in the display area, and at least one of the first via 162, the second via, and the third via is located in the non-display area. For ease of description, the following detailed description takes the second via located in the non-display area as an example.

[0078] In actual use, moisture outside the display panel 100 can easily enter the display panel 100 along the first conductive layer 140 between the first substrate 120 and the second substrate 150, thereby corroding the organic light-emitting material. For example, moisture outside can enter the display panel 100 along the power connection line between the first substrate 120 and the second substrate 150 through the second via hole, thereby corroding the organic light-emitting material.

[0079] Since the power connection line is located in the display area, after the second via hole is set in the non-display area, the distance between the power connection line and the second via hole is increased compared to when the second via hole is located in the display area, that is, the length of the power connection line is increased, so that external water vapor is not easy to enter the interior of the display panel 100 along the power connection line through the second via hole.

[0080] It is understandable that when the first via hole 162 or the third via hole is located in the non-display area, it can also achieve the corresponding effect, and the working principle is the same, which will not be repeated here.

[0081] The second via hole and the third via hole may be located in the non-display area, and the first via hole 162 may be located in the display area. Figure 5 As shown, the first via 162 is located in the display area, and multiple first vias 162 are spaced apart in the horizontal direction as shown. The signal connection lines electrically connected through the first vias 162 first converge toward the middle area of ​​the display panel 100 and then extend toward the lower end of the display panel 100. The second and third vias are located in the non-display area and are arranged on both sides of the display panel 100 in the vertical direction as shown. The power connection line and the cathode connection line are located on both sides of the signal connection line. This makes it easier to arrange the multiple connection lines in the first conductive layer 140.

[0082] The first via 162, the second via and the third via may also be located in the non-display area, so that the lengths of the signal connection line, the power connection line and the cathode connection line are longer, thereby preventing external moisture from entering the interior of the display panel 100 along the signal connection line, the power connection line and the cathode connection line.

[0083] Figure 6 for Figure 5 The enlarged view of the lower right corner of the figure is a partial enlarged view, and the position in the dotted box in the figure is the position of the first via 162. Figure 7 for Figure 5 A partial enlargement of the upper-right corner of the image. The dotted box in the image indicates the location of the second via. Data in the image refers to the signal connection line, and VDD refers to the power connection line.

[0084] In practical applications, an insulating layer 160 (e.g., an inorganic insulating layer 160) may be provided on the side of the second substrate 150 facing away from the first conductive layer 140. When etching the first via hole 162, the insulating layer 160 and the second substrate 150 need to be etched in sequence to form the first via hole 162 that penetrates the insulating layer 160 and the second substrate 150. Figure 8 As shown, because the etching rate of the second substrate 150 is faster than that of the insulating layer 160 (for example, the second substrate 150 is a PI film and the insulating layer 160 is an inorganic insulating layer 160), the aperture of the first via 162 on the second substrate 150 is likely to be larger than the aperture on the insulating layer 160, i.e., an overcut phenomenon. In this case, the insulating layer 160 forms a sharp corner within the first via 162, and the conductive layer formed on the sidewall of the first via 162 is likely to be disconnected at the sharp corner, resulting in poor conductivity.

[0085] In order to solve the above problem, it is usually necessary to etch the insulating layer 160 again to form Figure 9 and Figure 12 The step structure shown, i.e., the aperture of the insulating layer 160 is larger than that of the second substrate 150, eliminates the sharp corner of the insulating layer 160 extending toward the first via 162. However, when etching the insulating layer 160, the actual etching depth is often inconsistent with the designed etching depth, resulting in that after the insulating layer 160 is completely etched, the second substrate 150 located below the insulating layer 160 is partially etched, causing burrs to form on the surface of the second substrate 150. The conductive layer formed on the surface of the second substrate 150 is easily penetrated by the burrs, resulting in poor conductivity, such as Figure 10 and Figure 11 As shown in the figure, the position indicated by the arrow is the burr.

[0086] In view of this, in the embodiment of the present application, the side walls of the first via 162 located on the insulating layer 160 include a first side wall, a second side wall, and a step surface 163 connecting the first side wall and the second side wall; the projection of the step surface 163 on the first conductive layer 140 is located within the projection of the second substrate 150 on the first conductive layer 140.

[0087] like Figure 13 As shown, the insulating layer 160 is in a step shape after etching, and the aperture of the end of the insulating layer 160 facing away from the second substrate 150 is large, and the side wall here is the first side wall; the aperture of the end of the insulating layer 160 facing the second substrate 150 is small, and the side wall here is the second side wall; the step surface 163 connects the first side wall and the second side wall, and the step surface 163 covers the second substrate 150. That is, the end of the insulating layer 160 facing the second substrate 150 is not completely etched away, but a certain thickness is retained to prevent the second substrate 150 located below the insulating layer 160 from being etched and forming burrs. Among them, the retained thickness can be flexibly selected according to the actual process. The distance between the step surface 163 and the second substrate 150 can be less than or equal to

[0088] The insulating layer 160 may be a single layer or include multiple sub-layers. When the insulating layer 160 includes multiple sub-layers, the step surface 163 may be a boundary surface between two adjacent sub-layers or a surface formed by etching one of the sub-layers.

[0089] The insulating layer 160 may include a first sub-layer and a second sub-layer. The second sub-layer is located on a side of the first sub-layer away from the second substrate 150 . The step surface 163 and the second sidewall are located on the first sub-layer.

[0090] During etching, only the sharp corner structure 161 of the first sub-layer can be etched, while the first sub-layer located on the second substrate 150 is not etched. In this case, the step surface 163 is the interface between the first sub-layer and the second sub-layer. Of course, the first sub-layer can also be etched in the thickness direction to form the step surface 163 in the first sub-layer.

[0091] Figures 14 to 16 FIG. 1 is a schematic diagram of a method for preparing the first via 162. The method may include:

[0092] Step 100, providing a first substrate 120;

[0093] The first substrate 120 can be a flexible substrate or a rigid substrate. For example, the first substrate 120 is a PI film. In practical applications, the first substrate 120 can be disposed on a layer of glass substrate 110.

[0094] Step 200 , forming a buffer layer 130 on a first substrate 120 ;

[0095] The buffer layer 130 may be formed on a side of the first substrate 120 facing away from the glass substrate 110 , and is configured to prevent conductive particles in the first conductive layer 140 from entering the first substrate 120 .

[0096] Step 300 , forming a first conductive layer 140 on the buffer layer 130 ;

[0097] The first conductive layer 140 can be a patterned conductive layer. Through patterning, the first conductive layer 140 forms multiple connecting lines, such as signal connecting lines, power connecting lines, and cathode connecting lines. In practical applications, the type and number of connecting lines can be flexibly configured based on the structure and function of the display panel 100. The first conductive layer 140 can be a metal layer, formed by deposition on the buffer layer 130.

[0098] Step 400 , forming a second substrate 150 on the first conductive layer 140 ;

[0099] The second substrate 150 can be a flexible substrate or a rigid substrate. The material of the second substrate 150 can be the same as or different from that of the first substrate 120. For example, the second substrate 150 and the first substrate 120 are both PI films.

[0100] Step 500 , forming an insulating layer 160 on a second substrate 150 ;

[0101] The insulating layer 160 can be an organic insulating layer 160 or an inorganic insulating layer 160. The insulating layer 160 can be a single layer or a stack of multiple sub-insulating layers 160 made of the same or different materials. The second conductive layer is formed on the side of the insulating layer 160 facing away from the second substrate 150.

[0102] Step 600 , etching the insulating layer 160 and the second substrate 150 to form a blind hole, so that the first conductive layer 140 is exposed through the blind hole;

[0103] Before etching, a photoresist 300 may be provided on the side of the insulating layer 160 facing away from the second substrate 150 . The photoresist 300 is provided with a hollow region. During etching, the insulating layer 160 and the second substrate 150 are etched through the hollow region.

[0104] In actual application, the etching speed of the second substrate 150 may be faster than the etching speed of the insulating layer 160. For example, the insulating layer 160 is an inorganic insulating layer 160, and the second substrate 150 is a PI film. The etching speed of the PI film is faster than the etching speed of the inorganic insulating layer 160. Figure 6 In the structure shown, the diameter of the blind via on the second substrate 150 is larger than that on the insulating layer 160, a phenomenon known as overcutting. In this case, the insulating layer 160 forms a sharp corner within the blind via, and the conductive layer formed on the sidewall of the blind via is easily disconnected at the sharp corner, resulting in poor conductivity.

[0105] Step 700 , forming a photoresist 300 on the insulating layer 160 and in the blind hole;

[0106] like Figure 7 As shown, the photoresist 300 avoids the insulating layer 160 and extends into the sharp corner structure 161 of the blind hole, so that the sharp corner structure 161 of the insulating layer 160 is exposed, so that the sharp corner structure 161 can be etched.

[0107] Step 800, etching the insulating layer 160;

[0108] During etching, the etching depth must be controlled to prevent the insulating layer 160 from being completely etched through in the thickness direction. Specifically, while removing the sharp-cornered structures 161, a certain thickness of the insulating layer 160 is retained on the second substrate 150 to prevent burrs from forming on the second substrate 150 after the insulating layer 160 is completely etched through. In practical applications, the etching depth can be controlled by controlling the etching speed, etching time, and other factors.

[0109] For example, the thickness of the insulating layer 160 remaining on the second substrate 150 may be less than or equal to

[0110] Step 900 , removing the photoresist 300 .

[0111] Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0112] In the embodiments of the present application, words such as "first", "second", "third", and "fourth" are used to distinguish between identical or similar items with basically the same functions and effects. This is only for the purpose of clearly describing the technical solutions of the embodiments of the present application, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0113] In the embodiments of the present application, “a plurality of” means two or more, and “at least one” means one or more, unless otherwise clearly defined.

[0114] In the embodiments of the present application, the terms "upper" and "lower" indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0115] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A display panel, characterized in that: include: A first substrate and a second substrate are stacked; a first conductive layer, located between the first substrate and the second substrate, comprising signal connection lines; a second conductive layer, located on a side of the second substrate away from the first conductive layer, comprising a first bonding wire connected to the signal connection wire through a first via; a third conductive layer, located on a side of the second conductive layer away from the first conductive layer, comprising a data signal line, wherein the data signal line is electrically connected to the first bonding line; a fourth conductive layer, the fourth conductive layer being located on a side of the third conductive layer away from the first conductive layer; an anode layer and a cathode layer, wherein the cathode layer is located on a side of the anode layer away from the fourth conductive layer; The anode layer includes an anode and a fourth bonding wire that are not connected to each other; the first conductive layer also includes a cathode connection wire; the second conductive layer also includes a fifth bonding wire, the third conductive layer also includes a sixth bonding wire, and the fourth conductive layer also includes a seventh bonding wire; The fifth bonding wire is connected to the cathode connection wire through a third via hole, and the cathode layer is electrically connected to the cathode connection wire through the fourth bonding wire, the seventh bonding wire, the sixth bonding wire, and the fifth bonding wire in sequence.

2. The display panel according to claim 1, wherein: The fourth conductive layer includes a power line, the third conductive layer also includes a third bonding line, the second conductive layer also includes a second bonding line, and the first conductive layer also includes a power connection line; The second bonding wire is connected to the power connection wire through a second via hole; the power line is electrically connected to the power connection wire through a third bonding wire and a second bonding wire in sequence.

3. The display panel according to claim 1, wherein: The display panel includes a display area and a non-display area located around the display area. The signal connection line, the power connection line and the cathode connection line are located in the display area. At least one of the first via hole, the second via hole and the third via hole is located in the non-display area.

4. The display panel according to claim 3, wherein: The first via hole, the second via hole, and the third via hole are all located in the non-display area.

5. The display panel according to claim 3, wherein: The second via hole and the third via hole are located in the non-display area, and the first via hole is located in the display area.

6. The display panel according to any one of claims 1 to 5, characterized in that: An insulating layer is further provided on a side of the second substrate facing away from the first substrate, and the first via penetrates the insulating layer and the second substrate; The sidewall of the first via hole located on the insulating layer includes a first sidewall, a second sidewall, and a step surface connecting the first sidewall and the second sidewall; The projection of the step surface on the first conductive layer is located within the projection of the second substrate on the first conductive layer.

7. The display panel according to claim 6, wherein: The insulating layer includes a first sublayer and a second sublayer. The second sublayer is located on a side of the first sublayer away from the second substrate. The step surface and the second sidewall are located on the first sublayer.

8. The display panel according to claim 7, wherein: The first sublayer is an inorganic layer, and the second substrate is a polyimide film.

9. The display panel according to claim 6, wherein: The distance between the step surface and the second substrate is less than or equal to 10. The display panel according to claim 1, wherein A fifth conductive layer is further provided between the first conductive layer and the second conductive layer, and the fifth conductive layer includes a gate.

11. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 10.

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