Display panel, display device and preparation method of display panel

Abstract

Embodiments of the present application disclose a display panel, a display device and a preparation method of the display panel. The display panel comprises a substrate, a plurality of pixel units, a power supply circuit and a driving chip. The display area of the substrate is provided with a through hole penetrating to the second surface of the substrate. A plurality of power supply lines of the power supply circuit are electrically connected with corresponding pixel units, for inputting the power supply voltage provided by the driving chip to the pixel units. By arranging the through hole on the substrate of the display panel and locating the through hole in the display area, the power supply voltage is further input to the power supply line in the display area from the back (i.e. the second surface) of the substrate through the through hole by the second power supply output end on the basis of inputting the power supply voltage to the power supply line of the power supply circuit by the first power supply output end of the driving chip. Thus, the power supply voltage is input to the power supply lines in different positions, so that the power supply line can provide voltage compensation to the pixel unit, the problem of voltage drop is improved, and the display uniformity of the display panel is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel, a display device, and a method for manufacturing the display panel. Background Technology

[0002] At room temperature, the resistance of a metallic conductor is non-zero. The current flowing through the conductor will produce a certain voltage drop, a phenomenon known as IR drop. As the display area of ​​a display panel becomes larger and the resolution becomes higher, the number and length of interconnects (such as signal lines, scan lines, and power lines) on the display panel are gradually increasing.

[0003] However, voltage drop on interconnects can cause different potentials at different locations from the signal input, resulting in different input currents for display units at different locations. This leads to uneven light emission from the display panel and affects display quality. The voltage drop problem is particularly noticeable on large-size display panels. Summary of the Invention

[0004] This application discloses a display panel, a display device, and a method for manufacturing the display panel, which can improve the voltage drop problem of the display panel and thus improve the brightness uniformity of the display panel.

[0005] A first aspect of this application discloses a display panel, comprising: a substrate, the substrate including a first surface and a second surface opposite to each other, the first surface having a display area and a non-display area located around the display area, the display area having a through hole extending to the second surface; a plurality of pixel units, the plurality of pixel units being arrayed in the display area; a power circuit including a plurality of power lines, the plurality of power lines being disposed in the display area and electrically connected to the corresponding pixel units to input a power voltage to the corresponding pixel units; and a driver chip including a first power output terminal and a second power output terminal, the first power output terminal extending to the display area and electrically connected to the power lines of the power circuit, the second power output terminal being electrically connected to the power lines of the power circuit through the through hole, and the driver chip inputting the power voltage to the power lines of the power circuit through the first power output terminal and the second power output terminal.

[0006] As an optional implementation, the display area includes a central area and a peripheral area located around the central area, and the power line extends from the central area to the peripheral area; the power circuit includes a central circuit portion located in the central area and a peripheral circuit portion located in the peripheral area and electrically connected to the central circuit portion, the peripheral circuit portion having a first power input terminal, the central circuit portion having a second power input terminal, and the through hole being at least provided in the central area.

[0007] As an optional implementation, the power line includes a VDD power line and a VSS power line. The VDD power line is used to input a first power supply voltage to the pixel unit, and the VSS power line is used to input a second power supply voltage to the pixel unit. The second power output terminal is electrically connected to the VDD power line and / or the VSS power line through the through hole.

[0008] As an optional implementation, when the second power output terminal is electrically connected to the VDD power line and the VSS power line through the through hole, the through hole includes a first through hole and a second through hole spaced apart from the first through hole. The second power output terminal includes a first sub-output terminal and a second sub-output terminal. The first sub-output terminal is electrically connected to the VDD power line through the first through hole, and the second sub-output terminal is electrically connected to the VSS power line through the second through hole.

[0009] As an optional implementation, the via is a metallized via, which includes a first conductive portion located on the first surface and a second conductive portion located on the second surface. The power line is electrically connected to the first conductive portion, and the second power output terminal is electrically connected to the second conductive portion.

[0010] As an optional implementation, the through hole is a circular hole with a diameter of 20 micrometers to 150 micrometers.

[0011] As an optional implementation, there are multiple through holes, which are spaced apart, and at least one of the through holes is located in the middle of the display area.

[0012] As an optional implementation, the power cord includes a first power cord and a second power cord, with multiple first power cords and multiple second power cords intersecting to form multiple intersections, and the through hole is provided at the intersection.

[0013] The second aspect of this application discloses a display device, the display device including a display panel as described in any of the first aspects above.

[0014] The third aspect of this application discloses a method for manufacturing a display panel, comprising:

[0015] A substrate is provided, the substrate including a first side and a second side opposite to each other, the first side having a display area and a non-display area located around the display area;

[0016] A through hole extending to the second surface is formed in the display area;

[0017] Multiple pixel units are arranged in an array in the display area;

[0018] Multiple power lines are formed on the display area, and the power lines are electrically connected to the corresponding pixel units to input power voltage to the corresponding pixel units;

[0019] A driver chip is provided, the driver chip including a first power output terminal and a second power output terminal;

[0020] The first power output terminal is extended to the display area and electrically connected to the power cord;

[0021] The second power output terminal is electrically connected to the power line through the through hole, and the driver chip inputs the power voltage to the power line of the power circuit through the first power output terminal and the second power output terminal.

[0022] Compared with related technologies, the embodiments of this application have the following beneficial effects:

[0023] The display panel, display device, and method for manufacturing the display panel disclosed in this application have through holes penetrating the first and second surfaces of the substrate in the substrate of the display panel, and the through holes are located in the display area. Thus, in addition to the driver chip inputting power voltage to the power line of the power circuit through the first power output terminal, the power voltage is further input from the back side (i.e., the second surface) of the substrate through the through hole through the second power output terminal to the power line located in the display area. By inputting power voltage to the power line at different locations, the power line can provide voltage compensation to the pixel unit, improve the voltage drop problem, and thereby improve the display uniformity of the display panel. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a top view of the display panel structure in related technologies;

[0026] Figure 2a This is a top view of a display panel disclosed in an embodiment of this application;

[0027] Figure 2b yes Figure 2a A schematic diagram of the structural cross-section along the AA direction;

[0028] Figure 3 This is a schematic diagram of the structure of a pixel unit disclosed in an embodiment of this application;

[0029] Figure 4 This is a top view of another display panel disclosed in an embodiment of this application;

[0030] Figure 5 This is a schematic diagram of the power cord arrangement disclosed in an embodiment of this application;

[0031] Figure 6 This is a schematic flowchart of a method for manufacturing a display panel disclosed in an embodiment of this application. Detailed Implementation

[0032] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0033] It should be noted that the terms "comprising" and "having," and any variations thereof, in the embodiments and accompanying drawings of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the steps or units listed, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0034] Please refer to Figure 1 The diagram illustrates a structural schematic of a display panel in the related art. The display panel includes a substrate 10, multiple pixel units 20, multiple first power supply circuits, multiple second power supply circuits, a third power supply circuit 30, and a driver chip 40. The substrate 10 includes a display area (e.g., ...). Figure 1 The area enclosed by the dotted horizontal line shown in the diagram) and the non-display area located outside the display area. During the display process, the display area displays images, while the non-display area does not display images.

[0035] Multiple pixel units 20 are arrayed in the display area, and each pixel unit 20 includes a first electrode and a second electrode, wherein one of the first electrode and the second electrode is an anode and the other is a cathode. The first power supply circuit may include multiple first power lines (such as...). Figure 1 (As shown by the dashed line), multiple first power lines are arrayed in the display area, and each first power line is electrically connected to the first electrode of the corresponding pixel unit 20. The second power circuit may include multiple second power lines (such as...). Figure 1(Showing solid lines connecting to each pixel unit 20), multiple second power lines are also arrayed in the display area, and each second power line is electrically connected to the second electrode of the corresponding pixel unit 20. Optionally, the first power circuit and the second power circuit are stacked sequentially on the substrate 10 and electrically isolated from each other.

[0036] The third power supply circuit 30 is disposed in the non-display area of ​​the substrate 10 and is electrically connected to the driver chip 40 and multiple first power lines and multiple second power lines located in the display area, thereby providing the first power supply voltage provided by the driver chip 40 to the pixel unit 20 through the first power line and providing the second power supply voltage provided by the driver chip 40 to the pixel unit 20 through the second power line.

[0037] However, the inventors discovered through research that, regarding the above-mentioned... Figure 1 The current-driven display panel shown typically suffers from voltage drop issues. This is because the light-emitting elements require a continuous current supply to drive them to emit light. Different locations within the display panel have different current paths, resulting in varying resistances and thus different voltage drops. The further away from the current input, the greater the resistance and the larger the voltage drop (for high-level signals). This voltage drop causes variations in the voltage across the control circuits in different areas of the display panel, leading to inconsistent brightness of the light-emitting elements and ultimately affecting the uniformity of light emission across the display panel.

[0038] Micro LED (Micro Light Emitting Diode) display technology refers to a display technology that uses self-emissive, micrometer-sized LEDs (light-emitting diodes) as light-emitting pixel units, assembling them onto a driving panel to form a high-density LED array. Since LEDs require a continuous current supply to drive them, Micro LED displays also suffer from voltage drop issues. Similarly, OLED (Organic Electro-Laser) displays are also current-driven, and therefore, OLED displays also experience voltage drop problems.

[0039] To address the voltage drop issue in display panels, the resistance of the circuitry can be reduced, for example, by using a metal with a larger cross-sectional area, adding more metal circuitry, or selecting a metal material with lower resistivity (such as using copper (Cu) instead of aluminum (Al)) as the conductive material. Furthermore, increasing the electrical connection points between the third and first power supply circuits and / or between the third and second power supply circuits can increase the number of current input points and reduce the current transmission path. However, for large display panels, even with numerous additional connection points, the voltage drop at the center of the display area (far from the connection points) remains significant, resulting in uneven display brightness.

[0040] In view of this, embodiments of this application disclose a display panel, a display device, and a method for manufacturing a display panel. By providing a through hole penetrating a first and a second surface of the substrate in the substrate of the display panel, and the through hole being located in the display area, in addition to the driver chip inputting power voltage to the power line of the power circuit through the first power output terminal, a further power voltage is input from the back side (i.e., the second surface) of the substrate through the through hole via the second power output terminal to the power line located in the display area. Thus, by inputting power voltage to the power line at different locations, the power line can provide voltage compensation to the pixel unit, improve the voltage drop problem, and thereby improve the display uniformity of the display panel.

[0041] The specific scheme of this application will be described in detail below with reference to the accompanying drawings.

[0042] Please refer to Figures 2a-2b , Figure 2a This is a top view of a display panel disclosed in an embodiment of this application. Figure 2b This is one of the embodiments disclosed in this application. Figure 2a A schematic cross-sectional view of the structure along the AA direction. Figures 2a-2b The display panel shown is a current-driven display panel, such as a Micro LED display panel or an OLED display panel. This application embodiment does not limit this type of display panel.

[0043] like Figures 2a-2b As shown, the display panel may include: a substrate 100, a plurality of pixel units 200, a power supply circuit, and a driver chip 400. The substrate 100 includes a first surface 110 and a second surface 120 opposite to each other. The first surface 110 has a display area 111 (roughly referred to as...). Figure 2a The area enclosed by the dashed box shown is a non-display area 112, which is located around the display area 111. The display area 111 has a through hole 130 penetrating the second surface 120. The power supply circuit may include multiple power lines 300, and the driver chip 400 may include a first power output terminal 410 and a second power output terminal 420.

[0044] Multiple pixel units 200 are arrayed on the display area 111, and multiple power lines 300 are disposed in the display area 111 and electrically connected to the corresponding pixel units 200 to input power voltage to the corresponding pixel units 200. The first power output terminal 410 of the driver chip 400 extends to the display area 111 and is electrically connected to the power line 300 of the power circuit. The second power output terminal 420 is electrically connected to the power line 300 of the power circuit through the through hole 130. The driver chip 400 inputs power voltage to the power line 300 of the power circuit through the first power output terminal 410 and the second power output terminal 420, thereby providing power voltage to the pixel units 200.

[0045] It is understood that the number of pixel units 200 can be set according to the specifications and needs of the display panel, and this embodiment does not specifically limit this. The driver chip 400 can be used to provide power supply voltage, the pixel unit 200 is used to emit light under the drive of the driver chip 400, and the power supply circuit is used to electrically conduct the driver chip 400 and the pixel unit 200 so that the pixel unit 200 emits light under the drive of the driver chip 400. The first power output terminal 410 and the second power output terminal 420 can both be used to output power supply voltage. The first power output terminal 410 and the second power output terminal 420 can be the same output terminal or different output terminals. When the first power output terminal 410 and the second power output terminal 420 are the same power output terminal, the power output terminal inputs power supply voltage to the power line 300 through the through hole 130, and the power output terminal extends to the display area 111 to input power supply voltage to the power line 300.

[0046] As can be seen, the display panel provided in this application embodiment has a through hole 130 that penetrates the first surface 110 and the second surface 120 of the substrate 100 in the display area 111 of the substrate 100. Thus, on the basis that the driving chip 400 inputs power voltage to the power line 300 of the power circuit through the first power output terminal 410, it further inputs power voltage from the back side (i.e., the second surface) of the substrate 100 to the power line 300 located in the display area 111 through the through hole 130 via the second power output terminal 420. In this way, by inputting power voltage to the power line 300 at different positions, the power line 300 can provide voltage compensation to the pixel unit 200, improve the voltage drop problem, and thus improve the display uniformity of the display panel.

[0047] Optionally, the substrate 100 can be a glass substrate or a flexible substrate. For example, when the substrate 100 is a glass substrate, the thickness of the glass substrate can range from 100 micrometers to 500 micrometers, for example, the thickness of the glass substrate can be 300 micrometers.

[0048] In one embodiment, the substrate 100 may have one or more through-holes 130. Considering that for large-size panels, if the power supply voltage is input from the edge of the display area 111, the power supply voltage travels a long path from the edge to the center of the display area 111, resulting in the most significant voltage drop in the central region of the display area 111, this embodiment may place at least one through-hole 130 in the central position of the display area 111. That is, one through-hole 130 is placed at the location in the display area 111 where the voltage drop is most significant, meaning the voltage difference between the through-hole 130 and the power supply voltage is greatest at the location where the voltage difference is greatest. By setting at least one through-hole in the middle of the display area 111, the power supply voltage can be directly input from the second surface 120 of the substrate 100 to the middle position through the through-hole 130. Compared with obtaining the power supply voltage from the peripheral circuit (i.e. the edge of the display area 111), the current transmission path is shorter. Therefore, inputting the power supply voltage directly from the second surface 120 of the substrate 100 to the middle position can provide voltage compensation for the pixel unit 200 in the middle region of the display area 111, thereby alleviating or avoiding voltage drop.

[0049] When multiple vias 130 are formed in the substrate 100, the vias 130 are spaced apart. For example, besides having at least one via in the center of the display area 111, the other vias can be roughly distributed from the center of the display area 111 towards its edge, thereby increasing the number of input points for the power supply voltage, further shortening the current path, and thus further alleviating the voltage drop problem. Optionally, the number of vias 130 can range from 2 to 6. For example, the number of vias 130 can be 5. By setting a small number of vias 130 in the display area 111, the brightness uniformity of the display panel can be significantly improved. For display panels where the substrate 100 is a glass substrate, the number of openings is small, thus reducing the difficulty of opening the glass substrate and the requirements for its structural strength, making it easier to implement. Therefore, this application also provides a low-cost but significantly effective solution for improving the brightness uniformity of display panels where the substrate 100 is a glass substrate.

[0050] In one embodiment, the through hole 130 may be, but is not limited to, a rectangular hole, a trapezoidal hole, or a circular hole. Optionally, the through hole 130 is a circular hole, and the diameter of the through hole 130 ranges from 20 micrometers to 150 micrometers. For example, the diameter of the circular hole is 60 micrometers.

[0051] In an optional embodiment, the display panel may further include a first conductor, which is partially disposed within a through hole 130. One end of the first conductor is electrically connected to the power line 300 of the power circuit through the through hole 130, and the other end of the first conductor is electrically connected to the second power output terminal 420 of the driver chip 400, so that the driver chip 400 inputs power voltage to the power line 300 of the power circuit through the second power output terminal 420.

[0052] In another alternative embodiment, the via 130 can be a metallized via. Optionally, the metal deposited in the metallized via can be copper or gold. The via 130 includes a first conductive portion located on the first surface 110 of the substrate 100 and a second conductive portion located on the second surface 120 of the substrate 100. The first conductive portion is electrically connected to the power line 300, and the second power output terminal 420 is electrically connected to the second conductive portion. The metallized via is electrically connected to the second power output terminal 420 and the power line 300, thereby enabling the driver chip 400 to provide power voltage to the pixel unit 200. Since a metallized via is formed on the substrate 100, the cross-sectional area of ​​the metallized via can be set to be larger, which can further reduce the path resistance of the power voltage input from the back side of the substrate 100 to the power line 300, and better improve the voltage drop problem.

[0053] Please continue to refer to this. Figure 2b In this embodiment, a conductive layer 131 can be formed on the second surface 120 of the substrate 100, such that the conductive layer 131 is at least partially electrically connected to the second conductive portion of the metallized via. That is, forming the conductive layer 131 can reduce the resistance of the via and reduce the difficulty of electrically connecting the second conductive portion of the via 130 to the second power output terminal 420.

[0054] Optionally, the display panel may further include a second conductive wire, one end of which is electrically connected to the second conductive portion, and the other end of which is electrically connected to the second power output terminal 420 of the driver chip 400. The driver chip 400 can input power voltage to the power line 300 through the second power output terminal 420, the second conductive wire, and the through-hole 130. It is evident that the second conductive wire allows the driver chip 400 to provide power voltage to the pixel unit 200 through the second power output terminal 420, the second conductive portion, the first conductive portion, and the power line 300, eliminating the need for wiring on the second surface 120 of the substrate 100, thus reducing the complexity and cost of display panel fabrication.

[0055] Furthermore, for circuitry on glass substrates, the sheet resistance of Al processes is typically around 0.08 Ω / sq (thickness 0.2–0.5 μm), and that of Cu processes is 0.01–0.05 Ω / sq (thickness 0.3–1 μm). Assuming a VDD power line width of 10 μm in panel design, the resistance of a 6-inch (display panel size) diagonal length of 152.4 mm reaches 152.4 Ω to 1 kΩ. Currents near the input location can reach mA levels, even A levels, while currents far from the input location are typically <1 mA, meaning the voltage drop far from the input location can reach 0.1–5 V levels. In contrast, the resistivity of copper conductors (at 20 degrees Celsius) is 0.0185 Ω*mm. 2 The resistance of a copper wire with a cross-sectional area of ​​1 square millimeter and a length of 1 meter is 0.0185 Ω, which is far lower than the resistance of a conductive line formed on a glass substrate. Therefore, by using a second wire, especially when the second wire is a copper wire, to achieve an electrical connection between the second power output terminal 420 and the via 130, the resistance of the current transmission path from the second power output terminal 420 to the power line 300 can be reduced compared to directly forming a trace on the second surface 120 of the substrate 100.

[0056] Please refer to Figure 3 This illustrates a pixel unit 200 provided in an embodiment of this application. For example... Figure 3 As shown, pixel unit 200 may include a switch Q1, a capacitor C, a switch Q2, and a light-emitting element D. The first terminal of switch Q1 is electrically connected to scan line 310 to receive scan signals; the second terminal of switch Q1 is electrically connected to data line 320 to receive data signals; the third terminal of switch Q1 is electrically connected to the first terminal of capacitor C and the first terminal of switch Q2; the second terminal of switch Q2 is electrically connected to the VDD power line to receive VDD signals; the third terminal of switch Q2 is electrically connected to the second terminal of capacitor C and the positive terminal of light-emitting element D; and the negative terminal of light-emitting element D is electrically connected to the VSS power line to receive VSS signals. Optionally, both switch Q1 and switch Q2 are thin-film field-effect transistors (TFTs). The first terminal of switch Q1 is the gate of the TFT, the second terminal of switch Q1 is the source of the TFT, and the third terminal of switch Q1 is the drain of the TFT. Similarly, the first terminal of switch Q2 is the gate of the thin-film field-effect transistor (TFT), the second terminal of switch Q2 is the source of the TFT, and the third terminal of switch Q2 is the drain of the TFT. It should be noted that the embodiments of this application do not limit the color emitted by the light-emitting element D when emitting light, and the light-emitting element D can be selected as needed. For example, the color emitted by the light-emitting element D when emitting light can be one of white, red, green, or blue.

[0057] In one embodiment, a peripheral power supply circuit is provided in the non-display area. This peripheral power supply circuit is used to connect the power supply circuit and the driver chip 400, thereby inputting the power supply voltage provided by the driver chip 400 into the power line 300 of the display area.

[0058] In one embodiment, such as Figure 4 As shown, the display panel may further include a first connection circuit 500 and a printed circuit board 600. The driver chip is integrated on the printed circuit board 600. One end of the first connection circuit 500 is electrically connected to the printed circuit board 600, and the other end of the first connection circuit 500 is electrically connected to the peripheral power supply circuit of the non-display area of ​​the substrate 100. The peripheral power supply circuit of the non-display area of ​​the substrate 100 is correspondingly electrically connected to the power supply circuit of the display area, and is used to input the power supply voltage output from the first power output terminal 410 of the driver chip 400 to the power supply line 300 of the power supply circuit of the display area, so as to provide power supply voltage for each pixel unit 200. Optionally, the first connection circuit 500 is a circuit disposed on a chip-on-film (COF) film or a circuit disposed on a flexible printed circuit board (FPC).

[0059] Please continue to refer to this. Figure 4 In one embodiment, the display panel may further include a scanning chip 700 and a second connection circuit 800. One end of the second connection circuit 800 is electrically connected to the scanning chip 700, and the other end of the second connection circuit 800 is electrically connected to multiple scan lines (not shown in the figure) disposed on the display area of ​​the substrate 100. Each scan line is electrically connected to each pixel unit 200 to input a scan signal to each pixel unit 200. Optionally, the second connection circuit 800 may be a circuit disposed on a chip-on-film (COF) film or a circuit disposed on a flexible printed circuit board (FPC).

[0060] Please continue to refer to this. Figures 2a-2b Display area 111 can be divided into a central area (e.g., Figure 1 The area enclosed by the horizontal line at the midpoint) and the surrounding area (such as...) Figure 1The area enclosed by the horizontal line and the dashed line (midpoint) is the outer region of the central region. The power line 300 extends from the central region to the outer region, meaning that the power line 300 is electrically connected between the central region and the outer region of the display area 111. Correspondingly, the power circuit includes a central circuit portion located in the central region and an outer circuit portion located in the outer region and electrically connected to the central circuit portion. The outer circuit portion has a first power input terminal, and the central circuit portion has a second power input terminal. A through-hole is at least located in the central region. It should be noted that the first power input terminal is used to input the power voltage output by the driver chip through the first power output terminal into the power circuit to provide power voltage for the pixel unit 200. The second power input terminal is used to input the power voltage output by the driver chip from the second power output terminal into the central circuit, thereby providing power voltage to the pixel unit 200 through the second power output terminal 420, the through-hole 130, and the second power input terminal.

[0061] It is understandable that, since the voltage drop in the central region of the display area 111 is more significant than that in the peripheral region of the display area 111 when power supply voltage is supplied to the pixel unit 200 through the first power input terminal 410, by providing a through hole 130 in the central region of the display area 111 and supplying power supply voltage to the central circuit part of the central region through the through hole 130, voltage compensation can be provided to the pixel unit 200 in the central region of the display area 111, thereby improving the voltage drop problem and improving the brightness uniformity of the display panel.

[0062] In one embodiment, such as Figure 5 As shown, the power cord 300 may include a first power cord 311 and a second power cord 312. Multiple first power cords 311 and multiple second power cords 312 are interconnected to form multiple intersections 313. Therefore, when setting a through hole, the through hole 130 can be located at the intersection of the first power cord 311 and the second power cord 312. Optionally, the first power cord 311 and the second power cord 312 can be perpendicular to each other, that is, one of the first power cord 311 and the second power cord 312 can be arranged horizontally, and the other of the first power cord 311 and the second power cord 312 can be arranged vertically.

[0063] In one embodiment, the power line 300 may further include a VDD power line and a VSS power line, both of which include the aforementioned first power line 311 and second power line 312. It is understood that the VDD power line is used to input a first power supply voltage to the pixel unit, and the VSS power line is used to input a second power supply voltage to the pixel unit. The first power supply voltage is higher than the second power supply voltage, and the light-emitting element can be lit when the positive terminal of the light-emitting element is at the first power supply voltage and the negative terminal is at the second power supply voltage. The second power output terminal is electrically connected to the VDD power line and / or the VSS power line through a through-hole to supply the first power supply voltage and / or the second power supply voltage to the pixel unit. It should be noted that the VDD power line and the VSS power line should be isolated from each other to achieve the supply of the first and second power supply voltages to the pixel unit. In one embodiment, each pixel unit includes a VDD terminal and a VSS terminal. The VDD power line is connected to the VDD terminal of each pixel unit to input a first power supply voltage to the VDD terminal of the pixel unit. The VSS power line is connected to the VSS terminal of each pixel unit to input a second power supply voltage to the VSS terminal of the pixel unit.

[0064] The above embodiment describes that the second power output terminal can be connected to the VDD power line or the VSS power line through the through-hole 130. That is, when improving the voltage drop problem, the second power output terminal can be used to input power voltage to the VDD power line through the through-hole, or the second power output terminal can be used to input power voltage to the VSS power line through the through-hole. Of course, it is also possible to use the second power output terminal to input power voltage to the VDD power line through the through-hole, and at the same time, it is also possible to use the second power output terminal to also input power voltage to the VSS power line through the through-hole. The following will describe this situation in detail.

[0065] When power voltage needs to be input to both the VDD and VSS power lines simultaneously, considering that the VDD and VSS power lines should be insulated from each other, the through-hole 130 may include a first through-hole and a second through-hole, spaced apart from the first. The second power output terminal includes a first sub-output terminal and a second sub-output terminal. The first sub-output terminal is electrically connected to the VDD power line through the first through-hole, and the second sub-output terminal is electrically connected to the VSS power line through the second through-hole. The first sub-output terminal provides a first power voltage to the pixel unit, and the second sub-output terminal provides a second power voltage to the pixel unit. Correspondingly, the second power input terminal includes a first sub-input terminal and a second sub-input terminal. The first sub-input terminal may be located on the VDD power line in the central area of ​​the display area, and the second sub-input terminal may be located on the VSS power line in the central area of ​​the display area. Thus, the first sub-output terminal is electrically connected to the VDD power line through the first through hole, and the second sub-output terminal is electrically connected to the VSS power line through the second through hole, including: the first sub-output terminal is electrically connected to the first sub-input terminal through the first through hole, and the second sub-output terminal is electrically connected to the second sub-input terminal through the second through hole.

[0066] As can be seen, by opening a first through-hole and a second through-hole in the display area of ​​the substrate to the second surface of the substrate, the driving chip can directly input the first power supply voltage from the back side (i.e., the second surface) of the substrate to the VDD power line located in the display area through the first through-hole, and directly input the second power supply voltage from the back side (i.e., the second surface) of the substrate to the VSS power line located in the display area through the second through-hole. This shortens the current transmission path, provides voltage compensation to the pixel unit through the VDD power line and the VSS power line, improves the voltage drop problem, and thus improves the display uniformity of the display panel.

[0067] In one embodiment, the first power output terminal includes a third sub-output terminal and a fourth sub-output terminal. The third sub-output terminal provides a first power supply voltage to the pixel unit, and the fourth sub-output terminal provides a second power supply voltage to the pixel unit. The VDD power line of the peripheral circuit portion of the peripheral area of ​​the display area has a third sub-input terminal, and the VSS power line of the peripheral circuit portion of the peripheral area has a fourth sub-input terminal. The driver chip provides the first power supply voltage to the pixel unit from the peripheral area of ​​the display area through the third sub-output terminal and the third sub-input terminal, and the driver chip provides the second power supply voltage to the pixel unit from the peripheral area of ​​the display area through the fourth sub-output terminal and the fourth sub-input terminal.

[0068] In one embodiment, this application also provides a display device, which includes a display panel as described above. Exemplarily, the display device may include, but is not limited to, a Micro LED display device or an OLED display device.

[0069] Please refer to Figure 6This application also provides a method for manufacturing a display panel, such as... Figure 6 As shown, the method for manufacturing the display panel may include steps S601 to S607. Specifically, the method includes:

[0070] Step S601, provide a substrate.

[0071] The substrate includes a first surface and a second surface opposite to each other. The first surface has a display area and a non-display area located around the display area. Optionally, the substrate can be a glass substrate or a flexible substrate. A detailed description of the substrate is provided in the embodiments above and will not be repeated here.

[0072] Step S602: Create a through hole in the display area that extends to the second surface.

[0073] In one embodiment, before creating a through-hole extending to the second surface on the display area, the method further includes: determining the voltage drop of the display panel to be manufactured, and determining the location of the through-hole on the display area based on the voltage drop. Determining the voltage drop of the display panel to be manufactured includes: determining the voltage drop of the display panel to be manufactured based on the area of ​​the display panel, the location and number of the first power input terminals of the display panel. The determination of the through-hole location will be illustrated by the following example: multiple locations where the voltage drop of the display panel is most significant can be determined by simulation, and these multiple locations can be determined as the locations and number of through-holes.

[0074] In one embodiment, creating a through-hole extending to the second surface on the display area may include: creating a through-hole on the display area and depositing a conductive metal layer in the through-hole to form a metallized via. Optionally, the metal deposited in the through-hole may be copper or gold.

[0075] Step S603: Multiple array-configured pixel units are formed in the display area.

[0076] For a detailed description of the pixel unit, please refer to the above embodiments, which will not be repeated here.

[0077] In step S604, multiple power lines are formed on the display area, and the multiple power lines are electrically connected to the corresponding pixel units to input power voltage to the corresponding pixel units.

[0078] For a detailed description of the power cord, please refer to the above embodiment; it will not be described again here.

[0079] In one embodiment, forming multiple power lines on a display area includes: forming a conductive layer on the display area, and etching the conductive layer to form a patterned conductive layer, thereby forming multiple power lines.

[0080] Step S605: Provide the driver chip.

[0081] The driver chip is used to provide power supply voltage to the pixel unit. The driver chip includes a first power output terminal and a second power output terminal, both of which can be used to output power supply voltage.

[0082] Step S606: Extend the first power output terminal to the display area and connect it to the power cord.

[0083] Step S607: Connect the second power output terminal to the power line through the through hole.

[0084] The display panel prepared by the method provided in this application has a substrate with a through hole penetrating the first and second surfaces of the substrate, and the through hole is located in the display area. Thus, in addition to the driver chip inputting power voltage to the power line of the power circuit through the first power output terminal, the power voltage is further input from the back side (i.e., the second surface) of the substrate through the through hole through the second power output terminal to the power line located in the display area. By inputting power voltage to the power line at different positions, the power line at different positions can provide voltage compensation to the pixel unit, improve the voltage drop problem, and thus improve the display uniformity of the display panel.

[0085] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Those skilled in the art should also recognize that the embodiments described in the specification are optional embodiments, and the actions and modules involved are not necessarily essential to this application.

[0086] In the various embodiments of this application, it should be understood that the sequence number of each process does not necessarily imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0087] The foregoing has provided a detailed description of a display panel, display device, and method for manufacturing the display panel disclosed in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A display panel, characterized in that, include: A substrate, the substrate including a first surface and a second surface opposite to each other, the first surface having a display area and a non-display area located around the display area, the display area having a through hole extending to the second surface; Multiple pixel units, wherein the array of multiple pixel units is disposed in the display area; A power supply circuit, comprising multiple power lines, wherein the multiple power lines are disposed in the display area and electrically connected to the corresponding pixel unit, so as to input power voltage to the corresponding pixel unit; The driver chip includes a first power output terminal and a second power output terminal. The first power output terminal extends to the display area and is electrically connected to the power line of the power circuit. The second power output terminal is electrically connected to the power line of the power circuit through the through hole. The driver chip inputs the power voltage to the power line of the power circuit through the first power output terminal and the second power output terminal. The display area includes a central region, and the through hole is at least disposed in the central region. The power circuit includes a central circuit portion located in the central region. The central circuit portion has a second power input terminal, which is used to input the power voltage transmitted through the second power output terminal and the through hole to the central circuit portion.

2. The display panel according to claim 1, characterized in that, The display area also includes a peripheral area located around the central area, and the power cord extends from the central area to the peripheral area; The power supply circuit also includes an external circuit section located in the peripheral region and electrically connected to the central circuit section, the external circuit section having a first power input terminal.

3. The display panel according to claim 1, characterized in that, The power lines include a VDD power line and a VSS power line. The VDD power line is used to input a first power supply voltage to the pixel unit, and the VSS power line is used to input a second power supply voltage to the pixel unit. The second power output terminal is electrically connected to the VDD power line and / or the VSS power line through the through hole.

4. The display panel according to claim 3, characterized in that, When the second power output terminal is electrically connected to the VDD power line and the VSS power line through the through hole, the through hole includes a first through hole and a second through hole spaced apart from the first through hole. The second power output terminal includes a first sub-output terminal and a second sub-output terminal. The first sub-output terminal is electrically connected to the VDD power line through the first through hole, and the second sub-output terminal is electrically connected to the VSS power line through the second through hole.

5. The display panel according to any one of claims 1 to 4, characterized in that, The via is a metallized via, which includes a first conductive portion located on the first surface and a second conductive portion located on the second surface. The power line is electrically connected to the first conductive portion, and the second power output terminal is electrically connected to the second conductive portion.

6. The display panel according to any one of claims 1 to 4, characterized in that, The through hole is a round hole with a diameter of 20 micrometers to 150 micrometers.

7. The display panel according to any one of claims 1 to 4, characterized in that, There are multiple through holes, which are spaced apart, and at least one of the through holes is located in the middle of the display area.

8. The display panel according to any one of claims 1 to 4, characterized in that, The power cord includes a first power cord and a second power cord. Multiple first power cords and multiple second power cords are intersected to form multiple intersections, and the through hole is provided at the intersection.

9. A display device, characterized in that, The display device includes a display panel as described in any one of claims 1 to 8.

10. A method for manufacturing a display panel, characterized in that, include: A substrate is provided, the substrate including a first side and a second side opposite to each other, the first side having a display area and a non-display area located around the display area; A through hole extending to the second surface is formed in the display area; Multiple pixel units are arranged in an array in the display area; A power circuit is formed on the display area. The power circuit includes multiple power lines, which are electrically connected to the corresponding pixel units to input power voltage to the corresponding pixel units. A driver chip is provided, the driver chip including a first power output terminal and a second power output terminal; The first power output terminal is extended to the display area and electrically connected to the power cord; The second power output terminal is electrically connected to the power line through the through hole, and the driver chip inputs the power voltage to the power line of the power circuit through the first power output terminal and the second power output terminal; The display area includes a central region, the through hole is at least disposed in the central region, and the power circuit includes a central circuit portion located in the central region, the central circuit portion having a second power input terminal; The driver chip inputs the power supply voltage to the power supply line of the power supply circuit through the second power output terminal, including: The driver chip inputs the power supply voltage to the through hole through the second power output terminal, so as to input the power supply voltage to the central circuit section through the through hole and the second power input terminal of the central circuit section.

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