HEMT device and preparation method thereof

Abstract

The present application discloses a HEMT device and a method for fabricating the same. The method comprises: obtaining a substrate having a lateral polarity structure layer, wherein the lateral polarity structure layer comprises a patterned crystalline layer, a buffer layer, a channel layer, and a barrier layer stacked sequentially in a direction away from the substrate; wet etching the channel layer and barrier layer not corresponding to the patterned crystalline layer to form a three-dimensional channel structure; preparing a source electrode and a drain electrode, and preparing a gate electrode on the upper surface of the three-dimensional channel structure to obtain the HEMT device. The present application forms a patterned crystalline layer, a buffer layer, a channel layer, and a barrier layer on the substrate, wherein the buffer layer, channel layer, and barrier layer corresponding to the patterned crystalline layer are metal polarity film layers, and the layer not corresponding to the patterned crystalline layer is a nitrogen polarity film layer. Wet etching is performed to etch the channel layer and barrier layer in the nitrogen polarity film layer, resulting in a smooth and flat wet etching interface, avoiding ion damage caused by plasma etching and shortening process time.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to a HEMT device and a method for preparing the same. Background Art

[0002] A high electron mobility transistor (HEMT) is a heterojunction field-effect transistor (FET) with excellent performance, including a large breakdown field, high electron mobility, fast switching speed, and the absence of reverse minority carriers. To improve gate controllability and suppress short-channel effects, fin and tri-gate structures have been further applied to HEMT devices. These structures also increase the device's current switching ratio, reduce off-state leakage current and subthreshold swing (SS), and further reduce device power consumption.

[0003] Currently, channel isolation in fin-structure and tri-gate HEMT devices is primarily achieved through plasma etching. This technique primarily involves etching trenches deeper than the two-dimensional electron gas (2DEG) between multiple channels to isolate the conductive paths between devices. However, plasma etching can easily introduce a large number of acceptor-like defects and surface states on the surface and sidewalls of the etched areas, causing severe surface leakage and even significantly affecting the device's off-state leakage current.

[0004] Therefore, how to solve the above technical problems should be the focus of those skilled in the art. Summary of the Invention

[0005] The purpose of this application is to provide a HEMT device and a preparation method thereof to solve the damage caused by plasma etching and reduce the leakage current and surface state of the HEMT device.

[0006] To solve the above technical problems, the present application provides a method for preparing a HEMT device, comprising:

[0007] Obtaining a substrate having a lateral polarity structure layer, wherein the lateral polarity structure layer includes a patterned crystal layer, a buffer layer, a channel layer, and a barrier layer stacked in sequence in a direction away from the substrate;

[0008] etching the channel layer and the barrier layer not corresponding to the patterned crystalline layer by wet etching to form a three-dimensional channel structure;

[0009] A source electrode and a drain electrode are prepared, and a gate electrode is prepared on the upper surface of the three-dimensional channel structure to obtain a HEMT device.

[0010] Optionally, after preparing the source electrode and the drain electrode, and preparing the gate electrode on the upper surface of the three-dimensional channel structure, the method further includes:

[0011] Deposit a passivation layer.

[0012] Optionally, before obtaining the substrate having the lateral polarity structure layer, the method further includes:

[0013] growing a crystalline layer on the upper surface of the substrate, and etching the crystalline layer to form the patterned crystalline layer;

[0014] The buffer layer, the channel layer, and the barrier layer are sequentially grown on the upper surface of the patterned crystal layer and on a region of the upper surface of the substrate not covered by the patterned crystal layer.

[0015] Optionally, etching the crystal layer to form the patterned crystal layer includes:

[0016] The crystal layer is etched by plasma etching to form the patterned crystal layer.

[0017] Optionally, sequentially growing the buffer layer, the channel layer, and the barrier layer on the upper surface of the patterned crystal layer and an area of the upper surface of the substrate not covered by the patterned crystal layer includes:

[0018] The buffer layer, the channel layer and the barrier layer are sequentially grown on the upper surface of the patterned crystal layer and the area of the upper surface of the substrate not covered by the patterned crystal layer by metal organic chemical vapor deposition.

[0019] Optionally, the transverse polarity structure layer further includes:

[0020] An insertion layer is located between the channel layer and the barrier layer.

[0021] Optionally, before preparing the source electrode and the drain electrode and preparing the gate electrode on the upper surface of the three-dimensional channel structure, the method further includes:

[0022] growing a dielectric layer on the upper surface of the three-dimensional channel structure;

[0023] Accordingly, preparing a gate electrode on the upper surface of the three-dimensional channel structure includes:

[0024] A gate electrode is prepared on the upper surface of the dielectric layer.

[0025] Optionally, growing a dielectric layer on the upper surface of the three-dimensional channel structure includes:

[0026] The dielectric layer is grown on the upper surface of the three-dimensional channel structure by adopting a low-pressure chemical vapor deposition method.

[0027] The present application also provides a HEMT device, which is manufactured by any of the above-mentioned HEMT device manufacturing methods.

[0028] Optionally, the HEMT device is a fin-structured HEMT device.

[0029] The present application provides a method for fabricating a HEMT device, comprising: obtaining a substrate having a lateral polarity structure layer, wherein the lateral polarity structure layer comprises a patterned crystalline layer, a buffer layer, a channel layer, and a barrier layer stacked sequentially in a direction away from the substrate; wet etching the channel layer and the barrier layer not corresponding to the patterned crystalline layer to form a three-dimensional channel structure; fabricating a source electrode and a drain electrode, and fabricating a gate electrode on the upper surface of the three-dimensional channel structure to obtain a HEMT device.

[0030] As can be seen, in the present application, when fabricating a HEMT device, after forming a patterned crystalline layer, a buffer layer, a channel layer, and a barrier layer on a substrate, the buffer layer, channel layer, and barrier layer corresponding to the patterned crystalline layer are metal-polarity film layers, while the buffer layer, channel layer, and barrier layer not corresponding to the patterned crystalline layer are nitrogen-polarity film layers. The metal-polarity film layers and the nitrogen-polarity film layers have different etching characteristics. The nitrogen-polarity film layer etches rapidly in the etchant, while the metal-polarity film layer etches at a very low rate, with almost no etching occurring. Therefore, a wet etching method is used to etch the channel layer and barrier layer not corresponding to the patterned crystalline layer, exposing the channel layer in the metal-polarity film layer to form a three-dimensional channel structure. The wet etching method provides a smooth and flat interface, avoiding ion damage caused by plasma etching, reducing leakage current and surface states of the HEMT device, and avoiding subsequent tedious isolation processes such as photolithography, plasma etching, or ion beam implantation, thereby shortening process time, reducing process complexity, and reducing manufacturing costs.

[0031] In addition, the present application also provides a HEMT device having the above advantages. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present application or the technical solutions of the prior art, the following is a brief introduction to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0033] Figure 1 A flow chart of a method for preparing a HEMT device provided in an embodiment of the present application;

[0034] Figure 2Schematic diagram of a lateral polar structure layer of AlGaN / GaN, taking AlGaN / GaN heterojunction material as an example;

[0035] Figure 3(a) to Figure 3(d) This is a diagram of the chemical reaction mechanism of wet etching of nitrogen-polar gallium nitride in alkaline solution;

[0036] Figure 4 A flow chart of another method for preparing a HEMT device provided in an embodiment of the present application;

[0037] Figures 5 to 11 A HEMT device manufacturing process diagram provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below in conjunction with the accompanying drawings and specific embodiments. Obviously, the embodiments described are only some of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making any creative efforts are within the scope of protection of the present application.

[0039] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0040] As described in the background technology section, channel isolation in fin-structure and tri-gate HEMT devices is currently primarily achieved through plasma etching. Plasma etching can easily introduce a large number of acceptor-like defects and surface states on the surface and sidewalls of the etched area, causing severe surface leakage and even seriously affecting the off-state leakage current of the device.

[0041] In view of this, the present application provides a method for preparing a HEMT device, please refer to Figure 1 , Figure 1 A flow chart of a method for preparing a HEMT device provided in an embodiment of the present application, the method comprising:

[0042] Step S101: obtaining a substrate having a lateral polarity structure layer, wherein the lateral polarity structure layer comprises a patterned crystal layer, a buffer layer, a channel layer, and a barrier layer stacked in sequence in a direction away from the substrate.

[0043] The substrate is not specifically limited in this application and can be selected at will. For example, the substrate can be any one of a gallium nitride substrate, a diamond substrate, a sapphire substrate, a SiC substrate, and a Si substrate.

[0044] The patterned crystal layer is an AlN layer or a GaN layer; the buffer layer can be an Al x Ga 1-x Any one or a combination of several N layers, where 0≤x≤1, a value of x represents a buffer layer; the channel layer can be a GaN layer, and the barrier layer can be an Al y Ga 1-y N layers, where 0≤y≤1.

[0045] The buffer layer, channel layer, and barrier layer form a lateral polarity structure layer, which includes a metal polarity film layer portion and a nitrogen polarity film layer portion. The metal polarity film layer has metal polarity, and the nitrogen polarity film layer has nitrogen polarity. Among them, the buffer layer, channel layer, and barrier layer corresponding to the patterned crystal layer are metal polarity film layers, and the buffer layer, channel layer, and barrier layer not corresponding to the patterned crystal layer are nitrogen polarity film layers. Taking AlGaN / GaN heterojunction material as an example, the schematic diagram of the lateral polarity structure layer AlGaN / GaN is as follows: Figure 2 As shown in the figure, the polarization direction P of the metal-polarity film layer is from the surface to the substrate, while the polarization direction P of the nitrogen-polarity film layer is from the substrate to the surface. 2 represents the patterned crystalline layer, and 1 represents the substrate. Under the action of the polarization electric field, the metal-polarity AlGaN / GaN heterojunction induces a high-concentration and high-mobility 2DEG, so the metal-polarity film layer serves as the active region of the HEMT device.

[0046] In order to further increase the concentration and mobility of 2DEG, the lateral polar structure layer further includes:

[0047] An insertion layer is located between the channel layer and the barrier layer, wherein the insertion layer is an AlN layer.

[0048] Step S102: etching the channel layer and the barrier layer that do not correspond to the patterned crystalline layer using a wet etching method to form a three-dimensional channel structure.

[0049] It should be noted that the wet etching solution is not specifically limited in this application and can be selected at will. For example, the wet etching solution can be any one of potassium hydroxide solution, sodium hydroxide solution, tetramethylammonium hydroxide solution, and developer.

[0050] The depth of wet etching is between 20nm and 1000nm.

[0051] The metal polar film layer and the nitrogen polar film layer have different etching characteristics. The nitrogen polar film layer etches quickly in the etching solution, while the metal polar film layer has a very low etching rate and almost no etching occurs. The different etching characteristics of the metal polar film layer and the nitrogen polar film layer are caused by different surface bonding states.

[0052] The following uses a simplified ideal atomic configuration to explain the different etching behaviors of metal polar film layers and nitrogen polar film layers.

[0053] Gallium oxide is soluble in alkaline solutions, and the increase in the RMS value of metallic polar GaN after etching indicates that the surface oxide dissolves in the solution. However, once the Ga layer is removed, the surface is converted to nitrogen termination. The hydroxide ions in the alkaline solution cannot attack the nitrogen polar surface because OH - There is a strong repulsive force between the three occupied nitrogen dangling bonds, which may be the reason why the metal polar surface is resistant to corrosion in alkaline solutions. Please refer to the chemical reaction mechanism diagram of wet etching of nitrogen-polar gallium nitride in alkaline solution Figure 3(a) to Figure 3(d) For the nitrogen polar film, there is an upward dangling bond of nitrogen atom on the nitrogen polar surface, so OH - ions can attack the coordinated tetrahedral Ga atoms, as shown in Figure 3(a); and adsorb on the nitrogen polar surface, as shown in Figure 3(b); OH - The ions react with GaN to form gallium oxide and NH3, as shown in Figure 3(c); the process of Figure 3(a) is then repeated, as shown in Figure 3(d). Therefore, in alkaline solutions such as KOH and NaOH, the nitrogen-polar GaN surface can be continuously etched, while the metal polarity hardly changes.

[0054] Step S103: preparing a source electrode and a drain electrode, and preparing a gate electrode on the upper surface of the three-dimensional channel structure to obtain a HEMT device.

[0055] It should be pointed out that in order to isolate multiple HEMT devices from each other, after preparing the source electrode and the drain electrode, it is necessary to use dry etching to prepare a mesa structure.

[0056] The areas of the source electrode and the drain electrode are defined by photolithography, and the source electrode and the drain electrode are prepared by electron beam deposition or thermal evaporation. The mesa structure is prepared by dry etching, and then the gate electrode is prepared by electron beam evaporation or magnetron sputtering.

[0057] In order to reduce the contact resistance, after the source electrode and drain electrode areas are defined by photolithography, a step of etching the source electrode and drain electrode areas to the channel layer by plasma etching can be performed, and then subsequent steps such as preparing the source electrode and drain electrode can be performed.

[0058] It should be noted that when the source electrode and the drain electrode also have local areas on the upper surface of the three-dimensional channel structure, the HEMT device is a fin-structure HEMT device; when the source electrode and the drain electrode are completely not on the upper surface of the three-dimensional channel structure, the HEMT device is a tri-gate HEMT device.

[0059] In the present application, when preparing the HEMT device, after forming a patterned crystal layer, a buffer layer, a channel layer, and a barrier layer on the substrate, the buffer layer, the channel layer, and the barrier layer corresponding to the patterned crystal layer are metal polarity film layers, and the buffer layer, the channel layer, and the barrier layer not corresponding to the patterned crystal layer are nitrogen polarity film layers. The metal polarity film layer and the nitrogen polarity film layer have different etching characteristics. The nitrogen polarity film layer has a fast etching speed in the etching solution, while the metal polarity film layer has a very low etching rate and almost no etching occurs. Therefore, a wet method is used. The etching method etches the channel layer and barrier layer that do not correspond to the patterned crystalline layer, leaking out the channel layer in the metal polar film layer to form a three-dimensional channel structure. The wet etching interface is flat and smooth, avoiding the ion damage caused by plasma etching, reducing the leakage current and surface states of the HEMT device, which is of great significance for improving the short channel effect and dynamic characteristics of the device. It also avoids the subsequent tedious isolation processes such as photolithography, plasma etching, or ion beam implantation, shortening the process time, reducing process complexity and manufacturing cost. In addition, HEMT devices without ion damage are also of great significance for the application of HEMT devices and modules in high-efficiency monolithic integrated rectifier circuits, monolithic integrated RF power amplifiers, and terahertz communication circuits.

[0060] In order to improve the protection of the HEMT device and extend the service life of the HEMT device, in one embodiment of the present application, after preparing the source electrode and the drain electrode and preparing the gate electrode on the upper surface of the three-dimensional channel structure, the method further includes:

[0061] Deposit a passivation layer.

[0062] It should be noted that the passivation layer covers the surface of the HEMT device.

[0063] The passivation layer can be SiN x layer, Al2O3 layer, SiO x The passivation layer can be prepared by plasma enhanced chemical vapor deposition.

[0064] Based on the above embodiment, in one embodiment of the present application, before obtaining the substrate having the lateral polarity structure layer, the method further includes:

[0065] growing a crystalline layer on the upper surface of the substrate, and etching the crystalline layer to form the patterned crystalline layer;

[0066] The buffer layer, the channel layer, and the barrier layer are sequentially grown on the upper surface of the patterned crystal layer and on a region of the upper surface of the substrate not covered by the patterned crystal layer.

[0067] In a specific embodiment, etching the crystal layer to form the patterned crystal layer includes: etching the crystal layer to form the patterned crystal layer using plasma etching. However, this application does not specifically limit this. In another embodiment, etching the crystal layer to form the patterned crystal layer includes: etching the crystal layer to form the patterned crystal layer using wet etching. The wet etching solution is any one of potassium hydroxide solution, sodium hydroxide solution, tetramethylammonium hydroxide solution, and developer.

[0068] As a specific embodiment, the buffer layer, the channel layer and the barrier layer are sequentially grown on the upper surface of the patterned crystal layer and the area of the upper surface of the substrate not covered by the patterned crystal layer, including: using metal organic chemical vapor deposition to sequentially grow the buffer layer, the channel layer and the barrier layer on the upper surface of the patterned crystal layer and the area of the upper surface of the substrate not covered by the patterned crystal layer.

[0069] However, the present application does not specifically limit the method of growing the buffer layer, the channel layer, and the barrier layer. In other embodiments of the present application, magnetron sputtering or molecular beam epitaxy (MBE), etc., may also be used.

[0070] Based on any of the above embodiments, in one embodiment of the present application, before preparing the source electrode and the drain electrode and preparing the gate electrode on the upper surface of the three-dimensional channel structure, the method further includes:

[0071] growing a dielectric layer on the upper surface of the three-dimensional channel structure;

[0072] Accordingly, preparing a gate electrode on the upper surface of the three-dimensional channel structure includes:

[0073] A gate electrode is prepared on the upper surface of the dielectric layer.

[0074] The dielectric layer can reduce the leakage current of the gate electrode. The dielectric layer includes but is not limited to Al2O3 layer, SiN x layer, wherein the Al2O3 layer can be deposited by atomic layer deposition (ALD), SiN x The layers can be deposited using low pressure chemical vapor deposition (LPCVD).

[0075] Please refer to Figure 4 , Figure 4A flow chart of another HEMT device preparation method provided in this application, the method comprising:

[0076] Step S201: growing a crystalline layer on the upper surface of the substrate, and etching the crystalline layer to form a patterned crystalline layer.

[0077] For this step, please refer to Figure 5 and Figure 6 First, a uniform crystalline layer 2' is grown on the upper surface of the substrate 1, and then a patterned area is prepared by photolithography. The area not protected by the photoresist is etched by plasma etching or wet etching to form a patterned crystalline layer 2.

[0078] Step S202 : sequentially growing a buffer layer, a channel layer, an insertion layer, and a barrier layer on the upper surface of the patterned crystal layer and an area of the upper surface of the substrate not covered by the patterned crystal layer.

[0079] For this step, please refer to Figure 7 The substrate 1 with a patterned crystalline layer 2 formed on its surface is placed in an epitaxial growth device such as MOCVD (Metal-organic Chemical Vapor Deposition) or MBE, and a buffer layer 3, a channel layer 4, an insertion layer 5, and a barrier layer 6 with metal polarity and nitrogen polarity are grown in a single step at high temperature. The metal polarity region heterojunction induces a 2DEG as the active region. The buffer layer 3, channel layer 4, insertion layer 5, and barrier layer 6 corresponding to the patterned crystalline layer 2 are region A with metal polarity, while the buffer layer 3, channel layer 4, insertion layer 5, and barrier layer 6 not corresponding to the patterned crystalline layer 2 are region B with nitrogen polarity.

[0080] Step S203: etching the channel layer, the insertion layer, and the barrier layer that do not correspond to the patterned crystalline layer using a wet etching method to form a three-dimensional channel structure.

[0081] For this step, please refer to Figure 8 , take the substrate on which the buffer layer 3, channel layer 4, insertion layer 5 and barrier layer 6 are grown in step 7 out of the cavity, perform wet etching, etch the nitrogen polarity area to a depth of 20nm to 1000nm, and etch to the buffer layer 3 as an isolation area to form a three-dimensional channel structure.

[0082] Step S204: growing a dielectric layer on the upper surface of the three-dimensional channel structure.

[0083] For this step, please refer to Figure 9 , a dielectric layer 7 is deposited on the upper surface of the three-dimensional channel structure.

[0084] Step S205: preparing a source electrode and a drain electrode, and preparing a gate electrode on the upper surface of the three-dimensional channel structure.

[0085] It should be pointed out that, in this step, after preparing the source electrode and the drain electrode, it is also necessary to prepare the mesa structure by dry etching, and then prepare the gate electrode.

[0086] For this step, please refer to Figure 10 , using photolithography, etching and electron beam technology to deposit the source electrode, drain electrode and gate electrode 8. It should be noted that, Figure 10 The source electrode and the drain electrode are not shown, and only the gate electrode 8 is shown.

[0087] Step S206: depositing a passivation layer to obtain a HEMT device.

[0088] For this step, please refer to Figure 11 , the passivation layer 9 covers the surface of the HEMT device.

[0089] It should be noted that Figure 11 The HEMT device in the embodiment may be a fin-structured HEMT device or a local structure where the gate electrode of a triple-gate HEMT device is located.

[0090] The following uses sapphire substrate and silicon substrate as examples to fabricate HEMT devices.

[0091] Example 1

[0092] Step 1: grow a 20 nm AlN crystalline layer on a sapphire substrate based on MOCVD technology, and obtain a sapphire substrate with a patterned crystalline layer using photolithography and plasma etching processes.

[0093] Step 2: Place the sapphire substrate on the patterned crystal layer into the MOCVD device to epitaxially grow the heterojunction. The heterojunction consists of GaN high-resistance buffer layer, GaN channel layer, AlN insertion layer, AlN ion layer, and GaN ion layer from bottom to top. 0.3 Ga 0.7 The N barrier layer has thicknesses of 1μm, 100nm, 2nm, and 25nm, respectively. The area of the heterojunction corresponding to the patterned crystalline layer on the sapphire substrate is the metal polarity region, which is also the active area of the HEMT device; the area without the patterned crystalline layer is the nitrogen polarity region, which serves as the area to be etched.

[0094] Step 3: Prepare 3M KOH solution and etch the heterojunction for 5 minutes at 75°C. The metal polar region is not affected, while the nitrogen polar region is etched to the buffer layer region.

[0095] Step 4: Deposit a 20nm SiNx dielectric layer based on LPCVD.

[0096] Step 5: Define the source electrode and drain electrode areas by photolithography, perform plasma etching to the channel layer, and electron beam deposit Ti / Al / Ni / Au source and drain electrodes with a thickness of 200 nm.

[0097] Step 6: Prepare a mesa structure by dry etching to achieve the purpose of device isolation.

[0098] Step 7: Deposit a Ni / Au gate electrode by electron beam evaporation with a thickness of 120 nm.

[0099] Step 8: Deposit a 500nm SiNx passivation layer based on PECVD.

[0100] Example 2

[0101] Step 1: grow a 10 nm AlN crystalline layer on a silicon substrate based on magnetron sputtering technology, and obtain a silicon substrate with a patterned crystalline layer using photolithography and plasma etching processes.

[0102] Step 2: Based on the patterned crystalline silicon substrate, place the silicon substrate into the MOCVD device to epitaxially grow the heterojunction. The heterojunction is composed of AlGaN buffer layer, GaN channel layer, AlN insertion layer, AlGaN buffer layer, GaN channel layer, AlGaN insertion layer, AlGaN channel ... 0.3 Ga 0.7 The N barrier layer. The heterojunction corresponds to the metal polarity region where the patterned crystal layer is located on the silicon substrate, which is the active area of the HEMT device; the area without the patterned crystal layer is the nitrogen polarity region, which serves as the area to be etched.

[0103] Step 3: Prepare a TMAH / H2O2 solution with a mass fraction ratio of 1:5 and etch the heterojunction for 10 minutes at room temperature. The metal polar region is unaffected, while the nitrogen polar region is etched down to the buffer layer.

[0104] Step 4: Deposit a 20nm Al2O3 dielectric layer based on ALD.

[0105] Step 5: Define the source electrode and drain electrode regions by photolithography, perform plasma etching to the channel layer, and deposit Ti / Al source and drain electrodes by thermal evaporation with a thickness of 200 nm.

[0106] Step 6: Prepare a mesa structure by dry etching to achieve the purpose of device isolation.

[0107] Step 7: Deposit Ni / Au gate electrode by magnetron sputtering.

[0108] Step 8: Deposit 500nm SiN based on PECVD x passivation layer.

[0109] The present application also provides a HEMT device, which is manufactured by the HEMT device manufacturing method described in any of the above embodiments.

[0110] The type of HEMT device is not specifically limited in this application and may be selected based on the specific circumstances. For example, the HEMT device may be a fin-type HEMT device, or a tri-gate HEMT device.

[0111] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from the other embodiments. Reference can be made to the descriptions of the identical or similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions of the methods.

[0112] The above describes in detail the HEMT device and its fabrication method provided by this application. Specific examples are used herein to illustrate the principles and implementation methods of this application. The description of the above examples is intended only to facilitate understanding of the method and its core concept. It should be noted that those skilled in the art may make various improvements and modifications to this application without departing from the principles of this application, and such improvements and modifications fall within the scope of protection of the claims of this application.

Claims

1. A method for preparing a HEMT device, characterized in that: include: Obtaining a substrate having a lateral polarity structure layer, wherein the lateral polarity structure layer includes a patterned crystal layer, a buffer layer, a channel layer, and a barrier layer stacked in sequence in a direction away from the substrate; etching the channel layer and the barrier layer not corresponding to the patterned crystalline layer by wet etching to form a three-dimensional channel structure; A source electrode and a drain electrode are prepared, and a gate electrode is prepared on the upper surface of the three-dimensional channel structure to obtain a HEMT device.

2. The method for preparing a HEMT device according to claim 1, wherein: After the source electrode and the drain electrode are prepared, and the gate electrode is prepared on the upper surface of the three-dimensional channel structure, the method further includes: Deposit a passivation layer.

3. The method for preparing a HEMT device according to claim 1, wherein: Before obtaining the substrate having the lateral polarity structure layer, the method further comprises: growing a crystalline layer on the upper surface of the substrate, and etching the crystalline layer to form the patterned crystalline layer; The buffer layer, the channel layer, and the barrier layer are sequentially grown on the upper surface of the patterned crystal layer and on a region of the upper surface of the substrate not covered by the patterned crystal layer.

4. The method for preparing a HEMT device according to claim 3, wherein: The etching of the crystal layer to form the patterned crystal layer includes: The crystal layer is etched by plasma etching to form the patterned crystal layer.

5. The method for preparing a HEMT device according to claim 3, wherein: Growing the buffer layer, the channel layer, and the barrier layer in sequence on the upper surface of the patterned crystal layer and an area of the upper surface of the substrate not covered by the patterned crystal layer comprises: The buffer layer, the channel layer and the barrier layer are sequentially grown on the upper surface of the patterned crystal layer and the area of the upper surface of the substrate not covered by the patterned crystal layer by metal organic chemical vapor deposition.

6. The method for preparing a HEMT device according to claim 1, wherein: The transverse polarity structure layer further includes: An insertion layer is located between the channel layer and the barrier layer.

7. The method for preparing a HEMT device according to any one of claims 1 to 6, wherein: Before preparing the source electrode and the drain electrode and preparing the gate electrode on the upper surface of the three-dimensional channel structure, the method further includes: growing a dielectric layer on the upper surface of the three-dimensional channel structure; Accordingly, preparing a gate electrode on the upper surface of the three-dimensional channel structure includes: A gate electrode is prepared on the upper surface of the dielectric layer.

8. The method for preparing a HEMT device according to claim 7, wherein: The growing of a dielectric layer on the upper surface of the three-dimensional channel structure comprises: The dielectric layer is grown on the upper surface of the three-dimensional channel structure by adopting a low-pressure chemical vapor deposition method.

9. A HEMT device, characterized in that: The HEMT device is manufactured by the HEMT device manufacturing method according to any one of claims 1 to 8.

10. The HEMT device according to claim 9, wherein The HEMT device is a fin-structured HEMT device.

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