Common-source common-gate amplifier
By adding branch modules and cross-coupling modules to a single-stage cascode amplifier, the problem of traditional cascode amplifiers being unable to achieve high gain and short settling time under low power supply voltage is solved, achieving high gain, wide bandwidth and high slew rate.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHENGDU LIGHT COLLECTOR TECH
- Filing Date
- 2022-10-17
- Publication Date
- 2026-07-07
AI Technical Summary
In complementary metal-oxide-semiconductor (CMOS) technology, traditional folded cascode amplifiers struggle to achieve high gain, short settling time, and high signal establishment accuracy at low supply voltages, and two-stage amplifiers require significant power consumption and area.
A single-stage common-source cascode amplifier structure is adopted, and first and second branch modules are added to increase the small signal path. A positive feedback loop is formed through a cross-coupling module to improve the small signal settling speed and large signal slew rate.
Without increasing power consumption, the circuit gain, bandwidth, and slew rate are improved, and the signal settling time is shortened.
Smart Images
Figure CN115514332B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit design technology, and in particular to a common-source, common-gate amplifier. Background Technology
[0002] Transconductance amplifiers are widely used in analog and mixed-signal chips, such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and phase-locked loops (PLLs). For example, in high-precision ADCs, the operational transconductance amplifier (OTA) is used to drive large capacitive loads. In high-speed applications, the OTA needs to establish the signal in a very short time and also achieve a certain level of accuracy. To meet these requirements, the OTA needs to have high gain, unity-gain bandwidth product, and high slew rate. Compared to ordinary amplifiers, the single-pole folded cascode amplifier has high gain, a large signal output swing, and a high gain-bandwidth product, making it widely used. However, in Complementary Metal Oxide Semiconductor (CMOS) technology, to achieve high gain, short settling time, and high signal establishment accuracy at lower supply voltages, the traditional folded cascode amplifier is used. It is difficult for an amplifier (FCA) to meet the requirements of high gain and high bandwidth when the high slew rate is achieved. In this case, a two-stage amplifier is required. The FCA acts as the first stage to provide high gain, while the second stage provides a large output swing and driving capability while providing a certain gain. However, the two-stage amplifier needs to be compensated to meet the stability requirements, which consumes a lot of power and a large area overhead, increasing power consumption and circuit area.
[0003] Therefore, it is necessary to provide a novel common-source cascode amplifier to solve the aforementioned problems existing in the prior art. Summary of the Invention
[0004] The purpose of this invention is to provide a common-source cascode amplifier that improves the slew rate, gain, and bandwidth of the circuit in a single-stage amplifier structure.
[0005] To achieve the above objectives, the common-source cascode amplifier of the present invention comprises:
[0006] The signal input module is used to generate input signals based on the power supply voltage;
[0007] A cross-coupling module, electrically connected to the signal input module, is used to form internal positive feedback based on the input signal;
[0008] The first bias module is electrically connected to the cross-coupled module;
[0009] The first branch module is electrically connected to the first bias module;
[0010] The second bias module is electrically connected to the cross-coupled module.
[0011] The second branch module is electrically connected to the second bias module;
[0012] The first bias module and the second bias module are used to provide bias after the input common-mode feedback voltage, the first branch module and the second branch module are used to provide large swing output bias, and the first branch module and the second branch module are electrically connected to the signal input module respectively. The signal input module is also used to output branch signals to the first branch module and the second branch module.
[0013] The beneficial effects of the common-source cascode amplifier described in this invention are as follows: The common-source cascode amplifier described in this invention is based on a single-stage amplifier structure. It adds a first branch module and a second branch module inside to effectively increase the number of small-signal paths to form small-signal paths, thereby effectively improving the small-signal setup speed, expanding the bandwidth, and shortening the setup time. Moreover, the cross-coupling module forms a positive feedback loop inside the circuit, which improves the large-signal slew rate and enhances the circuit gain.
[0014] Optionally, the signal input module includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, and a fifth PMOS transistor. The source of the first PMOS transistor is connected to the operating voltage, and the drain of the first PMOS transistor is electrically connected to the sources of the second, third, fourth, and fifth PMOS transistors, respectively. The gate of the first PMOS transistor is connected to a first bias voltage, and the gates of the second and third PMOS transistors are both connected to a first input voltage. The fourth and fifth PMOS transistors are both connected to a second input voltage.
[0015] Optionally, the first branch module includes a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor. The sources of the sixth and seventh PMOS transistors are both connected to the operating voltage. The drain of the sixth PMOS transistor is electrically connected to the source of the eighth PMOS transistor, and the drain of the seventh PMOS transistor is electrically connected to the source of the ninth PMOS transistor. The gates of the sixth and seventh PMOS transistors are both electrically connected to the drain of the ninth PMOS transistor. The eighth PMOS transistor... The drain of the OS transistor and the drain of the first NMOS transistor serve as the first output terminal. The drain of the ninth PMOS transistor is electrically connected to the drain of the second NMOS transistor. The gates of the first NMOS transistor and the second NMOS transistor are connected to a second bias voltage. The gates of the eighth PMOS transistor and the ninth PMOS transistor are both connected to a third bias voltage. The source of the second NMOS transistor is electrically connected to the drain of the third NMOS transistor. The gate of the third NMOS transistor is electrically connected to the drain of the third PMOS transistor. The source of the first NMOS transistor is electrically connected to the drain of the second PMOS transistor.
[0016] The second branch module includes a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor. The sources of the tenth and eleventh PMOS transistors are both connected to the operating voltage. The drain of the tenth PMOS transistor is electrically connected to the source of the twelfth PMOS transistor, and the drain of the eleventh PMOS transistor is electrically connected to the source of the thirteenth PMOS transistor. The gates of the tenth and eleventh PMOS transistors are both electrically connected to the drain of the twelfth PMOS transistor. The drain of the PMOS transistor is electrically connected to the drain of the fourth NMOS transistor, the source of the fifth NMOS transistor is electrically connected to the drain of the fifth PMOS transistor, the gates of the fourth NMOS transistor and the fifth NMOS transistor are connected to a second bias voltage, the gates of the twelfth PMOS transistor and the thirteenth PMOS transistor are connected to a third bias voltage, the source of the fourth NMOS transistor is electrically connected to the drain of the sixth NMOS transistor, the gate of the sixth NMOS transistor is electrically connected to the drain of the fourth PMOS transistor, and the drain of the thirteenth PMOS transistor and the drain of the fifth NMOS transistor serve as a second output terminal.
[0017] Optionally, the cross-coupling module includes a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor. The gates of the seventh and eighth NMOS transistors are connected to a second bias voltage. The drain of the seventh NMOS transistor is electrically connected to the drain of the third PMOS transistor, the drain of the eighth NMOS transistor is electrically connected to the drain of the fourth PMOS transistor, the source of the seventh NMOS transistor is electrically connected to the drain of the ninth NMOS transistor, and the source of the eighth NMOS transistor is electrically connected to the drain of the tenth NMOS transistor. The sources of the ninth and tenth NMOS transistors are both grounded.
[0018] Optionally, the first bias module includes an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, and a fourteenth NMOS transistor. The drain of the eleventh NMOS transistor is electrically connected to the drain of the fourth PMOS transistor. The gate of the eleventh NMOS transistor is connected to a second bias voltage. The source of the eleventh NMOS transistor is electrically connected to the drain of the fourteenth NMOS transistor. The gates of the fourteenth NMOS transistor, the ninth NMOS transistor, and the thirteenth NMOS transistor are all electrically connected to the drain of the eleventh NMOS transistor. The drains of the twelfth and thirteenth NMOS transistors are all electrically connected to the drain of the second PMOS transistor. The sources of the twelfth, thirteenth, and fourteenth NMOS transistors are all grounded.
[0019] The second bias module includes a fifteenth NMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, and an eighteenth NMOS transistor. The drain of the fifteenth NMOS transistor is electrically connected to the drain of the third PMOS transistor. The gate of the fifteenth NMOS transistor is connected to a second bias voltage. The source of the fifteenth NMOS transistor is electrically connected to the drain of the sixteenth NMOS transistor. The gates of the tenth NMOS transistor, the sixteenth NMOS transistor, and the seventeenth NMOS transistor are all electrically connected to the drain of the fifteenth NMOS transistor. The drains of the seventeenth NMOS transistor and the eighteenth NMOS transistor are both electrically connected to the source of the fifth PMOS transistor. The sources of the sixteenth NMOS transistor, the seventeenth NMOS transistor, and the eighteenth NMOS transistor are all grounded.
[0020] Optionally, the gates of the twelfth NMOS transistor and the eighteenth NMOS transistor are both connected to a common-mode feedback voltage. Attached Figure Description
[0021] Figure 1 This is a circuit diagram of a single-stage folded cascode amplifier in the prior art.
[0022] Figure 2 This is a circuit diagram of the common-source cascode amplifier described in an embodiment of the present invention.
[0023] Figure 3 This is a comparison diagram of the AC characteristics of the common-source cascode amplifier described in the embodiment of the present invention and the single-stage folded common-source cascode amplifier in the prior art.
[0024] Figure 4 This is a comparison diagram of the DC characteristics of the common-source cascode amplifier described in the embodiment of the present invention and the single-stage folded common-source cascode amplifier in the prior art. Detailed Implementation
[0025] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without inventive effort are within the scope of protection of this invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, but do not exclude other elements or objects.
[0026] Existing single-stage folded cascode amplifiers, such as Figure 1As shown, the transistors include PMOS transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, and M11. The drain of PMOS transistor M11 is electrically connected to the source of PMOS transistors M1 and M2. The drain of PMOS transistor M1 is electrically connected to the drain of NMOS transistors M3 and M5. The drain of PMOS transistor M2 is electrically connected to the source of NMOS transistors M6 and M4. The gates of PMOS transistors M1 and M2 are respectively connected to the input voltages VI+ and VI-. The drains of NMOS transistors M5 and M7 both serve as the output interface VO-. The source of transistor M7 and the drain of PMOS transistor M9 are both used as output interfaces VO+. The drain of NMOS transistor M6 is electrically connected to the drain of PMOS transistor M8. The source of PMOS transistor M8 is electrically connected to the drain of PMOS transistor M10. The source of NMOS transistor M3 and the source of NMOS transistor M4 are grounded to GND. The gates of NMOS transistor M3 and NMOS transistor M4 are both connected to the common-mode feedback voltage. The gates of NMOS transistor M5 and NMOS transistor M6 are both connected to the bias voltage VN1. The gates of PMOS transistor M7 and PMOS transistor M8 are both connected to the bias voltage VP2. The gates of PMOS transistor M9 and PMOS transistor M10 are both connected to the bias voltage VP1. The sources of PMOS transistors M9, M10, and M11 are all connected to the operating voltage Vdd.
[0027] M1 and M2, as PMOS input differential pairs, can have lower 1 / f noise than NMOS. M5, M6, M7, and M8 are cascode transistors providing a larger output impedance, while M3, M4, M9, and M10 are current source transistors. From the small signal path perspective, the positive input terminal is output from M1 via M5, and the negative input terminal is output from M2 via M6. However, this single-stage folded cascode amplifier is difficult to meet the requirements of high gain and high bandwidth when achieving a high slew rate.
[0028] To address the problems existing in the prior art, embodiments of the present invention provide a common-source cascode amplifier. Based on the traditional single-stage folded common-source cascode amplifier, a first branch module and a second branch module are added internally to effectively increase the number of small-signal paths to form small-signal paths, thereby effectively improving the small-signal setup speed, expanding the bandwidth, and shortening the setup time. Moreover, the cross-coupling module forms a positive feedback loop inside the circuit, improving the large-signal slew rate and increasing the circuit gain.
[0029] In some embodiments, reference Figure 2The common-source common-gate amplifier of this solution includes a signal input module 1, a cross-coupling module 2, a first bias module 5, a first branch module 3, a second bias module 6, and a second branch module 4. The signal input module 1 generates an input signal based on the power supply voltage. The cross-coupling module 2 is electrically connected to the signal input module 1 and forms internal positive feedback based on the input signal. The first bias module 5 is electrically connected to the cross-coupling module 2. The first branch module 3 is electrically connected to the first bias module 5. The second bias module 6 is electrically connected to the cross-coupling module 2. The second branch module 4 is electrically connected to the second bias module 6. The first bias module 5 and the second bias module 6 provide bias after the input common-mode feedback voltage. The first branch module 3 and the second branch module 4 provide a large-swing output bias, and both are electrically connected to the signal input module 1. The signal input module 1 also outputs branch signals to the first branch module 3 and the second branch module 4.
[0030] In some embodiments, continue to refer to Figure 2 The signal input module 1 includes a first PMOS transistor 101, a second PMOS transistor 102, a third PMOS transistor 103, a fourth PMOS transistor 104, and a fifth PMOS transistor 105. The source of the first PMOS transistor 101 is connected to the operating voltage Vdd. The drain of the first PMOS transistor 101 is electrically connected to the sources of the second PMOS transistor 102, the third PMOS transistor 103, the fourth PMOS transistor 104, and the fifth PMOS transistor 105, respectively. The gate of the first PMOS transistor 101 is connected to a first bias voltage V1. The gates of the second PMOS transistor 102 and the third PMOS transistor 103 are both connected to a first input voltage Vin+. The fourth PMOS transistor 104 and the fifth PMOS transistor 105 are both connected to a second input voltage Vin-.
[0031] In some embodiments, the first branch module 3 includes a sixth PMOS transistor 301, a seventh PMOS transistor 302, an eighth PMOS transistor 303, a ninth PMOS transistor 304, a first NMOS transistor 305, a second NMOS transistor 306, and a third NMOS transistor 307. The sources of the sixth PMOS transistor 301 and the seventh PMOS transistor 302 are both connected to the operating voltage Vdd. The drain of the sixth PMOS transistor 301 is electrically connected to the source of the eighth PMOS transistor 303, and the drain of the seventh PMOS transistor 302 is electrically connected to the source of the ninth PMOS transistor 304. The gates of the sixth PMOS transistor 301 and the seventh PMOS transistor 302 are both electrically connected to the drain of the ninth PMOS transistor 304. The drain of PMOS transistor 303 and the drain of the first NMOS transistor 305 are used as the first output terminal Vout-. The drain of the ninth PMOS transistor 304 is electrically connected to the drain of the second NMOS transistor 306. The gates of the first NMOS transistor 305 and the second NMOS transistor 306 are connected to the second bias voltage V2. The gates of the eighth PMOS transistor 303 and the ninth PMOS transistor 304 are both connected to the third bias voltage V3. The source of the second NMOS transistor 306 is electrically connected to the drain of the third NMOS transistor 307. The gate of the third NMOS transistor 307 is electrically connected to the drain of the third PMOS transistor 103. The source of the first NMOS transistor 305 is electrically connected to the drain of the second PMOS transistor 102.
[0032] The second branch module 4 includes a tenth PMOS transistor 401, an eleventh PMOS transistor 402, a twelfth PMOS transistor 403, a thirteenth PMOS transistor 404, a fourth NMOS transistor 405, a fifth NMOS transistor 406, and a sixth NMOS transistor 407. The sources of the tenth PMOS transistor 401 and the eleventh PMOS transistor 402 are both connected to the operating voltage Vdd. The drain of the tenth PMOS transistor 401 is electrically connected to the source of the twelfth PMOS transistor 403, and the drain of the eleventh PMOS transistor 402 is electrically connected to the source of the thirteenth PMOS transistor 403. The gates of the tenth PMOS transistor 401 and the eleventh PMOS transistor 402 are both electrically connected to the drain of the twelfth PMOS transistor 403. The drain of PMOS transistor 403 is electrically connected to the drain of the fourth NMOS transistor 405. The source of the fifth NMOS transistor 406 is electrically connected to the drain of the fifth PMOS transistor 105. The gates of the fourth NMOS transistor 405 and the fifth NMOS transistor 406 are connected to a second bias voltage V2. The gate of the twelfth PMOS transistor 403 and the gate of the thirteenth PMOS transistor 404 are connected to a third bias voltage V3. The source of the fourth NMOS transistor 405 is electrically connected to the drain of the sixth NMOS transistor 407. The gate of the sixth NMOS transistor 407 is electrically connected to the drain of the fourth PMOS transistor 104. The drain of the thirteenth PMOS transistor 404 and the drain of the fifth NMOS transistor 406 serve as the second output terminal Vout+.
[0033] In some embodiments, the cross-coupling module 2 includes a seventh NMOS transistor 201, an eighth NMOS transistor 202, a ninth NMOS transistor 203, and a tenth NMOS transistor 204. The gates of the seventh NMOS transistor 201 and the eighth NMOS transistor 202 are connected to a second bias voltage V2. The drain of the seventh NMOS transistor 201 is electrically connected to the drain of the third PMOS transistor 103, the drain of the eighth NMOS transistor 202 is electrically connected to the drain of the fourth PMOS transistor 104, the source of the seventh NMOS transistor 201 is electrically connected to the drain of the ninth NMOS transistor 203, and the source of the eighth NMOS transistor 202 is electrically connected to the drain of the tenth NMOS transistor 204. The sources of the ninth NMOS transistor 203 and the tenth NMOS transistor 204 are both grounded to GND.
[0034] In some other embodiments, the first bias module 5 includes an eleventh NMOS transistor 501, a twelfth NMOS transistor 502, a thirteenth NMOS transistor 503, and a fourteenth NMOS transistor 504. The drain of the eleventh NMOS transistor 501 is electrically connected to the drain of the fourth NMOS transistor 504. The gate of the eleventh NMOS transistor 501 is connected to a second bias voltage V2. The source of the eleventh NMOS transistor 501 is electrically connected to the drain of the fourteenth NMOS transistor 504. The gates of OS transistor 504, the ninth NMOS transistor 203, and the thirteenth NMOS transistor 503 are all electrically connected to the drain of the eleventh NMOS transistor 501. The drains of the twelfth NMOS transistor 502 and the thirteenth NMOS transistor 503 are all electrically connected to the drain of the second PMOS transistor 102. The sources of the twelfth NMOS transistor 502, the thirteenth NMOS transistor 502, and the fourteenth NMOS transistor 504 are all grounded to GND.
[0035] The second bias module 6 includes a fifteenth NMOS transistor 601, a sixteenth NMOS transistor 602, a seventeenth NMOS transistor 603, and an eighteenth NMOS transistor 604. The drain of the fifteenth NMOS transistor 601 is electrically connected to the drain of the third PMOS transistor 103. The gate of the fifteenth NMOS transistor 601 is connected to a second bias voltage V2. The source of the fifteenth NMOS transistor 601 is electrically connected to the drain of the sixteenth NMOS transistor 602. The tenth NMOS transistor 604... The gates of transistor 04, the sixteenth NMOS transistor 602, and the seventeenth NMOS transistor 603 are all electrically connected to the drain of the fifteenth NMOS transistor 601. The drains of the seventeenth NMOS transistor 603 and the eighteenth NMOS transistor 604 are all electrically connected to the source of the fifth PMOS transistor 105. The sources of the sixteenth NMOS transistor 602, the seventeenth NMOS transistor 603, and the eighteenth NMOS transistor 604 are all grounded to GND.
[0036] In some embodiments, the gate of the twelfth NMOS transistor 502 and the gate of the eighteenth NMOS transistor 604 are both connected to the common-mode feedback voltage Vcmfb.
[0037] In this embodiment, the second PMOS transistor 102, the fifth PMOS transistor 105, the thirteenth NMOS transistor 502, the eighteenth NMOS transistor 604, the first NMOS transistor 305, the fourth NMOS transistor 405, the eighth PMOS transistor 303, the thirteenth PMOS transistor 404, the sixth PMOS transistor 301, and the eleventh PMOS transistor 402 constitute a traditional folded cascode amplifier structure. This solution further uses the seventh PMOS transistor 302, the ninth PMOS transistor 304, the second NMOS transistor 306, and the third NMOS transistor 307 in the first branch module 3 to provide a large swing output bias for the sixth PMOS transistor 301 and the eighth PMOS transistor 303. Through the mirroring of the sixth PMOS transistor 301 and the seventh PMOS transistor 302, the small signal that has passed through the third PMOS transistor 103 in the additional input branch is output through the eighth PMOS transistor 303 and the sixth PMOS transistor 301 branch. Similarly, the tenth PMOS transistor 401, the twelfth PMOS transistor 403, the fourth NMOS transistor 405, and the sixth NMOS transistor 407 provide a large swing output bias for the eleventh PMOS transistor 402 and the thirteenth PMOS transistor 404. Through the mirroring of the tenth PMOS transistor 401 and the eleventh PMOS transistor 402, the small signal that passed through the fourth PMOS transistor 104 in the additional input branch is output through the branches of the eleventh PMOS transistor 402 and the thirteenth PMOS transistor 404.
[0038] Compared to the traditional FCA structure, this design adds small-signal paths through the sixth PMOS transistor 301, the eighth PMOS transistor 303, the eleventh PMOS transistor 402, and the thirteenth PMOS transistor 404, improving small-signal response and thus increasing slew rate. On the other hand, for maximizing output swing and symmetry considerations, the eleventh NMOS transistor 501 and the fourteenth NMOS transistor 504 in the first bias module 5 provide bias for the thirteenth NMOS transistor 503, with a bias structure similar to that of the seventh PMOS transistor 302 and the ninth PMOS transistor 304 providing bias for the sixth PMOS transistor 301. Similarly, the fifteenth NMOS transistor 601 and the sixteenth NMOS transistor 602 in the second bias module 6 provide bias for the seventeenth NMOS transistor 603. Unlike the second PMOS transistor 102 and the fifth PMOS transistor 105, whose tail currents flow into the output branches of the twelfth NMOS transistor 502 and the eighteenth NMOS transistor 604, the tail currents of the third PMOS transistor 103 and the fourth PMOS transistor 104 flow into the output branches of the twelfth NMOS transistor 502 and the eighteenth NMOS transistor 604. Instead, they flow into the cross-coupling module 2. In the cross-coupling module 2, the seventh NMOS transistor 201, the eighth NMOS transistor 202, the ninth NMOS transistor 203, and the tenth NMOS transistor 204 form an internal positive feedback loop as a cross-coupling pair. When the first input voltage Vin+ increases and the second input voltage Vin- decreases, the potential at node A on the drain of the fourth PMOS transistor begins to increase, while the potential at node B on the drain of the third PMOS transistor begins to decrease. The increase in the potential at point A causes the current in the branches of the seventh NMOS transistor 201 and the ninth NMOS transistor 203 to increase, which in turn further pulls down the potential at point B. Similarly, the branches of the eighth NMOS transistor 202 and the tenth NMOS transistor 204 also cause the potential at point A to increase further. When the first input voltage Vin+ decreases and the second input voltage Vin- increases, the situation is exactly the opposite of what was described above, which will not be repeated here. Therefore, it can be seen that the seventh NMOS transistor 201, the eighth NMOS transistor 202, the ninth NMOS transistor 203, and the tenth NMOS transistor 204 in the cross-coupling module 2 can accelerate the signal switching speed and also help improve the slew rate.
[0039] For example, to further verify the slew rate of this solution, the following embodiment is used as an example. Assume that the width-to-length ratio of the second PMOS transistor 102 and the third PMOS transistor 103 is 1:a1, the width-to-length ratio of the sixteenth NMOS transistor 602 and the third NMOS transistor 307 is 1:a2, the width-to-length ratio of the seventh PMOS transistor 302 and the sixth PMOS transistor 301 is 1:a3, the width-to-length ratio of the fourteenth NMOS transistor 504 and the thirteenth NMOS transistor 503 is 1:a4, and the width-to-length ratio of the fourteenth NMOS transistor 504 and the ninth NMOS transistor 203 is 1:a5.
[0040] Due to the current I of the twelfth NMOS transistor 502 M3 If the current is equal to that of the eighteenth NMOS transistor 604, then:
[0041]
[0042] The current I of the thirteenth NMOS transistor 503 M3d The current of the seventeenth NMOS transistor 603 is equal, i.e., I M3d =a4×I M2a , where I M2a This represents the current of the fourth PMOS transistor 104. The current I of the sixth PMOS transistor 301 is... M9 If the current is equal to that of the eleventh PMOS transistor 402, then it is: I M9 =a2×a3×I M2a .
[0043] The current of the fourth PMOS transistor 104 is:
[0044]
[0045] To compare performance with a traditional FCA circuit, we assume the total current of the traditional FCA is equal to the total current of the cascode amplifier circuit in this design. We assume the current flowing into the left branch of the cascode amplifier circuit in this design is I2, while the left branch current of the traditional FCA is I1. For stability design considerations, the output branch current of the traditional FCA also needs to be I1. Therefore, the total current of the cascode amplifier in this design is:
[0046]
[0047] Since the total current of a traditional FCA amplifier is 2I1, based on the fact that the total current of the common-source common-gate amplifier in both the traditional and this schemes is equal, we can obtain:
[0048]
[0049] Assuming the slewing rate of a traditional FCA is S1, we can obtain:
[0050] Assuming the slew rate of the common-source common-gate amplifier in this scheme is S2, then:
[0051]
[0052] By setting a4 = 2, n = 0.5, a2 = 1, and a3 = 2.5, we can obtain S2 = 3.2 × S1. Therefore, the slew rate of the common-source common-gate amplifier in this scheme is three times that of the traditional FCA amplifier.
[0053] Figure 3 , 4These are the AC and DC characteristic curves obtained from simulations when the slew rate of the conventional FCA and the common-source cascode amplifier of this scheme is connected to a 5pF load. The solid line represents the characteristic curve of the common-source cascode amplifier of this scheme, and the dashed line represents the characteristic curve of the conventional FCA. (Reference) Figure 3 Because the common source common gate amplifier in this scheme has more branches, more nodes are introduced, and the number of high-frequency poles will increase. However, the proportion of mirror current set above is not large, so the phase margin is sufficient. However, the increase of additional small signal branches significantly improves the gain and gain-bandwidth product. Figure 4 This is a comparison chart of DC characteristics established by a large signal, for reference. Figure 4 The settling time of a traditional FCA amplifier is approximately 30ns, while the large-signal settling time of the cascode amplifier in this invention is approximately 10ns, a significant reduction. Therefore, the cascode amplifier proposed in this invention can effectively improve gain, bandwidth, and slew rate without changing power consumption.
[0054] The common-source common-gate amplifier of this invention is based on a single-stage amplifier structure. It adds a first branch module and a second branch module inside to effectively increase the number of small-signal paths to form small-signal paths, thereby effectively improving the small-signal setup speed, expanding the bandwidth, and shortening the setup time. Moreover, the cross-coupling module forms a positive feedback loop inside the circuit, which improves the large-signal slew rate and enhances the circuit gain.
[0055] While embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations fall within the scope and spirit of the invention as set forth in the claims. Furthermore, the invention described herein may have other embodiments and can be implemented or carried out in various ways.
Claims
1. A cascode amplifier characterized by, include: The signal input module is used to generate input signals based on the power supply voltage; A cross-coupling module, electrically connected to the signal input module, is used to form internal positive feedback based on the input signal; The first bias module is electrically connected to one input terminal of the cross-coupled module; The first branch module is electrically connected to the first bias module; The second bias module is electrically connected to the cross-coupled module. The second branch module is electrically connected to the second bias module; Wherein, the first bias module and the second bias module are used to provide bias after the input common-mode feedback voltage, the first branch module and the second branch module are used to provide large swing output bias, and the first branch module and the second branch module are respectively electrically connected to the signal input module, and the signal input module is also used to output branch signals to the first branch module and the second branch module; The first branch module includes a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor. The sources of the sixth and seventh PMOS transistors are both connected to the operating voltage. The drain of the sixth PMOS transistor is electrically connected to the source of the eighth PMOS transistor, and the drain of the seventh PMOS transistor is electrically connected to the source of the ninth PMOS transistor. The gates of the sixth and seventh PMOS transistors are both electrically connected to the drain of the ninth PMOS transistor. The drain of the eighth PMOS transistor is electrically connected to the source of the ninth PMOS transistor. The drain of an NMOS transistor serves as the first output terminal. The drain of the ninth PMOS transistor is electrically connected to the drain of the second NMOS transistor. The gates of the first NMOS transistor and the second NMOS transistor are connected to a second bias voltage. The gates of the eighth PMOS transistor and the ninth PMOS transistor are both connected to a third bias voltage. The source of the second NMOS transistor is electrically connected to the drain of the third NMOS transistor. The gate of the third NMOS transistor is electrically connected to the drain of the third PMOS transistor in the signal input module. The source of the first NMOS transistor is electrically connected to the drain of the second PMOS transistor in the signal input module. The second branch module includes a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, a thirteenth PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor. The sources of the tenth and eleventh PMOS transistors are both connected to the operating voltage. The drain of the tenth PMOS transistor is electrically connected to the source of the twelfth PMOS transistor, and the drain of the eleventh PMOS transistor is electrically connected to the source of the thirteenth PMOS transistor. The gates of the tenth and eleventh PMOS transistors are both electrically connected to the drain of the twelfth PMOS transistor. The drain of the twelfth PMOS transistor... The fourth NMOS transistor is electrically connected to its drain, the fifth NMOS transistor is electrically connected to its drain, the fourth NMOS transistor and the fifth NMOS transistor are connected to a second bias voltage, the twelfth PMOS transistor and the thirteenth PMOS transistor are connected to a third bias voltage, the fourth NMOS transistor is electrically connected to its drain, the sixth NMOS transistor is electrically connected to its drain, the thirteenth PMOS transistor and the fifth NMOS transistor are connected to each other as a second output terminal.
2. The common-source cascode amplifier according to claim 1, characterized in that, The signal input module includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, and a fifth PMOS transistor. The source of the first PMOS transistor is connected to the operating voltage, and the drain of the first PMOS transistor is electrically connected to the sources of the second, third, fourth, and fifth PMOS transistors, respectively. The gate of the first PMOS transistor is connected to a first bias voltage, the gates of the second and third PMOS transistors are both connected to a first input voltage, and the gates of the fourth and fifth PMOS transistors are both connected to a second input voltage.
3. The common-source cascode amplifier according to claim 1 or 2, characterized in that, The cross-coupling module includes a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, and a tenth NMOS transistor. The gates of the seventh and eighth NMOS transistors are connected to a second bias voltage. The drain of the seventh NMOS transistor is electrically connected to the drain of the third PMOS transistor, and the drain of the eighth NMOS transistor is electrically connected to the drain of the fourth PMOS transistor. The source of the seventh NMOS transistor is electrically connected to the drain of the ninth NMOS transistor, and the source of the eighth NMOS transistor is electrically connected to the drain of the tenth NMOS transistor. The sources of the ninth and tenth NMOS transistors are both grounded.
4. The common-source cascode amplifier according to claim 3, characterized in that, The first bias module includes an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, and a fourteenth NMOS transistor. The drain of the eleventh NMOS transistor is electrically connected to the drain of the fourth PMOS transistor. The gate of the eleventh NMOS transistor is connected to a second bias voltage. The source of the eleventh NMOS transistor is electrically connected to the drain of the fourteenth NMOS transistor. The gates of the fourteenth NMOS transistor, the ninth NMOS transistor, and the thirteenth NMOS transistor are all electrically connected to the drain of the eleventh NMOS transistor. The drains of the twelfth and thirteenth NMOS transistors are all electrically connected to the drain of the second PMOS transistor. The sources of the twelfth, thirteenth, and fourteenth NMOS transistors are all grounded. The second bias module includes a fifteenth NMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, and an eighteenth NMOS transistor. The drain of the fifteenth NMOS transistor is electrically connected to the drain of the third PMOS transistor. The gate of the fifteenth NMOS transistor is connected to a second bias voltage. The source of the fifteenth NMOS transistor is electrically connected to the drain of the sixteenth NMOS transistor. The gates of the tenth NMOS transistor, the sixteenth NMOS transistor, and the seventeenth NMOS transistor are all electrically connected to the drain of the fifteenth NMOS transistor. The drains of the seventeenth NMOS transistor and the eighteenth NMOS transistor are both electrically connected to the source of the fifth PMOS transistor. The sources of the sixteenth NMOS transistor, the seventeenth NMOS transistor, and the eighteenth NMOS transistor are all grounded.
5. The common-source cascode amplifier according to claim 4, characterized in that, The gates of the twelfth NMOS transistor and the eighteenth NMOS transistor are both connected to a common-mode feedback voltage.