Storage device and operating method thereof, method of operating nonvolatile memory device

Abstract

A storage device and an operating method thereof, a method of operating a nonvolatile memory device are provided. The storage device includes a controller configured to control a nonvolatile memory device having a plurality of memory blocks therein. The controller includes secure erase control logic configured to: (i) control a secure erase operation on the plurality of memory blocks in response to a secure erase request received from a host, and (ii) set flags corresponding to the plurality of memory blocks such that a first flag corresponding to a first memory block that has undergone at least two secure erase operations has a first value. Adaptive control logic is provided configured to, in response to detecting that the first flag has the first value, change at least one operating condition associated with a write operation and / or a read operation for the first memory block.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0083119, filed on June 25, 2021, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present invention relates to a storage device, and more specifically, to a controller for performing a secure erase operation within the storage device, a storage device including the controller, and a method for operating the storage device. Background Technology

[0004] As a non-volatile memory, flash memory retains the data stored within it even when power is off. Storage devices including flash memory (such as solid-state drives (SSDs) and memory cards) are widely used. Storage devices are used to store or move large amounts of data. With the widespread use of storage devices across various fields, the security of the data stored in them is becoming increasingly important. Specifically, in computing systems using storage devices, even if a user deletes data, the corresponding information can be physically retained in the storage device. Typically, in cases where data is repeatedly erased for secure deletion, a high erase frequency can lead to a deterioration of the threshold voltage distribution characteristics. In such cases, data reliability may decrease when programming data to or reading data from the storage block. Summary of the Invention

[0005] The present invention provides a storage device and a method of operating the storage device, which can reduce or prevent the reduction in data reliability of storage blocks that are degraded in response to repeated secure erase operations.

[0006] According to one aspect of the present invention, a storage device is provided, the storage device including a controller configured to control a non-volatile memory device comprising a plurality of blocks. The controller may include secure erase control logic configured to control secure erase operations on the plurality of blocks in response to a secure erase request received from a host, and to set flags corresponding to the plurality of blocks such that the flag corresponding to a block among the plurality of blocks that has been requested to undergo at least two secure erase operations has a first value. Adaptive control logic is provided, configured to perform a control operation such that when the flag corresponding to a first block has the first value, the operating condition of at least one operation selected from a write operation and a read operation changes from a normal write operation or a normal read operation, the first block being affected by a write or read request (from the host).

[0007] According to another aspect of the present invention, a method for operating a storage device is provided, wherein the storage device controls memory operations of a non-volatile memory device comprising a plurality of blocks. The method includes: performing a secure erase operation on the plurality of blocks in response to a secure erase request from a host; and setting flags corresponding to the plurality of blocks such that the flag corresponding to a block among the plurality of blocks that has been requested to undergo at least two consecutive secure erase operations has a first value. Furthermore, when the flag corresponding to the first block has the first value, a write operation or a read operation is performed on the first block after changing at least one operating condition compared to a normal write operation or read operation.

[0008] According to another aspect of the present invention, a method for operating a storage device is provided, the method comprising controlling memory operations of a non-volatile memory device having a plurality of memory blocks therein. The operation method includes: performing secure erase operations on the plurality of memory blocks in response to a secure erase request from a host, and counting the number of secure erase operations performed on the plurality of memory blocks. Then, a normal write operation or a write operation with modified operating conditions may be performed on a first memory block based on a count value of a first memory block corresponding to a write request from the host, and erase and programming operations may be performed sequentially on the first memory block in response to a write request from the host.

[0009] According to another aspect of the present invention, a method of operating a non-volatile memory device includes: performing a normal write operation on a first memory block within the non-volatile memory device, and then performing a secure erase operation on the first memory block by: (i) performing multiple consecutive erase operations on the first memory block, and (ii) setting a flag associated with the first memory block indicating that the first memory block has undergone a secure erase operation. Thereafter, in response to detecting the set flag associated with the first memory block, a modified write operation is performed on the first memory block using at least one modified write operation condition relative to the normal write operation. The execution of the modified write operation may further include resetting the flag associated with the first memory block, and a normal write operation may then be performed on the first memory block. To improve programming reliability, the at least one modified write operation condition takes into account over-erase conditions caused by secure erase operations within the first memory block. Attached Figure Description

[0010] Embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 This is a block diagram of a storage system according to an embodiment;

[0012] Figure 2 yes Figure 1 A block diagram of an exemplary implementation of the controller in the diagram;

[0013] Figure 3 This is a block diagram of an exemplary implementation of a controller according to an example embodiment;

[0014] Figure 4 This is a block diagram illustrating an embodiment of a non-volatile memory device according to an embodiment;

[0015] Figure 5 According to the embodiments Figure 4 A perspective view of the blocks in the image;

[0016] Figure 6 and Figure 7 This is a flowchart of an operation method of a storage device according to an example embodiment;

[0017] Figure 8 It is a graph showing the distribution of threshold voltages according to each state of the storage device;

[0018] Figure 9A and Figure 9B This is a diagram illustrating an example of determining the degree of degradation of a storage block;

[0019] Figure 10 This is a block diagram of a controller according to an example embodiment;

[0020] Figure 11 , Figure 12A and Figure 12B An adaptive control method is shown in the read operation;

[0021] Figures 13 to 15 An adaptive control method is shown in the read operation;

[0022] Figure 16A and Figure 16B This is a diagram illustrating an example operation of a storage device according to an example embodiment;

[0023] Figure 17 This is a block diagram illustrating an example of applying a storage device to a solid-state drive (SSD) system according to an embodiment. Detailed Implementation

[0024] In the following description, embodiments will be described in detail with reference to the accompanying drawings.

[0025] Figure 1 This is a block diagram of the storage system 10 according to an embodiment. (Refer to...) Figure 1Storage system 10 may include storage device 100 and host 11. Storage device 100 may include controller 110 and non-volatile memory (NVM) device 120. Storage device 100 may communicate with host 11 via various interfaces. For example, host 11 may include application processor (AP) or system-on-chip (SoC). Storage device 100 may communicate with host 11 via various interfaces such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), Fast PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Electronic Integrated Drive (IDE), Firewire, Universal Flash Memory (UFS), and Fast NVM (NVMe).

[0026] NVM device 120 may include NVM (such as NAND flash memory, vertical NAND flash memory, NOR flash memory, resistive random access memory (RAM), phase-change memory, or magnetoresistive RAM); however, other types of non-volatile memory may also be used. Controller 110 may perform control operations in response to requests from host 11, thereby writing data to or reading data from NVM device 120. For example, controller 110 may control data write and read operations on NVM device 120, or erase operations that erase data from NVM device 120.

[0027] NVM device 120 may include a storage cell array. The storage cell array may include multiple storage blocks, such as a first block BLK1 to a z-th block BLKz. Each storage block may include multiple word lines and at least one dummy word line, and the storage cells connected to each word line may form a single page. User data may be stored in the page corresponding to each word line, while legitimate data may not be stored in the page corresponding to the dummy word line.

[0028] Controller 110 can perform control operations on NVM device 120 based on various units. For example, a storage block can be an erase unit, and a page can be a write unit and a read unit. Controller 110 can provide NVM device 120 with commands CMD and addresses ADD to execute various requests from host 11.

[0029] Storage system 10 may include, for example, a personal computer (PC), a data server, network attached storage (NAS), an Internet of Things (IoT) device, or a portable electronic device. Portable electronic devices may include laptops, mobile phones, smartphones, tablet PCs, personal digital assistants (PDAs), enterprise digital assistants (EDAs), digital still cameras, digital video cameras, audio equipment, portable multimedia players (PMPs), personal navigation devices (PNDs), MP3 players, handheld game consoles, e-readers, or wearable devices.

[0030] According to an example embodiment, storage device 100 can receive a secure erase request (Req_SE) for data from host 11. Furthermore, in response to the secure erase request (Req_SE), storage device 100 can support the function of securely erasing user-selected data, making the erased data unrecoverable. Storage device 100 can receive the secure erase request (Req_SE) from host 11 via various types of interfaces. For example, storage device 100 can receive various requests related to secure erase based on the value of the Secure Erase Settings (SES) field defined in the NVMe interface.

[0031] When a secure erase request Req_SE is received from host 11, storage device 100 can perform a series of processing operations to physically erase data selected by the user. According to embodiments, host 11 may include a configuration for selecting data that the user wants to securely erase. For example, a host application capable of generating a secure erase request may be installed on host 11, and the user can run the host application and select the data to be securely erased. The series of processing operations for securely erasing data according to embodiments can be defined by various terms. For ease of description, the series of processing operations may be defined as those included in the secure erase operations in the following embodiments.

[0032] According to an example embodiment, controller 110 may include secure erase control logic 111 and adaptive control logic 112. Each of secure erase control logic 111 and adaptive control logic 112 may be implemented by hardware, software, or a combination thereof. For example, when each of secure erase control logic 111 and adaptive control logic 112 is implemented by software including firmware, controller 110 may include at least one processor (not shown) for executing the software and a memory (not shown) for storing the software, each of secure erase control logic 111 and adaptive control logic 112 may be loaded as software into the memory. According to an embodiment, controller 110 may include a flash translation layer (FTL), and at least a portion of the functionality of each of secure erase control logic 111 and adaptive control logic 112 may be included in the FTL.

[0033] In the example embodiments, the concept of the term "adaptive control" may include various control operations relating to changing the conditions of write and read operations performed on a memory block that has been degraded due to at least two secure erase operations. In the description of the embodiments, the concept of control operations may be defined as various other terms besides "adaptive control".

[0034] The secure erase control logic 111 can output a secure erase control signal Ctrl_SE and control a series of operations to securely erase user-selected data. When a secure erase request Req_SE is received from the host for at least one memory block, the secure erase control logic 111 can control the erase operation on the data stored in the memory block. For example, after performing an erase operation on the memory block, the secure erase control logic 111 can execute control operations that cause a programming operation (e.g., one-shot programming) to be performed to program the memory cells of the memory block to have a specific threshold voltage distribution.

[0035] According to an example embodiment, adaptive control logic 112 can perform control operations to adaptively control memory operations such as write or read operations. For example, adaptive control logic 112 can output an adaptive control signal Ctrl_AD based on the result of determining the secure erase state and / or degradation level of a memory block (for which a write or read operation has been requested) to control the conditions of write or read operations differently. Controller 110 can control secure erase operations and write or read operations on NVM device 120 by providing command CMD, address ADD, secure erase control signal Ctrl_SE, and adaptive control signal Ctrl_AD to NVM device 120 based on the control results of secure erase control logic 111 and adaptive control logic 112.

[0036] Typically, whenever storage device 100 receives a secure erase request Req_SE from host 11, storage device 100 can repeatedly perform physical erase operations on the storage block corresponding to the secure erase request Req_SE. When multiple secure erase operations are performed on a storage block, the threshold voltage distribution of the storage cells in the storage block can gradually change (or shift to the left). This change in the threshold voltage distribution may lead to a decrease in data reliability when subsequent write or read operations are performed on the storage block.

[0037] When describing an embodiment with respect to a first storage block, information indicating whether multiple secure erase operations have been performed on the first storage block (e.g., a flag (not shown)) may be stored in storage device 100. Secure erase control logic 111 may determine whether at least two secure erase operations have been requested or performed consecutively on the first storage block, and set the flag corresponding to the first storage block to the value "1" based on the determination result. It can be determined in various ways whether at least two secure erase operations have been requested. For example, it can be determined that at least two secure erase operations have been requested when two consecutive secure erase requests Req_SE are received for the first storage block. However, the embodiment is not limited to this. Furthermore, even if a secure erase request Req_SE is received a second time after an intermediate request (e.g., a read request) has been received following the first receipt of the secure erase request Req_SE, this does not change the threshold voltage distribution of the first storage block, and the flag corresponding to the first storage block can still be set to the value "1". The number of secure erase operations on which the flag is set to "1" may be set to 2 or various other values ​​greater than 2.

[0038] When a write or read request is received for the first storage block, the secure erase status and / or degradation of the first storage block can be assessed / determined first, and then the requested write or read operation can be adaptively controlled based on the assessment / determination results.

[0039] As described above, when the threshold voltage distribution of a particular memory block degrades in response to multiple secure erase operations on that memory block, the threshold voltage distribution can subsequently be controlled to move to an appropriate position by adaptively adjusting the nature of write operations, and the nature of read operations can be adaptively adjusted to control the reading of data within the corresponding memory block using (one or more) optimal read levels. In an example embodiment, to determine the degradation of a particular (e.g., first) memory block, a flag corresponding to that particular memory block can first be referenced and evaluated. The degree of degradation of the first memory block can be determined by analyzing the threshold voltage distribution of the memory cells of the first memory block. In an example operation, when the flag corresponding to the first memory block is "1", the degree of degradation of the first memory block can be determined based on the threshold voltage distribution of the memory cells of the first memory block, and adaptive write and / or read operations can be performed on the first memory block according to the degree of degradation.

[0040] According to this example embodiment, write and read operations can be adaptively performed based on the results of determining the secure erase state and / or degree of degradation of memory blocks whose characteristics have deteriorated due to successive secure erase operations. Therefore, the threshold voltage distribution can be appropriately positioned through programming operations, and read operations can be performed using (one or more) optimal read levels. As a result, data reliability can be increased, and the occurrence of uncorrectable errors in response to data read operations can be reduced. Therefore, the frequency of operations for data error recovery (e.g., entering recovery codes) can also be reduced, thereby further reducing read latency.

[0041] Figure 2 yes Figure 1 A block diagram illustrating an implementation of the controller 110. (Refer to...) Figure 2 The controller 110 may include secure erase control logic 111, adaptive control logic 112, and flag storage circuitry 113. The secure erase control logic 111 can control the secure erase operation for each memory block as described above, and may include an element (e.g., a counter) that can determine the secure erase count for each memory block during the execution of the secure erase operation. For example, the secure erase control logic 111 can determine the location of a memory block for which a secure erase has been requested, and the counter corresponding to the memory block can perform a counting operation.

[0042] According to the above embodiment, the secure erase control logic 111 can change the flag corresponding to a storage block having a count value of 2 or at least a set value of 2 to a first value (e.g., "1"), and this flag can be stored in the flag storage circuit 113. Conversely, when the storage block has a count value of 1 or less, the flag can remain at a second value (e.g., "0"). In other words, it can be determined based on the flags, which are stored in the flag storage circuit 113 corresponding to the storage block, whether at least two secure erase operations have been performed on the storage block.

[0043] The adaptive control logic 112 may include a flag determiner 112_1, a degradation determiner 112_2, and an adaptive controller 112_3. The flag determiner 112_1 determines a flag value and outputs a signal indicating whether at least two secure erase operations have been performed on the memory block. The degradation determiner 112_2 outputs a signal indicating the degree of degradation (i.e., the level of degradation) of the memory block based on at least one piece of information. For example, the degradation determiner 112_2 may determine the degree of degradation of the memory block based on a count value CNT_OC, which is obtained by counting the number of off-cells in the memory cells of at least one page of the memory block based on a specific read level. Referring to a first memory block, the threshold voltage distribution of the first memory block can be shifted to the left according to the degree of degradation of the first memory block; therefore, the number of off-cells in the memory cells of at least one page can be compared with a specific reference value, and when the number of off-cells is less than the specific reference value, the degree of degradation of the first memory block can be determined to be relatively high.

[0044] The adaptive controller 112_3 can receive a determination result and output an adaptive control signal Ctrl_AD. When a write request is received for a first memory block that has undergone a secure erase operation, an erase operation to offset the threshold voltage distribution of the memory cells of the first memory block to the erase state and a programming operation to offset the threshold voltage distribution to the programming state corresponding to the data to be written can be executed sequentially. When the flag corresponding to the first memory block is 1, the level of at least one selected from the programming voltage and the erase voltage can be adjusted according to the degree of degradation of the first memory block, or at least one selected from the programming time (or programming cycle count) and the erase time (or erase cycle count) can be adjusted. Optionally, during the data write process, the write operation can be performed by controlling the flow of multiple operations including erase and programming operations on the first memory block.

[0045] Assuming no adaptive write operation is used, when a read operation is requested for a first storage block where user data has already been written under normal operating conditions, an adaptive read operation can be performed based on the determination results in the above embodiments. For example, the threshold voltage distribution characteristics of the storage cells in the first storage block may differ when data is written to a storage block with undegraded characteristics compared to when data is written to a first storage block with degraded characteristics. In this case, according to the embodiments, an adaptive read operation can be performed, thereby allowing data to be read using the optimal read level.

[0046] Although Figure 2An embodiment for determining degradation based on the result of counting the shutdown cells is shown, but the embodiment is not limited thereto. The determination can also be performed based on the result of counting the on-cells. As the threshold voltage distribution of the first storage block shifts from the secure erase state to the threshold voltage distribution of the user data during adaptive write processing, the flag corresponding to the first storage block can be reset.

[0047] Figure 3 This is a block diagram illustrating an implementation of the controller according to an example embodiment. (Refer to...) Figure 3 The controller 200 may include a host interface 210, a processor 220, RAM 230, error correction code (ECC) circuitry 240, a buffer 250, and a memory interface 260. RAM 230 can be used as working memory. The processor 220 can generally control the operation of the controller 200 by executing firmware loaded into RAM 230. RAM 230 may include at least one of various types of memory (e.g., cache memory, dynamic RAM (DRAM), static RAM, phase-change RAM (PRAM), and flash memory). The flash memory transfer mode (FTL) can be loaded into RAM 230 as firmware, and various functions related to flash memory operation can be performed by driving the FTL.

[0048] The host interface 210 can communicate with the host via the various interfaces described above. The memory interface 260 can provide a physical connection between the controller 200 and the NVM device. Commands, addresses, data, etc., can be transmitted between the controller 200 and the NVM device via the memory interface 260. Data requested by the host to be written to the NVM device and data read from the NVM device can be temporarily stored in the buffer 250. The ECC circuit 240 can perform ECC encoding and decoding on the data to be written and the data already read, and can detect and correct errors in the data. When performing secure erase control operations and adaptive control operations based on software, the secure erase control module 231 and the adaptive control module 232 can be firmware including at least one program, and can be loaded into RAM 230 and executed by the processor 220.

[0049] Figure 4 This is a block diagram illustrating an implementation of an NVM device according to an embodiment. Figure 4 An embodiment of a flash memory device as an NVM device is shown. (Refer to...) Figure 4The NVM device 300 may include a memory cell array 310, a voltage generator 320, control logic 330, a row decoder 340, and a page buffer 350. The memory cell array 310 may include multiple memory blocks (including first memory blocks BLK1 to z-th memory blocks BLKz). The memory cells of the first memory blocks BLK1 to z-th memory blocks BLKz may be connected to word lines WL, serial select lines SSL, ground select lines GSL, and bit lines BL. The memory cell array 310 may be connected to the row decoder 340 via word lines WL, serial select lines SSL, and ground select lines GSL, and to the page buffer 350 via bit lines BL. Each memory cell may store one or more bits. For example, each memory cell may correspond to a multi-level cell (MLC), a triple-level cell (TLC), or a quad-level cell (QLC).

[0050] Control logic 330 can output various internal control signals for controlling programming, reading, and erasing operations of memory cell array 310 based on commands CMD, addresses ADD, and control signals received from the controller. For example, control logic 330 can output a voltage control signal CTRL_vol to control the levels of various voltages generated by voltage generator 320, and provide row address X-ADD to row decoder 340 and column address Y-ADD to page buffer 350. Voltage generator 320 can generate various voltages used by NVM device 300. For example, voltage generator 320 can generate programming voltage Vpgm for programming operations and erase voltage Vers for erasing operations.

[0051] According to the example embodiment, control logic 330 can receive a secure erase control signal Ctrl_SE and an adaptive control signal Ctrl_AD from the controller, and can perform secure erase operations and adaptive write or read operations on the memory cell array 310 based on the secure erase control signal Ctrl_SE and the adaptive control signal Ctrl_AD. For example, the NVM device 300 can perform normal write / read operations, or perform write / read operations under changed operating conditions according to the adaptive control signal Ctrl_AD.

[0052] Figure 5 According to the embodiments Figure 4 A perspective view of the first storage block BLK1 in the memory. (Refer to...) Figure 5A first memory block BLK1 is vertically formed on a substrate SUB. The substrate SUB has a first conductivity type (e.g., p-type). A common source line CSL extends in the substrate SUB along a second horizontal direction Y and is doped with impurities of a second conductivity type (e.g., n-type). In the region between two adjacent common source lines CSL of the substrate SUB, a plurality of insulating layers IL extend in the second horizontal direction Y and are sequentially disposed in the vertical direction Z. The insulating layers IL are spaced apart from each other by a specific distance in the vertical direction Z. For example, the insulating layers IL may comprise an insulating material such as silicon oxide.

[0053] In the region between two adjacent common source lines CSL of the substrate SUB, a plurality of pillars P pass through the insulating layer IL in the vertical direction Z. The plurality of pillars P are arranged in a first horizontal direction X. For example, the pillars P pass through the insulating layer IL to contact the substrate SUB. Specifically, the surface layer S of each pillar P may include a silicon material of a first conductivity type and may serve as a channel region. The inner layer I of each pillar P may include an insulating material such as silicon oxide or an air gap.

[0054] In the region between two adjacent common source lines CSL, a charge storage layer CS is disposed along the exposed surfaces of the insulating layer IL, pillar P, and substrate SUB. The charge storage layer CS may include a gate insulating layer (or "tunnel insulating layer"), a charge trapping layer, and a barrier insulating layer. For example, the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure. In the region between the two adjacent common source lines CSL, gate electrodes GE, such as the ground select line GSL, the string select line SSL, and the word lines WL1 to WL8, are disposed on the exposed surfaces of the charge storage layer CS.

[0055] Drains or drain contacts DR are respectively disposed on pillars P. For example, the drains or drain contacts DR may comprise silicon material doped with impurities of a second conductivity type. Bit lines BL1 to BL3 extend along a first horizontal direction X on the drains or drain contacts DR and are spaced apart from each other by a specific distance in a second horizontal direction Y.

[0056] Although Figure 5Not shown, but the first memory block BLK1 may include at least one dummy word line. For example, the first memory block BLK1 may also include at least one dummy word line (or upper dummy line) above word lines WL1 to WL8 and at least one dummy word line (or lower dummy line) below word lines WL1 to WL8. When the threshold voltage distribution of memory cells connected to the dummy word lines shifts to the left due to memory cell degradation, the memory cells connected to the dummy word lines may have an excessive turn-on state during data programming, resulting in a relatively large current flow compared to when the memory cell degradation is lower. As a result, the threshold voltage distribution characteristics of the memory cells connected to word lines WL1 to WL8 may deteriorate.

[0057] Figure 6 and Figure 7 This is a flowchart illustrating an operation method of a storage device according to an example embodiment. (Refer to...) Figure 6 The storage device may include a controller and an NVM device, and may receive a secure erase request from the host in operation S11. In operation S12, the storage device may perform a secure erase operation on at least one storage block of the NVM device in response to the secure erase request. In an example embodiment, the storage device may perform a secure erase operation on at least one storage block in response to a request from the host. In operation S13, the storage device may count the number of secure erase operations performed on the storage block corresponding to the secure erase request. In operation S14, the storage device may determine whether the storage block has a count value of N or greater based on the count result. Here, N may be an integer of at least 2. When the storage block has a count value less than N, the flag corresponding to the storage block may be kept at 0 in operation S15. Otherwise, when the storage block has a count value of N or greater, the flag corresponding to the storage block may be changed to 1 in operation S16.

[0058] Reference Figure 7 In operation S21, the storage device can receive a write or read request for the first storage block from the host, and in operation S22, determine whether the flag corresponding to the first storage block is 1. When the flag is determined to be not 1 (or 0), it can indicate that the first storage block is not in a secure erase state or has undergone one secure erase operation or a relatively small number of secure erase operations. In this case, in operation S23, a write or read operation can be performed on the first storage block under normal operating conditions. Otherwise, when the flag corresponding to the first storage block is 1, in operation S24, the degree of degradation of the first storage block can be determined based on the degradation determination method described above. Depending on the degree of degradation, in operation S25, an adaptive write or read operation can be performed on the first storage block under operating conditions different from normal operating conditions.

[0059] Specific example operations according to the embodiments are described below. Figure 8 This is a graph showing the threshold voltage distribution according to each state of the storage device. (See reference...) Figure 8 The storage cells of the storage device correspond to TLC (Transmission Linear Chromatography), therefore, when user data has been effectively stored in the storage cells, the storage cells have eight threshold voltage distributions. According to an embodiment, the secure erase operation includes an erase operation and a single programming operation.

[0060] like Figure 8 As shown in (a), when user data has been effectively stored in the storage unit, the storage unit can have multiple threshold voltage distributions, each with a threshold voltage Vth level that is different from the others. Figure 8 As shown in (b), when a memory cell is in an erase state, the memory cell can have a single threshold voltage distribution corresponding to the erase state. However, as Figure 8 As shown in (c), when a storage cell is in a secure erase state, erase operations and single-program operations are performed sequentially on the storage cell. Therefore, the storage cell can have a single threshold voltage distribution with a threshold voltage level higher than the threshold voltage level in the erase state. When a data write request is made for a storage block that has undergone a secure erase operation including a single-program operation, an erase operation can be performed on the storage block. Subsequently, a programming operation can be performed on the storage block to form a threshold voltage distribution corresponding to the actual user data.

[0061] Figure 9A and Figure 9B This is a diagram illustrating an example of determining the degree of degradation of a storage block. Figure 9A and Figure 9B An example of the threshold voltage distribution of a memory cell connected to a dummy word line of a memory block is shown. (Refer to...) Figure 9A During a secure erase operation, no erase or programming operations are performed on the memory cells connected to the dummy word line. Therefore, the memory cells connected to the dummy word line can initially have a single threshold voltage distribution. However, when a secure erase operation is repeatedly performed on the memory block, interference may occur in the memory cells connected to the dummy word line. Therefore, the threshold voltage distribution of the memory cells connected to the dummy word line may shift to the left in response to the secure erase operation. For example, as the number of secure erase operations performed on the memory block increases to N (where N is an integer of 2 or greater), the amount of shift in the threshold voltage distribution of the memory cells connected to the dummy word line can increase.

[0062] Figure 9B An example is shown that determines the degree of block degradation based on the threshold voltage distribution of memory cells connected to dummy word lines. Figure 9BIn the example, during a read operation on a memory cell connected to a dummy word line, the read level is changed based on the default read level, and the number of cells turned off due to the read operation is counted. For example... Figure 9B As shown, as the number of secure erase operations performed on the memory block increases, the threshold voltage distribution of the memory cells connected to the dummy word line can shift to the left, and the number of shutdown cells can be counted differently based on a specific read level, depending on the degree of degradation of the memory cells connected to the dummy word line. For example, the degree of degradation of the memory block can be determined by determining a changed read level, which gives at least a specific value (e.g., 100) as the shutdown cell difference between the number of shutdown cells based on the default read level and the number of shutdown cells based on the changed read level.

[0063] Figure 9B The value of the read level can correspond to an offset related to the default read level. When no secure erase operation is performed on the memory block, the threshold voltage distribution of the memory cells connected to the dummy word line is located at... Figure 9B The rightmost example. In the process of performing a read operation while changing the read level, when performing a read operation using a read level 0.1V higher than the default read level, the shutdown cell difference can be determined to be 100 or greater. When degradation occurs due to a secure erase operation performed on the memory block, the read level that gives a shutdown cell difference of at least 100 can be gradually reduced. If a secure erase operation has already been performed on the memory block, when performing a read operation on the memory block using a read level 0.3V lower than the default read level, the shutdown cell difference can be at least 100.

[0064] Similarly, when two secure erase operations have been performed on the memory block, the shutdown cell difference can be at least 100 when a read operation is performed on the memory block using a read level 0.5V lower than the default read level. When three secure erase operations have been performed on the memory block, the shutdown cell difference can be at least 100 when a read operation is performed on the memory block using a read level 0.7V lower than the default read level. When four secure erase operations have been performed on the memory block, the shutdown cell difference can be at least 100 when a read operation is performed on the memory block using a read level 0.8V lower than the default read level.

[0065] The degradation level of the memory cell connected to the dummy word line can be determined based on the read level determined using the method described above. When the degradation level of the memory cell connected to the dummy word line is high, it can be determined that the degradation level of the memory block including the memory cell is high. Based on the determination result, adaptive write or read operations can be performed according to the above embodiments.

[0066] Although Figure 9A and Figure 9B The figure shows a value for one scenario, but the embodiment is not limited to this. Various methods based on other, diverse values ​​can be used to determine the degree of degradation of the memory block. For example, without changing the read level, a specific read level or a small number of read levels can be used to count the shutdown cells, and the degree of degradation can be determined based on the count value. Although Figure 9A and Figure 9B The example shown is counting the off cells in memory cells connected to dummy word lines, but it is also possible to count the on cells in memory cells connected to dummy word lines, or to count the off cells (or on cells) in memory cells connected to normal word lines.

[0067] Figure 10 This is a block diagram of a controller according to an example embodiment. Figure 10 An example is shown of performing the various determinations described above based on the counting operation without setting a flag. Figure 10 The various components can be implemented through hardware, software, or a combination thereof, and at least some of these components can be implemented through processor-executable firmware. (See reference...) Figure 10 The storage device or its controller 400 may include a secure erase counter 410 and adaptive control logic 420. Although in Figure 10 It is not shown in the diagram, but the controller 400 may also include the aforementioned secure erase control logic.

[0068] The secure erase counter 410 can output a count value CNT[1:Z] to the adaptive control logic 420 based on counting operations. The count value CNT[1:Z] indicates the number of secure erase operations performed on each of a plurality of memory blocks (e.g., z blocks). For example, the secure erase counter 410 can receive secure erase information Info_SE and block address ADD_B, and count the number of secure erase operations on the memory block corresponding to block address ADD_B.

[0069] The adaptive control logic 420 can output an adaptive control signal Ctrl_AD for the aforementioned adaptive control operation based on the count value CNT[1:Z]. For example, the adaptive control logic 420 may include an erase state determiner 421, a degradation determiner 422, and an adaptive controller 423. The erase state determiner 421 can determine whether to use adaptive control during subsequent data write or read operations based on the count value CNT[1:Z]. For example, when the count value CNT[1:Z] of the memory block is at least N (where N is an integer of at least 2), the erase state determiner 421 can output a signal indicating the use of adaptive control. The degradation determiner 422 can output a signal determining the degree of degradation of the memory block based on the count value CNT[1:Z]. For example, when the count value CNT[1:Z] increases, it can be determined that the degree of degradation of the memory block increases.

[0070] The adaptive controller 423 can change the conditions for write or read operations on the memory block by outputting an adaptive control signal Ctrl_AD based on signals from the erase state determiner 421 and the degradation determiner 422. In an embodiment, the adaptive controller 423 may include a table (which stores information about the conditions for at least one operation selected from write and read operations) and output the adaptive control signal Ctrl_AD based on the information stored in the table.

[0071] According to an embodiment, an example of applying adaptive control to write and read operations is described below. Figure 11 , Figure 12A and Figure 12B An adaptive control method is shown in the read operation. (Refer to...) Figure 11 In operation S31, the storage device can receive a read request or read command for a page of one of the multiple storage blocks (e.g., the Nth storage block), and in operation S32, determine whether the flag corresponding to the Nth storage block is 1. When the flag corresponding to the Nth storage block is not 1, in operation S33, a read operation can be performed on the page of the Nth storage block under normal operating conditions.

[0072] Otherwise, when the flag corresponding to the Nth memory block is 1, various methods can be used to determine the degree of degradation of the Nth memory block in operation S34. For example, the degree of degradation of the Nth memory block can be determined based on the results of analyzing the threshold voltage distribution of the Nth memory block. The storage device can read information about read conditions from a predefined table (PDT) storing various types of information about adaptive control, and perform a read operation on the page based on the information read from the PDT in operation S35. Read operations on the page can be performed based on different read levels according to the degree of degradation.

[0073] Figure 12AAn example of information stored in the PDT is shown. Figure 12B An example of adaptive readout level for each state of a multi-level cell (e.g., TLC) is shown. (Refer to...) Figure 12A The read level for each state under normal operating conditions is defined as the default read level, and the value of the adaptive read level indicates the offset from the default read level.

[0074] According to the above embodiment, when the flag corresponding to the Nth memory block is 1, each of the states P0 to P6 can be determined based on the adaptive read level information stored in the PDT. For example, the state P0 of the leftmost threshold voltage distribution can be determined by using a read operation with a read level 200mV higher than the default read level. The state P1 of the second threshold voltage distribution can be determined by using a read operation with a read level 100mV higher than the default read level. In the case of the state P6 of the seventh threshold voltage distribution, the offset of the seventh threshold voltage distribution is substantially small, therefore, the seventh threshold voltage distribution can be determined by using a read operation with the default read level.

[0075] Figures 13 to 15 This illustrates an adaptive control method used in programming operations. (Refer to...) Figure 13 In operation S41, the storage device can receive a write request (or write command) for a page of one of the multiple storage blocks (e.g., the Nth storage block), and in operation S42, determine whether the flag corresponding to the Nth storage block is 1. When the flag corresponding to the Nth storage block is not 1, in operation S43, a programming operation can be performed on the page of the Nth storage block under normal operating conditions.

[0076] Otherwise, when the flag corresponding to the Nth memory block is 1, in operation S44, the degree of degradation of the Nth memory block can be determined using various methods as described above. The storage device can perform a programming operation on the page using write operation-related information stored in the PDT in operation S45. For example, the write operation may include an erase operation and a programming operation on the Nth memory block, and adaptive control can be applied to at least one operation selected from the erase and programming operations. For example, at least one condition selected from the erase voltage, programming voltage, erase time (or erase cycle count), and programming time (or programming cycle count) can be changed, and the write operation can be performed based on the selected condition according to the degree of degradation.

[0077] Figure 14 An example of table information related to a write operation is shown according to an example embodiment. Figure 14 An example of the number of safe erase operations is shown as a reference for indicating the degree of degradation. Figure 14The values ​​in the table can correspond to the offsets of the erase voltage, programming voltage, erase time, and programming time from the normal safe erase operation.

[0078] Reference Figure 14 In the case of a memory block that has already undergone consecutive secure erase operations, the threshold voltage distribution of the memory block tends to shift to the left. Therefore, operating conditions can be set so that the threshold voltage distribution of the memory block is located further to the right during adaptive write operations than during normal write operations. For example, when the corresponding values ​​of erase voltage Vers, erase time, programming voltage Vpgm, and programming time for a normal secure erase operation are defined as default values, the offset can be set differently depending on the degree of degradation of the memory block due to the secure erase operation. For example, when no secure erase operation is performed on the first memory block, a secure erase operation can be performed based on the erase voltage Vers, erase time, programming voltage Vpgm, and programming time corresponding to the default values, respectively.

[0079] However, as the degradation of the memory blocks requested for writing increases, the level of the erase voltage Vers can be reduced from the default value. Figure 14 Examples are shown where the erase voltage Vers level is reduced by 100mV or 200mV from its default value. As the erase voltage Vers level decreases, the amount by which the threshold voltage distribution of the memory cell shifts to the left due to the erase operation can be reduced. Additionally, as memory block degradation increases, the erase time (or erase cycle count) can be reduced. As the erase time or erase cycle count decreases, the amount by which the threshold voltage distribution of the memory cell shifts to the left due to the erase operation can be reduced.

[0080] Furthermore, as the memory block deteriorates, the programming voltage Vpgm level can be increased from the default value. Figure 14 Examples are shown where the programming voltage Vpgm level is increased by 50mV or 100mV from its default value. As the programming voltage Vpgm level increases, the amount by which the threshold voltage distribution of the memory cell shifts to the right due to programming operations can increase. Additionally, as memory block degradation increases, the programming time (or programming cycle count) can increase. As the programming time or programming cycle count increases, the amount by which the threshold voltage distribution of the memory cell shifts to the right due to programming operations can also increase.

[0081] Figure 15 An example of the operational flow controlling write operations during adaptive write processing is shown. (Refer to...) Figure 15In operation S51, the storage device can receive a write request (or write command) for a page of one of the multiple storage blocks (e.g., the Nth storage block), and in operation S52, determine whether the flag corresponding to the Nth storage block is 1. When the flag corresponding to the Nth storage block is not 1, in operation S53, a programming operation can be performed on the page of the Nth storage block under normal operating conditions. Otherwise, when the flag corresponding to the Nth storage block is 1, in operation S54, the degree of degradation of the Nth storage block can be determined using various methods as described above.

[0082] Depending on the degree of degradation of the Nth memory block, various operations can be sequentially performed in the adaptive write process. When an erase operation is performed on the Nth memory block in operation S55, the memory cells of the Nth memory block may have a threshold voltage distribution corresponding to the erase state. Subsequently, a programming operation (e.g., a dummy programming operation) can be performed in operation S56, such that the memory cells connected to at least some word lines of the Nth memory block are programmed to a specific threshold voltage distribution, or a dummy programming operation can be performed only on specific word lines (e.g., dummy word lines) among the word lines of the Nth memory block in operation S56. For example, the dummy programming operation on the Nth memory block may include a programming operation for shifting the threshold voltage distribution of the memory cells of the Nth memory block to a distribution corresponding to the state before degradation occurs. Optionally, the dummy programming operation on the dummy word line may include a programming operation for increasing the threshold voltage level of the memory cells connected to the dummy word line to the distribution before degradation occurs.

[0083] After completing the above-described dummy programming operation, the erase operation and data programming operation can be sequentially performed in operations S57 and S58 to store the valid user data in the Nth storage block. According to the example embodiment, the erase operation on the Nth storage block in operation S55 may not be included in the adaptive write process.

[0084] Figure 16A and Figure 16B This is a diagram illustrating an example operation of a storage device according to an example embodiment. Figure 16A and Figure 16B An example of using flags in background operations of a storage device is shown. The storage device can perform background operations related to improving data reliability during periods when user data is neither written to nor read from. Examples of background operations may include garbage collection, bad block management, read reclamation, and read replacement. In this case, background operations include actions to increase the reliability of degraded data. Therefore, an example is described where background operations are first performed on storage blocks with a relatively high probability of degradation based on the flag value of the storage block.

[0085] The controller of the storage device can determine in operation S61 whether to start background operations on the first to Nth storage blocks. When starting background operations on the first to Nth storage blocks, the controller can determine the flags corresponding to the first to Nth storage blocks respectively in operation S62, and set the background operation order of the first to Nth storage blocks based on the result of determining the flags. For example, in operation S63, it can be determined whether the flag corresponding to the Nth storage block is 1. For example, when the flag of the Nth storage block is not 1, in operation S64, the position of the Nth storage block in the background operation order can be moved down. Otherwise, when the flag of the Nth storage block is 1, in operation S65, the position of the Nth storage block in the background operation order can be moved up.

[0086] In operation S66, multiple pieces of information regarding the background operation order of moving the first to Nth storage blocks downwards and upwards according to the flags of the first to Nth storage blocks can be merged together, thus determining the background operation order of the first to Nth storage blocks. In operation S67, background operations can be performed on the first to Nth storage blocks according to the background operation order. Figure 16B The illustration shows a case in which background operations are performed sequentially on the first storage block BLK1 to the fourth storage block BLK4 according to an example embodiment, and a case in which the order of background operations is changed to the order of the first storage block BLK1, the fourth storage block BLK4, the second storage block BLK2, and the third storage block BLK3 based on flag information.

[0087] Figure 17 This is a block diagram illustrating an example of applying a storage device to a solid-state drive (SSD) system according to an embodiment. (Refer to...) Figure 17 The SSD system 500 may include a host 510 and an SSD 520. The SSD 520 can exchange signals SIG with the host 510 via a signal connector and can receive power PWR via a power connector. The SSD 520 may include an SSD controller 521, an auxiliary power supply 522, and NVM devices 523_1 to 523_n. The NVM devices 523_1 to 523_n may include NAND flash memory. Data can be exchanged between the SSD controller 521 and the NVM devices 523_1 to 523_n via channels Ch1 to Chn. At this time, the above reference can be used... Figures 1 to 1The embodiments described in 6 implement the SSD 520. In other words, according to the above embodiments, the SSD controller 521 of the SSD 520 may include secure erase control logic 521_1 and adaptive control logic 521_2. Secure erase control logic 521_1 may control secure erase operations on NVM devices 523_1 to 523_n in response to a secure erase request from host 510, and adaptive control logic 521_2 may adaptively control write and read operations based on the degradation of storage blocks. According to the above embodiments, adaptive control logic 521_2 may include a table (which stores various information related to adaptive control of data writing and reading), and control operations are performed based on the information stored in the table.

[0088] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A storage device, comprising: A controller configured to control a non-volatile memory device having multiple memory blocks therein, the controller comprising: A secure erase control logic, configured to: (i) control secure erase operations on the plurality of storage blocks in response to a secure erase request received from the host; and (ii) set a flag corresponding to the plurality of storage blocks such that a first flag corresponding to a first storage block that has undergone at least two secure erase operations has a first value; and An adaptive control logic is configured to: in response to detecting that the first flag has the first value, change at least one operating condition associated with a write operation and / or a read operation for the first storage block.

2. The storage device according to claim 1, wherein, The controller also includes a flag storage circuit for storing the flag set by the secure erase control logic.

3. The storage device according to claim 1, wherein, The secure erase control logic is further configured to: when at least two consecutive secure erase operations have been performed on the first storage block, set the first flag corresponding to the first storage block to the first value.

4. The storage device according to claim 1, wherein, The secure erase control logic is further configured to reset the first flag in response to performing a write operation on the first storage block using at least one changed operating condition.

5. The storage device according to claim 1, wherein, The adaptive control logic includes: A flag determiner, configured to determine flags for the plurality of storage blocks; and A degradation determiner is configured to determine the degree of degradation of each of the plurality of memory blocks based on the threshold voltage distribution of the memory cells in each of the plurality of memory blocks. The adaptive control logic is further configured to: vary the at least one operating condition associated with write and / or read operations on the first storage block according to the degree of degradation associated with the first storage block.

6. The storage device according to claim 5, wherein, The first memory block includes at least one dummy word line and multiple normal word lines; wherein the degree of degradation of the first memory block is determined based on the amount of leftward offset of the threshold voltage distribution of the memory cells connected to the at least one dummy word line of the first memory block.

7. The storage device according to claim 1, wherein, The adaptive control logic includes a table configured to store at least one piece of information related to the at least one operating condition; wherein, when the first flag corresponding to the first storage block has the first value, the read level used to determine the data state during the read operation is changed based on the at least one piece of information stored in the table.

8. The storage device according to claim 1, wherein, The adaptive control logic includes a table storing at least one piece of information related to the at least one operating condition; wherein the write operation includes an erase operation on a storage cell of the first storage block and a programming operation on a storage cell of at least one page of the first storage block after the erase operation; wherein, when the first flag corresponding to the first storage block has the first value, at least one of the erase voltage and the programming voltage is changed during the write operation based on the information stored in the table.

9. The storage device according to claim 8, wherein, When the first flag corresponding to the first storage block has the first value, the magnitude of the erase voltage decreases and / or the magnitude of the programming voltage increases compared to a normal write operation.

10. The storage device according to claim 1, wherein, The at least one operating condition corresponds to a plurality of sequential operations performed in response to a write request; wherein, when the first flag corresponding to the first storage block has the first value, a dummy programming operation on at least one page of the first storage block, an erase operation on the first storage block, and a programming operation on one or more pages of the first storage block that are requested to be written are sequentially performed in response to the write request.

11. A method of operating a storage device, the storage device controlling memory operation of a non-volatile memory device comprising a plurality of blocks, the method comprising: In response to a secure erase request received from the host, a secure erase operation is performed on the plurality of blocks; Set flags corresponding to the plurality of blocks, such that the flag corresponding to the first block among the plurality of blocks that has been requested to undergo at least two consecutive secure erase operations has a first value; and When the flag corresponding to the first block has the first value, a write operation and / or a read operation are performed on the first block after changing at least one operating condition compared to a normal write operation or read operation.

12. The operating method according to claim 11, further comprising: The flag corresponding to the first block is read from the flag storage circuit; wherein the storage device includes the flag storage circuit, which is configured to store flags corresponding to the plurality of blocks respectively.

13. The operating method according to claim 11, further comprising: After performing the write operation on the first block based on the changed operating conditions, the flag corresponding to the first block is reset to the second value.

14. The operating method according to claim 11, further comprising: When the flag corresponding to the first block has the first value, the degree of degradation of the first block is determined based on the threshold voltage distribution of the memory cells connected to the dummy word lines of the first block. The at least one operating condition for the first block is changed differently depending on the degree of degradation.

15. The operating method according to claim 11, wherein, The write operation on the first block includes: an erase operation on the storage cells of the first block and a programming operation on the storage cells of at least one page of the first block after the erase operation; wherein, when the flag corresponding to the first block has the first value, the magnitude of the erase voltage is reduced in the erase operation or the magnitude of the programming voltage is increased in the programming operation compared to the normal write operation.

16. The operating method according to claim 11, wherein, When the flag corresponding to the first block has the first value, the read voltage used to determine the data status during the read operation on the first block is changed.

17. The operating method according to claim 16, wherein, Each storage unit in the plurality of blocks includes a multi-level unit that stores at least two bits of data; wherein, compared to the normal read operation, the read voltage used to distinguish between erase and program states in the read operation on the first block is increased.

18. A method of operating a non-volatile memory device, comprising: Perform a normal write operation on the first memory block within the non-volatile memory device; A secure erase operation is performed on the first storage block by performing multiple consecutive erase operations on the first storage block and setting a flag associated with the first storage block, the flag indicating that the first storage block has undergone the secure erase operation; as well as In response to detecting a flag set and associated with the first storage block, a modified write operation is performed on the first storage block using at least one modified write operation condition relative to the normal write operation.

19. The method according to claim 18, wherein, The modified write operation includes resetting the flag associated with the first storage block; wherein, after the modified write operation, a normal write operation is performed on the first storage block.

20. The method according to claim 18, wherein, The at least one modified write operation condition takes into account over-erasure within the first storage block caused by the secure erase operation.

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