Methods, apparatus, and computer equipment for improving NAND flash memory read efficiency

Abstract

This application relates to a method, apparatus, computer device, and storage medium for improving the reread efficiency of NAND flash memory. The method includes: power-on initialization to construct multiple reread tables and reserving spare reread tables for updating; a controller providing multiple base address and restore address registers, writing the addresses of the constructed reread tables into the corresponding base address and restore address registers respectively; when a read error occurs and a reread is required, automatic rereading is performed by selecting the corresponding reread table in the auto retry descriptor; if the reread bias needs to be adjusted during the reread process, the addresses are updated using the spare reread tables and the addresses are replaced in the corresponding base address and restore address registers. This invention can optimize the set feature time and improve the flexibility of software applications.

Description

Technical Field

[0001] This invention relates to the field of solid-state drive technology, and in particular to a method, apparatus, computer device, and storage medium for improving the read efficiency of NAND flash memory. Background Technology

[0002] Currently, the vast majority of storage devices use NAND Flash as the storage medium. Due to some characteristics of the physical structure of NAND Flash and external environmental factors, NAND Flash data is prone to errors during the reading process, especially TLC and QLC chips, whose data stability is highly dependent on read retry.

[0003] Existing automatic read retry mechanisms maintain two fixed tables. Taking TLC particle size applications as an example, these tables are configured as one SLC table and one TLC table. The TLC table covers offset values ​​for seven read levels. When a read retry is needed, the controller needs to send multiple set feature commands, and even more for QLC particle size applications. However, in actual read operations, usually only a single subpage fails. Retrying doesn't require setting offsets for all read levels, and the controller has limited addressing space for the retry table. Multiple commands consume extra space, thus impacting the efficiency of the reread process. Summary of the Invention

[0004] Therefore, it is necessary to provide a method, apparatus, computer device, and storage medium for improving the read efficiency of NAND flash memory in response to the above-mentioned technical problems.

[0005] A method for improving the read reload efficiency of NAND flash memory, the method comprising:

[0006] Upon power-on initialization, multiple reread tables are constructed, and a backup reread table is reserved for updating.

[0007] The controller provides multiple base address and restore address registers, and writes the constructed reread table addresses into the corresponding base address and restore address registers respectively;

[0008] When an error occurs during reading and a reread is required, automatic rereading can be performed by selecting the corresponding reread table in the auto retry descriptor.

[0009] If the reread bias needs to be adjusted during the reread process, the address is updated using the backup reread table and the address is replaced in the corresponding base address and restore address registers.

[0010] In one embodiment, the step of constructing multiple reread tables during power-on initialization and reserving backup reread tables for updating further includes:

[0011] When constructing the reread table, the corresponding threshold voltage is selected based on the subpage to set the feature.

[0012] In one embodiment, the method further includes:

[0013] The software dynamically constructs and switches reread tables based on particle characteristics and updates them to the corresponding registers.

[0014] In one embodiment, the step of constructing multiple reread tables during power-on initialization and reserving backup reread tables for updating further includes:

[0015] The multiple reread tables include reread tables corresponding to SLC, Low page, Mid page and Upper page respectively, and a spare reread table is reserved for updating.

[0016] An apparatus for improving the read efficiency of NAND flash memory, the apparatus comprising:

[0017] A table construction module is used to construct multiple reread tables upon power-on initialization and reserve backup reread tables for updating.

[0018] The address writing module is used by the controller to provide multiple base address and restore address registers, and write the constructed multiple reread table addresses into the corresponding base address and restore address registers respectively;

[0019] The automatic reread module automatically rereads when an error occurs and a reread is required by selecting the corresponding reread table in the autoretry descriptor.

[0020] The update module is used to update the address using the spare reread table and replace the address in the corresponding base address and restore address registers if the reread bias needs to be adjusted during the reread process.

[0021] In one embodiment, the table construction module is further configured to:

[0022] When constructing the reread table, the corresponding threshold voltage is selected based on the subpage to set the feature.

[0023] In one embodiment, the device further includes:

[0024] The dynamic switching module is used to dynamically construct and switch the reread table according to the particle characteristics through software, and update it to the corresponding register.

[0025] In one embodiment, in the table construction module:

[0026] The multiple reread tables include reread tables corresponding to SLC, Low page, Mid page and Upper page respectively, and a spare reread table is reserved for updating.

[0027] A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of any of the methods described above.

[0028] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of any of the above methods.

[0029] In the aforementioned methods, apparatuses, computer devices, and storage media for improving NAND flash memory reread efficiency, the number of reread tables increases as needed during reread table construction. The controller provides multiple base addresses and restore addresses, and the appropriate table is selected based on actual needs, thus optimizing feature set time. Furthermore, a table is reserved during use to update the feature address or reread bias. When an update is required, the table is constructed, and the address is replaced in the register, improving the flexibility of software applications. Attached Figure Description

[0030] Figure 1 This is a flowchart illustrating a method for improving NAND flash memory reread efficiency in one embodiment;

[0031] Figure 2 This is a flowchart illustrating a method for improving NAND flash memory reread efficiency in another embodiment;

[0032] Figure 3 This is a schematic diagram illustrating the construction of a reread linked list in one embodiment;

[0033] Figure 4 This is a structural block diagram of an implementation device for improving NAND flash memory reread efficiency in one embodiment;

[0034] Figure 5 This is a structural block diagram of an apparatus for improving NAND flash memory reread efficiency in another embodiment;

[0035] Figure 6 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0037] Currently, existing automatic read retry mechanisms maintain two fixed tables. Taking TLC particle size applications as an example, these two tables are configured as one SLC table and one TLC table. The TLC table covers offset values ​​for seven read levels. When a read retry is needed, the controller needs to send multiple set feature commands, and even more for QLC particle size applications. However, in actual read operations, usually only a single subpage fails. Retrying does not require setting offsets for all read levels, and the controller's addressing space for the retry table is limited. Multiple commands consume extra space, thus affecting the efficiency of the reread process.

[0038] Based on this, the present invention proposes a method to improve the reread efficiency of NAND flash memory, which aims to optimize the read retry set feature time and improve reread efficiency.

[0039] In one embodiment, such as Figure 1 As shown, a method for improving the read efficiency of NAND flash memory is provided, the method including:

[0040] Step 102: Power-on initialization constructs multiple reread tables and reserves backup reread tables for updating;

[0041] Step 104: The controller provides multiple base address and restore address registers, and writes the constructed multiple reread table addresses into the corresponding base address and restore address registers respectively;

[0042] Step 106: When an error occurs during reading and a reread is required, automatic rereading is performed by selecting the corresponding reread table in the auto retry descriptor.

[0043] Step 108: If the reread bias needs to be adjusted during the reread process, the address is updated using the spare reread table and the address is replaced in the corresponding base address and restore address registers.

[0044] In this embodiment, a method for improving the reread efficiency of NAND flash memory is provided. In this method, the hardware provides multiple sets of retry table base address & restore address registers and provides selection information in the automatic read retry descriptor. When the software application selects the corresponding table, automatic reread can be performed.

[0045] Specifically, firstly, upon power-on initialization, multiple reread tables are constructed, and a backup reread table is reserved for updating. (See reference...) Figure 3 The diagram shown illustrates the reread linked list; the specific number of tables can be increased as needed. The controller provides multiple base addresses and restore addresses, and the appropriate table can be selected as required.

[0046] In one embodiment, the step of constructing multiple reread tables during power-on initialization and reserving backup reread tables for updating further includes: when constructing the reread tables, selecting the corresponding threshold voltage for feature setting based on the subpage.

[0047] Taking TLC as an example, one retry desc contains the number of commands corresponding to one subpage; the maximum number of commands that can set the threshold voltage is three. This reduces the space occupied by commands by nearly half compared to the original, and the actual time to set feature busy can be reduced by more than half.

[0048] In one embodiment, a method for improving the reread efficiency of NAND flash memory is provided, the method further comprising: dynamically constructing and switching the reread table according to the characteristics of the flash memory using software, and updating it to the corresponding register.

[0049] During use, the software reserves a table for updating feature addresses or read retry bias voltages. When an update is needed, the table is reconstructed and the addresses are replaced in the registers accordingly, which effectively improves the software's flexibility and adaptability.

[0050] In the above embodiments, the number of reread tables increases as needed when constructing the reread tables. The controller provides multiple base addresses and restore addresses, and the appropriate table is selected according to actual needs, which can optimize the setfeature time. In addition, a table is reserved during use to update the feature address or reread bias. When an update is needed, the table is constructed and the address is replaced in the register, which improves the flexibility of the software application.

[0051] In one embodiment, such as Figure 2 As shown, a method for improving the read efficiency of NAND flash memory is provided, the method including:

[0052] Step 202: Power-on initialization constructs multiple reread tables, including reread tables corresponding to SLC, Lowpage, Midpage and Upperpage respectively, and reserves a spare reread table for updating.

[0053] Step 204: Fill the constructed table address into the controller's base address and restore address registers respectively;

[0054] Step 206: When a read error occurs and a read retry is required, select the corresponding retry table in the auto retry descriptor to perform an auto retry.

[0055] Step 208: If the read retry bias needs to be adjusted during the process, reformat the spare table and replace the address in the corresponding base address & restore address register.

[0056] For specific details, please refer to Figure 3 The diagram shown illustrates the construction of the reread list. In this embodiment, TLC particles are used as an example. The complete implementation process is as follows:

[0057] Step 1: Power-on initialization, construct 4 read retry tables, which are the read retry tables corresponding to SLC (Single Level Cell), Low page, Mid page, and Upper page, and reserve one for backup update.

[0058] Step 2: Fill the table address constructed in Step 1 into the controller's base address and restore address registers respectively.

[0059] Step 3: When a read error occurs and a read retry is required, select the corresponding retrytable in the auto retry descriptor to perform an auto retry.

[0060] Step 4: If it is necessary to adjust the read retry bias during use, reformat the spare table and replace the address in the corresponding base address & restore address register.

[0061] In this embodiment, the time for the read retry set feature can be reduced, thereby improving reread efficiency. In addition, the flexibility of the software application can be improved.

[0062] It should be understood that, although Figure 1-3 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1-3 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0063] In one embodiment, such as Figure 4 As shown, an apparatus 400 for improving NAND flash memory reread efficiency is provided, the apparatus comprising:

[0064] The table construction module 401 is used to construct multiple reread tables upon power-on initialization and reserve backup reread tables for updating.

[0065] Address writing module 402, the address writing module is used by the controller to provide multiple base address and restore address registers, and write the constructed multiple reread table addresses into the corresponding base address and restore address registers respectively;

[0066] Automatic rereading module 403: When an error occurs during reading and rereading is required, the automatic rereading module automatically rereads by selecting the corresponding rereading table in the autoretry descriptor.

[0067] The update module 404 is used to update the address using the spare reread table and replace the address in the corresponding base address and restore address registers if the reread bias needs to be adjusted during the reread process.

[0068] In one embodiment, the table construction module 401 is further configured to:

[0069] When constructing the reread table, the corresponding threshold voltage is selected based on the subpage to set the feature.

[0070] In one embodiment, such as Figure 5 As shown, an apparatus 400 for improving NAND flash memory reread efficiency is provided, the apparatus further comprising:

[0071] The dynamic switching module 405 is used to dynamically construct and switch the reread table according to the particle characteristics through software, and update it to the corresponding register.

[0072] In one embodiment, in table construction module 401:

[0073] The multiple reread tables include reread tables corresponding to SLC, Low page, Mid page and Upper page respectively, and a spare reread table is reserved for updating.

[0074] For specific limitations on the implementation device for improving NAND flash memory reread efficiency, please refer to the limitations on the implementation method for improving NAND flash memory reread efficiency mentioned above, which will not be repeated here.

[0075] In one embodiment, a computer device is provided, the internal structure of which can be shown as follows: Figure 6 As shown, the computer device includes a processor, memory, and a network interface connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and databases. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The network interface is used for communication with external terminals via a network connection. When the computer program is executed by the processor, it implements a method to improve the read efficiency of NAND flash memory.

[0076] Those skilled in the art will understand that Figure 6The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0077] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps in the various method embodiments described above.

[0078] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps in the various method embodiments described above.

[0079] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM), etc.

[0080] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0081] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. An implementation method for improving the efficiency of NAND flash read retry, the method comprising: initializing a plurality of read retry tables and reserving a spare read retry table for updating upon power-up; selecting corresponding threshold voltages for set feature according to subpage when constructing read retry tables; the plurality of read retry tables include read retry tables corresponding to SLC, Low page, Mid page and Upper page respectively, and a spare read retry table is reserved for updating; providing a plurality of base address and restore address registers by a controller, and writing addresses of the plurality of constructed read retry tables into corresponding base address and restore address registers; when read error occurs and read retry is needed, selecting corresponding read retry tables in auto retry descriptor for automatic read retry; if read retry bias needs to be adjusted during read retry, updating addresses of the spare read retry table and replacing the addresses into corresponding base address and restore address registers; dynamically constructing and switching read retry tables according to particle characteristics by software, and updating the read retry tables into corresponding registers.

2. An implementation device for improving the read efficiency of NAND flash memory, characterized in that, The implementation device for improving the efficiency of NAND flash read retry comprises: a table construction module, configured to initialize a plurality of read retry tables and reserve a spare read retry table for updating upon power-up; select corresponding threshold voltages for set feature according to subpage when constructing read retry tables; the plurality of read retry tables include read retry tables corresponding to SLC, Low page, Mid page and Upper page respectively, and a spare read retry table is reserved for updating; an address writing module, configured to provide a plurality of base address and restore address registers by a controller, and write addresses of the plurality of constructed read retry tables into corresponding base address and restore address registers; an automatic read retry module, configured to select corresponding read retry tables in auto retry descriptor for automatic read retry when read error occurs and read retry is needed; an updating module, configured to update addresses of the spare read retry table and replace the addresses into corresponding base address and restore address registers if read retry bias needs to be adjusted during read retry; a dynamic switching module, configured to dynamically construct and switch read retry tables according to particle characteristics by software, and update the read retry tables into corresponding registers.

3. A computer device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor executes the computer program to implement the steps of the method of claim 1.

4. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the method of claim 1.

Images