Storage system, method of operating the same, memory controller and memory

Abstract

This disclosure provides a storage system and its operating method, a memory controller, and a memory. The storage system includes a memory, which comprises a memory cell array and peripheral circuitry coupled to the memory cell array. The memory cell array includes memory cells capable of storing m bits of information, where m is a positive integer greater than 1. The operating method includes: the peripheral circuitry determining the (n+1)th logical page data based on a received prefix command and n groups of received logical page data; where n is a positive integer and n+1 is a positive integer less than or equal to m; and writing the n groups of logical page data and the (n+1)th logical page data into the memory cell array to generate 2 in the memory cell array. n Different data states.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the semiconductor field, and particularly to a storage system and its operation method, a memory controller, and a memory. Background Technology

[0002] NAND flash memory cells consist of single-level cells that store 1 bit of data and multi-level cells that store at least 2 bits of data. While NAND flash memory with single-level cells has faster write speeds and higher reliability, it has smaller storage capacity and higher cost; while NAND flash memory with multi-level cells has relatively slower write speeds and relatively lower reliability, it has larger storage capacity and lower cost.

[0003] In some applications, NAND flash memory is required to simultaneously offer the high write speed and reliability of single-level cells, as well as the large storage capacity and low cost of multi-level cells. Therefore, how to flexibly configure NAND flash memory to achieve multiple storage cell modes has become a pressing technical problem to be solved. Summary of the Invention

[0004] In view of the above, embodiments of the present disclosure provide a storage system and its operation method, a memory controller, and a memory.

[0005] According to a first aspect of the present disclosure, a method for operating a storage system is provided. The storage system includes a memory, the memory including a storage cell array and peripheral circuitry coupled to the storage cell array, the storage cell array including storage cells capable of storing m bits of information, where m is a positive integer greater than 1; the method includes:

[0006] The peripheral circuit determines the (n+1)th logical page data based on the received prefix command and the received n sets of logical page data; where n is a positive integer and n+1 is a positive integer less than or equal to m.

[0007] Write the nth set of logical page data and the (n+1)th set of logical page data into the storage cell array to generate 2 in the storage cell array. n Different data states.

[0008] According to a second aspect of the present disclosure, a memory controller is provided, the memory controller being coupled to a memory, the memory including a memory cell array and peripheral circuitry coupled to the memory cell array, the memory cell array including memory cells capable of storing m bits of information, where m is a positive integer greater than 1; the memory controller is configured to:

[0009] The prefix command and n sets of logical page data are sent to the peripheral circuit, so that the peripheral circuit determines the (n+1)th set of logical page data based on the prefix command and n sets of logical page data, and generates 2 in the memory cell array. n There are 3 distinct data states; where n is a positive integer and n+1 is a positive integer less than or equal to m.

[0010] According to a third aspect of the present disclosure, a memory is provided, comprising:

[0011] A storage cell array, the storage cell array comprising storage cells capable of storing m bits of information;

[0012] Peripheral circuitry is coupled to the memory cell array; wherein,

[0013] The peripheral circuit is configured to determine the (n+1)th logical page data based on the received prefix command and the received n sets of logical page data; where n is a positive integer and n+1 is a positive integer less than or equal to m;

[0014] The peripheral circuitry is further configured to write the nth group of logical page data and the (n+1)th group of logical page data into the memory cell array to generate 2 in the memory cell array. n Different data states.

[0015] According to a fourth aspect of the present disclosure, a storage system is provided, comprising:

[0016] The memory as described in the third aspect of the embodiments of this disclosure;

[0017] The memory controller, as described in the second aspect of the present disclosure, is coupled to the memory and configured to control the memory.

[0018] In this embodiment of the disclosure, since the peripheral circuit can determine the (n+1)th logical page data based on the received prefix command and the received n groups of logical page data, and write the n groups of logical page data and the (n+1)th logical page data into the memory cell array, 2 can be generated in the memory cell array. n By using different data states, a portion of the memory space can be used as at least one of SLC, MLC, TLC, and QLC. This allows for flexible configuration of the NAND memory, enabling it to achieve multiple storage cell modes while simultaneously possessing advantages such as fast write speed, high reliability, large storage capacity, and low cost. Attached Figure Description

[0019] Figure 1 This is a schematic diagram illustrating different data states of a memory according to an exemplary embodiment;

[0020] Figure 2This is a flowchart illustrating a writing method for a storage system according to an example embodiment;

[0021] Figure 3 This is a schematic diagram of a storage system according to an example embodiment;

[0022] Figure 4 This is a schematic diagram illustrating a write state of a memory according to an example embodiment;

[0023] Figure 5 This is a flowchart illustrating an operation method of a storage system according to an embodiment of the present disclosure;

[0024] Figure 6 This is a schematic diagram illustrating the execution of a write command by a memory according to an embodiment of the present disclosure;

[0025] Figure 7 This is a timing diagram illustrating a write operation performed on a memory according to an embodiment of the present disclosure;

[0026] Figure 8 This is a schematic diagram illustrating a write state of a memory according to an embodiment of the present disclosure;

[0027] Figure 9 This is a partial schematic diagram of the peripheral circuitry of a memory according to an embodiment of the present disclosure;

[0028] Figure 10 This is a schematic diagram of a memory according to an embodiment of the present disclosure;

[0029] Figure 11 This is a cross-sectional view of a NAND flash memory string according to an embodiment of the present disclosure;

[0030] Figure 12 This is a block diagram of a memory including a memory cell array and peripheral circuitry, according to embodiments of the present disclosure.

[0031] Figure 13 This is a schematic diagram of a storage system according to an embodiment of the present disclosure;

[0032] Figure 14a This is a schematic diagram of a memory card according to an embodiment of the present disclosure;

[0033] Figure 14b This is a schematic diagram of a solid-state drive (SSD) according to an embodiment of the present disclosure. Detailed Implementation

[0034] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0035] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0036] In the embodiments of this disclosure, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0037] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0038] Figure 1 This is a schematic diagram illustrating different data states of a memory according to an exemplary embodiment. (Refer to...) Figure 1 As shown, with the development of NAND memory, the number of bits in the memory cell has increased from 1 bit to 2 bits, 3 bits, and 4 bits. Correspondingly, the memory cell has evolved from Single Level Cell (SLC) to Multiple Level Cell (MLC), Triple Level Cell (TLC), and Quad-Level Cell (QLC). Consequently, the number of data states in the memory has increased from 2 to 4, 8, and 16, resulting in increased memory capacity and reduced cost.

[0039] Reference Figure 1 As shown in (a), the storage cell of the SLC memory stores 1 bit of data. The data state of the SLC memory includes one erase state and one program state. The erase state is denoted as E, and the program state is denoted as P. The threshold voltage of the program state P is greater than the threshold voltage of the erase state E.

[0040] Reference Figure 1 As shown in (b), the storage cell of the MLC memory stores 2 bits of data. The data state of the MLC memory includes one erase state and three programming states. The erase state is denoted as E, and the programming states from the first state to the third state are denoted as P1, P2 and P3 respectively. From the P1 state to the P3 state, the threshold voltage gradually increases.

[0041] Reference Figure 1 As shown in (c), the storage cell of the TLC memory stores 3 bits of data. The data states of the TLC memory include 1 erase state and 7 programming states. The erase state is denoted as E, and the programming states from the 1st state to the 7th state are denoted as P1, P2, P3, P4, P5, P6 and P7 respectively. From the P1 state to the P7 state, the threshold voltage gradually increases.

[0042] Reference Figure 1 As shown in (d), the storage cell of the QLC memory stores 4 bits of data. The QLC memory data state includes 1 erase state and 15 programming states. The erase state is denoted as E, and the programming states from state 1 to state 15 are denoted as P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14 and P15 respectively. From state P1 to state P15, the threshold voltage gradually increases.

[0043] With the development of 3D NAND technology, the number of stacked layers in memory is constantly increasing. When the number of stacked layers is greater than or equal to 64, there will no longer be MLC memory. Although the main 3D NAND product at present is TLC memory, when the number of stacked layers is greater than or equal to 300, the main 3D NAND product will be QLC memory.

[0044] Developing new 3D NAND technology nodes is extremely costly, especially with increasing stacking layers. From a customer demand perspective, there remains a need for low-bit memory to meet better reliability requirements, for example, in the automotive industry. However, this market size is not large; from a cost perspective, developing dedicated low-bit memory is not worthwhile. For example, when mainstream NAND is TLC memory, there are still some applications requiring MLC memory; when mainstream NAND is QLC memory, there are still some applications requiring both TLC and MLC memory; from an application perspective, this is a mismatch.

[0045] One solution is to develop a universal NAND memory that supports all cell levels (SLC / MLC / TLC / QLC). However, this solution would be a huge burden for all development teams, including design, verification, validation, and testing. Furthermore, this work would cost three times more than SLC memory, especially for testing and certification teams.

[0046] Figure 2 This is a flowchart illustrating a writing method for a storage system according to an example embodiment. Figure 3 This is a schematic diagram illustrating a storage system 10 according to an example embodiment. (In conjunction with...) Figure 2 and Figure 3 As shown, the writing method includes at least the following steps:

[0047] S101: Controller 11 receives lower page (LP) data and upper page (UP) data;

[0048] S102: Scrambler 13 is enabled to randomize the LP and UP data;

[0049] S103: Error Correction Code (ECC) 14 enabled, performs parity check on randomized LP and UP data;

[0050] S104: After parity checking, transfer the LP data and UP data to memory, such as a page cache;

[0051] S105: Disable descrambler 16 and ECC decoder 15;

[0052] S106: Transfer LP data and UP data from memory to controller 11;

[0053] S107: The host-side Central Processing Unit (CPU) runs firmware (FW) to perform an XOR operation on the LP data and UP data to generate middle page (MP) data; here, the running firmware can be stored in memory.

[0054] S108: Disable scrambler 13 and ECC encoder 14, and transfer LP / MP / UP data to memory, such as a page buffer;

[0055] S109: Send a write command (e.g., 10h) to begin a write operation, such as writing LP / MP / UP data from the page cache to the storage cell array 12.

[0056] Figure 4 This is a schematic diagram illustrating a write state of a memory according to an example embodiment. (Refer to...) Figure 4 As shown, LP / MP / UP data is written to the memory cell array 12 using the normal write method. This stores 3 bits of data in the TLC memory's memory cells and generates 8 different data states: erase state E and programming states P1 to P7. By executing... Figure 2 The method shown writes LP / MP / UP data into the memory cell array 12, storing 3 bits of data in the TLC memory cells and generating four different data states: erase state E and programming states P2, P4, and P6. That is, by executing... Figure 2The method shown can use at least a portion of the storage space in a TLC memory as an MLC to meet the application requirements of MLC memory.

[0057] However, this method requires execution by the CPU on the host side, which makes the operation complex. It also requires the firmware to use the CPU to perform XOR operations on the raw data (e.g., LP data and UP data) and generate MP data, resulting in low efficiency.

[0058] In view of the above, this disclosure provides a storage system and its operation method.

[0059] Figure 5 This is a flowchart illustrating an operation method of a storage system according to an embodiment of the present disclosure. The storage system includes a memory, which includes a storage cell array and peripheral circuitry coupled to the storage cell array. The storage cell array includes storage cells capable of storing m bits of information, where m is a positive integer greater than 1; see reference... Figure 5 As shown, the operation method includes at least the following steps:

[0060] S201: The peripheral circuit determines the (n+1)th logical page data based on the received prefix command and the received n groups of logical page data; where n is a positive integer and n+1 is a positive integer less than or equal to m;

[0061] S202: Write the nth set of logical page data and the (n+1th)th set of logical page data into the storage cell array to generate 2 in the storage cell array. n Different data states.

[0062] The memory includes a memory cell array and peripheral circuitry coupled to the memory cell array. The memory cell array includes multiple memory cells, each of which can store m bits of information. For example, the memory is an MLC memory, i.e., m=2; another example is a TLC memory, i.e., m=3; yet another example is a QLC memory, i.e., m=4. The peripheral circuitry includes a logic control unit, a command register, a cache register, and a data register, etc.

[0063] In step S201, the logic control unit in the peripheral circuit can read the prefix command stored in the command register, and determine the (n+1)th group of logical page data based on the read prefix command and n groups of logical page data, and store the (n+1)th group of logical page data in the cache register or data register. The n groups of logical page data include at least one of LP data, MP data, UP data, and extra page XP data. In a specific embodiment, the peripheral circuit can perform logical operations on the n groups of logical page data to generate the (n+1)th group of logical page data.

[0064] In step S202, after receiving the write command, the nth set of logical page data and the (n+1th)th set of logical page data are sequentially written to the storage cell array, and a 2 is generated in the storage cell array. n Different data states.

[0065] In one example, the memory is an MLC memory. When a portion of the storage space in the MLC memory needs to be used as SLC, the peripheral circuitry determines the MP data based on the received prefix command and LP data, and writes the LP data and MP data into the memory cell array to generate two different data states in the memory cell array.

[0066] In one example, the memory is a TLC memory. When a portion of the storage space in the TLC memory needs to be used as an MLC, the peripheral circuitry determines the UP data based on the received prefix command, LP data, and MP data, and writes the LP data, MP data, and UP data into the memory cell array to generate four different data states in the memory cell array.

[0067] In one example, the memory is a TLC memory. When a portion of the storage space in the TLC memory needs to be used as SLC, the peripheral circuitry determines the MP data based on the received prefix command and LP data, and writes at least the LP data and MP data into the memory cell array to generate two different data states in the memory cell array.

[0068] In one example, the memory is a QLC memory. When a portion of the storage space in the QLC memory needs to be used as TLC, the peripheral circuitry determines the XP data based on the received prefix command, LP data, MP data, and UP data, and writes the LP data, MP data, UP data, and XP data into the memory cell array to generate eight different data states in the memory cell array.

[0069] In one example, the memory is a QLC memory. When a portion of the storage space in the QLC memory needs to be used as MLC, the peripheral circuitry determines the UP data based on the received prefix command and LP and MP data, and writes at least the LP data, MP data and UP data into the memory cell array to generate four different data states in the memory cell array.

[0070] In one example, the memory is a QLC memory. When a portion of the storage space in the QLC memory needs to be used as SLC, the peripheral circuitry determines the MP data based on the received prefix command and LP data, and writes at least the LP data and MP data into the memory cell array to generate two different data states in the memory cell array.

[0071] In this embodiment of the disclosure, since the peripheral circuit can determine the (n+1)th logical page data based on the received prefix command and the received n groups of logical page data, and write the n groups of logical page data and the (n+1)th logical page data into the memory cell array, 2 can be generated in the memory cell array. n By using different data states, a portion of the memory space can be used as at least one of SLC, MLC, TLC, and QLC. This allows for flexible configuration of the NAND memory, enabling it to achieve multiple storage cell modes while simultaneously possessing advantages such as fast write speed, high reliability, large storage capacity, and low cost.

[0072] Furthermore, compared to the CPU on the host side performing logical operations, the operation method of determining the (n+1)th logical page data through the peripheral circuits inside the memory in this embodiment is simple. While realizing multiple memory unit modes, it is beneficial to improve the operating efficiency of the memory.

[0073] Furthermore, compared to developing general-purpose NAND memory solutions, the operation method provided in this disclosure, which uses prefix commands, is more user-friendly, compatible with existing NAND protocols, and helps save development costs.

[0074] In some embodiments, when n+1 equals m, the prefix command includes: a first sub-prefix command A; wherein, the first sub-prefix command A instructs to perform an XOR operation on n groups of logical page data;

[0075] The above step S201 includes: the peripheral circuit performs an XOR operation on the n groups of logical page data according to the first sub-prefix command A to generate the m-th group of logical page data;

[0076] Step S202 above includes: writing n sets of logical page data and the mth set of logical page data into the storage cell array to store m bits of information in the storage cell.

[0077] Taking QLC memory as an example, the memory controller sends a first sub-prefix command A, along with LP data, MP data, and UP data, to the peripheral circuit. The peripheral circuit performs an XOR operation on the LP data, MP data, and UP data according to the first sub-prefix command A to generate XP data. A write command (e.g., 80h) is then sent to the peripheral circuit, which begins writing the LP data, MP data, UP data, and XP data into the memory cell array to store 4 bits of information in each memory cell and generate 8 different data states. This means that a portion of the storage space in the QLC memory is used as TLC, such as... Figure 6 As shown in ②.

[0078] It should be noted that the first sub-prefix command A is sent before the 80h command. Specifically, Figure 7(b) illustrates a timing diagram for writing to TLC using a portion of the QLC memory. This timing diagram includes the data type signal CycleType and the data signal DQx. When writing to TLC mode in the QLC memory, the first sub-prefix command A is sent first, followed by the 80h command after determining the XP data. Then, address signals C1, C2, R1, R2, and R3 are sent during the address cycle. These address signals determine the logical address of the memory cell to be written, and the LP data, MP data, UP data, and XP data are written to the memory cell. Here, the logical address includes the logical cell number (LUN), plane, block, and page address.

[0079] In a specific example, combined Figure 8 As shown in (a), the LP data is a sequence of (1111111100000000), the MP data is a sequence of (1111000000001111), and the UP data is a sequence of (1100001111000011). The peripheral circuit performs an XOR operation on the LP, MP, and UP data according to the first sub-prefix command A, generating the XP data as a sequence of (1100110011001100). The LP, MP, UP, and XP data are then written into the memory cell array, generating eight data states in the memory cell array, as shown below. Figure 8 As shown in (b), the states are erase state E (1111), programming state P2 (1100), programming state P4 (1001), programming state P6 (1010), programming state P8 (0011), programming state P10 (0000), programming state P12 (0101) and programming state P14 (0110).

[0080] It should be noted that this example uses the sequence (1111111100000000) for LP data, (1111000000001111) for MP data, and (1100001111000011) for UP data as an example to illustrate the present disclosure to those skilled in the art; however, the present disclosure is not limited thereto. The LP data, MP data, and UP data can also be other sequences composed of "1" and "0", as long as it is ensured that after generating XP data by executing the first prefix command A on the LP data, MP data, and UP data, any eight different data states from erase state E to programming state P15 are generated in the QLC memory.

[0081] Preferably, the LP data is a sequence of (1111111100000000), the MP data is a sequence of (1111000000001111), and the UP data is a sequence of (1100001111000011), such as... Figure 8As shown in (b), when a portion of the storage space in the QLC memory is used as TLC, the threshold voltage difference M2 between two adjacent data states is basically the same, that is, the read margin distribution is relatively uniform, which is beneficial to ensuring the accuracy of read operations when used as TLC.

[0082] In this embodiment of the present disclosure, when n+1 equals m, the peripheral circuit performs an XOR operation on the n groups of logical page data according to the first sub-prefix command to generate the m-th group of logical page data. The n groups of logical page data and the m-th group of logical page data are then written into the storage cell array. While storing m bits of information in the storage cell, 2 bits can be generated in the storage cell array. n Different data states can be used. For example, when the memory is QLC, part of the storage space of the QLC memory can be used as TLC, so that the memory has at least two storage unit modes. This is beneficial to increase the application scenarios of the memory and can better meet customer needs while being compatible with mainstream memory.

[0083] In other embodiments, when n+1 equals m, the peripheral circuit can also perform XOR NOT or copy operations on the n groups of logical page data according to the prefix command to generate the m-th group of logical page data. Here, the choice can be made according to the actual situation, and this disclosure does not have any special limitations in this regard.

[0084] In some embodiments, before performing step S202, the above operation method further includes: storing n sets of logical page data into a plurality of data registers respectively; wherein each data register is used to store a set of logical page data; and storing the m-th set of logical page data into a cache register. The peripheral circuitry includes a page cache, and the data registers or cache registers may be located in the page cache for caching logical page data.

[0085] For example, combined Figure 9 As shown, LP data (1111111100000000) is stored in data register 1, MP data (1111000000001111) is stored in data register 2, and UP data (1100001111000011) is stored in data register 3. After generating XP data (1100110011001100), XP data is stored in the cache register. After receiving the 80h command, the LP data stored in data register 1, the MP data stored in data register 2, the UP data stored in data register 3, and the XP data stored in the cache register are sequentially written into the storage cell array.

[0086] In some embodiments, when the difference between m and n is 2, the prefix command includes: a second sub-prefix command B; wherein the second sub-prefix command B instructs to perform an XOR NOT operation on n sets of logical page data;

[0087] The above step S201 includes: the peripheral circuit performs an XOR NOT operation on the n groups of logical page data according to the second sub-prefix command B to generate the (n+1)th group of logical page data;

[0088] The above operation method also includes: writing the data of the m-th logical page into the storage cell array to store m bits of information in the storage cell; wherein the data of the m-th logical page is a sequence of all 0s or a sequence of all 1s.

[0089] Taking QLC memory as an example, the memory controller sends a second sub-prefix command B, along with LP and MP data, to the peripheral circuit. The peripheral circuit performs an XOR operation on the LP and MP data according to the second sub-prefix command B, generating UP data. A write command (e.g., 80h) is then sent to the peripheral circuit, which begins writing the LP, MP, UP, and XP data into the memory cell array to store four bits of information in each cell and generate four different data states. This means that a portion of the QLC memory is used as MLC, such as... Figure 6 As shown in ③. Here, XP data is either a sequence of all zeros or a sequence of all one values.

[0090] It should be noted that the second sub-prefix command B is sent before the 80h command. Specifically, Figure 7 (c) shows a timing diagram for writing MLC using a portion of the storage space in the QLC memory. When writing MLC mode in the QLC memory, the second sub-prefix command B is sent first. After determining the UP data, the 80h command is sent. Then, address signals C1, C2, R1, R2 and R3 are sent during the address cycle. The logical address of the memory cell to be written can be determined through the address signals, and LP data, MP data, UP data and XP data are written to the memory cell.

[0091] In a specific example, combined Figure 8 As shown in (a), the LP data is a sequence of (1111111100000000) and the MP data is a sequence of (1111000000001111). The peripheral circuit performs an XOR operation on the LP and MP data according to the second sub-prefix command B, generating the UP data as a sequence of (1111000011110000) and the XP data as a sequence of (1111111111111111). The LP, MP, UP, and XP data are written into the memory cell array, generating four data states in the memory cell array, as follows: Figure 8 As shown in c, these are the erase state E (1111), the programming state P4 (1001), the programming state P8 (0011), and the programming state P12 (0101), respectively.

[0092] It should be noted that this example uses the sequence (1111111100000000) for LP data, (1111000000001111) for MP data, and (11111111111111111) for XP data as an example to illustrate the present disclosure to those skilled in the art; however, the present disclosure is not limited thereto. The LP data and MP data can also be other sequences composed of "1" and "0", or the XP data can be a sequence of all zeros. It is only necessary to ensure that after generating UP data by executing the second prefix command B on the LP data and MP data, any four different data states from erase state E to programming state P15 are generated in the QLC memory.

[0093] Preferably, the LP data is a sequence of (1111111100000000), the MP data is a sequence of (1111000000001111), and the XP data is a sequence of (11111111111111111), such as... Figure 8 As shown in (c), when a portion of the storage space in the QLC memory is used as MLC, the threshold voltage difference M3 between two adjacent data states is basically the same, that is, the read margin distribution is relatively uniform, which is beneficial to ensuring the accuracy of read operations when used as MLC.

[0094] In this embodiment, when the difference between m and n is 2, the peripheral circuit performs an XOR NOT operation on the n groups of logical page data according to the second sub-prefix command, generating the (n+1)th group of logical page data. The nth group of logical page data, the (n+1)th group of logical page data, and the mth group of logical page data are then written into the memory cell array. This allows for the storage of m bits of information in the memory cell while simultaneously generating 2 bits in the memory cell array. n Different data states can be used. For example, when the memory is QLC, part of the storage space of the QLC memory can be used as MLC, so that the memory has at least two storage unit modes. This is beneficial to increase the application scenarios of the memory and can better meet customer needs while being compatible with mainstream memory.

[0095] In other embodiments, when the difference between m and n is 2, the peripheral circuit can also perform an XOR operation or a copy operation on the n groups of logical page data according to the prefix command to generate the (n+1)th group of logical page data. This can be selected according to the actual situation, and this disclosure does not impose any special restrictions on it.

[0096] In some embodiments, before performing step S202, the above operation method further includes: storing n sets of logical page data and the (n+1)th set of logical page data into a plurality of data registers respectively; wherein, each data register is used to store a set of logical page data; before writing the mth set of logical page data into the storage cell array, the above operation method further includes: storing the mth set of logical page data into a cache register.

[0097] For example, combined Figure 9 As shown, LP data (1111111100000000) is stored in data register 1, MP data (1111000000001111) is stored in data register 2, and XP data (11111111111111111) is stored in cache register. After generating UP data, UP data (1111000011110000) is stored in data register 3. After receiving the 80h command, the LP data stored in data register 1, the MP data stored in data register 2, the UP data stored in data register 3, and the XP data stored in cache register are sequentially written into the storage cell array.

[0098] In some embodiments, when the difference between m and n is 3, the prefix command includes: a third sub-prefix command C; wherein the third sub-prefix command C indicates that the (n+1)th logical page data is equal to the nth logical page data;

[0099] The above step S201 includes: the peripheral circuit performs a copy operation on the n groups of logical page data according to the third sub-prefix command C to generate the (n+1)th group of logical page data;

[0100] The above operation method further includes: writing the (n+2)th logical page data and the mth logical page data into the storage cell array to store m bits of information in the storage cell; wherein the (n+2)th logical page data and the mth logical page data are either all-zero sequences or all-one sequences.

[0101] Taking QLC memory as an example, the memory controller sends a third sub-prefix command C and LP data to the peripheral circuit. The peripheral circuit performs a copy operation on the LP data according to the third sub-prefix command C, generating MP data, i.e., MP data is the same as LP data. A write command (e.g., 80h) is then sent to the peripheral circuit, which begins writing LP data, MP data, UP data, and XP data into the memory cell array to store 4 bits of information in the memory cell and generate 2 different data states. This means that a portion of the storage space in the QLC memory is used as SLC, such as... Figure 6 As shown in ④. Here, the UP data and XP data are either all-zero sequences or all-one sequences.

[0102] It should be noted that the third sub-prefix command C is sent before the 80h command. Specifically, Figure 7(d) shows the timing diagram for writing a portion of the storage space in the QLC memory as SLC. When writing SLC mode in the QLC memory, the third sub-prefix command C is sent first. After determining the MP data, the 80h command is sent. Then, address signals C1, C2, R1, R2 and R3 are sent during the address cycle. The logical address of the memory cell to be written can be determined through the address signal, and the LP data, MP data, UP data and XP data are written to the memory cell.

[0103] In a specific example, combined Figure 8 As shown in (a), the LP data is a sequence of (1111111100000000). The peripheral circuit performs a copy operation on the LP data according to the third sub-prefix command C, generating the MP data as a sequence of (1111111100000000), the UP data as a sequence of (1111111111111111), and the XP data as a sequence of (1111111111111111). The LP data, MP data, UP data, and XP data are written into the memory cell array, generating two data states in the memory cell array, as follows: Figure 8 As shown in (d), these are the erase state E (1111) and the programming state P8 (0011), respectively.

[0104] It should be noted that this example uses the sequence (1111111100000000) for LP data, (1111111111111111) for UP data, and (1111111111111111) for XP data as an example to illustrate the present disclosure to those skilled in the art; however, the present disclosure is not limited thereto. The LP data can also be other sequences composed of "1" and "0", or the UP and XP data can be sequences of all zeros. It is only necessary to ensure that after generating MP data by executing the third prefix command C on the LP data, any two different data states from erase state E to programming state P15 are generated in the QLC memory.

[0105] Preferably, the LP data is a sequence of (1111111100000000), the UP data is a sequence of (1111111111111111), and the XP data is a sequence of (1111111111111111), such as... Figure 8 As shown in (d), when a portion of the storage space in the QLC memory is used as an SLC, the threshold voltage difference M4 between the erase state E and the programming state P8 is relatively large, which is beneficial to ensuring the accuracy of read operations when used as an MLC.

[0106] In this embodiment, when the difference between m and n is 3, the peripheral circuit performs a copy operation on the n groups of logical page data according to the third sub-prefix command, which generates the (n+1)th group of logical page data. The nth group of logical page data, the (n+1)th group of logical page data, the (n+2)th group of logical page data, and the mth group of logical page data are then written into the storage cell array. While storing m bits of information in the storage cell, 2 bits of information can be generated in the storage cell array. n Different data states can be used. For example, when the memory is QLC, part of the storage space of the QLC memory can be used as SLC, so that the memory has at least two storage unit modes. This is beneficial to increase the application scenarios of the memory and can better meet customer needs while being compatible with mainstream memory.

[0107] In some embodiments, before performing step S202, the above operation method further includes: storing n sets of logical page data and the (n+1)th set of logical page data into a plurality of data registers respectively; wherein, each data register is used to store a set of logical page data;

[0108] Before writing the (n+2)th logical page data and the mth logical page data into the storage cell array, the above operation method further includes: storing the (n+2)th logical page data into the data register; and storing the mth logical page data into the cache register.

[0109] For example, combined Figure 9 As shown, LP data (1111111100000000) is stored in data register 1, UP data (11111111111111111) is stored in data register 3, and XP data (11111111111111111) is stored in cache register. After generating MP data, MP data (1111111100000000) is stored in data register 2. After receiving the 80h command, the LP data stored in data register 1, the MP data stored in data register 2, the UP data stored in data register 3, and the XP data stored in cache register are sequentially written into the storage cell array.

[0110] In some embodiments, before determining the (n+1)th logical page data, the above operation method further includes:

[0111] Determine whether the peripheral circuit has received the prefix command and generate the determination result;

[0112] When the judgment result indicates that the peripheral circuit has received a prefix command, the (n+1)th logical page data is determined based on the received prefix command and n sets of logical page data.

[0113] When the judgment result indicates that the peripheral circuit has not received the prefix command, m sets of logic page data are written to the memory cell array to generate 2 in the memory cell array.m Different data states.

[0114] Taking QLC memory as an example, the logic control unit in the peripheral circuit can read the command register and determine whether the command register stores a prefix command (e.g., the first sub-prefix command, the second sub-prefix command, or the third sub-prefix command) based on the read result. When the read result indicates that the command register stores a prefix command, the peripheral circuit determines the (n+1)th group of logic page data based on the prefix command and n groups of logic page data, that is, a portion of the storage space of the QLC memory is used as TLC, MLC, or SLC.

[0115] If the read result indicator command register does not contain a prefix command, an 80h command is sent to the peripheral circuit. The peripheral circuit writes m sets of logic page data into the memory cell array to store m bits of information in the memory cells and generates 2 in the memory cell array. m There are several different data states. Here, the storage space for writing m sets of logical page data is used as QLC, such as... Figure 6 As shown in ①.

[0116] In a specific example, refer to Figure 8 As shown in (a), LP data is a sequence of (1111111100000000), MP data is a sequence of (1111000000001111), UP data is a sequence of (1100001111000011), and XP data is a sequence of (1001100110011001). The peripheral circuit writes the LP, MP, UP, and XP data into the memory cell array according to the 80h command, generating 16 data states in the memory cell array, such as... Figure 8 As shown in (a), the programming states are E (1111), P1 (1110), P2 (1100), P3 (1101), P4 (1001), P5 (1000), P6 (1010), P7 (1011), P8 (0011), P9 (0010), P10 (0000), P11 (0001), P12 (0101), P13 (0100), P14 (0110), and P15 (0111).

[0117] In this embodiment of the disclosure, by determining whether the peripheral circuit has received a prefix command and generating a determination result, and based on the determination result, determining whether to use a portion of the storage space of the QLC memory as at least one of SLC, MLC, and TLC, it is beneficial to accurately configure the NAND memory.

[0118] In some embodiments, the above-described operation method further includes: when the data register is damaged, the peripheral circuit stores one set of logical page data from the n sets of logical page data into a spare data register. For example, refer to... Figure 9 As shown, when data register 1 is damaged, the peripheral circuit stores the LP data to the spare data register 4; and / or, when data register 2 is damaged, the peripheral circuit stores the MP data to the spare data register 5, etc.

[0119] It should be noted that this example only illustrates two spare data registers. The number of spare data registers in the memory is not limited to two; it can also be one, three, or even more. This disclosure does not impose any restrictions. In practical applications, the number of spare data registers can be reasonably set according to requirements.

[0120] This disclosure also provides a memory controller coupled to a memory, the memory including a memory cell array and peripheral circuitry coupled to the memory cell array. The memory cell array includes memory cells capable of storing m bits of information, where m is a positive integer greater than 1. The memory controller is configured to send a prefix command and n sets of logical page data to the peripheral circuitry, so that the peripheral circuitry determines the (n+1)th set of logical page data based on the prefix command and the n sets of logical page data, and generates 2 in the memory cell array. n There are 3 distinct data states; where n is a positive integer and n+1 is a positive integer less than or equal to m.

[0121] In some embodiments, the prefix command includes: a first sub-prefix command, which is used to instruct the XOR operation to be performed on n groups of logical page data;

[0122] The memory controller is specifically configured to send a first sub-prefix command and n sets of logical page data to the peripheral circuit, so that the peripheral circuit performs an XOR operation on the n sets of logical page data according to the first sub-prefix command to generate the mth set of logical page data; where n+1 equals m.

[0123] In some embodiments, the prefix command includes: a second sub-prefix command, which is used to instruct the XOR operation to be performed on n sets of logical page data;

[0124] The memory controller is specifically configured to send the second sub-prefix command and n sets of logical page data to the peripheral circuit, so that the peripheral circuit performs an XOR NOT operation on the n sets of logical page data according to the second sub-prefix command to generate the (n+1)th set of logical page data.

[0125] The memory controller is also configured to send the data of the m-th logical page to the peripheral circuitry; wherein the data of the m-th logical page is a sequence of all zeros or all one, and the difference between m and n is 2.

[0126] In some embodiments, the prefix command includes: a third sub-prefix command, which is used to indicate that the (n+1)th logical page data is equal to the nth logical page data;

[0127] The memory controller is specifically configured to send the third sub-prefix command and n sets of logical page data to the peripheral circuit, so that the peripheral circuit performs a copy operation on the n sets of logical page data according to the third sub-prefix command to generate the (n+1)th set of logical page data.

[0128] The memory controller is also configured to send the (n+2)th logical page data and the mth logical page data to the peripheral circuitry; wherein the (n+2)th logical page data and the mth logical page data are either all-zero sequences or all-one sequences, and the difference between m and n is 3.

[0129] In some embodiments, the memory controller is further configured to send a write command to the peripheral circuitry after sending a prefix command, so that the peripheral circuitry writes at least n sets of logical page data and the (n+1)th set of logical page data to the memory cell array according to the write command.

[0130] Figure 10 This is a schematic diagram illustrating a memory 100 according to an embodiment of the present disclosure. (Refer to...) Figure 10 As shown, the memory 100 includes:

[0131] The storage cell array 101 includes a storage cell 106 capable of storing m bits of information.

[0132] Peripheral circuit 102 is coupled to memory cell array 101; wherein,

[0133] The peripheral circuit 102 is configured to determine the (n+1)th logical page data based on the received prefix command and the received n groups of logical page data; where n is a positive integer and n+1 is a positive integer less than or equal to m;

[0134] The peripheral circuit 102 is also configured to write n sets of logical page data and the (n+1)th set of logical page data into the memory cell array 101 to generate 2 in the memory cell array 101. n Different data states.

[0135] The memory cell array 101 may be a NAND flash memory cell array, wherein the memory cell array 101 is provided in the form of an array of NAND memory strings 108, each NAND memory string 108 extending vertically. In some embodiments, each NAND memory string 108 includes a plurality of memory cells 106 coupled in series and stacked vertically. Each memory cell 106 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 106. Each memory cell 106 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0136] In some implementations, each memory cell 106 is a single-level cell having two possible data states and thus capable of storing 1 bit of data. For example, the first data state "0" may correspond to a first voltage range, and the second data state "1" may correspond to a second voltage range.

[0137] In some implementations, each memory cell 106 is a cell capable of storing more than 1 bit of data in more than four data states. For example, it can store 2 bits per cell (also known as a multi-level cell), 3 bits per cell (also known as a three-level cell), or 4 bits per cell (also known as a four-level cell). Each multi-level cell can be programmed to take a range of possible nominal storage values. In one example, if each multi-level cell stores 2 bits of data, the multi-level cell can be written to take one of three possible data states from the erase state by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erase state.

[0138] like Figure 10 As shown, each NAND memory string 108 may include a source select transistor (SST) 110 at its source end and a drain select transistor (DST) 112 at its drain end. The source select transistor 110 and the drain select transistor 112 may be configured to activate the selected NAND memory string 108 (column of the array) during read and write operations.

[0139] In some implementations, the sources of NAND flash strings 108 in the same memory block 104 are coupled through the same source line (SL) 114. In other words, according to some implementations, all NAND flash strings 108 in the same memory block 104 have an array common source (ACS).

[0140] According to some implementations, the drain select transistor 112 of each NAND memory string 108 is coupled to a corresponding bit line 116, and data can be read from or written to the bit line 116 via an output bus (not shown).

[0141] In some implementations, each NAND flash memory string 108 is configured to apply a select voltage (e.g., higher than the threshold voltage of the drain select transistor 112) or a deselect voltage (e.g., 0V) to the corresponding drain select gate via one or more drain select gate lines 111, where the select voltage is used to turn on the drain select transistor 112 and the deselect voltage is used to turn off the drain select transistor 112. And / or, in some implementations, each NAND flash memory string 108 is configured to apply a select voltage (e.g., higher than the threshold voltage of the source select transistor 110) or a deselect voltage (e.g., 0V) to the corresponding source select gate via one or more source select gate lines 115, where the select voltage is used to turn on the source select transistor 110 and the deselect voltage is used to turn off the source select transistor 110.

[0142] like Figure 10 As shown, the NAND storage string 108 can be organized into multiple storage blocks 104, each of which can have a common source line 114 (e.g., coupled to ground). In some implementations, each storage block 104 is the basic data unit for an erase operation, i.e., all storage cells 106 on the same storage block 104 are erased simultaneously.

[0143] It should be understood that, in some examples, erasure operations can be performed at the half-block level, at the quarter-block level, or at any level with any suitable number of blocks or any suitable fraction of blocks. Storage cells 106 of adjacent NAND storage strings 108 can be coupled via word lines 118, which select which row of storage cells 106 is affected by read and write operations.

[0144] In some implementations, each word line 118 is designated as a memory page 120. The size of a memory page 120, in bits, can be related to the number of NAND memory strings 108 coupled by word lines 118 in a memory block 104. Each word line 118 may include multiple control gates (gate electrodes) at each memory cell 106 in the corresponding memory page 120, as well as gate lines coupling the control gates. It is understood that a memory cell row is a plurality of memory cells 106 located in the same memory page 120.

[0145] Figure 11 This is a cross-sectional view of a NAND storage string 108 according to an embodiment of the present disclosure. Figure 11As shown, the NAND memory string 108 can extend vertically through the memory stack layer 204 above the substrate 202. The substrate 202 can include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0146] The memory stack layer 204 may include alternating gate conductive layers 206 and gate dielectric layers 208. The number of pairs of gate conductive layers 206 and gate dielectric layers 208 in the memory stack layer 204 determines the number of memory cells 106 in the memory cell array 101.

[0147] The gate conductive layer 206 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 206 may include a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 206 may include a doped polysilicon layer. Each gate conductive layer 206 may include a control gate surrounding the memory cell 106 and may extend laterally at the top of the memory stack 204 as a drain select gate line 111, at the bottom of the memory stack 204 as a source select gate line 115, or between the drain select gate line 111 and the source select gate line 115 as a word line 118.

[0148] like Figure 11 As shown, the NAND flash memory string 108 includes a channel structure 212 extending vertically through the memory stack layer 204. In some embodiments, the channel structure 212 includes channel vias filled with one or more semiconductor materials (e.g., as semiconductor channel 220) and one or more dielectric materials (e.g., as storage film 218). In some embodiments, the semiconductor channel 220 includes silicon, for example, polysilicon. In some embodiments, the storage film 218 is a composite dielectric layer including a tunneling layer 226, a storage layer 224 (also referred to as a "charge trap / storage layer"), and a barrier layer 222. The channel structure 212 may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel 220, tunneling layer 226, storage layer 224, and barrier layer 222 are arranged radially from the center of the cylinder toward the outer surface of the cylinder in this order. The tunneling layer 226 may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 224 may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer 222 may comprise silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the storage film 218 may comprise a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0149] According to some implementation methods, such as Figure 11 As shown, well 214 (e.g., a P-well and / or an N-well) is formed in substrate 202, and the source end of NAND memory string 108 contacts well 214. In some embodiments, NAND memory string 108 also includes a channel plug 216 at the drain end of NAND memory string 108. It should be understood that, although in Figure 11 Additional components, not shown, but which may form the memory cell array 101, include, but are not limited to, gate line gaps / source contacts, local contacts, interconnect layers, etc.

[0150] Return to reference Figure 10 The peripheral circuitry 102 can be coupled to the memory cell array 101 via bit line 116, word line 118, source line 114, source select gate line 115, and drain select gate line 111. The peripheral circuitry 102 may include any suitable analog, digital, and mixed-signal circuitry for facilitating the operation of the memory cell array 101 by applying voltage and / or current signals to each memory cell 106 and sensing voltage and / or current signals from each memory cell 106 via bit line 116, word line 118, source line 114, source select gate line 115, and drain select gate line 111.

[0151] In some embodiments, when n+1 equals m, the prefix command includes: a first sub-prefix command; wherein the first sub-prefix command indicates that an XOR operation is performed on n groups of logical page data;

[0152] The peripheral circuit 102 is specifically configured to: perform an XOR operation on the n groups of logical page data according to the first sub-prefix command to generate the m-th group of logical page data;

[0153] The peripheral circuit 102 is further configured to write n sets of logical page data and m sets of logical page data into the memory cell array to store m bits of information in the memory cell.

[0154] In some embodiments, the peripheral circuit 102 includes:

[0155] Multiple data registers are used to store n sets of logical page data; where each data register is used to store one set of logical page data.

[0156] The cache register is used to store the data of the m-th logical page.

[0157] In some embodiments, the peripheral circuit 102 includes:

[0158] The spare data register is used to store one set of logical page data from n sets of logical page data in the event of a data register failure.

[0159] In some embodiments, when the difference between m and n is 2, the prefix command includes: a second sub-prefix command; wherein the second sub-prefix command instructs to perform an XOR NOT operation on n sets of logical page data;

[0160] The peripheral circuit 102 is specifically configured to perform an XOR NOT operation on the n groups of logical page data according to the second sub-prefix command, and generate the (n+1)th group of logical page data;

[0161] The peripheral circuit 102 is also configured to write the data of the m-th logical page into the memory cell array to store m bits of information in the memory cell; wherein the data of the m-th logical page is either an all-zero sequence or an all-one sequence.

[0162] In some embodiments, the peripheral circuit 102 includes:

[0163] Multiple data registers are used to store n sets of logical page data and the (n+1)th set of logical page data; each data register is used to store one set of logical page data.

[0164] The cache register is used to store the data of the m-th logical page.

[0165] In some embodiments, when the difference between m and n is 3, the prefix command includes: a third sub-prefix command; wherein the third sub-prefix command indicates that the (n+1)th logical page data is equal to the nth logical page data;

[0166] The peripheral circuit 102 is specifically configured to: perform a copy operation on the n groups of logical page data according to the third sub-prefix command, and generate the (n+1)th group of logical page data;

[0167] The peripheral circuit 102 is also configured to write the (n+2)th logical page data and the mth logical page data into the memory cell array to store m bits of information in the memory cell; wherein the (n+2)th logical page data and the mth logical page data are either all-zero sequences or all-one sequences.

[0168] In some embodiments, the peripheral circuit 102 includes:

[0169] Multiple data registers are used to store n sets of logical page data, the (n+1)th set of logical page data, and the (n+2)th set of logical page data; wherein each data register is used to store one set of logical page data;

[0170] The cache register is used to store the data of the m-th logical page.

[0171] In some embodiments, the peripheral circuit 102 is further configured to:

[0172] Before determining the data of the (n+1)th logical page, check whether a prefix command has been received and generate a result.

[0173] When the judgment result indicates that a prefix command has been received, the (n+1)th logical page data is determined based on the received prefix command and n sets of logical page data.

[0174] If the judgment result indicates that no prefix command has been received, m sets of logical page data are written to the storage cell array to generate 2 in the storage cell array. m Different data states.

[0175] Peripheral circuitry 102 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 12 Some exemplary peripheral circuitry 102 is shown, including a page buffer / sensor amplifier 304, a column decoder / bit line (BL) driver 306, a row decoder / word line (WL) driver 308, a voltage generator 310, a control logic unit 312, a register 314, an interface 316, and a data bus 318. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 12 Additional peripheral circuitry not shown.

[0176] Page buffer / sensor amplifier 304 can be configured to read data from and write (program) data to memory cell array 101 according to control signals from control logic unit 312. In one example, page buffer / sensor amplifier 304 can store page write data (programming data) to be programmed into a memory page 120 of memory cell array 101. In another example, page buffer / sensor amplifier 304 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 106 coupled to selected word line 118. In yet another example, page buffer / sensor amplifier 304 can also sense a low-power signal from bit line 116 representing data bits stored in memory cell 106 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 306 can be configured to be controlled by control logic unit 312 and select one or more NAND memory strings 108 by applying a bit line voltage generated from voltage generator 310.

[0177] The line decoder / word line driver 308 can be configured to be controlled by the control logic unit 312 and to select / deselect memory blocks 104 of the memory cell array 101 and select / deselect word lines 118 of memory blocks 104. The line decoder / word line driver 308 can also be configured to use word line voltages (V) generated from the voltage generator 310. WLThe line decoder / word line driver 308 can also select / deselect and drive the source select gate 115 and the drain select gate 111. As described in detail below, the line decoder / word line driver 308 is configured to perform an erase operation on memory cells 106 coupled to one or more selected word lines 118. The voltage generator 310 can be configured to be controlled by the control logic unit 312 and generate word line voltages (e.g., read voltage, write voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 101.

[0178] Control logic unit 312 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 314 can be coupled to control logic unit 312 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 316 can be coupled to control logic unit 312 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic unit 312, as well as to buffer status information received from control logic unit 312 and relay it to the host. Interface 316 can also be coupled to column decoder / bit line driver 306 via data bus 318 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory cell array 101.

[0179] It should be emphasized that the peripheral circuit 102 is configured to perform the write operation provided in the embodiments of this disclosure on a selected memory cell row among a plurality of memory cell rows.

[0180] Figure 13 This is a schematic diagram illustrating a storage system 400 according to an embodiment of the present disclosure. (Refer to...) Figure 13 As shown, the storage system 400 includes:

[0181] One or more memory 100 as described in the above embodiments;

[0182] As in the above embodiment, the memory controller 406 is coupled to the memory 100 and configured to control the memory 100.

[0183] System 400 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0184] like Figure 13 As shown, system 400 may include a host 408 and a storage subsystem 402, the storage subsystem 402 having one or more memories 100, and the storage subsystem also including a memory controller 406. The host 408 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 408 may be configured to send data to the memory 100. Alternatively, the host 408 may be configured to receive data from the memory 100.

[0185] Memory 100 can be any memory device disclosed in this disclosure. Memory 100 (e.g., a NAND flash memory device (e.g., a three-dimensional (3D) NAND flash memory device)) can have reduced leakage current from drive transistors (e.g., string drivers) coupled to unselected word lines during erase operations, which allows for further reduction in the size of the drive transistors.

[0186] According to some implementations, the memory controller 406 is also coupled to the host 408. The memory controller 406 can manage data stored in the memory 100 and communicate with the host 408.

[0187] In some implementations, the memory controller 406 is designed to operate in low duty cycle environments, such as secure digital (SD) cards, compact flash (CF) cards, universal serial bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0188] In some implementations, the memory controller 406 is designed to operate in a high duty cycle environment solid-state drive (SSD) or embedded multimedia card (eMMC), which serves as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays.

[0189] The memory controller 406 can be configured to control operations of the memory 100, such as read, erase, and program operations. The memory controller 406 can also be configured to manage various functions relating to data stored or to be stored in the memory 100, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 406 is also configured to handle error correction codes (ECC) relating to data read from or written to the memory 100.

[0190] The memory controller 406 can also perform any other suitable functions, such as formatting the memory 100. The memory controller 406 can communicate with external devices (e.g., the host 408) according to a specific communication protocol. For example, the memory controller 406 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0191] The memory controller 406 and one or more memories 100 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the storage system 400 can be implemented and packaged into different types of end electronic products.

[0192] In such Figure 14a In one example shown, the memory controller 406 and a single memory 100 can be integrated into a memory card 502. The memory card 502 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 502 can also include a connection between the memory card 502 and a host computer (e.g., Figure 13 The memory card connector 504 is coupled to the host 408.

[0193] In such Figure 14b In another example shown, the memory controller 406 and multiple memories 100 may be integrated into a solid-state drive (SSD) 506. The solid-state drive 506 may also include a connection between the solid-state drive 506 and a host (e.g., Figure 13 The solid-state drive connector 508 is coupled to the host 408 in the memory card 502. In some embodiments, the storage capacity and / or operating speed of the solid-state drive 506 is greater than that of the memory card 502.

[0194] It is understood that the memory controller 406 can perform the operating methods provided in any embodiment of this disclosure.

[0195] It should be understood that the phrase "some embodiments" mentioned throughout the specification means that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this disclosure. Therefore, "in some embodiments" or "in other embodiments" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0196] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0197] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0198] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0199] In addition, each functional unit in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0200] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for operating a storage system, characterized in that, The storage system includes a memory, which includes a storage cell array and peripheral circuitry coupled to the storage cell array. The storage cell array includes storage cells capable of storing m bits of information, where m is a positive integer greater than 1. The operation method includes: Determine whether a prefix command has been received and generate the result. When the judgment result indicates that the prefix command has been received, the peripheral circuit determines the (n+1)th logical page data based on the received prefix command and the received n sets of logical page data; where n is a positive integer and n+1 is a positive integer less than or equal to m; Write the nth set of logical page data and the (n+1)th set of logical page data into the storage cell array to generate 2 in the storage cell array. n Different data states.

2. The operating method according to claim 1, characterized in that, When n+1 equals m, the prefix command includes: a first sub-prefix command; wherein the first sub-prefix command indicates that an XOR operation is performed on the n groups of logical page data; The peripheral circuit determines the (n+1)th logical page data based on the received prefix command and n groups of logical page data, including: The peripheral circuit performs the XOR operation on the n groups of logical page data according to the first sub-prefix command to generate the m-th group of logical page data; The step of writing the nth group of logical page data and the (n+1)th group of logical page data into the storage cell array includes: The nth set of logical page data and the mth set of logical page data are written into the storage cell array to store m bits of information in the storage cell.

3. The operating method according to claim 2, characterized in that, Before writing the nth set of logical page data and the mth set of logical page data into the storage cell array, the operation method further includes: The n sets of logical page data are stored in multiple data registers respectively; wherein each data register is used to store a set of logical page data; The m-th logical page data is stored in the cache register.

4. The operating method according to claim 1, characterized in that, When the difference between m and n is 2, the prefix command includes: a second sub-prefix command; wherein the second sub-prefix command indicates that an XOR NOT operation is performed on the n groups of logical page data; The peripheral circuit determines the (n+1)th logical page data based on the received prefix command and n groups of logical page data, including: The peripheral circuit performs the XOR NOT operation on the n groups of logical page data according to the second sub-prefix command to generate the (n+1)th group of logical page data. The operation method further includes: The data of the m-th logical page is written into the storage cell array to store m bits of information in the storage cell; wherein the data of the m-th logical page is either an all-zero sequence or an all-one sequence.

5. The operating method according to claim 1, characterized in that, When the difference between m and n is 3, the prefix command includes: a third sub-prefix command; wherein, the third sub-prefix command indicates that the (n+1)th logical page data is equal to the nth logical page data; The peripheral circuit determines the (n+1)th logical page data based on the received prefix command and n groups of logical page data, including: The peripheral circuit performs a copy operation on the nth group of logical page data according to the third sub-prefix command to generate the (n+1)th group of logical page data. The operation method further includes: The (n+2)th logical page data and the mth logical page data are written into the storage cell array to store m bits of information in the storage cell; wherein the (n+2)th logical page data and the mth logical page data are either all-zero sequences or all-one sequences.

6. The operating method according to claim 1, characterized in that, When the determination result indicates that the prefix command has not been received, m sets of logical page data are written to the storage cell array to generate 2 in the storage cell array. m Different data states.

7. A memory controller, characterized in that, The memory controller is coupled to a memory, which includes a memory cell array and peripheral circuitry coupled to the memory cell array. The memory cell array includes memory cells capable of storing m bits of information, where m is a positive integer greater than 1. The memory controller is configured to: The prefix command and n sets of logical page data are sent to the peripheral circuit, so that the peripheral circuit can determine whether the prefix command has been received and generate a determination result. When the generated determination result indicates that the prefix command has been received, the peripheral circuit determines the (n+1)th set of logical page data based on the prefix command and the n sets of logical page data, and generates 2 in the memory cell array. n There are 3 distinct data states; where n is a positive integer and n+1 is a positive integer less than or equal to m.

8. The memory controller according to claim 7, characterized in that, The prefix command includes: a first sub-prefix command, which is used to instruct the n groups of logical page data to perform an XOR operation; The memory controller is specifically configured to send the first sub-prefix command and n sets of logical page data to the peripheral circuit, so that the peripheral circuit performs the XOR operation on the n sets of logical page data according to the first sub-prefix command to generate the mth set of logical page data; where n+1 equals m.

9. The memory controller according to claim 7, characterized in that, The prefix command includes: a second sub-prefix command, which is used to instruct the n groups of logical page data to perform an XOR NOT operation; The memory controller is specifically configured to send the second sub-prefix command and n sets of logical page data to the peripheral circuit, so that the peripheral circuit performs the XOR NOT operation on the n sets of logical page data according to the second sub-prefix command to generate the (n+1)th set of logical page data. The memory controller is further configured to send the m-th logical page data to the peripheral circuit; wherein the m-th logical page data is a sequence of all 0s or all 1s, and the difference between m and n is 2.

10. The memory controller according to claim 7, characterized in that, The prefix command includes a third sub-prefix command, which is used to indicate that the (n+1)th logical page data is equal to the nth logical page data; The memory controller is specifically configured to send the third sub-prefix command and n sets of logical page data to the peripheral circuit, so that the peripheral circuit performs a copy operation on the n sets of logical page data according to the third sub-prefix command to generate the (n+1)th set of logical page data. The memory controller is further configured to send the (n+2)th logical page data and the mth logical page data to the peripheral circuit; wherein the (n+2)th logical page data and the mth logical page data are either all-zero sequences or all-one sequences, and the difference between m and n is 3.

11. The memory controller according to claim 7, characterized in that, The memory controller is also configured to: After sending the prefix command, a write command is sent to the peripheral circuit, so that the peripheral circuit writes at least the nth group of logical page data and the (n+1)th group of logical page data into the memory cell array according to the write command.

12. A memory, characterized in that, include: A storage cell array, the storage cell array comprising storage cells capable of storing m bits of information, where m is a positive integer greater than 1; An external circuit is coupled to the memory cell array; wherein the external circuit is configured to determine whether a prefix command has been received and generate a determination result; and when the determination result indicates that the prefix command has been received, to determine the (n+1)th logical page data based on the received prefix command and the received n groups of logical page data; wherein n is a positive integer and n+1 is a positive integer less than or equal to m; The peripheral circuitry is further configured to write the nth group of logical page data and the (n+1)th group of logical page data into the memory cell array to generate 2 in the memory cell array. n Different data states.

13. The memory according to claim 12, characterized in that, When n+1 equals m, the prefix command includes: a first sub-prefix command; wherein the first sub-prefix command indicates that an XOR operation is performed on the n groups of logical page data; The peripheral circuit is specifically configured to: perform the XOR operation on the n groups of logical page data according to the first sub-prefix command to generate the mth group of logical page data; The peripheral circuit is further configured to write the nth set of logical page data and the mth set of logical page data into the storage cell array to store m bits of information in the storage cell.

14. The memory according to claim 13, characterized in that, The peripheral circuit includes: Multiple data registers are used to store the n sets of logical page data; wherein each data register is used to store one set of logical page data; A cache register is used to store the data of the m-th logical page.

15. The memory according to claim 14, characterized in that, The peripheral circuit includes: A spare data register is used to store one set of logical page data from the n sets of logical page data when the data register is damaged.

16. The memory according to claim 12, characterized in that, When the difference between m and n is 2, the prefix command includes: a second sub-prefix command; wherein the second sub-prefix command indicates that an XOR NOT operation is performed on the n groups of logical page data; The peripheral circuit is specifically configured to: perform the XOR NOT operation on the n groups of logical page data according to the second sub-prefix command to generate the (n+1)th group of logical page data; The peripheral circuit is further configured to write the m-th logical page data into the storage cell array to store m bits of information in the storage cell; wherein the m-th logical page data is an all-zero sequence or an all-one sequence.

17. The memory according to claim 12, characterized in that, When the difference between m and n is 3, the prefix command includes: a third sub-prefix command; wherein, the third sub-prefix command indicates that the (n+1)th logical page data is equal to the nth logical page data; The peripheral circuit is specifically configured to: perform a copy operation on the nth group of logical page data according to the third sub-prefix command, and generate the (n+1)th group of logical page data; The peripheral circuit is further configured to write the (n+2)th logical page data and the mth logical page data into the memory cell array to store m bits of information in the memory cell; wherein the (n+2)th logical page data and the mth logical page data are either all-zero sequences or all-one sequences.

18. The memory according to claim 17, characterized in that, The peripheral circuit is further configured to: when the judgment result indicates that the prefix command has not been received, write m sets of logical page data into the memory cell array to generate 2 in the memory cell array. m Different data states.

19. A storage system, characterized in that, include: One or more memories as described in any one of claims 12 to 18; The memory controller as described in any one of claims 7 to 11 is coupled to the memory and configured to control the memory.

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