Semiconductor memory device and method of operating the same

Abstract

Embodiments of the present disclosure relate to a semiconductor memory device and an operating method thereof. A method of operating a semiconductor memory device includes performing a plurality of program loops to program selected memory cells among a plurality of memory cells. Each of the plurality of program loops includes a program phase and a verify phase. The program phase includes setting a state of a select line connected with a selected memory block including the selected memory cells, wherein the setting the state of the select line connected with the selected memory block includes applying a voltage to the select line based on a program progress state of the selected memory cells, setting a state of a bit line connected with the selected memory block, applying a program voltage to a selected word line among word lines connected with the selected memory block, and applying a pass voltage to unselected word lines.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0082891, filed on June 25, 2021, which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to electronic devices, and more particularly to semiconductor memory devices and methods of operating semiconductor memory devices. Background Technology

[0004] Semiconductor memory devices can be formed as a two-dimensional structure in which strings are horizontally arranged on a semiconductor substrate, or as a three-dimensional structure in which strings are vertically stacked on a semiconductor substrate. Three-dimensional semiconductor memory devices are designed to overcome the integration limitations of two-dimensional memory devices and can include multiple memory cells vertically stacked on a semiconductor substrate. A controller can control the operation of the semiconductor memory device. Summary of the Invention

[0005] Embodiments of this disclosure relate to semiconductor memory devices and methods of operating semiconductor memory devices, which can prevent interference while narrowing the threshold voltage distribution width of memory cells during programming.

[0006] According to one embodiment of this disclosure, a selected memory cell among a plurality of memory cells is programmed by a method of operating a semiconductor memory device. The method includes executing a plurality of programming cycles. Each programming cycle includes a programming phase and a verification phase. The programming phase includes: setting the state of a selection line coupled to a selected memory block including the selected memory cell, wherein setting the state of the selection line coupled to the selected memory block includes applying a voltage to the selection line based on the programming progress state of the selected memory cell; setting the state of bit lines coupled to the selected memory block; applying a programming voltage to the selected word lines coupled to the selected memory block; and applying a voltage to the unselected word lines coupled to the selected memory block.

[0007] In one embodiment, each of the plurality of memory cells may be able to store N bits of data. Setting the state of the selection line coupled to the selected memory block may include: checking the programming state in the verification phase of the immediately preceding programming cycle when its programming has been completed; and when to be programmed to the first programming state to the (2) N-1) When the programming of the memory cell in the i-th programming state is not completed, a first voltage is applied to the select line. Here, N can be a natural number greater than 1, and i can be greater than 0 and less than (2π / 2). N A natural number of -1.

[0008] In one embodiment, setting the state of the selection line coupled to the selected memory block may include: when the programming of the memory cell to be programmed to the i-th programming state is completed, applying a second voltage to the selection line, the second voltage being different from the first voltage.

[0009] In one embodiment, the selection line can be a drain selection line.

[0010] In one embodiment, the selection line can be a source selection line.

[0011] In one embodiment, the second voltage may be less than the first voltage.

[0012] In one embodiment, the second voltage may be greater than the first voltage.

[0013] In one embodiment, N can be 2, and i can be 2.

[0014] In one embodiment, N can be 3 and i can be 6.

[0015] In one embodiment, the verification phase may include: applying a pre-verification voltage to a word line coupled to a selected memory cell; and applying a main verification voltage to the word line coupled to the selected memory cell, the main verification voltage being greater than the pre-verification voltage.

[0016] In one embodiment, the verification phase may further include: identifying memory cells with a threshold voltage higher than the main verification voltage as programmable disabled cells.

[0017] In one embodiment, the verification phase may further include: identifying memory cells having a threshold voltage lower than the pre-verification voltage as first programming-enabled cells; and identifying memory cells having a threshold voltage higher than the pre-verification voltage and lower than the main verification voltage as second programming-enabled cells.

[0018] In one embodiment, setting the state of a bit line coupled to a selected memory block may include: applying a first programming enable voltage to a bit line coupled to a first programming enable cell; and applying a second programming enable voltage to a bit line coupled to a second programming enable cell, the second programming enable voltage being greater than the first programming enable voltage.

[0019] In one embodiment, setting the state of a bit line coupled to a selected memory block including a selected memory cell may further include: applying a programming disable voltage to the bit line coupled to the programming disable cell, the programming disable voltage being greater than a second programming enable voltage.

[0020] According to another embodiment of this disclosure, a semiconductor memory device includes: a memory block comprising a plurality of memory cells, each memory cell capable of storing N bits of data; peripheral circuitry configured to perform a programming operation on a selected memory cell among the plurality of memory cells included in the memory block; and control logic circuitry configured to control the programming operation performed on the selected memory cell. The programming operation includes a plurality of programming cycles, each programming cycle including a programming phase and a verification phase. In the programming phase, the control logic circuitry is configured to control the peripheral circuitry to: set the state of a selected line coupled to the memory block based on the programming progress state of the selected memory cell; set the state of a bit line coupled to the selected memory block; and apply a programming voltage to the selected word lines coupled to the selected memory block, and apply a voltage to unselected word lines. Here, N is a natural number greater than 1.

[0021] In one embodiment, the control logic circuitry can be configured to control peripheral circuitry to set the state of a selection line coupled to the memory block based on the programming progress state of the selected memory cell by: checking the programming state in the verification phase of the immediately preceding programming cycle when its programming is completed; and when to be programmed to the first programming state up to the (2)th programming cycle. N -1) When the programming of the memory cell in the i-th programming state is not complete, the peripheral circuit is controlled to apply a first voltage to the select line. Here, i can be greater than 0 and less than (2... N A natural number of -1.

[0022] In one embodiment, the control logic circuitry can be configured to set the state of the selection line coupled to the memory block based on the programming progress state of the selected memory cell by controlling the peripheral circuitry to apply a second voltage to the selection line, the second voltage being different from the first voltage, when the programming of the memory cell to be programmed to the i-th programming state is completed.

[0023] In one embodiment, the selection line can be a drain selection line, and the second voltage can be less than the first voltage.

[0024] In one embodiment, during the verification phase, the control logic circuitry can be configured to control peripheral circuitry to apply a pre-verification voltage to a word line coupled to the selected memory cell and to apply a main verification voltage to the word line coupled to the selected memory cell, the main verification voltage being greater than the pre-verification voltage. The control logic circuitry can identify memory cells having a threshold voltage higher than the main verification voltage as programming-disabled cells, memory cells having a threshold voltage lower than the pre-verification voltage as first programming-enabled cells, and memory cells having a threshold voltage higher than the pre-verification voltage and lower than the main verification voltage as second programming-enabled cells.

[0025] In one embodiment, the control logic circuitry may be configured to control peripheral circuitry during the process of setting the state of a bit line coupled to a selected memory block, to apply a first programming enable voltage to a bit line coupled to a first programming enable cell, apply a second programming enable voltage greater than the first programming enable voltage to a bit line coupled to a second programming enable cell, and apply a programming disable voltage greater than the second programming enable voltage to a bit line coupled to a programming disable cell.

[0026] This technology can provide a semiconductor memory device and its operation method that can narrow the threshold voltage distribution width of memory cells during programming while preventing interference. Attached Figure Description

[0027] Figure 1 This is a block diagram illustrating a memory system including a semiconductor memory device and a controller according to an embodiment of the present disclosure.

[0028] Figure 2 It's a diagram. Figure 1 A block diagram of a semiconductor memory device.

[0029] Figure 3 It's a diagram. Figure 2 A diagram illustrating one embodiment of a memory cell array.

[0030] Figure 4 It's a diagram. Figure 3 The circuit diagram of any memory block BLKa among memory blocks BLK1 to BLKz.

[0031] Figure 5 It's a diagram. Figure 3 A circuit diagram of another embodiment of any memory block BLKb among memory blocks BLK1 to BLKz.

[0032] Figure 6 It is illustrated in Figure 2A circuit diagram of an embodiment of any one of the memory blocks BLKc among the plurality of memory blocks BLK1 to BLKz included in the memory cell array 110.

[0033] Figure 7 It is a diagram illustrating the multiple programming loops included in the programming operation, as well as the programming and verification phases included in each programming loop.

[0034] Figure 8 This is a flowchart illustrating a method of operating a semiconductor memory device according to an embodiment of the present disclosure.

[0035] Figure 9 It's a diagram. Figure 8 A flowchart of an embodiment of step S110.

[0036] Figure 10 It is a graph illustrating the threshold voltage distribution after programming operations of a single-level cell (SLC).

[0037] Figure 11 It's a diagram. Figure 9 A flowchart of an embodiment of step S210.

[0038] Figure 12 It's a diagram. Figure 9 A flowchart of an embodiment of step S250.

[0039] Figure 13 This is a diagram illustrating the threshold voltages of the programming enable and programming disable units.

[0040] Figure 14 It is a graph illustrating the verification operation using the pre-verification voltage Vvf_p and the main verification voltage Vvf_m according to an embodiment of the present disclosure.

[0041] Figure 15 It's a diagram. Figure 9 A flowchart of another embodiment of step S250.

[0042] Figure 16 It's a diagram. Figure 9 A flowchart of another embodiment of step S210.

[0043] Figure 17 It is a diagram illustrating the threshold voltages of the first programming enable unit, the second programming enable unit, and the programming disable unit.

[0044] Figure 18 It is a graph illustrating the threshold voltage distribution after programming operations of the multi-level cell (MLC).

[0045] Figure 19This is a timing diagram illustrating programming operations according to an embodiment of the present disclosure.

[0046] Figure 20 It's a diagram. Figure 9 A flowchart of an embodiment of step S200.

[0047] Figure 21A This is a timing diagram illustrating the operation of a semiconductor memory device according to one embodiment when the programming of a memory cell to be programmed to the i-th programming state is not completed.

[0048] Figure 21B This is a timing diagram illustrating the operation of a semiconductor memory device according to one embodiment when the programming of a memory cell to be programmed to the i-th programming state is completed.

[0049] Figure 22 The illustration shows, on the other hand, based on the reference. Figure 21A and Figure 21B A graph illustrating a method of operating a semiconductor memory device according to an embodiment of the present disclosure.

[0050] Figure 23A This is a timing diagram illustrating the operation of a semiconductor memory device according to another embodiment when the programming of a memory cell to be programmed to the i-th programming state is not completed.

[0051] Figure 23B This is a timing diagram illustrating the operation of a semiconductor memory device according to another embodiment when the programming of a memory cell to be programmed to the i-th programming state is completed.

[0052] Figure 24 The illustration shows, on the other hand, based on the reference. Figure 23A and Figure 23B A graph illustrating a method of operating a semiconductor memory device according to an embodiment of the present disclosure.

[0053] Figure 25 It's a diagram. Figure 9 A flowchart of another embodiment of step S200.

[0054] Figure 26 It's a diagram. Figure 1 A block diagram of an example controller shown.

[0055] Figure 27 It's a diagram. Figure 26 A block diagram illustrating an application example of a memory system.

[0056] Figure 28 It is illustrated, including references. Figure 27 A block diagram of the computing system describing the memory system. Detailed Implementation

[0057] The specific structural or functional descriptions disclosed in this specification depict embodiments based on the concept of this disclosure. These embodiments may take various different forms and should not be construed as being limited to the specific forms described herein.

[0058] Figure 1 This is a block diagram illustrating a memory system 1000 including a semiconductor memory device 100 and a controller 200 according to an embodiment of the present disclosure.

[0059] refer to Figure 1 The memory system 1000 includes a semiconductor memory device 100 and a controller 200. Additionally, the memory system 1000 communicates with a host 300. The controller 200 controls the overall operation of the semiconductor memory device 100. Furthermore, the controller 200 controls the operation of the semiconductor memory device 100 based on commands received from the host 300.

[0060] Figure 2 It's a diagram. Figure 1 Block diagram of semiconductor memory device 100.

[0061] refer to Figure 2 The semiconductor memory device 100 includes a memory cell array 110, an address decoder 120, a read and write circuit 130, a control logic circuit 140, and a voltage generator 150.

[0062] The memory cell array 110 includes multiple memory blocks BLK1 to BLKz. The multiple memory blocks BLK1 to BLKz are connected to the address decoder 120 via word lines WL. The multiple memory blocks BLK1 to BLKz are connected to read and write circuitry 130 via bit lines BL1 to BLm. Each of the multiple memory blocks BLK1 to BLKz includes multiple memory cells. In one embodiment, the multiple memory cells are non-volatile memory cells and may be composed of non-volatile memory cells with a vertical channel structure. The memory cell array 110 can be configured as a two-dimensional memory cell array. According to one embodiment, the memory cell array 110 can be configured as a three-dimensional memory cell array. Furthermore, each memory cell included in the memory cell array can store at least one bit of data. In one embodiment, each memory cell included in the memory cell array 110 can be a single-level cell (SLC) storing one bit of data. In another embodiment, each memory cell included in the memory cell array 110 can be a multi-level cell (MLC) storing two bits of data. In another embodiment, each memory cell in the plurality of memory cells included in the memory cell array 110 may be a tertiary cell storing three bits of data. In yet another embodiment, each memory cell in the plurality of memory cells included in the memory cell array 110 may be a quadrilateral cell storing four bits of data. According to one embodiment, the memory cell array 110 may include a plurality of memory cells, each storing five or more bits of data.

[0063] Address decoder 120, read and write circuitry 130, and voltage generator 150 operate as peripheral circuitry driving memory cell array 110. Address decoder 120 is connected to memory cell array 110 via word line WL. Address decoder 120 is configured to operate in response to control of control logic circuitry 140. Address decoder 120 receives addresses via input / output buffers (not shown) within semiconductor memory device 100.

[0064] Address decoder 120 is configured to decode block addresses among received addresses. Address decoder 120 selects at least one memory block based on the decoded block address. Additionally, during a read operation, address decoder 120 applies a read voltage Vread generated by voltage generator 150 to the selected word line of the selected memory block and applies a voltage Vpass to the remaining unselected word lines. Additionally, during a program verification operation, address decoder 120 applies a verification voltage generated by voltage generator 150 to the selected word line of the selected memory block and applies a voltage Vpass to the remaining unselected word lines.

[0065] Address decoder 120 is configured to decode the column address of the received address. Address decoder 120 sends the decoded column address to read and write circuitry 130.

[0066] Read and programming operations of the semiconductor memory device 100 are performed on a page-by-page basis. The address received when requesting a read or programming operation includes a block address, a row address, and a column address. The address decoder 120 selects a memory block and a word line based on the block and row addresses. The column address is decoded by the address decoder 120 and provided to the read and write circuitry 130.

[0067] Address decoder 120 may include block decoder, row decoder, column decoder, address buffer, etc.

[0068] The read and write circuit 130 includes multiple page buffers PB1 to PBm. The read and write circuit 130 can operate as a "read circuit" during read operations of the memory cell array 110 and as a "write circuit" during write operations of the memory cell array 110. The multiple page buffers PB1 to PBm are connected to the memory cell array 110 via bit lines BL1 to BLm. During read and program verification operations, in order to sense the threshold voltage of the memory cell, the multiple page buffers PB1 to PBm continuously supply sensing current to the bit lines connected to the memory cell, sense changes in the amount of current flowing according to the programming state of the corresponding memory cell through sensing nodes, and latch the sensed changes as sensed data. The read and write circuit 130 operates in response to a page buffer control signal output from the control logic circuit 140.

[0069] During a read operation, the read and write circuit 130 senses the data in the memory cell, temporarily stores the read data, and outputs the data DATA to the input / output buffer (not shown) of the semiconductor memory device 100. In one embodiment, in addition to a page buffer (or page register), the read and write circuit 130 may also include a column select circuit, etc.

[0070] Control logic circuitry 140 is connected to address decoder 120, read and write circuitry 130, and voltage generator 150. Control logic circuitry 140 receives commands CMD and control signals CTRL via input / output buffers (not shown) of semiconductor memory device 100. Control logic circuitry 140 is configured to control the overall operation of semiconductor memory device 100 in response to control signal CTRL. Additionally, control logic circuitry 140 outputs control signals to adjust the precharge potential levels of sensing nodes in multiple page buffers PB1 to PBm. Control logic circuitry 140 can control read and write circuitry 130 to perform read operations on memory cell array 110.

[0071] Voltage generator 150 generates a read voltage Vread and a pass voltage Vpass during a read operation in response to a control signal output from control logic circuit 140. To generate multiple voltages with various voltage levels, voltage generator 150 may include multiple pump capacitors that receive an internal power supply voltage, and multiple voltages are generated by selectively activating the multiple pump capacitors in response to control of control logic circuit 140. As described above, voltage generator 150 may include a charge pump, and the charge pump may include the aforementioned multiple pump capacitors. The specific configuration of the charge pump included in voltage generator 150 can be designed in various ways as needed.

[0072] The address decoder 120, read and write circuitry 130, and voltage generator 150 can be used as "peripheral circuitry" to perform read, write, and erase operations on the memory cell array 110. The peripheral circuitry performs these operations based on the control logic circuitry 140.

[0073] Figure 3 It's a diagram. Figure 2 A diagram illustrating one embodiment of the memory cell array 110.

[0074] refer to Figure 3 The memory cell array 110 includes multiple memory blocks BLK1 to BLKz. Each memory block may have a three-dimensional structure. Each memory block includes multiple memory cells stacked on a substrate. These multiple memory cells are arranged along the +X, +Y, and +Z directions. (Reference) Figure 4 and Figure 5 The structure of each memory block is described in more detail.

[0075] Figure 4 It's a diagram. Figure 3 The circuit diagram of any one of the memory blocks BLKa from BLK1 to BLKz.

[0076] refer to Figure 4 The memory block BLKa comprises multiple cell strings CS11 to CS1m and CS21 to CS2m. In one embodiment, each of the multiple cell strings CS11 to CS1m and CS21 to CS2m can be formed in a "U" shape. In the memory block BLKa, m cell strings are arranged along the row direction (i.e., the +X direction). Figure 4 In this diagram, two unit strings are arranged along the column direction (i.e., the +Y direction). However, this is for ease of description; it can be understood that three or more unit strings can be arranged along the column direction.

[0077] Each of the multiple cell strings CS11 to CS1m and CS21 to CS2m includes at least one source selection transistor SST, first to nth memory cells MC1 to MCn, a pipe transistor PT, and at least one drain selection transistor DST.

[0078] The selector transistors SST and DST, and each of the memory cells MC1 to MCn, can have similar structures. In one embodiment, each of the selector transistors SST and DST, and each of the memory cells MC1 to MCn, may include a channel layer, a tunneling insulating film, a charge storage film, and a barrier insulating film. In one embodiment, a pillar for providing the channel layer may be provided in each cell string. In one embodiment, a pillar for providing at least one of the following may be provided in each cell string: a channel layer, a tunneling insulating film, a charge storage film, and a barrier insulating film.

[0079] The source selection transistor SST of each cell string is connected between the common source line CSL and memory cells MC1 to MCp.

[0080] In one embodiment, source select transistors of cell strings arranged in the same row are connected to source select lines extending along the row direction, and source select transistors of cell strings arranged in different rows are connected to different source select lines. Figure 4 In the first row, the source selection transistors CS11 to CS1m are connected to the first source selection line SSL1. The source selection transistors CS21 to CS2m in the second row are connected to the second source selection line SSL2.

[0081] In another embodiment, the source selection transistors of cell strings CS11 to CS1m and CS21 to CS2m can be connected together to a single source selection line.

[0082] The first to nth memory cells MC1 to MCn of each cell string are connected between the source selection transistor SST and the drain selection transistor DST.

[0083] The first to nth memory cells MC1 to MCn can be divided into the first to pth memory cells MC1 to MCp and the (p+1)th to nth memory cells MCp+1 to MCn. The first to pth memory cells MC1 to MCp are arranged sequentially in the direction opposite to the +Z direction and are connected in series between the source selection transistor SST and the channel transistor PT. The (p+1)th to nth memory cells MCp+1 to MCn are arranged sequentially in the +Z direction and are connected in series between the channel transistor PT and the drain selection transistor DST. The first to pth memory cells MC1 to MCp and the (p+1)th to nth memory cells MCp+1 to MCn are connected to each other through the channel transistor PT. The gates of the first to nth memory cells MC1 to MCn in each cell string are respectively connected to the first to nth word lines WL1 to WLn.

[0084] The gate of the pipe transistor PT in each cell string is connected to the pipe line PL.

[0085] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and memory cells MCp+1 to MCn. The drain select transistors of the cell strings arranged along the row direction are connected to drain select lines extending along the row direction. The drain select transistors of the cell strings CS11 to CS1m in the first row are connected to the first drain select line DSL1. The drain select transistors of the cell strings CS21 to CS2m in the second row are connected to the second drain select line DSL2.

[0086] The cell strings arranged along the column direction are connected to bit lines extending along the column direction. Figure 4 In the diagram, the cell strings CS11 and CS21 of the first column are connected to the first bit line BL1. The cell strings CS1m and CS2m of the m-th column are connected to the m-th bit line BLm.

[0087] Memory cells connected to the same word line in a cell string arranged along a row constitute a page. For example, memory cells in cell strings CS11 to CS1m in the first row connected to the first word line WL1 constitute one page. Memory cells in cell strings CS21 to CS2m in the second row connected to the first word line WL1 constitute another page. A cell string arranged in a row direction can be selected by choosing either the drain select line DSL1 or DSL2. A page of the selected cell string can be selected by choosing any of the word lines WL1 to WLn.

[0088] In another embodiment, even-numbered bit lines and odd-numbered bit lines can be provided instead of the first to m-th bit lines BL1 to BLm. Additionally, even-numbered cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged along the row direction can be connected to the even-numbered bit lines, and odd-numbered cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged along the row direction can be connected to the odd-numbered bit lines.

[0089] In one embodiment, at least one of the first to nth memory cells MC1 to MCn can be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCp. Alternatively, at least one dummy memory cell is provided to reduce the electric field between the drain selection transistor DST and the memory cells MCp+1 to MCn. When more dummy memory cells are provided, the reliability of operation of the memory block BLKa is improved; however, the size of the memory block BLKa increases. When fewer dummy memory cells are provided, the size of the memory block BLKa can be reduced; however, the reliability of operation of the memory block BLKa may decrease.

[0090] To efficiently control at least one dummy memory cell, each dummy memory cell can have a desired threshold voltage. Programming operations can be performed on all or some of the dummy memory cells before or after an erase operation on the memory block BLKa. When an erase operation is performed after the programming operation, the dummy memory cells can have a desired threshold voltage by controlling the voltage applied to the dummy word line connected to the corresponding dummy memory cell.

[0091] Figure 5 It's a diagram. Figure 3 A circuit diagram of another embodiment of any memory block BLKb among memory blocks BLK1 to BLKz.

[0092] refer to Figure 5 The memory block BLKb includes multiple cell strings CS11' to CS1m' and CS21' to CS2m'. Each of the multiple cell strings CS11' to CS1m' and CS21' to CS2m' extends along the +Z direction. Each of the multiple cell strings CS11' to CS1m' and CS21' to CS2m' includes at least one source selection transistor SST, first to nth memory cells MC1 to MCn, and at least one drain selection transistor DST stacked on a substrate (not shown) below the memory block BLKb.

[0093] The source select transistor SST of each cell string is connected between the common source line CSL and memory cells MC1 to MCn. Source select transistors of cell strings arranged in the same row are connected to the same source select line. The source select transistors of cell strings CS11' to CS1m' arranged in the first row are connected to the first source select line SSL1. The source select transistors of cell strings CS21' to CS2m' arranged in the second row are connected to the second source select line SSL2. In another embodiment, the source select transistors of cell strings CS11' to CS1m' and CS21' to CS2m' may be connected to a common source select line.

[0094] The first to nth memory cells MC1 to MCn of each cell string are connected in series between the source select transistor SST and the drain select transistor DST. The gates of the first to nth memory cells MC1 to MCn are respectively connected to the first to nth word lines WL1 to WLn.

[0095] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and memory cells MC1 to MCn. The drain select transistors of cell strings arranged along the row direction are connected to drain select lines extending along the row direction. The drain select transistors of cell strings CS11' to CS1m' in the first row are connected to the first drain select line DSL1. The drain select transistors of cell strings CS21' to CS2m' in the second row are connected to the second drain select line DSL2.

[0096] result, Figure 5 The memory block BLKb represents the memory block with Figure 4 The circuitry of the memory block BLKa is similar, except that the pipe transistor PT is excluded from each cell string of the memory block BLKb.

[0097] In another embodiment, even-numbered bit lines and odd-numbered bit lines can be provided instead of the first to m-th bit lines BL1 to BLm. Additionally, even-numbered cell strings in the row-oriented cell strings CS11' to CS1m' or CS21' to CS2m' can be connected to the even-numbered bit lines, and odd-numbered cell strings in the row-oriented cell strings CS11' to CS1m' or CS21' to CS2m' can be connected to the odd-numbered bit lines.

[0098] In one embodiment, at least one of the first to nth memory cells MC1 to MCn can be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCn. Alternatively, at least one dummy memory cell is provided to reduce the electric field between the drain selection transistor DST and the memory cells MC1 to MCn. When more dummy memory cells are provided, the operational reliability of the memory block BLKb is improved; however, the size of the memory block BLKb increases. When fewer dummy memory cells are provided, the size of the memory block BLKb can be reduced; however, the operational reliability of the memory block BLKb decreases.

[0099] To efficiently control at least one dummy memory cell, each dummy memory cell can have a desired threshold voltage. Programming operations can be performed on all or some of the dummy memory cells before or after an erase operation on the memory block BLKb. When an erase operation is performed after a programming operation, the dummy memory cell can have a desired threshold voltage by controlling the voltage applied to the dummy word line connected to the corresponding dummy memory cell.

[0100] Figure 6 It is illustrated in Figure 2 A circuit diagram of an embodiment of any one of the memory blocks BLKc among the plurality of memory blocks BLK1 to BLKz included in the memory cell array 110.

[0101] refer to Figure 6 The memory block BLKc comprises multiple cell strings CS1 to CSm. These cell strings CS1 to CSm can be connected to multiple bit lines BL1 to BLm respectively. Each cell string CS1 to CSm includes at least one source select transistor SST, first to nth memory cells MC1 to MCn, and at least one drain select transistor DST.

[0102] The selector transistors SST and DST, and each of the memory cells MC1 to MCn, can have similar structures. In one embodiment, each of the selector transistors SST and DST, and each of the memory cells MC1 to MCn, may include a channel layer, a tunneling insulating film, a charge storage film, and a barrier insulating film. In one embodiment, pillars for providing the channel layer may be provided in each cell string. In one embodiment, pillars for providing at least one of the following may be provided in each cell string: a channel layer, a tunneling insulating film, a charge storage film, and a barrier insulating film.

[0103] The source selection transistor SST of each cell string is connected between the common source line CSL and the memory cells MC1 to MCn.

[0104] The first to nth memory cells MC1 to MCn of each cell string are connected between the source selection transistor SST and the drain selection transistor DST.

[0105] The drain selection transistor (DST) of each cell string is connected between the corresponding bit line and the memory cells MC1 to MCn.

[0106] Memory cells connected to the same word line constitute a page. Cell strings CS1 to CSm can be selected by choosing the drain select line DSL. A page within the selected cell string can be selected by choosing any of the word lines WL1 to WLn.

[0107] In another embodiment, even-numbered bit lines and odd-numbered bit lines can be provided instead of the first to m-th bit lines BL1 to BLm. The even-numbered cell strings in the cell strings CS1 to CSm can be connected to the even-numbered bit lines, and the odd-numbered cell strings can be connected to the odd-numbered bit lines respectively.

[0108] Figure 7 It is a diagram illustrating the multiple programming loops included in the programming operation, as well as the programming and verification phases included in each programming loop.

[0109] refer to Figure 7 Programming operations can include multiple programming loops. For example... Figure 7 As shown, programming operations can be performed by executing the first programming loop 1. st Let's begin with the PGM Loop. Even if it's the first programming loop 1... st If the PGM Loop is executed and programming of the selected memory cell is not yet complete, the second programming loop can be executed. nd PGM Loop. Even in the second programming loop 2 nd If the PGM Loop is executed and programming of the selected memory cell is not yet complete, the third programming loop can be executed. rd PGM Loop. In this way, the programming loop can be repeated until the programming operation is complete.

[0110] At the same time, if the programming operation is not completed even after the programming loop has been repeated a predetermined maximum number of times, it can be determined that the programming operation has failed.

[0111] Figure 8 This is a flowchart illustrating a method of operating a semiconductor memory device according to an embodiment of the present disclosure. Selected memory cells are programmed using this method of operating a semiconductor memory device according to an embodiment of the present disclosure. Reference Figure 8The method includes: performing a programming cycle (S110) on memory cells among selected memory cells to be programmed to a target threshold voltage state, and determining whether programming of the selected memory cells is complete (S130). Step S110 includes the following operations: adjusting the voltage of the bit lines connected to the programming enable and programming disable cells in the selected memory cells, respectively, and increasing the threshold voltage of the programming enable cells by applying a programming voltage to the word lines connected to the programming enable cells. Additionally, step S110 also includes the following operations: after applying the programming voltage to the word lines connected to the selected memory cells, determining whether the threshold voltage of each memory cell is greater than a verification voltage by applying a verification voltage to the word lines connected to the selected memory cells. (Reference) Figure 9 An embodiment of step S110 will be described in more detail below.

[0112] Meanwhile, the method of operating a semiconductor memory device according to an embodiment of the present disclosure further includes: when programming of the selected memory cell is completed (S130: Yes), determining that the programming operation of the selected memory cell is successful (S140).

[0113] Additionally, a method for operating a semiconductor memory device according to an embodiment of this disclosure further includes: when programming of a selected memory cell is incomplete (S130: No), determining whether the number of currently executed programming loops is less than a maximum number of loops (S150). During the programming operation of the selected memory cell, the programming loop of step S110 can be executed multiple times. However, to prevent the programming loop of the selected memory cell from repeating indefinitely, a maximum number of loops can be set. Each time a programming loop is executed, the number of executed programming loops increases by one. In the case where programming of the selected memory cell is incomplete (S130: No), when the number of executed programming loops is less than the maximum number of loops (S150: Yes), the method returns to step S110, and the programming loop is executed again.

[0114] Meanwhile, the method of operating a semiconductor memory device according to an embodiment of the present disclosure further includes: determining that the programming operation on the selected memory cell has failed (S170) when the number of currently executed programming loops is not less than the maximum number of loops (S150: No). That is, if the programming of the selected memory cell is not completed (S130: No), when the number of executed programming loops is greater than or equal to the maximum number of loops (S150: No), the programming loops are no longer executed, and it is determined that the programming operation on the selected memory cell has failed (S170).

[0115] As described above, in a method for operating a semiconductor memory device according to an embodiment of the present disclosure, a programming loop is repeatedly executed until programming of the selected memory cell is completed. However, if programming is not completed even when the number of currently executed programming loops reaches the maximum number of loops, it is determined that the programming operation on the selected memory cell has failed.

[0116] Figure 9 It's illustrated in more detail. Figure 8 A flowchart of an embodiment of step S110. Figure 10 It is a graph illustrating the threshold voltage distribution after the SLC programming operation. Figure 11 It's illustrated in more detail. Figure 9 A flowchart of one embodiment of step S210. Referring hereafter, together with the above... Figures 9 to 11 This describes the steps for setting the state of the bit lines connected to the selected memory cell.

[0117] refer to Figure 9 The programming cycle (S110) performed on the selected memory cell to be programmed to the target threshold voltage state includes: setting the state of the selection line connected to the selection transistor included in the selected memory block (S200), setting the state of the bit line connected to the selected memory cell (S210), applying the programming voltage to the word line connected to the memory cell (S230), and performing a verification operation on the selected memory cell (S250).

[0118] In this instruction manual, the selection line can be referred to as a reference. Figures 4 to 6 At least one of the drain select line DSL and source select line SSL described. That is, in step S200, the state of at least one of the drain select line DSL and source select line SSL connected to the selected memory block including the programming target memory cell can be set. More specifically, in step S200, a specific voltage can be applied to at least one of the drain select line DSL and source select line SSL connected to the selected memory block.

[0119] Among the selected memory cells, one or more memory cells whose threshold voltage increases during the current programming cycle are programming enable cells, and one or more memory cells whose threshold voltage is maintained are programming disable cells. Both programming enable and programming disable cells are applied to the same word line. When a programming voltage is applied to the word line, the bit line voltage is adjusted to increase the threshold voltage of the programming enable cells and maintain the threshold voltage of the programming disable cells. In step S210, the voltages of the bit lines connected to the programming enable cells and the bit lines connected to the programming disable cells are adjusted. Figure 11As shown, step S210 includes: applying a programming enable voltage to a bit line connected to a programming enable unit (S211), and applying a programming disable voltage to a bit line connected to a programming disable unit (S213). In one embodiment, the programming disable voltage may be greater than the programming enable voltage. For example, the programming enable voltage may be a ground voltage. Meanwhile, in Figure 11 In this embodiment, step S213 is executed after step S211; however, this disclosure is not limited thereto. That is, according to one embodiment, step S211 may be executed after step S213, or steps S211 and S213 may be executed simultaneously.

[0120] refer to Figure 10 After the SLC programming operation, the threshold voltage distribution can be divided into erase state E and programming state PVA. During the read operation, the read voltage Ra is used to determine whether the memory cell is in erase state E or programming state PVA. Simultaneously, the threshold voltage of the memory cell to be programmed into programming state PVA is greater than the verification voltage Vvfa.

[0121] In the initial phase of the programming operation, all selected memory cells can have a threshold voltage for the erase state E. Among the selected memory cells, those that need to remain in the erase state E become programming-disabled cells from the initial phase of the programming operation. Simultaneously, among the selected memory cells, all memory cells to be programmed into the programming state PVA become programming-enabled cells from the initial phase of the programming operation.

[0122] In the state where a programming enable voltage is applied to the bit line connected to the programming enable unit (S211) and a programming disable voltage is applied to the bit line connected to the programming disable unit (S213), when a programming voltage is applied to the word line connected to the selected memory cell (S230), the threshold voltage of the programming enable unit increases, and the threshold voltage of the programming disable unit is maintained. Subsequently, a verification operation (S250) is performed on the selected memory cell to determine whether the threshold voltage of the memory cell to be programmed to the programming state PVA is greater than the verification voltage Vvfa.

[0123] As described above, in the initial stage of the programming operation, all threshold voltages of the memory cells to be programmed into the programming state PVA can be less than the verification voltage Vvfa. Therefore, in the initial stage of the programming operation, all memory cells to be programmed into the programming state PVA become programming-enabled cells. As the programming cycle is repeatedly executed, the threshold voltages of the programming-enabled cells increase. Therefore, the threshold voltages of some programming-enabled cells become greater than the verification voltage Vvfa. When the verification operation (S250) is performed on the selected memory cells, the state of the programming-enabled cells with threshold voltages greater than the verification voltage Vvfa is changed to programming-disabled cells. Therefore, in subsequent programming cycles, the threshold voltages of the corresponding memory cells no longer increase.

[0124] Furthermore, according to one embodiment of this disclosure, the programming operation can be performed using the Incremental Step Pulse Programming (ISPP) method. The ISPP method programs a memory cell while gradually increasing the programming voltage. As the programming cycle is repeated, the programming voltage applied to the word line connected to the memory cell selected in step S230 can be gradually increased.

[0125] Figure 12 It's illustrated in more detail. Figure 9 A flowchart of an embodiment of step S250.

[0126] refer to Figure 12 The verification operation (S250) performed on the selected memory cell includes: applying a verification voltage Vvfa to the word line connected to the selected memory cell (S251); identifying memory cells with a threshold voltage higher than the verification voltage Vvfa among the memory cells to be programmed into programming state PVA as programming disabled cells (S253); and identifying memory cells with a threshold voltage lower than the verification voltage Vvfa among the memory cells to be programmed into programming state PVA as programming enabled cells (S255).

[0127] That is, after the programming voltage is applied to the word line connected to the selected memory cell (S230), it is determined whether the threshold voltage of the programming enable cell becomes higher than the verification voltage Vvfa. To do this, by applying the verification voltage Vvfa to the selected word line (S251), it is determined whether the threshold voltage of the programming enable cell in the selected memory cell is greater than the verification voltage Vvfa.

[0128] In step S253, among the memory cells to be programmed into the programming state PVA, memory cells with a threshold voltage higher than the verification voltage Vvfa are identified as programming-prohibited cells. Figure 10As shown, memory cells with a threshold voltage higher than the verification voltage Vvfa are memory cells that are fully programmed to belong to the programming state PVA. Therefore, memory cells with a threshold voltage higher than the verification voltage Vvfa are identified as programming-inhibited cells so that the threshold voltage is not increased in subsequent programming cycles.

[0129] In step S255, among the memory cells to be programmed into the programming state PVA, memory cells with a threshold voltage lower than the verification voltage Vvfa are identified as programming-enabled cells. Figure 10 As shown, memory cells with a threshold voltage lower than the verification voltage Vvfa are memory cells that are not yet in the programming state PVA and are memory cells that require additional programming. Therefore, memory cells with a threshold voltage lower than the verification voltage Vvfa are identified as programming-enabled cells so that the threshold voltage can be increased in subsequent programming cycles.

[0130] Figure 13 This is a diagram illustrating the threshold voltages of the programming enable and programming disable units.

[0131] refer to Figure 13 The threshold voltage of the memory cell at location A is lower than the verification voltage Vvfa. Therefore, the memory cell at location A is a programmable cell. In the next programming cycle, the threshold voltage of the programmable cell can be increased, and thus the programmable cell can move to location B. The threshold voltage of the memory cell at location B is higher than the verification voltage Vvfa. Therefore, the memory cell moved to location B due to the programming cycle is identified as a programmable inactive cell, and the threshold voltage does not increase in the next programming cycle.

[0132] According to the reference Figure 10 and Figure 13 In the described embodiments, even in the case of memory cells with a threshold voltage slightly lower than the verification voltage Vvfa, the threshold voltage shifts by a width similar to that of other programming-enabled cells. This results in a wide distribution of the threshold voltage range for memory cells belonging to the programming state PVA after the programming operation. According to another embodiment of this disclosure, by using a pre-verification voltage and a main verification voltage instead of a single verification voltage, the threshold voltage shift width of programming-enabled cells with threshold voltages close to the main verification voltage can be reduced. Consequently, the distribution width of the threshold voltage for memory cells belonging to the programming state PVA after the programming operation can be reduced.

[0133] Figure 14This is a graph illustrating a verification operation using a pre-verification voltage Vvf_p and a main verification voltage Vvf_m according to an embodiment of the present disclosure. According to an embodiment of the present disclosure, the pre-verification voltage Vvf_p and the main verification voltage Vvf_m can be used to determine the threshold voltage state of a memory cell to be programmed into a programming state PVA. Figure 14 The main verification voltage Vvf_m can be compared with Figure 10 The verification voltage Vvfa is essentially the same. According to one embodiment of this disclosure, by additionally using a pre-verification voltage Vvf_p in addition to the main verification voltage Vvf_m, the threshold voltage distribution of the memory cell can be reduced after the programming operation.

[0134] Figure 15 It's illustrated in more detail. Figure 9 A flowchart of another embodiment of step S250.

[0135] refer to Figure 15 The verification operation (S250) performed on the selected memory cell includes: applying a pre-verification voltage Vvf_p to the word line connected to the selected memory cell (S311), applying a main verification voltage Vvf_m to the word line connected to the selected memory cell (S313), identifying memory cells in the memory cells to be programmed into programming state PVA that have a threshold voltage higher than the main verification voltage Vvf_m as programming disabled cells (S315), identifying memory cells in the memory cells to be programmed into programming state PVA that have a threshold voltage lower than the pre-verification voltage Vvf_p as first programming enabled cells (S317), and identifying memory cells in the memory cells to be programmed into programming state PVA that have a threshold voltage lower than the main verification voltage Vvf_m and higher than the pre-verification voltage Vvf_p as second programming enabled cells (S319).

[0136] That is, after the programming voltage is applied to the word line connected to the selected memory cell (S230), it is determined whether the threshold voltage of the programming enable cell is lower than the pre-verification voltage Vvf_p, between the pre-verification voltage Vvf_p and the main verification voltage Vvf_m, or higher than the main verification voltage Vvf_m. To this end, by applying the pre-verification voltage Vvf_p to the selected word line (S311), it is determined whether the threshold voltage of the programming enable cell in the selected memory cell is greater than the pre-verification voltage Vvf_p. Additionally, by applying the main verification voltage Vvf_m to the selected word line (S313), it is determined whether the threshold voltage of the programming enable cell in the selected memory cell is greater than the main verification voltage Vvf_m.

[0137] In step S315, among the memory cells to be programmed into the programming state PVA, memory cells with a threshold voltage higher than the main verification voltage Vvf_m are identified as programming-disabled cells. For example... Figure 14 As shown, memory cells with a threshold voltage higher than the main verification voltage Vvf_m are memory cells that are fully programmed to belong to the programming state PVA. Therefore, memory cells with a threshold voltage higher than the main verification voltage Vvf_m are identified as programming-inhibited cells so that the threshold voltage is not increased in subsequent programming cycles.

[0138] In step S317, among the memory cells to be programmed into the programming state PVA, the memory cell having a threshold voltage lower than the pre-verification voltage Vvf_p is identified as the first programming-enabled cell. For example... Figure 14 As shown, memory cells with a threshold voltage lower than the pre-verification voltage Vvf_p are memory cells that are not yet in the programming state PVA and are memory cells that require additional programming. Therefore, memory cells with a threshold voltage lower than the pre-verification voltage Vvf_p are identified as first programming-enabled cells, so that the threshold voltage can be increased in subsequent programming cycles.

[0139] Simultaneously, in step S319, among the memory cells to be programmed into the programming state PVA, memory cells having a threshold voltage lower than the main verification voltage Vvf_m and higher than the pre-verification voltage Vvf_p are identified as second programming-enabled cells. For example... Figure 14 As shown, memory cells with a threshold voltage lower than the main verification voltage Vvf_m and higher than the pre-verification voltage Vvf_p are also memory cells that are not yet in the programming state PVA and require additional programming. Therefore, memory cells with a threshold voltage lower than the main verification voltage Vvf_m and higher than the pre-verification voltage Vvf_p are identified as second programming-enabled cells to increase the threshold voltage in subsequent programming cycles.

[0140] Let's refer to each other. Figure 14 The first programming enable cell is a memory cell having a threshold voltage lower than the pre-verification voltage Vvf_p, and the second programming enable cell is a memory cell having a threshold voltage between the pre-verification voltage Vvf_p and the main verification voltage Vvf_m. That is, the second programming enable cell has a threshold voltage closer to the main verification voltage Vvf_m than the first programming enable cell. Therefore, in a semiconductor memory device and its operation method according to an embodiment of this disclosure, in subsequent programming cycles, the threshold voltage shift width of the second programming enable cell is controlled to be smaller than the threshold voltage shift width of the first programming enable cell. For this purpose, the voltage applied to the bit line connected to the first programming enable cell and the voltage applied to the bit line connected to the second programming enable cell are applied differently. Hereinafter, reference is made to... Figure 16 To describe this disclosure.

[0141] Figure 16 It's illustrated in more detail. Figure 9 A flowchart of another embodiment of step S210. Figure 17 This is a diagram illustrating the threshold voltages of the first programming enable unit, the second programming enable unit, and the programming disable unit. It will be referenced together in the following text. Figure 16 and Figure 17 This describes the state of the bit lines that are connected to the selected memory cell.

[0142] refer to Figure 16 Step S210 may include: applying a first programming enable voltage to a bit line connected to a first programming enable unit (S331), applying a second programming enable voltage to a bit line connected to a second programming enable unit (S333), and applying a programming disable voltage to a bit line connected to a programming disable unit (S335). In one embodiment, the programming disable voltage may be greater than the second programming enable voltage, and the second programming enable voltage may be greater than the first programming enable voltage. For example, the first programming enable voltage may be a ground voltage.

[0143] Because the first programming enable voltage and the second programming enable voltage are different from each other, the threshold voltage shift width of the first programming enable unit and the second programming enable unit can be different when a programming voltage is applied to the selected word line (S230). More specifically, because the second programming enable voltage is greater than the first programming enable voltage, the threshold voltage shift width of the first programming enable unit is greater than the threshold voltage shift width of the second programming enable unit.

[0144] refer to Figure 17 The threshold voltage of the memory cell at location C is lower than the pre-verification voltage Vvf_p. Therefore, the memory cell at location C is the first programmable cell. Additionally, the threshold voltage of the memory cell at location E is higher than the pre-verification voltage Vvf_p and lower than the main verification voltage Vvf_m. Therefore, the memory cell at location E is the second programmable cell.

[0145] As described above, the first programming enable voltage applied to the bit line connected to the first programming enable unit is less than the second programming enable voltage applied to the bit line connected to the second programming enable unit. Therefore, the threshold voltage shift width of the first programming enable unit is greater than the threshold voltage shift width of the second programming enable unit. Figure 17As shown, the first programming enable cell at position C moves to position D and thus becomes a programming disable cell, while the second programming enable cell at position E moves to position F and thus becomes a programming disable cell. Because the threshold voltage shift width of the second programming enable cell at position E is smaller than the threshold voltage shift width of the first programming enable cell at position C, the threshold voltage distribution difference between the programming disable cells at positions D and F becomes smaller. As a result, the threshold voltage distribution width of the memory cell that has been programmed becomes narrower.

[0146] Figure 18 It is a graph illustrating the threshold voltage distribution after the programming operation of the MLC.

[0147] refer to Figure 18 Each memory cell stores two bits of the MLC, which, after a programming operation, belongs to any of the following states: erase state E, first programming state PV1, second programming state PV2, and third programming state PV3. According to one embodiment of this disclosure, a pre-verification voltage and a main verification voltage are used during the verification operation corresponding to each of the first to third programming states PV1 to PV3.

[0148] For example, according to one embodiment of this disclosure, during the verification operation corresponding to the first programming state PV1, a first pre-verification voltage Vvf_p1 and a first main verification voltage Vvf_m1 corresponding to the first programming state PV1 are used. Additionally, during the verification operation corresponding to the second programming state PV2, a second pre-verification voltage Vvf_p2 and a second main verification voltage Vvf_m2 corresponding to the second programming state PV2 are used. Finally, during the verification operation corresponding to the third programming state PV3, a third pre-verification voltage Vvf_p3 and a third main verification voltage Vvf_m3 corresponding to the third programming state PV3 are used.

[0149] Similarly, in the programming operation of TLC, verification operations can be performed using pre-verification voltage and main verification voltage for each programming state.

[0150] Figure 19 This is a timing diagram illustrating programming operations according to an embodiment of the present disclosure. More specifically, in Figure 7 The timing diagrams corresponding to the programming and verification phases of each programming cycle are shown below. Figure 19 As shown. Reference Figure 19 This shows the voltages of the word line WL, bit line BL, drain select line DSL, and source select line SSL connected to the selected memory block during the programming phase. See below for further details. Figure 9 and Figure 19 To describe this disclosure.

[0151] refer to Figure 19 At time t1, voltage VDSL is applied to the drain select line DSL, and voltage VSSL is applied to the source select line SSL (S200). Subsequently, at time t2, bit line voltages are applied to the bit lines connected to the selected memory block (S210). More specifically, a first bit line voltage VBL1 is applied to the bit line connected to the memory cell identified as the first programmable cell in the previous verification phase. Simultaneously, a second bit line voltage VBL2 is applied to the bit line connected to the memory cell identified as the second programmable cell in the previous verification phase. The second bit line voltage VBL2 may be greater than the first bit line voltage VBL1. Additionally, a third bit line voltage VBL3 is applied to the bit line connected to the memory cell identified as the programmable disabled cell in the previous verification phase. The third bit line voltage VBL3 may be a voltage greater than the second bit line voltage VBL2, and may be a programmable disabled voltage.

[0152] Subsequently, at time t3, a voltage Vpass can be applied to the word line connected to the selected memory block. Then, at time t4, a programming voltage Vpgm can be applied to the selected word line, which is the word line connected to the memory cell to be programmed. Through this process, the threshold voltages of the first and second programming enable cells in the selected memory cell can be increased. At this time, the increase in the threshold voltage of the first programming enable cell can be greater than the increase in the threshold voltage of the second programming enable cell.

[0153] According to one embodiment of this disclosure, during the programming phase, while the programming operation begins and the programming cycle is repeatedly executed, the voltage VDSL applied to the drain select line DSL and the voltage VSSL applied to the source select line SSL can remain constant. To improve the threshold voltage distribution characteristics of the memory cells during the programming operation, the second bit line voltage VBL2 needs to be increased, and the voltage VDSL of the drain select line DSL also needs to be increased. In this case, interference may occur due to leakage current in the drain select line DSL in the programming disable string. Therefore, a programming method that can improve the threshold voltage distribution characteristics of the memory cells while reducing interference is needed.

[0154] According to another embodiment of this disclosure, when programming verification of a memory cell for a specific programming state among a plurality of programming states is completed, the voltage applied to the select line can be reduced during the programming phase of a subsequent programming cycle. Figure 18Taking the MLC shown as an example, the important programming states are the first and second programming states PV1 and PV2 between the erase state E and the third programming state PV3. Additionally, the region experiencing the most interference during programming is the third programming state PV3, to which a relatively high programming voltage is applied. When the target cell is programmed to the third programming state PV3, the electric field on the word line increases compared to the low channel potential, thus increasing the likelihood of interference. Therefore, the operating methods before programming verification for the first and second programming states PV1 and PV2 is completed and the operating methods after programming verification for the first and second programming states PV1 and PV2 is completed can be applied differently. For example, in the programming operation of the MLC, a relatively large voltage can be applied to the select line before the programming of the memory cell to be programmed to the second programming state PV2 is completed, and a relatively small voltage can be applied to the select line after the programming of the memory cell to be programmed to the second programming state PV2 is completed.

[0155] Therefore, during the programming operation of the memory cells to be programmed into the first and second programming states PV1 and PV2, a relatively high select line voltage can be applied to improve the threshold voltage distribution of the first and second programming states PV1 and PV2. Additionally, after the programming of the memory cells to be programmed into the first and second programming states PV1 and PV2 is completed, a relatively low select line voltage can be applied to reduce programming interference by mitigating leakage current in the select transistor.

[0156] Figure 20 It's illustrated in more detail. Figure 9 A flowchart of an embodiment of step S200.

[0157] refer to Figure 20 Setting the state of the select line connected to the select transistor included in the selected memory block (S200) may include: checking the programming state (S201) in the verification phase of the preceding programming cycle to determine whether the programming of the memory cell whose target programming state is the i-th programming state is complete; when the programming of the memory cell to be programmed to the i-th programming state is not complete (S203: No), applying a first voltage to the select line connected to the select transistor (S205). Simultaneously, setting the state of the select line connected to the select transistor included in the selected memory block (S200) may include: when the programming of the memory cell to be programmed to the i-th programming state is complete (S203: Yes), applying a second voltage lower than the first voltage to the select line connected to the select transistor (S207).

[0158] The i-th programming state can be appropriately selected as needed. For example, in the case of MLC programming operation, the i-th programming state can be selected as the second programming state PV2. In this case, in step S201, the programming state whose verification was completed in the verification phase of the immediately preceding programming cycle is checked. More specifically, it is checked whether the verification of the memory cell to be programmed as the second programming state PV2 has passed. As a result of the check, when the programming of the memory cell whose target programming state is the second programming state PV2 is not completed (S203: No), a first voltage is applied to the select line connected to the select transistor (S205). Therefore, in the programming cycle of the initial stage of the programming operation, the first voltage can be applied to the select line connected to the select transistor.

[0159] Conversely, when the programming of the memory cell to be programmed to the second programming state PV2 is completed (S203: Yes), this means that the memory cell whose programming is not yet completed is the memory cell to be programmed to the third programming state PV3. Therefore, a second voltage less than the first voltage is applied to the selection line connected to the selection transistor to reduce the leakage current appearing in the selection transistor (S207).

[0160] The foregoing described the case where the i-th programming state in the MLC programming operation is the second programming state, but this disclosure is not limited thereto. In another embodiment, the i-th programming state in the MLC programming operation can be the first programming state.

[0161] Additionally, in the programming operation of the TLC, the i-th programming state can be the sixth programming state. However, this disclosure is not limited to this, and in the programming operation of the TLC, the i-th programming state can be any of the first to fifth programming states.

[0162] Meanwhile, the selection transistor in steps S205 and S207 can be either a drain selection transistor or a source selection transistor. When the selection transistor in steps S205 and S207 is a drain selection transistor, the selection line can be a drain selection line. When the selection transistor in steps S205 and S207 is a source selection transistor, the selection line can be a source selection line.

[0163] Figure 21A This is a timing diagram illustrating the operation of a semiconductor memory device according to one embodiment when the programming of a memory cell to be programmed to the i-th programming state is not completed. Figure 21B This is a timing diagram illustrating the operation of a semiconductor memory device according to one embodiment when the programming of a memory cell to be programmed to the i-th programming state is completed.

[0164] refer to Figure 21ASince the programming of the memory cell to be programmed to the i-th programming state is incomplete (S203: No), at time t5, a first voltage VDSL1 is applied to the drain select line DSL (S205), and a voltage VSSL is applied to the source select line SSL. Subsequently, at time t6, bit line voltages are applied to the bit lines connected to the selected memory block (S210). More specifically, the first bit line voltage VBL1 is applied to the bit lines connected to the memory cell identified as the first programming enabled cell in the previous verification phase. Simultaneously, a second bit line voltage VBL2 is applied to the bit lines connected to the memory cell identified as the second programming enabled cell in the previous verification phase. The second bit line voltage VBL2 may be greater than the first bit line voltage VBL1. Additionally, a third bit line voltage VBL3 is applied to the bit lines connected to the memory cell identified as the programming disabled cell in the previous verification phase. The third bit line voltage VBL3 may be a voltage greater than the second bit line voltage VBL2, and may be a programming disabled voltage.

[0165] Subsequently, at time t7, a voltage Vpass can be applied to the word line connected to the selected memory block. Then, at time t8, a programming voltage Vpgm can be applied to the selected word line, which is the word line connected to the memory cell to be programmed.

[0166] refer to Figure 21B Since the programming of the memory cell to be programmed to the i-th programming state is completed (S203: Yes), at time t9, the second voltage VDSL2 is applied to the drain selection line DSL, and the voltage VSSL is applied to the source selection line SSL. Figure 21B The second voltage VDSL2 is less than Figure 21A The first voltage VDSL1 is applied. Then, at time t10, a bit line voltage is applied to the bit line connected to the selected memory block. Then, at time t11, a voltage Vpass can be applied to the word line connected to the selected memory block. Then, at time t12, a programming voltage Vpgm can be applied to the selected word line, which is the word line connected to the memory cell to be programmed.

[0167] Figure 21A and Figure 21BAn embodiment is shown below: when the programming of the memory cell to be programmed to the i-th programming state is not completed (S203: No), a first voltage VDSL1 is applied to the drain select line DSL, and when the programming of the memory cell to be programmed to the i-th programming state is completed (S203: Yes), a second voltage VDSL2, which is less than the first voltage VDSL1, is applied to the drain select line DSL. However, the present invention is not limited thereto, and the voltage of the source select line can be as follows: Figure 23A and Figure 23B Adjustments are made as shown.

[0168] Figure 22 The illustration shows, on the other hand, based on the reference. Figure 21A and Figure 21B A graph illustrating a method of operating a semiconductor memory device according to an embodiment of the present disclosure. (See reference...) Figure 22 As the programming cycle is repeated, the magnitude of the DSL voltage applied to the drain select line during the programming phase is shown. In the initial phase of the programming operation, i.e., in the first to Kth programming cycles before the programming of the memory cell corresponding to the i-th programming state PVi is completed, a first voltage VDSL1 can be applied to the drain select line DSL. Figure 22 The diagram illustrates an embodiment where the programming of the memory cell corresponding to the i-th programming state PVi is completed when the K-th programming loop is executed. Therefore, in the (K+1)-th programming loop and subsequent programming loops thereafter, a second voltage VDSL2, which is less than the first voltage VDSL1, can be applied to the drain selection line DSL.

[0169] Figure 23A This is a timing diagram illustrating the operation of a semiconductor memory device according to another embodiment when the programming of a memory cell to be programmed to the i-th programming state is not completed. Figure 23B This is a timing diagram illustrating the operation of a semiconductor memory device according to another embodiment when the programming of a memory cell to be programmed to the i-th programming state is completed.

[0170] refer to Figure 23ASince the programming of the memory cell to be programmed to the i-th programming state is incomplete (S203: No), at time t13, a first voltage VSSL1 is applied to the source select line SSL (S205), and a voltage VDSL is applied to the drain select line DSL. Subsequently, at time t14, bit line voltages are applied to the bit lines connected to the selected memory block (S210). More specifically, the first bit line voltage VBL1 is applied to the bit lines connected to the memory cell identified as the first programming enabled cell in the previous verification phase. Simultaneously, a second bit line voltage VBL2 is applied to the bit lines connected to the memory cell identified as the second programming enabled cell in the previous verification phase. The second bit line voltage VBL2 may be greater than the first bit line voltage VBL1. Additionally, a third bit line voltage VBL3 is applied to the bit lines connected to the memory cell identified as the programming disabled cell in the previous verification phase. The third bit line voltage VBL3 may be a voltage greater than the second bit line voltage VBL2, and may be a programming disabled voltage.

[0171] Subsequently, at time t15, a voltage Vpass can be applied to the word line connected to the selected memory block. Then, at time t16, a programming voltage Vpgm can be applied to the selected word line, which is the word line connected to the memory cell to be programmed.

[0172] refer to Figure 23B Since the programming of the memory cell to be programmed to the i-th programming state is completed (S203: Yes), at time t17, the second voltage VSSL2 is applied to the source selection line SSL, and the voltage VDSL is applied to the drain selection line DSL. Figure 23B The second voltage VSSL2 is less than Figure 23A The first voltage VSSL1 is applied. Then, at time t18, a bit line voltage is applied to the bit line connected to the selected memory block. Then, at time t19, a voltage Vpass can be applied to the word line connected to the selected memory block. Then, at time t20, a programming voltage Vpgm can be applied to the selected word line, which is the word line connected to the memory cell to be programmed.

[0173] exist Figure 23A and Figure 23BIn one embodiment, when programming of the memory cell to be programmed to the i-th programming state is not complete (S203: No), a first voltage VSSL1 is applied to the source select line SSL, and when programming of the memory cell to be programmed to the i-th programming state is complete (S203: Yes), a second voltage VSSL2, less than the first voltage VSSL1, is applied to the source select line SSL. However, this disclosure is not limited thereto, and the voltage of the drain select line can be as follows: Figure 21A and Figure 21B Adjustments are made as shown.

[0174] Figure 24 The illustration shows, on the other hand, based on the reference. Figure 23A and Figure 23B A graph illustrating a method of operating a semiconductor memory device according to an embodiment of the present disclosure. (See reference...) Figure 24 As the programming cycle is repeated, the magnitude of the SSL voltage applied to the source select line during the programming phase is shown. In the initial phase of the programming operation, i.e., in the first to Kth programming cycles before the programming of the memory cell corresponding to the i-th programming state PVi is completed, a first voltage VSSL1 can be applied to the source select line SSL. Figure 24 The diagram illustrates an embodiment where the programming of the memory cell corresponding to the i-th programming state PVi is completed when the K-th programming loop is executed. Therefore, in the (K+1)-th programming loop and its subsequent programming loops, a second voltage VSSL2, which is less than the first voltage VSSL1, can be applied to the source selection line SSL.

[0175] Figure 25 It's a diagram. Figure 9 A flowchart of another embodiment of step S200.

[0176] refer to Figure 25 Setting the state of the select line connected to the select transistor included in the selected memory block (S200) may include: checking the programming state (S202) in the verification phase of the preceding programming cycle; when the programming of the memory cell to be programmed to the i-th programming state is not completed (S204: No), applying a first voltage to the select line connected to the select transistor (S206). Simultaneously, setting the state of the select line connected to the select transistor included in the selected memory block (S200) may include: when the programming of the memory cell to be programmed to the i-th programming state is completed (S204: Yes), applying a second voltage greater than the first voltage to the select line connected to the select transistor (S208).

[0177] refer to Figure 20In the illustrated embodiment, when the programming of the memory cell to be programmed to the i-th programming state is not completed (S203: No), a first voltage is applied to the select line connected to the select transistor (S205), and when the programming of the memory cell to be programmed to the i-th programming state is completed (S203: Yes), a second voltage less than the first voltage is applied to the select line connected to the select transistor (S207).

[0178] At the same time, refer to Figure 25 In the illustrated embodiment, when the programming of the memory cell to be programmed to the i-th programming state is not completed (S204: No), a first voltage is applied to the select line connected to the select transistor (S206), and when the programming of the memory cell to be programmed to the i-th programming state is completed (S204: Yes), a second voltage greater than the first voltage is applied to the select line connected to the select transistor (S208). That is, according to Figure 25 In the embodiment shown, during the initial programming cycle of the programming operation, a relatively small first voltage can be applied to the select line connected to the select transistor, and after the programming of the memory cell corresponding to the i-th programming state is completed, a relatively large second voltage can be applied to the select line connected to the select transistor.

[0179] Figure 26 It's a diagram. Figure 1 A block diagram of an example controller 200 shown.

[0180] refer to Figure 26 The controller 200 is connected to the semiconductor memory device 100 and the host. The semiconductor memory device 100 may be a reference. Figure 2 The semiconductor memory device described.

[0181] Controller 200 is configured to access semiconductor memory device 100 in response to requests from a host. For example, controller 200 is configured to control read, write, erase, and background operations of semiconductor memory device 100. Controller 200 is configured to provide an interface between semiconductor memory device 100 and the host. Controller 200 is configured to drive firmware for controlling semiconductor memory device 100.

[0182] The controller 200 includes random access memory (RAM) 210, a processing unit 220, a host interface 230, a memory interface 240, and an error correction block 250. The RAM 210 is used as at least one of the following: operating memory of the processing unit 220, cache memory between the semiconductor storage device 100 and the host, and buffer memory between the semiconductor storage device 100 and the host.

[0183] The processing unit 220 controls the overall operation of the controller 200.

[0184] The host interface 230 includes protocols for performing data exchange between the host and the controller 200. In one embodiment, the controller 200 is configured to communicate with the host via at least one of a variety of interface protocols, such as Universal Serial Bus (USB), Multimedia Card (MMC), Peripheral Component Interconnect (PCI), PCI-Fast (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), and proprietary protocols.

[0185] The memory interface 240 is interfaced with the semiconductor memory device 100. For example, the memory interface 1240 includes a NAND interface or a NOR interface. Figure 10 The memory interface 240 can be with Figure 7 The memory interface 207 is basically the same component.

[0186] Error correction block 250 is configured to use error correction code (ECC) to detect and correct errors in data received from semiconductor memory device 100. Processing unit 220 can control semiconductor memory device 100 to adjust read voltage and perform reread based on the error detection results of error correction block 250.

[0187] The controller 200 and the semiconductor memory device 100 can be integrated into a single semiconductor device. In one embodiment, the controller 200 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a memory card. For example, the controller 200 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form memory cards such as: PC cards (Personal Computer Memory Card International Association (PCMCIA)), compact flash memory cards (CF), smart media cards (SM or SMC), memory sticks, multimedia cards (MMC, RS-MMC, or MMCmicro), SD cards (SD, miniSD, microSD, or SDHC), and universal flash memory (UFS).

[0188] The controller 200 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a semiconductor drive (solid-state drive (SSD)). The semiconductor drive (SSD) includes a memory system 1000 configured to store data in the semiconductor memory. When the memory system 1000, including the controller 200 and the semiconductor memory device 100, is used as a semiconductor drive (SSD), the operating speed of the host connected to the memory system 1000 is significantly improved.

[0189] As another example, the memory system 1000, including the controller 200 and the semiconductor memory device 100, is provided as one of various components of an electronic device such as: a computer, an ultra-mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a cordless phone, a mobile phone, a smartphone, an e-book reader, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a 3D television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a device capable of sending and receiving information in a wireless environment, one of various electronic devices configured for a home network, one of various electronic devices configured for a computer network, one of various electronic devices configured for a telematics network, an RFID device, or one of various components configured for a computing system.

[0190] In one embodiment, the semiconductor memory device 100 and the memory system including it can be mounted in various types of packages. For example, the semiconductor memory device 100 or the memory system can be packaged and mounted in methods such as: stacked package (PoP), ball grid array (BGA), chip-scale package (CSP), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), waffle package die, die-on-chip, chip-on-board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat package (MQFP), thin quad flat package (TQFP), small outline integrated circuit package (SOIC), shrink small outline package (SSOP), thin small outline package (TSOP), system-in-package (SIP), multi-chip package (MCP), wafer-level fabrication package (WFP), or wafer-level processing stacked package (WSP).

[0191] Figure 27 It's a diagram. Figure 26 A block diagram illustrating an application example of the memory system 1000.

[0192] refer to Figure 27The memory system 2000 includes a semiconductor memory device 2100 and a controller 2200. The semiconductor memory device 2100 includes multiple semiconductor memory chips. The multiple semiconductor memory chips are divided into multiple groups.

[0193] exist Figure 27 In this process, multiple groups communicate with the controller 2200 through channels CH1 to CHk, respectively. Each semiconductor memory chip is connected to a reference... Figure 2 The semiconductor memory device 100 described is similarly configured and operated.

[0194] Each group is configured to communicate with controller 2200 via a common channel. Controller 2200 and reference Figure 26 The controller 200 described is similarly configured and is configured to control multiple memory chips of the semiconductor memory device 2100 via multiple channels CH1 to CHk.

[0195] Figure 28 It is illustrated, including references. Figure 27 A block diagram of the memory system 2000 and the computing system 3000 described.

[0196] The computing system 3000 includes a central processing unit 3100, random access memory (RAM) 3200, a user interface 3300, a power supply 3400, a system bus 3500, and a memory system 2000.

[0197] The memory system 2000 is electrically connected to the central processing unit 3100, RAM 3200, user interface 3300, and power supply 3400 via system bus 3500. Data provided through the user interface 3300 or data processed by the central processing unit 3100 is stored in the memory system 2000.

[0198] exist Figure 28 In this configuration, the semiconductor memory device 2100 is connected to the system bus 3500 via the controller 2200. However, the semiconductor memory device 2100 can also be configured to be directly connected to the system bus 3500. In this case, the functions of the controller 2200 are performed by the central processing unit 3100 and the RAM 3200.

[0199] exist Figure 28 In the middle, for reference Figure 27 The memory system 2000 described is provided. However, the memory system 2000 can be used with reference to [reference]. Figure 26 The memory system 1000, which includes a controller 200 and a semiconductor memory device 100, is described instead.

[0200] The embodiments of the present invention disclosed in this specification and accompanying drawings are merely illustrative examples to describe the technical content of the present invention and to aid in understanding it, and are not intended to limit the scope of this disclosure. Those skilled in the art will understand that other modifications based on the technical spirit of this disclosure can be implemented in addition to the embodiments disclosed herein.

Claims

1. A method of operating a semiconductor memory device for programming a selected memory cell among a plurality of memory cells, the method comprising executing a plurality of programming cycles, wherein each programming cycle of the plurality of programming cycles includes a programming phase and a verification phase, wherein the programming phase includes: Based on the number of times the plurality of programming loops are executed, a first voltage or a second voltage is applied to a selection line coupled to a selected memory block including the selected memory cell; Set the state of the bit line coupled to the selected memory block; When the first voltage or the second voltage is applied to the select line, a programming voltage is applied to the selected word line coupled to the selected memory block; as well as The unselected word lines coupled to the selected memory block are connected by applying voltage to the word lines.

2. The method of claim 1, wherein applying the first voltage or the second voltage to the select line comprises: Check the programming status of the program in the verification phase of the preceding programming loop when the programming has been completed; as well as When to be programmed into the first programming state up to (2) N -1) When the programming of the memory cell in the i-th programming state is not completed, the first voltage is applied to the selection line. Each of the plurality of memory units can store N bits of data, where N is a natural number greater than 1, and i is a number greater than 0 and less than (2π / 2). N The natural number of -1.

3. The method of claim 2, wherein applying the first voltage or the second voltage to the select line comprises: When the programming of the memory cell to be programmed into the i-th programming state is completed, the second voltage, which is different from the first voltage, is applied to the select line.

4. The method of claim 3, wherein the selection line is a drain selection line.

5. The method of claim 3, wherein the selection line is a source selection line.

6. The method of claim 3, wherein the second voltage is less than the first voltage.

7. The method of claim 3, wherein the second voltage is greater than the first voltage.

8. The method of claim 2, wherein N is 2 and i is 2.

9. The method of claim 2, wherein N is 3 and i is 6.

10. The method of claim 1, wherein the verification stage comprises: A pre-verification voltage is applied to the word line coupled to the selected memory cell; as well as A primary verification voltage is applied to the word line coupled to the selected memory cell, and the primary verification voltage is greater than the pre-verification voltage.

11. The method of claim 10, wherein the verification stage further comprises: Memory cells with a threshold voltage higher than the main verification voltage are identified as programmable disabled cells.

12. The method of claim 11, wherein the verification phase further comprises: Memory cells with a threshold voltage lower than the pre-verified voltage are identified as first programming-enabled cells; as well as Memory cells with a threshold voltage higher than the pre-verification voltage and lower than the main verification voltage are identified as second programming-enabled cells.

13. The method of claim 12, wherein setting the state of the bit line coupled to the selected memory block comprises: A first programming enable voltage is applied to the bit line coupled to the first programming enable cell; as well as A second programming enable voltage is applied to the bit line coupled to the second programming enable cell, the second programming enable voltage being greater than the first programming enable voltage.

14. The method of claim 13, wherein setting the state of the bit line coupled to the selected memory block including the selected memory cell further comprises: A programming disable voltage is applied to the bit line coupled to the programming disable unit, the programming disable voltage being greater than the second programming enable voltage.

15. A semiconductor memory device, comprising: A memory block comprising multiple memory cells, each capable of storing N bits of data, where N is a natural number greater than 1; Peripheral circuitry is configured to perform programming operations on selected memory cells among the plurality of memory cells included in the memory block. as well as Control logic circuitry is configured to control the programming operation performed on the selected memory cell. The programming operation includes multiple programming loops, each programming loop including a programming phase and a verification phase, and During the programming phase, the control logic circuit is configured to control the peripheral circuit to: Based on the number of times the plurality of programming loops are executed, a first voltage or a second voltage is applied to the selection line coupled to the memory block; Set the state of the bit line coupled to the selected memory block; When the first voltage or the second voltage is applied to the select line, a programming voltage is applied to the selected word line coupled to the selected memory block; as well as Voltage will be applied to the unselected word line.

16. The semiconductor memory device of claim 15, wherein the control logic circuitry is configured to control the peripheral circuitry to apply the first voltage or the second voltage to the select line by: checking the programming state in the verification phase of the immediately preceding programming cycle where programming has been completed; and when to be programmed to the first programming state up to the (2) N -1) When the programming of the memory cell in the i-th programming state is not completed, control the peripheral circuit to apply the first voltage to the selection line, and Where i is greater than 0 and less than (2). N The natural number of -1.

17. The semiconductor memory device according to claim 16, The control logic circuit is configured to control the peripheral circuit to apply a second voltage to the select line when the programming of the memory cell to be programmed to the i-th programming state is completed, the second voltage being different from the first voltage.

18. The semiconductor memory device of claim 17, wherein: The selection line is a drain selection line; and The second voltage is less than the first voltage.

19. The semiconductor memory device of claim 15, wherein the control logic circuitry is configured to, during the verification phase, The peripheral circuitry is controlled to apply a pre-verification voltage to a word line coupled to the selected memory cell and to apply a main verification voltage to the word line coupled to the selected memory cell, the main verification voltage being greater than the pre-verification voltage. Memory cells with a threshold voltage higher than the main verification voltage are identified as programmable disabled cells; Memory cells with a threshold voltage lower than the pre-verified voltage are identified as first programming-enabled cells; as well as Memory cells with a threshold voltage higher than the pre-verification voltage and lower than the main verification voltage are identified as second programming-enabled cells.

20. The semiconductor memory device of claim 19, wherein the control logic circuitry is configured to control the peripheral circuitry to: during the process of setting the state of the bit line coupled to the selected memory block. A first programming enable voltage is applied to the bit line coupled to the first programming enable cell; A second programming enable voltage is applied to the bit line coupled to the second programming enable cell, the second programming enable voltage being greater than the first programming enable voltage; as well as A programming disable voltage is applied to the bit line coupled to the programming disable unit, the programming disable voltage being greater than the second programming enable voltage.

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