An svm-based igbt chip welding layer cavity positioning method

Abstract

The application discloses an IGBT chip welding layer cavity positioning method based on SVM, and first, an electric-thermal simulation model and a SPICE circuit model of an IGBT module are established, the welding layer in the field-circuit coupling model is divided into a plurality of fault regions after the field-circuit coupling model is obtained through coupling, then, cavity fault simulation is respectively performed on each fault region, and an influence factor of the IGBT chip is calculated based on joint simulation, a fault region number-influence factor data set is constructed, the influence factor in the data set is taken as input data, and the fault region number is taken as output data, a SVM algorithm with strong non-linear capability is adopted to analyze the mapping relationship between the input data and the output data, and thus, the IGBT welding layer cavity positioning is realized. The method takes the turn-off time, the junction temperature, and the voltage drop difference between the collector and the emitter as the influence factor, jointly judges the position of the cavity, and makes the cavity positioning result more accurate.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to a method for locating voids in the bonding layer of an IGBT chip based on SVM. Background Technology

[0002] Insulated-gate bipolar transistors (IGBTs) have become representative devices in modern power electronics due to their advantages such as high input impedance, simple control circuitry, high current density, fast switching speed, and low saturation voltage. However, as the current density and voltage levels of IGBT modules continue to increase, and due to the different coefficients of thermal expansion of the materials in each layer of the IGBT module, coupled with unavoidable manufacturing defects, voids of varying degrees can easily form in the solder layer of the IGBT module after long-term operation. These voids will reduce the heat dissipation performance and electrical performance of the IGBT device, seriously affecting the reliability and overall lifespan of the IGBT module.

[0003] Since the impact of voids on the overall performance of IGBT modules varies greatly depending on their location, locating the voids can provide a reliable basis for device maintenance. If the void appears in the middle area of ​​the IGBT module, which has a significant impact on performance, it needs to be closely monitored to prevent IGBT module failure. If the void appears in the corner area of ​​the IGBT module, which has a smaller impact on performance, there is no risk of failure in the short term.

[0004] The difficulty in locating voids in the IGBT chip solder layer lies in the fact that IGBT modules have opaque packaging structures, and the working environment of IGBTs is mostly complex, making it unacceptable to arbitrarily stop operation and disassemble for inspection. Therefore, it is particularly important to locate voids in the solder layer of IGBT modules without affecting the normal operation of IGBTs or disassembling the IGBT packaging structure. Summary of the Invention

[0005] The purpose of this invention is to overcome the above-mentioned problems in the prior art and provide an IGBT chip solder layer void location method based on SVM that can realize the location of solder layer voids.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] A method for locating voids in the bonding layer of an IGBT chip based on SVM, the method comprising the following steps:

[0008] S1. In COMSOL software, establish the electrothermal simulation model and SPICE circuit model of the IGBT chip respectively, and obtain the field-circuit coupling model by coupling the electrothermal simulation model and the SPICE circuit model.

[0009] S2. First, divide the welding layer in the field-circuit coupling model into multiple fault regions and number each fault region. Then, simulate the void fault for each fault region and obtain the influence factors of the IGBT chip based on the joint simulation calculation. The influence factors include the junction temperature of the IGBT chip, the voltage drop difference between the collector and the emitter, and the turn-off time.

[0010] S3. Construct a fault area number-influence factor dataset, and use the influence factors in this dataset as model input and the fault area number as model output to train the SVM network model.

[0011] S4. Input the influence factors of the IGBT chip obtained in real time into the trained SVM network model to obtain the actual fault area number of the IGBT chip.

[0012] In step S2, the void fault simulation specifically involves creating cylindrical voids in the fault area to simulate void faults in the weld layer.

[0013] When simulating void faults, the height of the cylindrical void is made equal to the thickness of the chip solder layer. The radius of the cylindrical void is gradually increased, thereby gradually increasing the void ratio, to simulate the gradual increase in the degree of void faults until the highest temperature of the IGBT chip in the field-circuit coupling model exceeds the maximum specified temperature. Then, the influence factor of the IGBT chip under different void ratios is calculated through co-simulation.

[0014] In step S3, the SVM network model training specifically involves: using RBF as the kernel function and SVC as the loss function; using cross-validation to find the optimal (C, gamma) parameters of the SVM network model; dividing the fault area number-influence factor dataset into a training set and a test set; and continuously adjusting the ratio of the training set to the test set to obtain the SVM network model with the highest diagnostic accuracy.

[0015] In step S2, the fault area division is specifically as follows: the welding layer in the field-circuit coupling model is divided into a nine-square grid. The first row of the nine-square grid, from left to right, includes fault area 1, fault area 2, and fault area 3. The second row of the nine-square grid, from left to right, includes fault area 4, fault area 5, and fault area 6. The third row of the nine-square grid, from left to right, includes fault area 7, fault area 8, and fault area 9. When a void occurs in fault area 5, the impact of the void on the IGBT chip performance is at level 1. When a void occurs in fault area 2, fault area 4, fault area 6, or fault area 8, the impact of the void on the IGBT chip performance is at level 2. When a void occurs in fault area 1, fault area 3, fault area 6, or fault area 9, the impact of the void on the IGBT chip is at level 3. The first level is greater than the second level, and the second level is greater than the third level.

[0016] In step S1, the simulation loading conditions of the electrothermal simulation model are as follows: the rated current of the IGBT chip is 800 A, the IGBT chip is composed of 4 identical IGBT units connected in parallel, the current applied to each IGBT unit is 200 A, the rest of the IGBT chip except the base heat sink is set to be adiabatic, the heat transfer coefficient of the lower surface of the base heat sink is set to 8000, the fixed position of the base heat sink is set to 0, and the temperature is set to 25 ℃.

[0017] In step S4, the actual junction temperature of the IGBT chip is acquired in real time by a temperature sensor placed on the IGBT model chip, and the actual turn-off time and the actual voltage drop difference between the collector and emitter of the IGBT chip are obtained by real-time monitoring of the IGBT chip circuit.

[0018] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0019] This invention discloses an SVM-based method for locating voids in the solder layer of IGBT chips. First, an electrothermal simulation model of the IGBT module and a SPICE circuit model are established and coupled to obtain a field-circuit coupling model. The solder layer in the field-circuit coupling model is then uniformly divided into multiple fault regions. Next, void fault simulation is performed on each fault region, and the influence factors of the IGBT chip are obtained based on the co-simulation calculation. Then, a fault region number-influence factor dataset is constructed. Using the influence factors in this dataset as input data and the fault region number as output data, the SVM algorithm, which has strong nonlinear capabilities, is used to analyze the mapping relationship between the input and output data, thereby achieving the purpose of locating voids in the IGBT solder layer. The influence factors include the junction temperature of the IGBT chip, the voltage drop difference between the collector and emitter, and the turn-off time. Since the SPICE circuit model of the IGBT can accurately reflect the switching characteristics of the IGBT during operation, and the turn-off time in the IGBT switching characteristics is affected by the location of voids in its internal solder layer, the turn-off time also contains void location information. By jointly determining the void location using the turn-off time, junction temperature, and voltage drop difference between the collector and emitter, the void location result is more accurate. Attached Figure Description

[0020] Figure 1 This is a flowchart of the present invention.

[0021] Figure 2 This is a schematic diagram of the fault region division of the welding layer in the field coupling model of the present invention. Detailed Implementation

[0022] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0023] See Figure 1 A method for locating voids in the solder layer of an IGBT chip based on SVM is described below.

[0024] S1. Select the commonly used IGBT chip (model 5SNA0800N330100) for the converter valve as the object. In COMSOL software, first establish the electrothermal simulation model and SPICE circuit model of the IGBT chip respectively. Then, the electrothermal simulation model and SPICE circuit model are coupled to obtain the field-circuit coupling model. The simulation loading conditions of the electrothermal simulation model are as follows: the rated current of the IGBT chip is 800 A, the IGBT chip is composed of 4 identical IGBT units connected in parallel, the current applied to each IGBT unit is 200 A, the rest of the IGBT chip except the base heat sink is set to adiabatic, the heat transfer coefficient of the lower surface of the base heat sink is set to 8000, the fixed position of the base heat sink is set to 0, and the temperature is set to 25 ℃.

[0025] S2. Divide the welding layer in the field-circuit coupling model into a nine-square grid. The first row of the nine-square grid includes fault region 1, fault region 2, and fault region 3 from left to right. The second row of the nine-square grid includes fault region 4, fault region 5, and fault region 6 from left to right. The third row of the nine-square grid includes fault region 7, fault region 8, and fault region 9 from left to right. When a void occurs in fault region 5, the impact of the void on the IGBT chip performance is at level one. When a void occurs in fault region 2, fault region 4, fault region 6, or fault region 8, the impact of the void on the IGBT chip performance is at level two. When a void occurs in fault region 1, fault region 3, fault region 6, or fault region 9, the impact of the void on the IGBT chip performance is at level three. The first level is greater than the second level, and the second level is greater than the third level.

[0026] S3. Perform void fault simulation for each fault region and obtain the influence factor of the IGBT chip based on co-simulation calculation. The influence factor includes the junction temperature of the IGBT chip, the voltage drop difference between the collector and emitter, and the turn-off time. The void fault simulation is specifically as follows: by creating cylindrical voids in the fault region to simulate void faults in the solder layer, by making the height of the cylindrical voids equal to the thickness of the chip solder layer, the radius of the cylindrical voids is gradually increased, thereby gradually increasing the void ratio to simulate the gradual increase of the void fault degree until the highest temperature of the IGBT chip in the field-circuit coupling model exceeds the maximum specified temperature. Then, the influence factor of the IGBT chip under different void ratios is calculated through co-simulation.

[0027] S4. Construct a fault area number-influence factor dataset. Use the influence factors in this dataset as model input and the fault area number as model output to train the SVM network model. The SVM network model training is specifically as follows: the kernel function of the SVM network model is RBF and the loss function is SVC. Cross-validation is used to find the optimal (C, gamma) parameters of the SVM network model. The fault area number-influence factor dataset is divided into training set and test set. The ratio of the training set and test set is continuously adjusted to obtain the SVM network model with the highest diagnostic accuracy.

[0028] S5. Twenty-one IGBT chips with void faults (model 5SNA0800N330100) were randomly selected as test cases. First, the actual junction temperature of the IGBT chip was collected in real time using a temperature sensor placed on the IGBT chip. The actual turn-off time and the actual voltage drop difference between the collector and emitter of the IGBT chip were obtained by real-time monitoring of the IGBT circuit. Then, the actual junction temperature, actual turn-off time, and actual voltage drop difference between the collector and emitter of the IGBT chip were input into the trained SVM network model obtained in step S4 to obtain the actual fault region number of the IGBT chip. The void location results of the 21 test cases are shown in Table 1.

[0029] Table 1. Cavity localization results for 21 test cases

[0030] .

[0031] As shown in Table 1, 19 out of 21 test cases were successfully located, with only test cases 3 and 19 failing to locate the cavity. The cavity location accuracy rate reached over 90%, indicating that the method has a high accuracy rate in locating cavity fault areas. In test cases 13 and 20, the cavity occurred in fault area 5, meaning that the impact of the cavity on the IGBT chip performance was at the first level. Therefore, test cases 13 and 20 need to be closely monitored to prevent the IGBT chip from failing due to the continued expansion of the cavity area.

Claims

1. A method for locating voids in the solder layer of an IGBT chip based on SVM, characterized in that: The cavity location method includes the following steps in sequence: S1. In COMSOL software, establish the electrothermal simulation model and SPICE circuit model of the IGBT chip respectively, and obtain the field-circuit coupling model by coupling the electrothermal simulation model and the SPICE circuit model. S2. First, divide the welding layer in the field-circuit coupling model into multiple fault regions and number each fault region. Then, simulate the void fault for each fault region and obtain the influence factors of the IGBT chip based on the joint simulation calculation. The influence factors include the junction temperature of the IGBT chip, the voltage drop difference between the collector and the emitter, and the turn-off time. S3. Construct a fault area number-influence factor dataset, and use the influence factors in this dataset as model input and the fault area number as model output to train the SVM network model. S4. Input the influence factors of the IGBT chip obtained from real-time acquisition into the trained SVM network model to obtain the actual fault area number of the IGBT chip. In step S3, the SVM network model training specifically involves: using RBF as the kernel function and SVC as the loss function; using cross-validation to find the optimal (C, gamma) parameters of the SVM network model; dividing the fault area number-influence factor dataset into a training set and a test set; and continuously adjusting the ratio of the training set to the test set to obtain the SVM network model with the highest diagnostic accuracy. In step S2, the fault area division is specifically as follows: the welding layer in the field-circuit coupling model is divided into a nine-square grid. The first row of the nine-square grid, from left to right, includes fault area 1, fault area 2, and fault area 3. The second row of the nine-square grid, from left to right, includes fault area 4, fault area 5, and fault area 6. The third row of the nine-square grid, from left to right, includes fault area 7, fault area 8, and fault area 9. When a void occurs in fault area 5, the impact of the void on the IGBT chip performance is at level 1. When a void occurs in fault area 2, fault area 4, fault area 6, or fault area 8, the impact of the void on the IGBT chip performance is at level 2. When a void occurs in fault area 1, fault area 3, fault area 7, or fault area 9, the impact of the void on the IGBT chip is at level 3. The first level is greater than the second level, and the second level is greater than the third level.

2. The method for locating voids in the solder layer of an IGBT chip based on SVM according to claim 1, characterized in that: In step S2, the void fault simulation specifically involves creating cylindrical voids in the fault area to simulate void faults in the weld layer.

3. The method for locating voids in the solder layer of an IGBT chip based on SVM according to claim 2, characterized in that: When simulating void faults, the height of the cylindrical void is made equal to the thickness of the chip solder layer. The radius of the cylindrical void is gradually increased, thereby gradually increasing the void ratio, to simulate the gradual increase in the degree of void faults until the highest temperature of the IGBT chip in the field-circuit coupling model exceeds the maximum specified temperature. Then, the influence factor of the IGBT chip under different void ratios is calculated through co-simulation.

4. The method for locating voids in the solder layer of an IGBT chip based on SVM according to claim 1, characterized in that: In step S1, the simulation loading conditions of the electrothermal simulation model are as follows: the rated current of the IGBT chip is 800 A, the IGBT chip is composed of 4 identical IGBT units connected in parallel, the current applied to each IGBT unit is 200 A, the rest of the IGBT chip except the base heat sink is set to be adiabatic, the heat transfer coefficient of the lower surface of the base heat sink is set to 8000, the fixed position of the base heat sink is set to 0, and the temperature is set to 25 ℃.

5. The method for locating voids in the solder layer of an IGBT chip based on SVM according to claim 1, characterized in that: In step S4, the actual junction temperature of the IGBT chip is acquired in real time by a temperature sensor placed on the IGBT model chip, and the actual turn-off time and the actual voltage drop difference between the collector and emitter of the IGBT chip are obtained by real-time monitoring of the IGBT circuit.

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