A power semiconductor module with a double-sided heat dissipation structure

By adopting a hollow structure and terminal stacking design in the power semiconductor module, the problem of excessive stray inductance in the commutation circuit is solved, a more efficient current path design is achieved, the balance between the module's electrical and thermal performance is improved, and costs are reduced.

CN115547954BActive Publication Date: 2025-10-17LEADRIVE TECH (SHANGHAI) CO LTD
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Patent Information

Application Number
CN202211287278.2
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2022-10-20
Publication Date
2025-10-17
Estimated Expiration
2042-10-20

AI Technical Summary

Technical Problem

The existing power semiconductor module's commutation circuit has excessively large stray inductance, which increases turn-off losses and reduces system efficiency. Furthermore, existing processes are costly and make it difficult to achieve a balance between thermal and electrical performance.

Method used

A double-sided heat dissipation power semiconductor module design with a hollow structure is adopted. By setting a hollow area between the upper substrate and the lower substrate, the current path is widened, and the DC positive terminal and the DC negative terminal are overlapped to reduce the stray inductance of the commutation circuit.

Benefits of technology

It significantly reduces the stray inductance of the power module, improves the reverse bias safe operating area, reduces the driving resistance, improves the power output capability and power density of the controller, and enhances reliability and work efficiency.

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Abstract

The application provides a double-sided heat dissipation power semiconductor module with a hollow structure, comprising an upper substrate and a lower substrate, wherein a direct current positive terminal is arranged on the lower substrate, a direct current negative terminal is arranged on the upper substrate, and the direct current positive terminal and the direct current negative terminal are arranged in a superposition mode; a plurality of upper bridge arm chips and a plurality of lower bridge arm chips are arranged on the lower substrate, and a first pad is arranged between the plurality of upper bridge arm chips and the plurality of lower bridge arm chips, and the first pad is connected to the upper substrate and the lower substrate simultaneously; the upper substrate comprises an upper surface metal layer, an insulating dielectric layer and a lower surface metal layer, a hollow area corresponding to the lower bridge arm chip is arranged on the upper substrate, and the hollow area only comprises the lower surface metal layer; and the edge of one end of the hollow area penetrates the upper substrate.
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