A high-side driver circuit

Abstract

The application provides a high-side drive circuit, which is applied to the technical field of power electronics and comprises a voltage conversion circuit, a pull-up current circuit and a pull-down current circuit, wherein the signal input end of a low-side-to-high-side circuit is used as the input end of the high-side drive circuit; the signal output end of the low-side-to-high-side circuit is connected with the control end of the pull-up current circuit and the control end of the pull-down current circuit respectively; the output end of the pull-up current circuit is connected with the output end of the pull-down current circuit, and the connecting point is used as the output end of the high-side drive circuit. The application provides a high-side drive circuit, which can be connected in series between a power supply and an electrical load, can realize high-side drive of the electrical load, and can further improve the safety of power supply of the electrical load.

Description

Technical Field

[0001] This invention belongs to the field of power electronics technology, and particularly relates to a high-side drive circuit. Background Technology

[0002] High-side drive refers to a control method that directly controls the conduction state of the power line upstream of the electrical load to supply or cut off power to the load.

[0003] High-side drive control is applicable in many scenarios. Taking automotive control systems as an example, due to the existing automotive structure, grounded metal plates are ubiquitous on the vehicle body, and various electrical loads of the vehicle are very prone to grounding faults. High-side drive is used for these electrical loads because the power supply control is upstream of the electrical load. Even if the electrical load experiences a grounding fault, it will not directly connect the electrical load to the power supply. Therefore, the electrical load will not be directly powered on and run. This is very important in the actual use of vehicles and can effectively prevent traffic accidents.

[0004] Given the crucial role of high-side drive, providing a high-side drive circuit to improve the safety of power supply to electrical loads has become one of the technical problems that urgently need to be solved by those skilled in the art. Summary of the Invention

[0005] In view of this, the purpose of this invention is to provide a high-side drive circuit to improve the safety of power supply to electrical loads, and the specific solution is as follows:

[0006] This application provides a high-side driving circuit, including: a low-side to high-side conversion circuit, a pull-up current circuit, a pull-down current circuit, and a bootstrap circuit; wherein:

[0007] The input terminal of the bootstrap circuit is connected to the power supply terminal of the corresponding branch of the high-side drive circuit; the output terminal of the bootstrap circuit is connected to the first power supply terminal of the pull-up current circuit, the first power supply terminal of the pull-down current circuit, and the power supply terminal of the low-side to high-side circuit.

[0008] The signal input terminal of the low-side to high-side conversion circuit serves as the input terminal of the high-side driving circuit.

[0009] The signal output terminal of the low-side to high-side circuit is connected to the control terminal of the pull-up current circuit and the control terminal of the pull-down current circuit, respectively.

[0010] The output terminal of the pull-up current circuit is connected to the output terminal of the pull-down current circuit, and the connection point serves as the output terminal of the high-side drive circuit.

[0011] Optionally, it also includes: a voltage generation circuit; wherein:

[0012] The reference terminal of the voltage generation circuit is connected to the connection point between the first power supply terminal of the pull-up current circuit and the first power supply terminal of the pull-down current circuit.

[0013] The output terminal of the voltage generation circuit is connected to the second power supply terminal of the pull-up current circuit and the second power supply terminal of the pull-down current circuit, respectively.

[0014] The output voltage of the voltage generation module is equal to the input voltage of the voltage generation module minus the preset voltage.

[0015] Optionally, the voltage generation circuit includes: a first conversion circuit and a second conversion circuit; wherein:

[0016] The input terminal of the first conversion circuit receives the preset voltage, and the output terminal of the first conversion circuit is connected to the input terminal of the second conversion circuit. The first conversion circuit is used to convert the preset voltage into a preset current.

[0017] The reference terminal of the second conversion circuit serves as the reference terminal of the voltage generation circuit, and the output terminal of the second conversion circuit serves as the output terminal of the voltage generation circuit. The second conversion circuit is used to convert the preset current into a preset voltage, and the output voltage of the second conversion circuit is equal to the potential of its own reference terminal minus the preset voltage.

[0018] Optionally, the first conversion circuit includes: a first resistor and three NMOS transistors; wherein:

[0019] The connection point between the gate of the first NMOS transistor and the gate of the second NMOS transistor is connected to the drain of the first NMOS transistor.

[0020] The drain of the first NMOS transistor is connected to one end of the first resistor, and the other end of the first resistor receives the preset voltage.

[0021] The drain of the second NMOS transistor is connected to the source of the third NMOS transistor. The drain of the third NMOS transistor serves as the output terminal of the voltage-to-current conversion current, and the gate of the third NMOS transistor receives an enable signal.

[0022] The source of both the first NMOS transistor and the source of the second NMOS transistor are connected to the low-side ground.

[0023] The first NMOS transistor is the same as the second NMOS transistor.

[0024] Optionally, the second conversion circuit includes: two resistors, two capacitors, four NMOS transistors, and two PMOS transistors; wherein:

[0025] The connection point between the gate of the first PMOS transistor and the gate of the second PMOS transistor is connected to the drain of the first PMOS transistor.

[0026] The drain of the first PMOS transistor serves as the input terminal of the second conversion circuit, and the source of the first PMOS transistor is connected to the source of the fourth NMOS transistor.

[0027] The connection point between the gate of the fourth NMOS transistor and the gate of the fifth NMOS transistor is connected to the drain of the fourth NMOS transistor.

[0028] The drain of the fourth NMOS transistor is connected to the drain of the fifth NMOS transistor through a second resistor, and the connection point serves as the reference terminal of the second conversion circuit.

[0029] The source of the second PMOS transistor is connected to the source of the fifth NMOS transistor and the drain of the seventh NMOS transistor, respectively, and the drain of the second PMOS transistor is connected to the drain of the sixth NMOS transistor.

[0030] The connection point between the gate of the sixth NMOS transistor and the gate of the seventh NMOS transistor is connected to the drain of the sixth NMOS transistor, respectively.

[0031] The connection point between the source of the sixth NMOS transistor and the source of the seventh NMOS transistor is connected to the high-side ground.

[0032] One end of the first capacitor is connected to the source of the fourth NMOS transistor, and the other end is connected to the reference terminal of the second conversion circuit;

[0033] One end of the second capacitor is connected to the source of the fifth NMOS transistor, and the other end is connected to the reference terminal of the second conversion circuit;

[0034] One end of the third resistor is connected to the gate of the sixth NMOS transistor, and the other end is connected to the source of the sixth NMOS transistor;

[0035] The first resistor and the second resistor have the same resistance value, and the first NMOS transistor is the same as the fifth NMOS transistor.

[0036] Optionally, the pull-up current circuit includes: a first current-stabilizing circuit and a pull-up main circuit; wherein:

[0037] The input terminal of the pull-up main circuit receives the first reference current, the output terminal of the pull-up main circuit serves as the output terminal of the pull-up current circuit, and the control terminal of the pull-up main circuit serves as the control terminal of the pull-up current circuit.

[0038] The input terminal of the first current stabilizing circuit is connected to the first power supply terminal of the pull-up main circuit, the ground terminal of the first current stabilizing circuit is connected to the low-side ground, and the output terminal of the first current stabilizing circuit is connected to the pull-up main circuit. The first current stabilizing circuit is used to input a compensation current to the pull-up main circuit according to the potential change of the first power supply terminal of the pull-up main circuit.

[0039] Optionally, the first current-stabilizing circuit includes: an eighth NMOS transistor, a third PMOS transistor, and a fourth PMOS transistor; wherein:

[0040] The connection point between the gate and source of the eighth NMOS transistor is connected to the low-side ground.

[0041] The drain of the eighth NMOS transistor is connected to the drain of the third PMOS transistor.

[0042] The connection point between the gate of the third PMOS transistor and the gate of the fourth PMOS transistor is connected to the drain of the third PMOS transistor.

[0043] The connection point between the source of the third PMOS transistor and the source of the fourth PMOS transistor is connected to the first power supply terminal of the pull-up main circuit.

[0044] The connection point between the gate of the third PMOS transistor and the gate of the fourth PMOS transistor is connected to the drain of the third PMOS transistor.

[0045] The drain of the fourth PMOS transistor serves as the output terminal of the pull-up main circuit.

[0046] Optionally, the pull-down current circuit includes: a second current stabilizing circuit and a pull-down main circuit; wherein:

[0047] The input terminal of the pull-down main circuit receives the second reference current, the output terminal of the pull-down main circuit serves as the output terminal of the pull-down current circuit, and the control terminal of the pull-down main circuit serves as the control terminal of the pull-down current circuit.

[0048] The reference terminal of the second current stabilizing circuit is connected to the first power supply terminal of the pull-down main circuit. The second current stabilizing circuit is disposed in the pull-down main circuit and is used to filter out the potential changes of the first power supply terminal of the pull-down main circuit.

[0049] Optionally, the second current-stabilizing circuit includes: a third capacitor, a fourth resistor, and a fifth resistor; wherein:

[0050] The fourth resistor and the fifth resistor are connected in series in the pull-down main circuit;

[0051] The connection point of the fourth resistor and the fifth resistor is connected to the first power supply terminal of the pull-down main circuit through the third capacitor.

[0052] Optionally, the low-side to high-side conversion circuit includes: four NMOS transistors, four PMOS transistors, and three inverters; wherein:

[0053] The connection point between the source of the ninth NMOS transistor and the source of the tenth NMOS transistor is connected to the low-side ground.

[0054] The gate of the tenth NMOS transistor is connected to the output terminal of the first inverter, and the gate of the ninth NMOS transistor and the input terminal of the first inverter are both connected to the signal input terminal of the low-side to high-side circuit.

[0055] The drain of the ninth NMOS transistor is connected to the source of the eleventh NMOS transistor, the gate of the eleventh NMOS transistor receives an enable signal, and the drain of the eleventh NMOS transistor is connected to the drain of the fifth PMOS transistor.

[0056] The drain of the tenth NMOS transistor is connected to the source of the twelfth NMOS transistor, the gate of the twelfth NMOS transistor receives the enable signal, and the drain of the twelfth NMOS transistor is connected to the drain of the sixth PMOS transistor.

[0057] The gates of the fifth PMOS transistor and the sixth PMOS transistor are both connected to high-side ground.

[0058] The source of the fifth PMOS transistor is connected to the drain of the seventh PMOS transistor and the gate of the eighth PMOS transistor, respectively.

[0059] The source of the sixth PMOS transistor is connected to the drain of the eighth PMOS transistor and the gate of the seventh PMOS transistor, respectively.

[0060] The connection point between the source of the seventh PMOS transistor and the source of the eighth PMOS transistor serves as the power supply terminal of the low-side to high-side circuit.

[0061] The input terminal of the second inverter is connected to the drain of the eighth PMOS transistor, and the output terminal of the second inverter is connected to the input terminal of the third inverter. The output terminal of the third inverter serves as the signal output terminal of the low-side to high-side circuit.

[0062] Based on the above technical solution, the high-side drive circuit provided by this invention includes a voltage conversion circuit, a pull-up current circuit, and a pull-down current circuit. The signal input terminal of the low-side to high-side conversion circuit serves as the input terminal of the high-side drive circuit. The signal output terminal of the low-side to high-side conversion circuit is connected to the control terminals of the pull-up current circuit and the pull-down current circuit, respectively. The output terminal of the pull-up current circuit is connected to the output terminal of the pull-down current circuit, and the connection point serves as the output terminal of the high-side drive circuit. This invention provides a high-side drive circuit that can be connected in series between the power supply and the electrical load, enabling high-side drive of the electrical load and thus improving the safety of power supply to the electrical load. Attached Figure Description

[0063] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0064] Figure 1 and Figure 2 These are schematic diagrams of two structures of a high-side driving circuit provided in an embodiment of the present invention;

[0065] Figure 3 This is a schematic diagram of the voltage generation circuit 50 provided in an embodiment of the present invention;

[0066] Figure 4 This is a schematic diagram of the pull-up current circuit 20 provided in an embodiment of the present invention;

[0067] Figure 5 This is a schematic diagram of the pull-down current circuit 30 provided in an embodiment of the present invention;

[0068] Figure 6 This is a schematic diagram of the low-side to high-side circuit 10 provided in an embodiment of the present invention;

[0069] Figure 7 This is a schematic diagram of another structure of a high-side driving circuit provided in an embodiment of the present invention. Detailed Implementation

[0070] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0071] To improve the safety of power supply to electrical loads, this application provides a high-side drive circuit, the specific structure of which is as follows: Figure 1 As shown, it specifically includes: a low-side to high-side circuit 10, a pull-up current circuit 20, a pull-down current circuit 30, and a bootstrap circuit 40; their specific connection relationships are as follows:

[0072] The input terminal of the bootstrap circuit 40 is connected to the power supply terminal of the corresponding branch of the high-side drive circuit, that is, it is connected to the power supply and receives the power supply voltage Vv; the output terminal of the bootstrap circuit 40 is connected to the first power supply terminal of the pull-up current circuit 20, the first power supply terminal of the pull-down current circuit 30, and the power supply terminal of the low-side to high-side circuit 10, and outputs the drive voltage VBST.

[0073] The enable terminal of the low-side to high-side circuit 10 receives the enable signal EN. The first ground terminal of the low-side to high-side circuit 10 is connected to the high-side ground SW, and the second ground terminal of the low-side to high-side circuit 10 is connected to the low-side ground GND. The signal input terminal of the low-side to high-side circuit 10 serves as the input terminal of the high-side drive circuit and receives the drive signal CMD. The signal output terminal of the low-side to high-side circuit 10 is connected to the control terminal of the pull-up current circuit 20 and the control terminal of the pull-down current circuit 30, respectively.

[0074] The first power supply terminal of the pull-up current circuit 20 receives the driving voltage VBST, the second power supply terminal of the pull-up current circuit 20 receives the target voltage, the ground terminal of the pull-up current circuit 20 is connected to the low-side ground GND, the enable terminal of the pull-up current circuit 20 receives the enable signal EN, the input terminal of the pull-up current circuit 20 receives the first reference current Iref1, and the output terminal of the pull-up current circuit 20 is connected to the output terminal OUT of the high-side drive circuit.

[0075] The first power supply terminal of the pull-down current circuit 30 receives the driving voltage VBST, the second power supply terminal of the pull-down current circuit 30 receives the target voltage, the first ground terminal of the pull-down current circuit 30 is connected to the high-side ground SW, the second ground terminal of the pull-down current circuit 30 is connected to the low-side ground GND, the enable terminal of the pull-down current circuit 30 receives the enable signal EN, the input terminal of the pull-down current circuit 30 receives the second reference current Iref2, and the output terminal of the pull-down current circuit 30 is connected to the output terminal OUT of the high-side drive circuit.

[0076] Preferably, the first reference current Iref1 and the second reference current Iref2 can be the same; in practical applications, this is not limited to, but is not specifically limited here. It can be determined according to the specific situation, and all are within the protection scope of this application.

[0077] The working principle of the high-side drive circuit is as follows:

[0078] After the enable signal EN goes high, the low-side to high-side circuit 10, the pull-up current circuit 20, and the pull-down current circuit 30 enter the working mode. The low-side to high-side circuit 10 converts the drive signal CMD from a low-side signal to a high-side signal. When the drive signal CMD is high, the pull-up current circuit 20 outputs a pull-up current, and when the drive signal CMD is low, the pull-down current circuit 30 outputs a pull-down current.

[0079] This invention provides a high-side drive circuit that can be connected in series between the power supply and the electrical load, enabling high-side drive of the electrical load and thus improving the safety of the power supply to the electrical load.

[0080] Another embodiment of this application provides another implementation of the high-side drive circuit, the specific structure of which is as follows: Figure 2 As shown, based on the above embodiment, it further includes: a voltage generation circuit 50; its specific connection relationship is as follows:

[0081] The reference terminal of the voltage generation circuit 50 is connected to the connection point of the first power supply terminal of the pull-up current circuit 20 and the first power supply terminal of the pull-down current circuit 30; the first ground terminal of the voltage generation circuit 50 is connected to the high-side ground SW, the second ground terminal of the voltage generation circuit 50 is connected to the low-side ground GND, and the enable terminal of the voltage generation circuit 50 receives the enable signal EN; the output terminal of the voltage generation circuit 50 is connected to the second power supply terminal of the pull-up current circuit 20 and the second power supply terminal of the pull-down current circuit 30, respectively.

[0082] The output voltage of the voltage generation module is equal to the input voltage of the voltage generation module minus the preset voltage. In practical applications, the preset voltage is a voltage value set according to the actual situation, and no specific limitation is made here. All of these are within the protection scope of this application.

[0083] Therefore, the voltage between the two power supply terminals of the pull-up current circuit 20 and the voltage between the two power supply terminals of the pull-down current circuit 30 are both equal to the preset voltage. Thus, the voltage between the two power supply terminals of the pull-up current circuit 20 will not change with the jump of the driving voltage VBST.

[0084] Another embodiment of this application provides a specific implementation of the voltage generation circuit 50, the specific structure of which is as follows: Figure 3 As shown, it specifically includes: a first conversion circuit 51 and a second conversion circuit 52.

[0085] The input terminal of the first conversion circuit 51 receives a preset voltage, the ground terminal of the first conversion circuit 51 is connected to the low-side ground GND, and the output terminal of the first conversion circuit 51 is connected to the input terminal of the second conversion circuit 52.

[0086] The reference terminal of the second conversion circuit 52 serves as the reference terminal of the voltage generation circuit 50. The ground terminal of the second conversion circuit 52 is connected to the high-side ground SW. The output terminal of the second conversion circuit 52 serves as the output terminal of the voltage generation circuit 50.

[0087] Optionally, the preset voltage can be equal to the high level of the enable signal EN. In practical applications, this may include, but is not limited to, this application. It is not specifically limited here and can be determined according to the specific circumstances. All of these are within the protection scope of this application.

[0088] During operation, the first conversion circuit 51 converts the preset voltage into a preset current and inputs it into the second conversion circuit 52; then, after receiving the preset current, the second conversion circuit 52 converts the preset current into a preset voltage; finally, the second conversion circuit 52 subtracts the preset voltage from the potential of its own reference terminal to obtain the output voltage of the second conversion circuit 52.

[0089] This embodiment provides another specific implementation of the first conversion circuit 51 and the second conversion circuit 52, the specific structure of which is as follows: Figure 3 As shown, both together include: three resistors, two capacitors, seven NMOS transistors and two PMOS transistors.

[0090] The connection point between the gate of the first NMOS transistor MN1 and the gate of the second NMOS transistor MN2 is connected to the drain of the first NMOS transistor MN1; the drain of the first NMOS transistor MN1 is connected to one end of the first resistor R1, and the other end of the first resistor R1 receives a preset voltage; the drain of the second NMOS transistor MN2 is connected to the source of the third NMOS transistor MN3, and the drain of the third NMOS transistor MN3 serves as the output terminal for voltage-to-current conversion, and the gate of the third NMOS transistor MN3 receives the enable signal EN; the sources of the first NMOS transistor MN1 and the source of the second NMOS transistor MN2 are both connected to the low-side ground GND; the first NMOS transistor MN1 is the same as the second NMOS transistor MN2.

[0091] The connection point between the gate of the first PMOS transistor MP1 and the gate of the second PMOS transistor MP2 is connected to the drain of the first PMOS transistor MP1; the drain of the first PMOS transistor MP1 serves as the input terminal of the second conversion circuit 52, and the source of the first PMOS transistor MP1 is connected to the source of the fourth NMOS transistor MN4.

[0092] The connection point between the gate of the fourth NMOS transistor MN4 and the gate of the fifth NMOS transistor MN5 is connected to the drain of the fourth NMOS transistor MN4; the drain of the fourth NMOS transistor MN4 is connected to the drain of the fifth NMOS transistor MN5 through the second resistor R2, and the connection point serves as the reference terminal of the second conversion circuit 52.

[0093] The source of the second PMOS transistor MP2 is connected to the source of the fifth NMOS transistor MN5 and the drain of the seventh NMOS transistor MN7. The drain of the second PMOS transistor MP2 is connected to the drain of the sixth NMOS transistor MN6. The connection point between the gate of the sixth NMOS transistor MN6 and the gate of the seventh NMOS transistor MN7 is connected to the drain of the sixth NMOS transistor MN6.

[0094] The connection point between the source of the sixth NMOS transistor MN6 and the source of the seventh NMOS transistor MN7 is connected to the high-side ground SW; one end of the first capacitor C1 is connected to the source of the fourth NMOS transistor MN4, and the other end is connected to the reference terminal of the second conversion circuit 52; one end of the second capacitor C2 is connected to the source of the fifth NMOS transistor MN5, and the other end is connected to the reference terminal of the second conversion circuit 52; one end of the third resistor R3 is connected to the gate of the sixth NMOS transistor MN6, and the other end is connected to the source of the sixth NMOS transistor MN6; the resistance values ​​of the first resistor R1 and the second resistor R2 are the same, and the first NMOS transistor MN1 is the same as the fifth NMOS transistor MN5.

[0095] In this embodiment, the third NMOS, the first PMOS, the second PMOS, the sixth NMOS, and the seventh NMOS are all high-voltage MOS transistors, while the rest are low-voltage MOS transistors.

[0096] Its working principle is as follows:

[0097] Under the preset voltage and the high-level enable signal EN, the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor MN5, the sixth NMOS transistor, the seventh NMOS transistor, the first PMOS transistor MP1, and the second PMOS transistor MP2 are all turned on. Since the first NMOS transistor MN1 and the second NMOS transistor MN2 form a current mirror and the first NMOS transistor MN1 and the second NMOS transistor MN2 are the same, the current in the second resistor R2 is equal to the current in the first resistor R1. Therefore, the voltage across the second resistor R2 is V2 = V1 × R2 ÷ R1 = (VCC - VGS_MN1) × R2 ÷ R1.

[0098] In addition, the output voltage of voltage generation circuit 50 is VBSTmVCC=V2+VGS_MN 5=(VCC-VGS_MN 1)×R2÷R1+VGS_MN 5.

[0099] Since the first resistor R1 and the second resistor R2 have the same resistance value, and the first NMOS transistor MN1 and the fifth NMOS transistor MN5 are the same, VBSTmVCC = VCC.

[0100] The above is only one specific implementation of the first conversion circuit 51 and the second conversion circuit 52. In practical applications, there are other implementations, including but not limited to the above. No specific limitation is made here, and all are within the protection scope of this application.

[0101] Another embodiment of this application provides a specific implementation of the pull-up current circuit 20, the specific structure of which is as follows: Figure 4 As shown, it specifically includes: a first current-stabilizing circuit and a pull-up main circuit.

[0102] The first power supply terminal of the pull-up main circuit receives the driving voltage VBST, the second power supply terminal of the pull-up main circuit receives the target voltage, the ground terminal of the pull-up main circuit is connected to the low-side ground GND, the enable terminal of the pull-up main circuit receives the enable signal EN, the input terminal of the pull-up main circuit receives the first reference current Iref1, the output terminal of the pull-up main circuit serves as the output terminal of the pull-up current circuit 20, and the control terminal of the pull-up main circuit serves as the control terminal of the pull-up current circuit 20. The input terminal of the first current stabilizing circuit is connected to the first power supply terminal of the pull-up main circuit, the ground terminal of the first current stabilizing circuit is connected to the low-side ground GND, and the output terminal of the first current stabilizing circuit is connected to the pull-up main circuit. The first current stabilizing circuit is used to input a compensation current to the pull-up main circuit according to the potential change of the first power supply terminal of the pull-up main circuit.

[0103] In this embodiment, the specific structure of the pull-up main circuit is as follows: Figure 4 As shown, it specifically includes: three NMOS transistors and four PMOS transistors.

[0104] The connection point between the gate of the thirteenth NMOS transistor MN13 and the gate of the fourteenth NMOS transistor MN14 is connected to the drain of the thirteenth NMOS transistor MN13; the drain of the thirteenth NMOS transistor MN13 receives the first reference current Iref1; the connection point between the source of the thirteenth NMOS transistor MN13 and the source of the fourteenth NMOS transistor MN14 is connected to the low-side ground GND.

[0105] The drain of the fourteenth NMOS transistor MN14 is connected to the source of the fifteenth NMOS transistor MN15. The gate of the fifteenth NMOS transistor MN15 receives the enable signal EN. The drain of the fifteenth NMOS transistor MN15, the drain of the ninth PMOS transistor MP9, the gate of the ninth PMOS transistor MP9, the gate of the eleventh PMOS transistor MP11, and the drain of the tenth PMOS transistor MP10 are all connected.

[0106] The sources of the ninth PMOS transistor MP9, the tenth PMOS transistor MP10, and the eleventh PMOS transistor MP11 are all connected, and the connection point serves as the first power supply terminal of the pull-up main circuit; the gate of the tenth PMOS transistor MP10 serves as the control terminal of the pull-up main circuit.

[0107] The drain of the eleventh PMOS transistor MP11 is connected to the source of the twelfth PMOS transistor MP12. The gate of the twelfth PMOS transistor MP12 serves as the second power supply terminal of the pull-up main circuit. The drain of the twelfth PMOS transistor MP12 serves as the output terminal of the pull-up main circuit.

[0108] In this embodiment, the fifteenth NMOS transistor and the twelfth PMOS transistor are both high-voltage MOS transistors, while the rest are low-voltage MOS transistors.

[0109] It should be noted that the pull-up main circuit in this embodiment is the same as that in the prior art, and will not be described again here.

[0110] In the embodiment, the specific structure of the first current stabilizing circuit is as follows: Figure 4 As shown, it specifically includes: the eighth NMOS transistor MN8, the third PMOS transistor MP3, and the fourth PMOS transistor MP4.

[0111] The gate and source of the eighth NMOS transistor MN8 are connected to the low-side ground GND; the drain of the eighth NMOS transistor MN8 is connected to the drain of the third PMOS transistor MP3; the connection point between the gate of the third PMOS transistor MP3 and the gate of the fourth PMOS transistor MP4 is connected to the drain of the third PMOS transistor MP3; the connection point between the source of the third PMOS transistor MP3 and the source of the fourth PMOS transistor MP4 is connected to the first power supply terminal of the pull-up main circuit; the connection point between the gate of the third PMOS transistor MP3 and the gate of the fourth PMOS transistor MP4 is connected to the drain of the third PMOS transistor MP3; the drain of the fourth PMOS transistor MP4 serves as the output terminal of the pull-up main circuit.

[0112] Specifically, the drain of the fourth PMOS transistor MP4 is connected to the drain of the ninth PMOS transistor MP9. When the drive voltage VBST changes, the drain-to-ground current of the eighth NMOS transistor MN8 is used to compensate for the drain-to-ground current of the fifteenth NMOS transistor MN15, so that the output current of the pull-up main circuit is not affected when the drive voltage VBST changes.

[0113] In this embodiment, the eighth NMOS transistor is a high-voltage MOS transistor, and the rest are low-voltage MOS transistors.

[0114] Another embodiment of this application provides a specific implementation of the pull-down current circuit 30, the specific structure of which is as follows: Figure 5 As shown, it specifically includes: a second current stabilizing circuit and a pull-down main circuit.

[0115] The first power supply terminal of the pull-down main circuit receives the driving voltage VBST, the second power supply terminal of the pull-down main circuit receives the target voltage, the first ground terminal of the pull-down main circuit is connected to the high-side ground SW, the second ground terminal of the pull-down main circuit is connected to the low-side ground GND, the enable terminal of the pull-down main circuit receives the enable signal EN, the input terminal of the pull-down main circuit receives the second reference current Iref2, the output terminal of the pull-down main circuit serves as the output terminal of the pull-down current circuit 30, and the control terminal of the pull-down main circuit serves as the control terminal of the pull-down current circuit 30. The reference terminal of the second current stabilizing circuit is connected to the first power supply terminal of the pull-down main circuit. The second current stabilizing circuit is set in the pull-down main circuit and is used to filter out the potential changes of the first power supply terminal of the pull-down main circuit.

[0116] In this embodiment, the specific structure of the pull-down main circuit is as follows: Figure 5 As shown, it specifically includes: nine NMOS transistors and six PMOS transistors.

[0117] The connection point between the gate of the sixteenth NMOS transistor MN16 and the gate of the seventeenth NMOS transistor MN17 is connected to the drain of the sixteenth NMOS transistor MN16; the drain of the sixteenth NMOS transistor MN16 receives the second reference current Iref2; the connection point between the source of the sixteenth NMOS transistor MN16 and the source of the seventeenth NMOS transistor MN17 is connected to the low-side ground GND.

[0118] The drain of the seventeenth NMOS transistor MN17 is connected to the source of the eighteenth NMOS transistor MN18, and the gate of the eighteenth NMOS transistor MN18 receives the enable signal EN.

[0119] The connection point between the gate of the sixteenth PMOS transistor and the gate of the seventeenth PMOS transistor is connected to the drain of the sixteenth PMOS transistor; the drain of the sixteenth PMOS transistor is connected to the drain of the eighteenth NMOS transistor MN18.

[0120] The drain of the seventeenth PMOS transistor is connected to the source of the twenty-first PMOS transistor, and the drain of the twenty-first PMOS transistor is connected to the drain of the nineteenth NMOS transistor MN19 and the gate of the nineteenth NMOS transistor MN19, respectively.

[0121] The source of the nineteenth NMOS transistor MN19 is connected to the gate of the twentieth NMOS transistor MN20, the source of the twentieth NMOS transistor MN20 is connected to the gate of the twenty-first NMOS transistor MN21, and the source of the twenty-first NMOS transistor MN21 is connected to the high-side ground SW.

[0122] The source of the eighteenth PMOS transistor serves as the first power supply terminal of the pull-down main circuit. The gate of the eighteenth PMOS transistor is connected to the gate of the sixteenth PMOS transistor. The drain of the eighteenth PMOS transistor is connected to the source of the nineteenth PMOS transistor. The gate of the nineteenth PMOS transistor serves as the control terminal of the pull-down main circuit.

[0123] The drain of the nineteenth PMOS transistor is connected to the source of the twentieth PMOS transistor; the gate of the twentieth PMOS transistor is connected to the gate of the twenty-first PMOS transistor, and the connection point serves as the second power supply terminal of the pull-down main circuit; the drain of the twentieth PMOS transistor is connected to the drain of the twenty-second NMOS transistor MN22.

[0124] The connection point between the gate of the 22nd NMOS transistor MN22 and the gate of the 23rd NMOS transistor MN23 is connected to the drain of the 22nd NMOS transistor MN22; the connection point between the source of the 22nd NMOS transistor MN22 and the source of the 23rd NMOS transistor MN23 is connected to the high-side ground SW.

[0125] The drain of the 23rd NMOS transistor MN23 is connected to the source of the 24th NMOS transistor MN24, and the gate of the 24th NMOS transistor MN24 is connected to the gate of the 19th NMOS transistor MN19. The drain of the 24th NMOS transistor MN24 serves as the output terminal of the pull-down main circuit.

[0126] It should be noted that the pull-down main circuit in this embodiment is the same as the prior art, and will not be described again here; in addition, it should be noted that in practical applications, the sixteenth NMOS transistor MN16 in the pull-down main circuit can use the same NMOS transistor as the thirteenth NMOS transistor MN13 in the pull-up main circuit. No specific limitation is made here, and it can be determined according to the specific situation. All of them are within the protection scope of this application.

[0127] In this embodiment, the eighth NMOS transistor is a high-voltage MOS transistor, and the rest are low-voltage MOS transistors.

[0128] The eighteenth NMOS transistor, the twenty-first PMOS transistor, the twentieth PMOS transistor, and the twenty-fourth MOS transistor are all high-voltage MOS transistors, while the rest are low-voltage MOS transistors.

[0129] In the embodiment, the specific structure of the second current stabilizing circuit is as follows: Figure 5 As shown, it specifically includes: the third capacitor C3, the fourth resistor R4, and the fifth resistor R5.

[0130] The fourth resistor R4 and the fifth resistor R5 are connected in series in the pull-down main circuit; the connection point of the fourth resistor R4 and the fifth resistor R5 is connected to the first power supply terminal of the pull-down main circuit through the third capacitor C3.

[0131] Specifically, one end of the fourth resistor R4 is connected to one end of the fifth resistor R5, the other end of the fourth resistor R4 is connected to the drain of the sixteenth PMOS transistor, and the other end of the fifth resistor R5 is connected to the drain of the eighteenth NMOS transistor MN18.

[0132] When the drive voltage VBST changes, the third capacitor C3, the fourth resistor R4, and the fifth resistor R5 filter the drive voltage VBST to ensure the stability of the output current pulling down the main current.

[0133] Another embodiment of this application provides a specific implementation of the low-side to high-side circuit 10, the specific structure of which is as follows: Figure 6 As shown, it specifically includes: four NMOS transistors, four PMOS transistors, and three inverters.

[0134] The connection point between the source of the ninth NMOS transistor MN9 and the source of the tenth NMOS transistor MN10 is connected to the low-side ground GND; the gate of the tenth NMOS transistor MN10 is connected to the output terminal of the first inverter; the gate of the ninth NMOS transistor MN9 and the input terminal of the first inverter are both connected to the signal input terminal of the low-side to high-side circuit 10.

[0135] The drain of the ninth NMOS transistor MN9 is connected to the source of the eleventh NMOS transistor MN11. The gate of the eleventh NMOS transistor MN11 receives the enable signal EN. The drain of the eleventh NMOS transistor MN11 is connected to the drain of the fifth PMOS transistor MP5. The drain of the tenth NMOS transistor MN10 is connected to the source of the twelfth NMOS transistor MN12. The gate of the twelfth NMOS transistor MN12 receives the enable signal EN. The drain of the twelfth NMOS transistor MN12 is connected to the drain of the sixth PMOS transistor MP6.

[0136] The gates of the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6 are both connected to the high-side ground SW; the source of the fifth PMOS transistor MP5 is connected to the drain of the seventh PMOS transistor MP7 and the gate of the eighth PMOS transistor MP8, respectively; the source of the sixth PMOS transistor MP6 is connected to the drain of the eighth PMOS transistor MP8 and the gate of the seventh PMOS transistor MP7, respectively.

[0137] The connection point between the source of the seventh PMOS transistor MP7 and the source of the eighth PMOS transistor MP8 serves as the power supply terminal of the low-side to high-side circuit 10; the input terminal of the second inverter is connected to the drain of the eighth PMOS transistor MP8, the output terminal of the second inverter is connected to the input terminal of the third inverter, and the output terminal of the third inverter serves as the signal output terminal of the low-side to high-side circuit 10.

[0138] In this embodiment, the eleventh MOS transistor, the twelfth MOS transistor, the fifth PMOS transistor, and the sixth PMOS transistor are high-voltage MOS transistors, while the rest are low-voltage MOS transistors.

[0139] Another embodiment of this application provides a specific implementation of a bootstrap circuit, the specific structure of which is as follows: Figure 7 (only in) Figure 1 As shown in the diagram (based on the above), it includes: a fourth capacitor C4 and a diode Z; wherein, the positive terminal of the diode Z receives the power supply voltage Vv, the negative terminal of the diode Z serves as the output terminal of the bootstrap circuit, one end of the fourth capacitor C4 is connected to the negative terminal of the diode Z, and the other end of the fourth capacitor C4 is connected to the high-side ground SW.

[0140] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.

[0141] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0142] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0143] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the core spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A high-side driving circuit, characterized in that, include: Low-side to high-side circuit, pull-up current circuit, pull-down current circuit, and bootstrap circuit; among which: The input terminal of the bootstrap circuit is connected to the power supply terminal of the corresponding branch of the high-side drive circuit; the output terminal of the bootstrap circuit is connected to the first power supply terminal of the pull-up current circuit, the first power supply terminal of the pull-down current circuit, and the power supply terminal of the low-side to high-side circuit. The signal input terminal of the low-side to high-side conversion circuit serves as the input terminal of the high-side driving circuit. The signal output terminal of the low-side to high-side circuit is connected to the control terminal of the pull-up current circuit and the control terminal of the pull-down current circuit, respectively. The output terminal of the pull-up current circuit is connected to the output terminal of the pull-down current circuit, and the connection point serves as the output terminal of the high-side drive circuit. The pull-up current circuit includes a first current stabilizing circuit and a pull-up main circuit; the input terminal of the pull-up main circuit receives a first reference current, the output terminal of the pull-up main circuit serves as the output terminal of the pull-up current circuit, and the control terminal of the pull-up main circuit serves as the control terminal of the pull-up current circuit; the input terminal of the first current stabilizing circuit is connected to the first power supply terminal of the pull-up main circuit, the ground terminal of the first current stabilizing circuit is connected to the low-side ground, and the output terminal of the first current stabilizing circuit is connected to the pull-up main circuit; the first current stabilizing circuit is used to input a compensation current to the pull-up main circuit according to the potential change of the first power supply terminal of the pull-up main circuit. The pull-down current circuit includes a second current stabilizing circuit and a pull-down main circuit; the input terminal of the pull-down main circuit receives a second reference current, the output terminal of the pull-down main circuit serves as the output terminal of the pull-down current circuit, and the control terminal of the pull-down main circuit serves as the control terminal of the pull-down current circuit; the reference terminal of the second current stabilizing circuit is connected to the first power supply terminal of the pull-down main circuit, the second current stabilizing circuit is disposed in the pull-down main circuit, and the second current stabilizing circuit is used to filter out potential changes at the first power supply terminal of the pull-down main circuit.

2. The high-side driving circuit according to claim 1, characterized in that, Also includes: Voltage generation circuit; wherein: The reference terminal of the voltage generation circuit is connected to the connection point between the first power supply terminal (VBST) of the pull-up current circuit and the first power supply terminal of the pull-down current circuit. The output terminal of the voltage generation circuit is connected to the second power supply terminal of the pull-up current circuit and the second power supply terminal of the pull-down current circuit, respectively. The output voltage of the voltage generation circuit is equal to the input voltage of the voltage generation circuit minus the preset voltage.

3. The high-side driving circuit according to claim 2, characterized in that, The voltage generation circuit includes: a first conversion circuit and a second conversion circuit; wherein: The input terminal of the first conversion circuit receives the preset voltage, and the output terminal of the first conversion circuit is connected to the input terminal of the second conversion circuit. The first conversion circuit is used to convert the preset voltage into a preset current. The reference terminal of the second conversion circuit serves as the reference terminal of the voltage generation circuit, and the output terminal of the second conversion circuit serves as the output terminal of the voltage generation circuit. The second conversion circuit is used to convert the preset current into a preset voltage, and the output voltage of the second conversion circuit is equal to the potential of its own reference terminal minus the preset voltage.

4. The high-side driving circuit according to claim 3, characterized in that, The first conversion circuit includes: a first resistor, a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor; wherein: The connection point between the gate of the first NMOS transistor and the gate of the second NMOS transistor is connected to the drain of the first NMOS transistor. The drain of the first NMOS transistor is connected to one end of the first resistor, and the other end of the first resistor receives the preset voltage. The drain of the second NMOS transistor is connected to the source of the third NMOS transistor. The drain of the third NMOS transistor serves as the output terminal of the first conversion circuit, and the gate of the third NMOS transistor receives an enable signal. The source of both the first NMOS transistor and the source of the second NMOS transistor are connected to the low-side ground. The first NMOS transistor is the same as the second NMOS transistor.

5. The high-side driving circuit according to claim 4, characterized in that, The second conversion circuit includes: a second resistor, a third resistor, a first capacitor, a second capacitor, a first PMOS transistor, a second PMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor; wherein: The connection point between the gate of the first PMOS transistor and the gate of the second PMOS transistor is connected to the drain of the first PMOS transistor. The drain of the first PMOS transistor serves as the input terminal of the second conversion circuit, and the source of the first PMOS transistor is connected to the source of the fourth NMOS transistor. The connection point between the gate of the fourth NMOS transistor and the gate of the fifth NMOS transistor is connected to the drain of the fourth NMOS transistor. The drain of the fourth NMOS transistor is connected to the drain of the fifth NMOS transistor through a second resistor, and the connection point serves as the reference terminal of the second conversion circuit. The source of the second PMOS transistor is connected to the source of the fifth NMOS transistor and the drain of the seventh NMOS transistor, respectively, and the drain of the second PMOS transistor is connected to the drain of the sixth NMOS transistor. The connection point between the gate of the sixth NMOS transistor and the gate of the seventh NMOS transistor is connected to the drain of the sixth NMOS transistor, respectively. The connection point between the source of the sixth NMOS transistor and the source of the seventh NMOS transistor is connected to the high-side ground. One end of the first capacitor is connected to the source of the fourth NMOS transistor, and the other end is connected to the reference terminal of the second conversion circuit; One end of the second capacitor is connected to the source of the fifth NMOS transistor, and the other end is connected to the reference terminal of the second conversion circuit; One end of the third resistor is connected to the gate of the sixth NMOS transistor, and the other end is connected to the source of the sixth NMOS transistor; The first resistor and the second resistor have the same resistance value, and the first NMOS transistor is the same as the fifth NMOS transistor.

6. The high-side driving circuit according to claim 1, characterized in that, The first current-stabilizing circuit includes: an eighth NMOS transistor, a third PMOS transistor, and a fourth PMOS transistor; wherein: The connection point between the gate and source of the eighth NMOS transistor is connected to the low-side ground. The drain of the eighth NMOS transistor is connected to the drain of the third PMOS transistor. The connection point between the gate of the third PMOS transistor and the gate of the fourth PMOS transistor is connected to the drain of the third PMOS transistor. The connection point between the source of the third PMOS transistor and the source of the fourth PMOS transistor is connected to the first power supply terminal of the pull-up main circuit. The connection point between the gate of the third PMOS transistor and the gate of the fourth PMOS transistor is connected to the drain of the third PMOS transistor. The drain of the fourth PMOS transistor serves as the output terminal of the pull-up main circuit.

7. The high-side driving circuit according to claim 1, characterized in that, The second current-stabilizing circuit includes: a third capacitor, a fourth resistor, and a fifth resistor; wherein: The fourth resistor and the fifth resistor are connected in series in the pull-down main circuit; The connection point of the fourth resistor and the fifth resistor is connected to the first power supply terminal of the pull-down main circuit through the third capacitor.

8. The high-side driving circuit according to any one of claims 1 to 5, characterized in that, The low-side to high-side conversion circuit includes: a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a first inverter, a second inverter, and a third inverter; wherein: The connection point between the source of the ninth NMOS transistor and the source of the tenth NMOS transistor is connected to the low-side ground. The gate of the tenth NMOS transistor is connected to the output terminal of the first inverter, and the gate of the ninth NMOS transistor and the input terminal of the first inverter are both connected to the signal input terminal of the low-side to high-side circuit. The drain of the ninth NMOS transistor is connected to the source of the eleventh NMOS transistor, the gate of the eleventh NMOS transistor receives an enable signal, and the drain of the eleventh NMOS transistor is connected to the drain of the fifth PMOS transistor. The drain of the tenth NMOS transistor is connected to the source of the twelfth NMOS transistor, the gate of the twelfth NMOS transistor receives the enable signal, and the drain of the twelfth NMOS transistor is connected to the drain of the sixth PMOS transistor. The gates of the fifth PMOS transistor and the sixth PMOS transistor are both connected to high-side ground. The source of the fifth PMOS transistor is connected to the drain of the seventh PMOS transistor and the gate of the eighth PMOS transistor, respectively. The source of the sixth PMOS transistor is connected to the drain of the eighth PMOS transistor and the gate of the seventh PMOS transistor, respectively. The connection point between the source of the seventh PMOS transistor and the source of the eighth PMOS transistor serves as the power supply terminal of the low-side to high-side circuit. The input terminal of the second inverter is connected to the drain of the eighth PMOS transistor, and the output terminal of the second inverter is connected to the input terminal of the third inverter. The output terminal of the third inverter serves as the signal output terminal of the low-side to high-side circuit.

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