Encoding method and encoder, decoding method and decoder, communication system

Abstract

The present disclosure provides an encoding method and an encoder, a decoding method and a decoder, and a communication system, and relates to the field of communication. The encoding method comprises: obtaining a plurality of to-be-transmitted bit sequences; and performing an encoding operation on each of the plurality of to-be-transmitted bit sequences by using a corresponding frozen bit distribution model in a plurality of preset frozen bit distribution models to obtain a plurality of encoded bit sequences, wherein the plurality of frozen bit distribution models are arranged in a predetermined order. The decoding method comprises: receiving a group of to-be-decoded sequences, wherein the to-be-decoded sequences comprise a plurality of to-be-decoded log likelihood ratio (LLR) sequences; and performing a decoding operation on each of the plurality of to-be-decoded LLR sequences by using a corresponding frozen bit distribution model in a plurality of preset frozen bit distribution models, wherein the plurality of frozen bit distribution models are arranged in a predetermined order, and the plurality of frozen bit distribution models are the same as those set in a corresponding target encoder and the decoder.

Description

Technical Field

[0001] This disclosure relates to the field of communications, and in particular to an encoding method and encoder, a decoding method and decoder, and a communication system. Background Technology

[0002] In a transmission system using CA-SCL (CRC-Aided Successive Cancellation List) polar code encoding and decoding, the encoding and decoding sides employ the exact same frozen bit distribution model. The SCL decoder directly classifies a bit as a frozen bit (typically 0) regardless of the calculated log-likelihood ratio. Simulation results show that polar code decoding is highly sensitive to differences in the frozen bit distribution model; even a slight difference between the frozen bit distribution model used by the decoder and the encoding side can lead to complete decoding failure. Therefore, this characteristic allows for easy implementation of multi-user transmission based on the polar code frozen bit distribution model. Summary of the Invention

[0003] The inventors discovered through research that, in related technologies, the difference window length 2P that satisfies decoding performance requirements is very small in scenarios involving short codes (e.g., 128 bits), medium codes with high code rates (e.g., N=512, R=7 / 8), and medium codes with low code rates (e.g., N=512, R=1 / 8). In other words, the number of available frozen bit distribution models is very limited, making it difficult to meet the needs of a massive number of users.

[0004] Accordingly, this disclosure provides a coding and decoding scheme that uses multiple frozen bit distribution models arranged in a predetermined order on both the encoder and decoder sides. If the number of frozen bit distribution models used by the encoder and decoder differs, or if the order of the frozen bit distribution models differs, decoding failure will occur. Compared to a scheme where only one frozen bit distribution model is configured in both the encoder and decoder, the scheme of configuring multiple frozen bit distribution models arranged in a predetermined order in both the encoder and decoder can effectively expand the user scale and is suitable for multi-user coding and decoding transmission in scenarios with short codes, medium codes at high code rates, and medium codes at low code rates.

[0005] According to a first aspect of the present disclosure, an encoding method is provided, executed by an encoder, comprising: acquiring a plurality of bit sequences to be transmitted; encoding each of the plurality of bit sequences to be transmitted using a corresponding frozen bit distribution model among a plurality of preset frozen bit distribution models to obtain a plurality of encoded bit sequences, wherein the plurality of frozen bit distribution models are arranged in a predetermined order and the plurality of frozen bit distribution models are not completely identical.

[0006] In some embodiments, the encoding operation includes: arranging each bit sequence to be transmitted using a corresponding frozen bit distribution model to generate multiple bit sequences to be encoded; and encoding each bit sequence to be encoded in the multiple bit sequences to be encoded to generate multiple encoded bit sequences.

[0007] In some embodiments, encoding each of the plurality of bit sequences to be encoded includes: performing polar code encoding on each of the plurality of bit sequences to be encoded.

[0008] In some embodiments, each bit sequence to be transmitted is arranged using a corresponding frozen bit distribution model to generate multiple bit sequences to be encoded, including: performing a check code generation operation on each bit sequence to be transmitted in the multiple bit sequences to be encoded to obtain multiple check codes; and arranging each check code and the corresponding bit sequence to be transmitted in the multiple check codes using the corresponding frozen bit distribution model to generate multiple bit sequences to be encoded.

[0009] In some embodiments, the plurality of coded bit sequences are sent to a decoder.

[0010] According to a second aspect of the present disclosure, an encoder is provided, comprising: a first encoding processing module configured to acquire a plurality of bit sequences to be transmitted; and a second encoding processing module configured to encode each of the plurality of bit sequences to be transmitted using a corresponding frozen bit distribution model among a plurality of preset frozen bit distribution models to obtain a plurality of encoded bit sequences, wherein the plurality of frozen bit distribution models are arranged in a predetermined order and are not completely identical.

[0011] In some embodiments, the second encoding processing module is configured to arrange each bit sequence to be transmitted using a corresponding frozen bit distribution model to generate multiple bit sequences to be encoded, and to encode each bit sequence to be encoded in the multiple bit sequences to generate multiple encoded bit sequences.

[0012] In some embodiments, the second encoding processing module is configured to perform polar code encoding on each of the plurality of bit sequences to be encoded.

[0013] In some embodiments, the second encoding processing module is configured to perform check code generation operations on each of the plurality of bit sequences to be encoded and transmitted to obtain a plurality of check codes, and to arrange each of the plurality of check codes and the corresponding bit sequence to be transmitted using a corresponding frozen bit distribution model to generate a plurality of bit sequences to be encoded.

[0014] In some embodiments, the second encoding processing module is configured to send the plurality of encoded bit sequences to the decoder.

[0015] According to a third aspect of the present disclosure, an encoder is provided, comprising: a memory configured to store instructions; and a processor coupled to the memory, the processor being configured to execute the encoding method as described in any of the foregoing embodiments based on the instructions stored in the memory.

[0016] According to a fourth aspect of the present disclosure, a decoding method is provided, executed by a decoder, comprising: receiving a set of sequences to be decoded, wherein the sequences to be decoded include a plurality of log-likelihood ratio sequences to be decoded; performing a decoding operation on each of the plurality of log-likelihood ratio sequences to be decoded using a frozen bit distribution model corresponding to a preset plurality of frozen bit distribution models, wherein the plurality of frozen bit distribution models are arranged in a predetermined order, the plurality of frozen bit distribution models are not completely identical, and the plurality of frozen bit distribution models and their arrangement order in the decoder are the same as the plurality of frozen bit distribution models and their arrangement order in a corresponding target encoder.

[0017] In some embodiments, the decoding operation includes: performing polar code decoding on each of the plurality of log-likelihood ratio sequences to be decoded using the corresponding frozen bit distribution model among a plurality of preset frozen bit distribution models.

[0018] In some embodiments, the polar code decoding operation includes: performing polar code decoding on each of the plurality of log-likelihood ratio sequences to be decoded in sequence to generate multiple sets of candidate bit sequences, wherein each set of candidate bit sequences includes multiple candidate bit sequences; verifying each set of candidate bit sequences to obtain multiple decoded bit sequences; if at least one candidate bit sequence in each set of candidate bit sequences passes the verification, then determining that the set of sequences to be decoded comes from the target encoder, and performing reverse encoding on each of the plurality of decoded bit sequences using the corresponding frozen bit distribution model to obtain multiple decoding results.

[0019] In some embodiments, if at least one set of candidate bit sequences among multiple sets of candidate bit sequences fails the verification, then based on the verification results of multiple sets of candidate bit sequences corresponding to each set of M consecutively received sequences to be decoded, it is determined whether the M sets of sequences to be decoded come from the target encoder, where M is a positive integer; wherein, if at least one candidate bit sequence in each set of candidate bit sequences corresponding to each set of M consecutively received sequences to be decoded passes the verification, then it is determined that the M sets of sequences to be decoded come from the target encoder, and each of the multiple decoded bit sequences is de-sorted using the corresponding frozen bit distribution model to obtain multiple decoding results.

[0020] In some embodiments, if at least one set of candidate bit sequences fails the verification in each of the multiple sets of candidate bit sequences corresponding to the M sets of sequences to be decoded in succession, then the M sets of sequences to be decoded are determined to be from a non-target encoder.

[0021] In some embodiments, the magnitude of parameter M is positively correlated with the block error rate.

[0022] According to a fifth aspect of the present disclosure, a decoder is provided, comprising: a first decoding processing module configured to receive a set of sequences to be decoded, wherein the sequences to be decoded include a plurality of log-likelihood ratio sequences to be decoded; and a second decoding processing module configured to perform a decoding operation on each of the plurality of log-likelihood ratio sequences to be decoded using a frozen bit distribution model corresponding to a preset plurality of frozen bit distribution models, wherein the plurality of frozen bit distribution models are arranged in a predetermined order, the plurality of frozen bit distribution models are not completely identical, and the plurality of frozen bit distribution models and their arrangement order in the decoder are the same as the plurality of frozen bit distribution models and their arrangement order in a corresponding target encoder.

[0023] In some embodiments, the second decoding processing module is configured to perform polar code decoding operation on each of the plurality of log-likelihood ratio sequences to be decoded using the corresponding frozen bit distribution model among a plurality of preset frozen bit distribution models.

[0024] In some embodiments, the second decoding processing module is configured to perform polar code decoding on each of the plurality of log-likelihood ratio sequences to be decoded in sequence to generate multiple sets of candidate bit sequences, wherein each set of candidate bit sequences includes multiple candidate bit sequences. Each set of candidate bit sequences is verified to obtain multiple decoded bit sequences. If at least one candidate bit sequence in each set of candidate bit sequences passes the verification, it is determined that the set of sequences to be decoded comes from the target encoder. Each of the plurality of decoded bit sequences is then de-sorted using the corresponding frozen bit distribution model to obtain multiple decoding results.

[0025] In some embodiments, the second decoding processing module is configured to, if at least one set of candidate bit sequences in a plurality of candidate bit sequences fails the verification, determine whether the M sets of candidate bit sequences to be decoded come from the target encoder based on the verification results of the plurality of candidate bit sequences corresponding to each set of candidate bit sequences in the continuously received M sets of candidate bit sequences to be decoded, where M is a positive integer. If at least one candidate bit sequence in each set of candidate bit sequences corresponding to each set of candidate bit sequences in the continuously received M sets of candidate bit sequences to be decoded passes the verification, then it is determined that the M sets of candidate bit sequences to be decoded come from the target encoder, and each of the plurality of decoded bit sequences is de-sorted using the corresponding frozen bit distribution model to obtain multiple decoding results.

[0026] In some embodiments, the second decoding processing module is configured to determine that the M groups of sequences to be decoded come from a non-target encoder if at least one set of candidate bit sequences in each of the multiple sets of candidate bit sequences corresponding to the M groups of sequences to be decoded in succession fails the verification.

[0027] In some embodiments, the magnitude of parameter M is positively correlated with the block error rate.

[0028] According to a sixth aspect of the present disclosure, a decoder is provided, comprising: a memory configured to store instructions; and a processor coupled to the memory, the processor being configured to execute the decoding method as described in any of the foregoing embodiments based on the instructions stored in the memory.

[0029] According to a seventh aspect of the present disclosure, a communication system is provided, comprising: an encoder as described in any of the preceding embodiments; and a decoder as described in any of the preceding embodiments.

[0030] According to an eighth aspect of the present disclosure, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions that, when executed by a processor, implement the method as described in any of the above embodiments.

[0031] Other features and advantages of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a flowchart illustrating an encoding method according to an embodiment of the present disclosure;

[0034] Figure 2 This is a schematic flowchart of the encoder side according to an embodiment of the present disclosure;

[0035] Figure 3 This is a schematic diagram of the structure of an encoder according to an embodiment of the present disclosure;

[0036] Figure 4 This is a schematic diagram of the encoder structure according to another embodiment of the present disclosure;

[0037] Figure 5 This is a flowchart illustrating a decoding method according to an embodiment of the present disclosure;

[0038] Figure 6 This is a schematic diagram of the decoder side of one embodiment of the present disclosure;

[0039] Figure 7 This is a schematic diagram of the structure of a decoder according to an embodiment of the present disclosure;

[0040] Figure 8 This is a schematic diagram of the structure of a decoder according to another embodiment of the present disclosure;

[0041] Figure 9 This is a schematic diagram of the structure of a communication system according to an embodiment of the present disclosure. Detailed Implementation

[0042] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0043] Unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure.

[0044] At the same time, it should be understood that, for ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn according to actual scale.

[0045] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0046] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0047] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0048] Figure 1 This is a schematic flowchart illustrating an encoding method according to an embodiment of the present disclosure. In some embodiments, the following encoding method is performed by an encoder.

[0049] In step 101, multiple bit sequences to be transmitted are obtained.

[0050] In step 102, each of the multiple bit sequences to be transmitted is encoded using the corresponding frozen bit distribution model in the multiple preset frozen bit distribution models to obtain multiple encoded bit sequences, wherein the multiple frozen bit distribution models are arranged in a predetermined order.

[0051] It should be noted that the frozen bit distribution model refers to the distribution pattern of frozen bits in the bit sequence to be encoded. Different distribution patterns of frozen bits in the bit sequence to be encoded result in different frozen bit distribution models.

[0052] The frozen channel distribution model is determined based on the reliability of the polar code polar channel, the length of the polar code, and the number of information bits. The frozen bit distribution model is determined by the frozen channel distribution model, and the distribution pattern of frozen bits in the bit sequence to be encoded is exactly the same as the distribution pattern of the frozen channel in the polar code polar channel.

[0053] In some embodiments, the above encoding operation includes:

[0054] 1) Arrange each bit sequence to be transmitted using the corresponding frozen bit distribution model to generate multiple bit sequences to be encoded.

[0055] In some embodiments, a checksum generation operation is performed on each of the multiple bit sequences to be encoded and transmitted to obtain multiple checksums. Next, each checksum and its corresponding bit sequence to be transmitted are arranged using a corresponding frozen bit distribution model to generate multiple bit sequences to be encoded.

[0056] For example, the first bit sequence to be transmitted and its corresponding check code are arranged using the second frozen bit distribution model to obtain the first bit sequence to be encoded. The second bit sequence to be transmitted and its corresponding check code are arranged using the first frozen bit distribution model to obtain the second bit sequence to be encoded.

[0057] 2) Encode each of the multiple bit sequences to be encoded to generate multiple encoded bit sequences.

[0058] In some embodiments, each of the multiple bit sequences to be encoded is polar-coded to generate multiple encoded bit sequences.

[0059] In some embodiments, multiple coded bit sequences are sent to the decoder.

[0060] It should be noted that the decoder and the corresponding target encoder have the same set of frozen bit distribution models, meaning the number of frozen bit distribution models is the same and their arrangement order is identical. This ensures that the decoder can only successfully decode sequences from the target encoder, and cannot successfully decode sequences from non-target encoders, thus effectively realizing multi-user transmission based on the polar code frozen bit distribution model.

[0061] like Figure 2 As shown, on the encoder side, check code generation operations are performed on each of the multiple bit sequences to be encoded and transmitted to obtain multiple check codes.

[0062] Next, each check code and its corresponding bit sequence to be transmitted are arranged using the corresponding frozen bit distribution model in the frozen bit distribution model group to generate multiple bit sequences to be encoded.

[0063] Next, each of the multiple bit sequences to be encoded is encoded using polar codes to generate multiple encoded bit sequences, which are then sent to the decoder via the channel.

[0064] Figure 3 This is a schematic diagram of the structure of an encoder according to an embodiment of this disclosure. Figure 3As shown, the encoder includes a first encoding processing module 31 and a second encoding processing module 32.

[0065] The first encoding processing module 31 is configured to acquire multiple bit sequences to be transmitted.

[0066] The second encoding processing module 32 is configured to encode each of the multiple bit sequences to be transmitted using the corresponding frozen bit distribution model among the multiple preset frozen bit distribution models to obtain multiple encoded bit sequences, wherein the multiple frozen bit distribution models are arranged in a predetermined order and the multiple frozen bit distribution models are not completely the same.

[0067] In some embodiments, the second encoding processing module 32 arranges each bit sequence to be transmitted using the corresponding frozen bit distribution model to generate multiple bit sequences to be encoded, and encodes each bit sequence to be encoded in the multiple bit sequences to generate multiple encoded bit sequences.

[0068] For example, the second encoding processing module 32 performs polar code encoding on each of the multiple bit sequences to be encoded to generate multiple bit sequences to be encoded.

[0069] In some embodiments, the second encoding processing module 32 performs check code generation operations on each of the multiple bit sequences to be encoded and transmitted to obtain multiple check codes, and arranges each check code and the corresponding bit sequence to be transmitted using the corresponding frozen bit distribution model to generate multiple bit sequences to be encoded.

[0070] In some embodiments, the second encoding processing module 32 sends a plurality of encoded bit sequences to the decoder.

[0071] It should be noted that the decoder and encoder use the same set of frozen bit distribution models. This means that while the frozen bit distribution models in the set are not identical, the number of models is the same, and their arrangement is identical. This ensures that the decoder can only successfully decode sequences from the target encoder, and will not be able to decode sequences from non-target encoders, thus effectively enabling multi-user transmission based on the polar code frozen bit distribution model.

[0072] Figure 4 This is a schematic diagram of the encoder structure according to another embodiment of this disclosure. Figure 4 As shown, the encoder includes a memory 41 and a processor 42.

[0073] Memory 41 is used to store instructions, and processor 42 is coupled to memory 41. Processor 42 is configured to execute instructions based on the memory storage, as shown in the example. Figure 1 The method involved in any of the embodiments.

[0074] like Figure 4 As shown, the encoder also includes a communication interface 43 for exchanging information with other devices. Additionally, the encoder includes a bus 44, through which the processor 42, communication interface 43, and memory 41 communicate with each other.

[0075] The memory 41 may include high-speed RAM, and may also include non-volatile memory, such as at least one disk storage device. The memory 41 may also be a memory array. The memory 41 may also be divided into blocks, and the blocks may be combined into virtual volumes according to certain rules.

[0076] Furthermore, processor 42 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present disclosure.

[0077] This disclosure also relates to a computer-readable storage medium storing computer instructions that, when executed by a processor, implement... Figure 1 The method involved in any of the embodiments.

[0078] Figure 5 This is a schematic flowchart illustrating a decoding method according to an embodiment of the present disclosure. In some embodiments, the following decoding method is performed by a decoder.

[0079] In step 501, a set of sequences to be decoded is received, wherein the sequences to be decoded include multiple sequences of log-likelihood ratios to be decoded.

[0080] In step 502, each of the multiple log-likelihood ratio sequences to be decoded is decoded using the corresponding frozen bit distribution model from among the multiple preset frozen bit distribution models. The multiple frozen bit distribution models are arranged in a predetermined order, and the multiple frozen bit distribution models are not completely identical. The multiple frozen bit distribution models and their arrangement order in the decoder are the same as those in the corresponding target encoder.

[0081] In some embodiments, the above decoding operation includes: performing polar code decoding operation on each of the plurality of log-likelihood ratio sequences to be decoded using the corresponding frozen bit distribution model among the plurality of preset frozen bit distribution models.

[0082] For example, the polar code decoding operations described above include:

[0083] 1) Perform polar code decoding on each of the multiple log-likelihood ratio sequences to be decoded in sequence to generate multiple sets of candidate bit sequences, wherein each set of candidate bit sequences includes multiple candidate bit sequences.

[0084] For example, CA-SCL decoding or PC-CA-SCL decoding is performed sequentially on each of the multiple log-likelihood ratio sequences to be decoded to generate multiple sets of candidate bit sequences.

[0085] 2) Verify each of the multiple candidate bit sequences to obtain multiple decoded bit sequences.

[0086] 3) If at least one candidate bit sequence in each set of candidate bit sequences passes the check, then the received set of decoded sequences is determined to be from the target encoder. Each decoded bit sequence in the multiple decoded bit sequences is then de-sorted using the corresponding frozen bit distribution model to obtain multiple decoding results. Here, the polar codes that fail the check can be called error blocks.

[0087] It should be noted that the reverse arrangement performed by the decoder is the inverse operation of the arrangement performed in the target encoder.

[0088] In some embodiments, if at least one set of candidate bit sequences among multiple sets of candidate bit sequences fails the verification, then based on the verification results of multiple sets of candidate bit sequences corresponding to each set of M sets of sequences to be decoded received consecutively, it is determined whether the M sets of sequences to be decoded are from the target encoder, where M is a positive integer.

[0089] If, in each of the multiple candidate bit sequences corresponding to the M groups of sequences to be decoded received consecutively, at least one candidate bit sequence in each candidate bit sequence passes the verification, then it is determined that the M groups of sequences to be decoded come from the target encoder. Each of the multiple decoded bit sequences is then reverse-sorted using the corresponding frozen bit distribution model to obtain multiple decoding results.

[0090] If, in each of the M groups of sequences to be decoded received consecutively, at least one set of candidate bit sequences fails the verification, then the M groups of sequences to be decoded are determined to be from a non-target encoder.

[0091] It should be noted that if one set of candidate bit sequences fails the verification, it could be due to channel noise interference or the non-target encoder using different frozen bit distribution model groups. In this case, decoding operations need to be performed on the continuously received multiple sets of sequences to be decoded. If at least one candidate bit sequence in each of the multiple sets of candidate bit sequences corresponding to each of the M continuously received sets of sequences to be decoded passes the verification, then the M sets of sequences to be decoded are determined to be from the target encoder. If at least one candidate bit sequence in each of the multiple sets of candidate bit sequences corresponding to each of the M continuously received sets of sequences to be decoded fails the verification, then the M sets of sequences to be decoded are determined to be from a non-target encoder.

[0092] In some embodiments, the magnitude of parameter M is positively correlated with the block error rate (BRR). The higher the BRR, the greater the number of consecutively received sequences to be decoded; conversely, the lower the BRR, the smaller the number of consecutively received sequences to be decoded.

[0093] like Figure 6 As shown, on the decoder side, CA-SCL decoding or PC-CA-SCL decoding is performed on each of the multiple log-likelihood ratio sequences to be decoded in sequence to generate multiple sets of candidate bit sequences, wherein each set of candidate bit sequences includes multiple candidate bit sequences.

[0094] Next, each of the multiple candidate bit sequences is verified to obtain multiple decoded bit sequences.

[0095] Next, if at least one candidate bit sequence in each set of candidate bit sequences passes the verification, it is determined that the received set of decoded sequences comes from the target encoder. Each decoded bit sequence in the multiple decoded bit sequences is de-sorted using the corresponding frozen bit distribution model to obtain multiple decoding results.

[0096] Figure 7 This is a schematic diagram of the structure of a decoder according to an embodiment of this disclosure. Figure 7 As shown, the decoder includes a first decoding processing module 71 and a second decoding processing module 72.

[0097] The first decoding processing module 71 is configured to receive a set of sequences to be decoded, wherein the sequences to be decoded include multiple sequences of log-likelihood ratios to be decoded.

[0098] The second decoding processing module 72 is configured to perform decoding operations on each of the multiple log-likelihood ratio sequences to be decoded using the corresponding frozen bit distribution model from among the multiple preset frozen bit distribution models. The multiple frozen bit distribution models are arranged in a predetermined order, and the multiple frozen bit distribution models are not completely identical. The multiple frozen bit distribution models and their arrangement order in the decoder are the same as the multiple frozen bit distribution models and their arrangement order in the corresponding target encoder.

[0099] In some embodiments, the second decoding processing module 72 performs polar code decoding operation on each of the multiple log-likelihood ratio sequences to be decoded using the corresponding frozen bit distribution model among the multiple preset frozen bit distribution models.

[0100] For example, the second decoding processing module 72 sequentially performs polar code decoding on each of the multiple log-likelihood ratio sequences to be decoded to generate multiple sets of candidate bit sequences. Each set of candidate bit sequences includes multiple candidate bit sequences. Each set of candidate bit sequences is verified to obtain multiple decoded bit sequences. If at least one candidate bit sequence in each set passes the verification, it is determined that a set of decoded sequences comes from the target encoder. Each decoded bit sequence in the multiple decoded bit sequences is de-sorted using the corresponding frozen bit distribution model to obtain multiple decoding results.

[0101] It should be noted that the reverse arrangement performed by the decoder is the inverse operation of the arrangement performed in the target encoder.

[0102] For example, polar code decoding includes CA-SCL decoding or PC (parity check)-CA-SCL decoding.

[0103] In some embodiments, the second decoding processing module 72 is configured to determine whether the M sets of candidate bit sequences to be decoded come from the target encoder based on the verification results of the multiple sets of candidate bit sequences corresponding to each set of candidate bit sequences in the M sets of candidate bit sequences to be decoded received consecutively, where M is a positive integer, if at least one set of candidate bit sequences in the multiple sets of candidate bit sequences fails the verification.

[0104] If, in each of the multiple candidate bit sequences corresponding to the M groups of sequences to be decoded received consecutively, at least one candidate bit sequence in each candidate bit sequence passes the verification, then the M groups of sequences to be decoded are determined to be from the target encoder. Each of the multiple decoded bit sequences is then reverse-sorted using the corresponding frozen bit distribution model to obtain multiple decoding results.

[0105] If, in each of the M groups of sequences to be decoded received consecutively, at least one set of candidate bit sequences fails the verification, then the M groups of sequences to be decoded are determined to be from a non-target encoder.

[0106] In some embodiments, the magnitude of parameter M is positively correlated with the block error rate (BRR). The higher the BRR, the greater the number of consecutively received sequences to be decoded; conversely, the lower the BRR, the smaller the number of consecutively received sequences to be decoded.

[0107] Figure 8 This is a schematic diagram of the decoder according to another embodiment of the present disclosure. Figure 8 As shown, the decoder includes a memory 41, a processor 42, a communication interface 43, and a bus 44. Figure 8 and Figure 4 The difference is that, in Figure 8 In the illustrated embodiment, processor 82 is configured to execute instructions stored in memory 81 as follows: Figure 5 The method involved in any of the embodiments.

[0108] This disclosure also relates to a computer-readable storage medium storing computer instructions that, when executed by a processor, implement... Figure 5 The method involved in any of the embodiments.

[0109] Figure 9 This is a schematic diagram of the structure of a communication system according to an embodiment of this disclosure. Figure 9 As shown, the communication system includes an encoder 91 and a decoder 92. The encoder is... Figure 3 or Figure 4 In any embodiment of the encoder, the decoder 92 is Figure 7 or Figure 8 The decoder involved in any of the embodiments.

[0110] It should be noted that if the encoder and decoder are only assigned one frozen bit distribution model, the number of frozen bit distribution models that can be used is as shown in formula (1).

[0111]

[0112] If parameter P = 4, then the number of usable frozen bit distribution models obtained by formula (1) is 69.

[0113] If the encoder and decoder are each configured with a set of frozen bit distribution models, the number of frozen bit distribution models that can be used is shown in formula (2).

[0114]

[0115] Where m is the number of frozen bit distribution models in a set of frozen bit distribution models. If a set of frozen bit distribution models includes a maximum of 2 frozen bit distribution models, and if P = 4, then the number of usable frozen bit distribution models obtained by formula (2) is 4761.

[0116] Therefore, compared to the scheme where only one frozen bit distribution model is configured in the encoder and decoder, the scheme where multiple frozen bit distribution models are configured in the encoder and decoder in a predetermined order can increase the user scale by tens of times. Thus, it is suitable for multi-user encoding and decoding transmission in scenarios with high code rate for short codes and medium codes, and low code rate for medium codes.

[0117] In some embodiments, the functional units described above may be implemented as general-purpose processors, programmable logic controllers (PLCs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or any suitable combination thereof for performing the functions described herein.

[0118] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0119] The description in this disclosure is provided for illustrative and descriptive purposes only and is not intended to be exhaustive or to limit the disclosure to its forms. Many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described in order to better illustrate the principles and practical application of this disclosure and to enable those skilled in the art to understand this disclosure and to design various embodiments with various modifications suitable for a particular purpose.

Claims

1. A decoding method, executed by a decoder, comprising: Receive a set of sequences to be decoded, wherein the sequences to be decoded include multiple sequences of log-likelihood ratios to be decoded; For each of the plurality of log-likelihood ratio sequences to be decoded, a decoding operation is performed using the corresponding frozen bit distribution model among a plurality of preset frozen bit distribution models. The plurality of frozen bit distribution models are arranged in a predetermined order, and the plurality of frozen bit distribution models are not completely identical. The plurality of frozen bit distribution models and their arrangement order in the decoder are the same as the plurality of frozen bit distribution models and their arrangement order in the corresponding target encoder. The decoding operation includes: For each of the plurality of log-likelihood ratio sequences to be decoded, a polar code decoding operation is performed using the corresponding frozen bit distribution model from among a plurality of preset frozen bit distribution models. The polar code decoding operation includes: Polar code decoding is performed on each of the plurality of log-likelihood ratio sequences to be decoded in sequence to generate multiple sets of candidate bit sequences, wherein each set of candidate bit sequences includes multiple candidate bit sequences. Each of the multiple sets of candidate bit sequences is verified to obtain multiple decoded bit sequences; If at least one candidate bit sequence in each group of candidate bit sequences passes the verification, then the group of sequences to be decoded is determined to be from the target encoder. Each of the multiple decoded bit sequences is then de-encoded using the corresponding frozen bit distribution model to obtain multiple decoding results.

2. The method according to claim 1, further comprising: If at least one of the candidate bit sequences fails the verification, the M groups of candidate bit sequences to be decoded are determined to be from the target encoder based on the verification results of the multiple candidate bit sequences corresponding to each of the M groups of candidate bit sequences to be decoded received consecutively. M is a positive integer. If, in each of the multiple candidate bit sequences corresponding to the M groups of sequences to be decoded received consecutively, at least one candidate bit sequence in each candidate bit sequence passes the verification, then the M groups of sequences to be decoded are determined to be from the target encoder. Each of the multiple decoded bit sequences is then reverse-sorted using the corresponding frozen bit distribution model to obtain multiple decoding results.

3. The method according to claim 2, further comprising: If, in each of the M groups of sequences to be decoded received consecutively, at least one set of candidate bit sequences fails the verification, then the M groups of sequences to be decoded are determined to be from a non-target encoder.

4. The method according to claim 2, wherein, The magnitude of parameter M is positively correlated with the block error rate.

5. A decoder, comprising: The first decoding processing module is configured to receive a set of sequences to be decoded, wherein the sequences to be decoded include multiple log-likelihood ratio sequences to be decoded. The second decoding processing module is configured to perform decoding operations on each of the plurality of log-likelihood ratio sequences to be decoded using a corresponding frozen bit distribution model from a set of preset frozen bit distribution models. Specifically, the module performs polar code decoding operations on each of the plurality of log-likelihood ratio sequences to be decoded using a corresponding frozen bit distribution model from the set of preset frozen bit distribution models. The polar code decoding operations include: sequentially performing polar code decoding on each of the plurality of log-likelihood ratio sequences to be decoded to generate multiple sets of candidate bit sequences, wherein each set of candidate bit sequences includes multiple candidate bits. The sequence is processed by verifying each of the multiple candidate bit sequences to obtain multiple decoded bit sequences. If at least one candidate bit sequence in each group passes the verification, it is determined that the group of sequences to be decoded comes from the target encoder. Each of the multiple decoded bit sequences is then de-sorted using the corresponding frozen bit distribution model to obtain multiple decoding results. The multiple frozen bit distribution models are arranged in a predetermined order, and the multiple frozen bit distribution models are not completely identical. The multiple frozen bit distribution models and their arrangement order in the decoder are the same as those in the corresponding target encoder.

6. The decoder according to claim 5, wherein, The second decoding processing module is configured to, if at least one set of candidate bit sequences in a plurality of candidate bit sequences fails the verification, determine whether the M sets of candidate bit sequences to be decoded come from the target encoder based on the verification results of the plurality of candidate bit sequences corresponding to each set of candidate bit sequences in the M sets of candidate bit sequences to be decoded received consecutively, where M is a positive integer. If at least one candidate bit sequence in each set of candidate bit sequences corresponding to each set of candidate bit sequences in the M sets of candidate bit sequences to be decoded passes the verification, then it is determined that the M sets of candidate bit sequences to be decoded come from the target encoder. Each of the plurality of decoded bit sequences is then de-sorted using the corresponding frozen bit distribution model to obtain multiple decoding results.

7. The decoder according to claim 6, wherein, The second decoding processing module is configured to determine that the M groups of decoding sequences come from a non-target encoder if at least one of the multiple candidate bit sequences corresponding to each group of decoding sequences in the continuously received M groups of decoding sequences fails the verification.

8. The decoder according to claim 6, wherein, The magnitude of parameter M is positively correlated with the block error rate.

9. A decoder, comprising: The memory is configured to store instructions; A processor, coupled to memory, configured to implement the method as described in any one of claims 1-4 based on memory-stored instruction execution.

10. A communication system, comprising: The decoder as described in any one of claims 5-9; Encoder, including: The memory is configured to store instructions; The processor, coupled to memory, is configured to execute instructions stored in memory. Acquire multiple bit sequences to be transmitted; Each of the plurality of bit sequences to be transmitted is encoded using a corresponding frozen bit distribution model from a plurality of preset frozen bit distribution models to obtain a plurality of encoded bit sequences, wherein the plurality of frozen bit distribution models are arranged in a predetermined order and are not completely identical.

11. The communication system according to claim 10, wherein, The encoding operation includes: Each bit sequence to be transmitted is arranged using the corresponding frozen bit distribution model to generate multiple bit sequences to be encoded. Each of the plurality of bit sequences to be encoded is encoded to generate a plurality of encoded bit sequences.

12. The communication system according to claim 11, wherein, Encoding each of the plurality of bit sequences to be encoded includes: Each of the plurality of bit sequences to be encoded is encoded using polar codes.

13. The communication system according to claim 11, wherein, Each bit sequence to be transmitted is arranged using the corresponding frozen bit distribution model to generate multiple bit sequences to be encoded, including: Perform check code generation operation on each of the multiple bit sequences to be encoded and transmitted to obtain multiple check codes; Each of the multiple check codes and its corresponding bit sequence to be transmitted is arranged using the corresponding frozen bit distribution model to generate multiple bit sequences to be encoded.

14. The communication system according to any one of claims 10-13, wherein the processor is further configured to execute instructions stored in the memory: The plurality of encoded bit sequences are sent to the decoder.

15. A non-transient computer-readable storage medium, wherein, A computer-readable storage medium stores computer instructions that, when executed by a processor, implement the method as described in any one of claims 1-4.

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