An injection stage circuit and readout timing control method for an infrared detector

Abstract

This invention relates to an injection stage circuit and readout timing control method for an infrared detector. The circuit includes a photodiode PD, a reset transistor Mrst, a source follower transistor Msf, and a column gating transistor Msel. The positive terminal of the photodiode PD is connected to the reverse bias voltage Vdet of the infrared detector, and the negative terminal is connected to the drain of the reset transistor Mrst and the gate of the source follower transistor Msf. The source of the reset transistor Mrst is connected to the drain of the source follower transistor Msf and connected to ground potential Vss. The gate of the reset transistor Mrst is connected to the reset control signal Vrst. The source of the source follower transistor Msf is connected to the drain of the column gating transistor Msel. The source of the column gating transistor Msel is connected to the column output bus of the infrared detector, and the gate of the column gating transistor Msel is connected to the column gating control voltage signal Vsel. The substrate potential of the source follower transistor Msf can be switched between power supply VDD and ground VSS.

Description

Technical Field

[0001] This invention relates to an injection stage circuit and readout timing control method for an infrared detector, belonging to the field of integrated circuit devices. It is applicable to the readout circuit design of various types of infrared detectors, especially for infrared detector readout circuits with ultra-low readout noise requirements. Background Technology

[0002] Infrared detectors are widely used in aerospace, defense, and other fields. Particularly in space astronomical observation, high-performance infrared detectors, leveraging their superior observation bands, play an irreplaceable role in detecting faint deep-space objects and near-Earth asteroids. High-performance infrared detectors are characterized by high sensitivity, low dark current, low power consumption, and low readout noise. High sensitivity and low dark current typically require infrared detectors to operate at cryogenic temperatures (4K–77K). However, due to power limitations imposed by spacecraft coolers, detectors need to have the lowest possible power consumption to reduce the burden on the coolers. Readout noise directly affects the system's signal-to-noise ratio; the lower the readout noise, the better for detecting faint targets in exposure signals.

[0003] Three of the most commonly used traditional infrared detector injection stage circuit structures are as follows: Figure 1 , Figure 2 , Figure 3 As shown.

[0004] Figure 1 The photodiode parasitic capacitance Cdet, the gate capacitance of transistor M1, and the source capacitance of transistor Mrst in the source follower injection stage circuit shown together constitute the integrating capacitance Cint of this injection stage circuit. After exposure, the photogenerated carriers accumulated on Cint are buffered onto the bus by transistor Msf and column select switch transistor Msel. This structure has a small number of transistors and can reduce kTC noise through correlated double sampling. However, the 1 / f noise of transistor Msf cannot be reduced in this circuit structure.

[0005] Figure 2 The direct injection stage circuit shown injects photocurrent into the integrating capacitor Cint through a transistor Mb operating in subthreshold mode. The direct injection stage circuit structure is particularly simple, the integrating capacitor Cint can be designed to be very large, and the injection efficiency is high under high photocurrent conditions. However, this type of injection stage circuit performs only moderately well in low-flux, low-noise applications. Furthermore, when column strobe is enabled, its integrating capacitor Cint is directly exposed on the column bus, causing the output voltage to decrease as carriers in the integrating capacitor Cint are drawn away by the bus capacitor Cbus. This voltage drop is particularly severe in large array applications.

[0006] Figure 3The capacitor transconductance injection stage circuit shown has a high equivalent input impedance observed at the photodiode terminal due to the use of amplifier A, resulting in excellent control over the photodiode bias voltage during exposure. Furthermore, by decreasing the value of the integrating capacitor Cint while increasing the value of the load capacitor, i.e., the bus capacitor Cbus, very low equivalent input noise can be achieved at the input of amplifier A. However, the disadvantages of the capacitor transconductance injection stage amplifier circuit are its complex structure, excessive number of transistors, and high power consumption.

[0007] Based on the analysis of the above three traditional infrared injection stage circuits, it can be seen that they each have the following shortcomings that need to be addressed in the design of high-performance infrared detectors:

[0008] a) The 1 / f noise in the source follower injection stage cannot be eliminated. Current infrared injection stage circuits, including techniques such as correlated double sampling, are only effective against noise sources originating from white noise, such as kTC noise.

[0009] b) The bus capacitor Cbus of the direct injection stage circuit draws carriers from the integrating capacitor Cint, which reduces the output voltage and consequently reduces the circuit output swing, ultimately affecting the system's dynamic range and signal-to-noise ratio.

[0010] c) The capacitor transconductance injection stage circuit has a complex structure and high power consumption, making it unsuitable for the design of high-performance infrared detector readout circuits in the field of space astronomical observation. Summary of the Invention

[0011] The technical problem solved by this invention is to overcome the shortcomings of the prior art and propose an injection stage circuit and readout timing control method for infrared detectors. This method uses a substrate potential switching transistor to periodically switch the channel state of the source follower transistor and perform oversampling, thereby reducing 1 / f noise.

[0012] The solution of the present invention is: an infrared injection stage circuit, the circuit structure of which includes a photodiode PD, a reset transistor Mrst, a source follower transistor Msf, and a column gating transistor Msel;

[0013] The positive terminal of the photodiode PD is connected to the reverse bias voltage Vdet of the infrared detector, and the negative terminal is connected to the drain of the reset transistor Mrst and the gate of the source follower transistor Msf. The source of the reset transistor Mrst is connected to the drain of the source follower transistor Msf and connected to ground potential Vss. The gate of the reset transistor Mrst is connected to the reset control signal Vrst.

[0014] The source of the source follower transistor Msf is connected to the drain of the column gating transistor Msel. The source of the column gating transistor Msel is connected to the column output bus of the infrared detector. The gate of the column gating transistor Msel is connected to the column gating control voltage signal Vsel. The substrate potential of the source follower transistor Msf can be switched between the power supply VDD and the ground VSS.

[0015] Preferably, the column gate transistor Msel and the source follower transistor Msf are P-type transistors, and the reset transistor Mrst is an N-type transistor.

[0016] Preferably, the infrared injection stage circuit structure further includes a first substrate potential switching transistor Msp and a second substrate potential switching transistor Msn;

[0017] The substrate terminal of the source follower transistor Msf is connected to the drain of the second substrate potential switching transistor Msn and the drain of the first substrate potential switching transistor Msp, respectively; the source of the first substrate potential switching transistor Msp is connected to the power supply Vdd; and the source of the second substrate potential switching transistor Msn is connected to the ground Vss.

[0018] The gates of the first substrate potential switching transistor Msp and the second substrate potential switching transistor Msn are controlled by the potential switching voltage signal Vsb. When the potential switching voltage signal Vsb is low, the first substrate potential switching transistor Msp is turned on, and vice versa.

[0019] Preferably, the first substrate potential switching transistor Msp is a P-type transistor and the second substrate potential switching transistor Msn is an N-type transistor.

[0020] Preferably, the voltage of the power supply Vdd is 3.3V or 5V.

[0021] Another technical solution of the present invention is: an infrared detector readout timing control method based on the above-mentioned injection stage circuit, wherein each readout operation of the detector includes the following steps:

[0022] S1. Set the reset control signal Vrst to control the reset transistor Mrst to turn on, so that the gate node voltage of the source follower transistor Msf is reset to the ground potential Vss.

[0023] S2. The control reset transistor Vrst is turned off, and the photodiode PD starts the exposure integration process. During this period, photogenerated carriers will be stored in the integration capacitor Cint, and the gate node voltage of the source follower transistor Msf will gradually decrease. After the exposure time reaches the system set time, the process proceeds to step S3.

[0024] S3. Turn on the column gating transistor Msel and output the source voltage signal of the source follower transistor Msf to the column output bus of the total infrared detector.

[0025] S4. The first substrate potential switching transistor Msp and the second substrate potential switching transistor Msn are turned on alternately by the potential switching voltage signal Vsb, and the substrate potential of the source follower transistor Msf is switched repeatedly, so that the channel of the source follower transistor Msf is alternately in the inversion state and the non-inversion state.

[0026] S5: Set the column gating control voltage signal Vsel to turn off the column gating transistor Msel.

[0027] Preferably, the frequency at which the first substrate potential switching transistor Msp and the second substrate potential switching transistor Msn are turned on alternately is set to tens to hundreds of kHz.

[0028] The advantages of this invention compared to the prior art are:

[0029] (1) The present invention refreshes the channel inversion state of the source follower transistor by using the method of switching the substrate potential of the source follower transistor. Compared with the prior art, it can reduce the 1 / f noise from the source follower transistor to a certain extent.

[0030] (2) The present invention uses a P-type transistor Msp and an N-type transistor Msn to form a substrate potential switching circuit for the source follower transistor Msf. Only one control signal is needed to quickly realize the switching function, which simplifies the circuit design and keeps the power consumption at a low level.

[0031] (3) The present invention adopts a periodic sampling quantization method. During a single readout operation, the same signal is read multiple times in the inverted state of the source follower transistor Msf channel. The large amount of data obtained can be conveniently processed later, such as averaging, to obtain a lower noise voltage value.

[0032] (4) This invention proposes a novel infrared injection stage circuit structure, which can be used in the design of readout circuits for high-performance infrared detectors in the field of future space astronomical observation. Attached Figure Description

[0033] Figure 1 Injection stage circuitry for existing source follower;

[0034] Figure 2 For existing direct injection stage circuits;

[0035] Figure 3 For existing capacitor transconductance injection stage circuits;

[0036] Figure 4 This is the infrared injection stage circuit structure according to an embodiment of the present invention;

[0037] Figure 5 This is a timing diagram for transistor control according to an embodiment of the present invention. Detailed Implementation

[0038] The present invention will be further described below with reference to the embodiments.

[0039] Example 1

[0040] This invention describes an infrared injection stage circuit structure. It retains the advantages of having a small number of transistors in the source follower injection stage and the direct injection stage, with only one reset transistor, one source follower transistor, one column gating transistor, and a pair of substrate potential switching transistors.

[0041] like Figure 4 As shown, an injection stage circuit is described. This injection stage circuit includes a photodiode PD, a reset transistor Mrst, a source follower transistor Msf, a column gating transistor Msel, a first substrate potential switching transistor Msp, and a second substrate potential switching transistor Msn.

[0042] When the photodiode PD is working, it is in reverse bias. Its positive terminal is connected to the reverse bias voltage Vdet of the infrared detector, and its negative terminal is connected to the drain of the reset transistor Mrst and the gate of the source follower transistor Msf. The source of the reset transistor Mrst is connected to the drain of the source follower transistor Msf and connected to the ground potential Vss. The gate of the reset transistor Mrst is connected to the reset control signal Vrst.

[0043] The source of the source follower transistor Msf is connected to the drain of the column gating transistor Msel. The source of the column gating transistor Msel is connected to the column output bus of the infrared detector. The gate of the column gating transistor Msel is connected to the column gating control voltage signal Vsel. The substrate potential of the source follower transistor Msf can be switched between the power supply VDD and the ground VSS.

[0044] The substrate terminal of the source follower transistor Msf is connected to the drain of the second substrate potential switching transistor Msn and the drain of the first substrate potential switching transistor Msp, respectively; the source of the first substrate potential switching transistor Msp is connected to the power supply Vdd; and the source of the second substrate potential switching transistor Msn is connected to the ground Vss.

[0045] The gates of the first substrate potential switching transistor Msp and the second substrate potential switching transistor Msn are controlled by the potential switching voltage signal Vsb. When the potential switching voltage signal Vsb is low, the first substrate potential switching transistor Msp is turned on; conversely, the second substrate potential switching transistor Msp is turned on when Vsb is high. Only one of the first substrate potential switching transistor Msp and the second substrate potential switching transistor Msn will be turned on at any given time.

[0046] The column select transistor Msel is a P-type transistor, and the reset transistor Mrst is an N-type transistor. The source follower transistor Msf needs to be a P-type CMOS transistor, and its substrate potential is switched between power supply Vdd and ground Vss by a first substrate potential switching transistor Msp and a second substrate potential switching transistor Msn, thus allowing the substrate to switch between inverted and non-inverted states. Furthermore, the first substrate potential switching transistor Msp is a P-type CMOS transistor, and the second substrate potential switching transistor Msn is an N-type CMOS transistor.

[0047] The VDD voltage depends on the specific process and is generally 3.3V or 5V.

[0048] Figure 4 In this circuit, the integrating capacitor Cint is the sum of the parasitic capacitances of the photodiode, the gate of the Msf transistor, and the drain of the Mrst transistor; it serves as the storage node for the photogenerated carrier signal. The Cbus capacitor is the equivalent capacitance of the column bus. The Mload transistor provides column bias current to the injection stage circuit. The column output bus is also connected to the drain of the bias current transistor Mload. The gate of transistor Msel is controlled by the voltage signal Vsel. The gate of transistor Mload is controlled by the voltage signal Vload, and its source is connected to the power supply Vdd. The bus ultimately connects to the input of the analog-to-digital converter D, which converts the analog voltage signal output from the injection stage circuit into a quantized digital signal for output.

[0049] The control timing of the transistors used in this invention is as follows: Figure 5As shown. The control signal Vrst is set at the start of a readout operation, turning on the Mrst transistor. At this time, the gate node voltage of the source follower transistor Msf is reset to the system ground potential Vss. Afterwards, the control signal Vrst is reset, transistor Mrst is turned off, and the photodiode PD begins the exposure integration process. During this process, photogenerated carriers are stored in the integrating capacitor Cint, and the node voltage gradually decreases. Transistor Msel then turns on, outputting the source voltage signal of transistor Msf to the bus. Vsb then controls the Msn and Msp transistors to repeatedly switch the substrate potential of transistor Msf. When entering the inversion state, the subsequent analog-to-digital converter D quantizes the voltage on the bus, repeating this process (typically 100 to 1000 quantization conversions). Finally, the signal Vsel is set, turning off transistor Msel, and the readout operation ends.

[0050] In summary, this invention also proposes an infrared detector readout timing control method based on the above-mentioned injection stage circuit. Each readout operation of the detector in this method includes the following steps:

[0051] S1. Set the reset control signal Vrst to control the reset transistor Mrst to turn on, so that the voltage of the gate node of the source follower transistor Msf is reset to the ground potential Vss.

[0052] S2. Control reset transistor Vrst is turned off, and photodiode PD starts the exposure integration process. During this period, photogenerated carriers will be stored in the integration capacitor Cint, and the gate node voltage of transistor Msf will gradually decrease. After the exposure time reaches the system set time (usually a few milliseconds to a few seconds), step S3 can be entered to start column gating operation row by row.

[0053] S3. Turn on the column gating transistor Msel and output the source voltage signal of the source follower transistor Msf to the column output bus of the total infrared detector.

[0054] S4. The first substrate potential switching transistor Msp and the second substrate potential switching transistor Msn are turned on alternately by the potential switching voltage signal Vsb, and the substrate potential of the source follower transistor Msf is switched repeatedly, so that the channel of the source follower transistor Msf is alternately in the inversion state and the non-inversion state.

[0055] When the channel of transistor Msf enters the inversion state, the analog-to-digital converter D can quantize the voltage on the bus. When the channel of transistor Msf enters the non-inversion state, transistor Msf enters a new channel charge refresh cycle, and the analog-to-digital converter D does not quantize the voltage on the bus.

[0056] S5: Set the column gating control voltage signal Vsel to turn off the column gating transistor Msel.

[0057] The frequency at which the first substrate potential switching transistor Msp and the second substrate potential switching transistor Msn alternately conduct is set to tens to hundreds of kHz.

[0058] The above-mentioned device can reduce 1 / f noise to a certain extent by periodically switching the channel state of the source follower transistor and oversampling through a substrate potential switching transistor.

[0059] According to the 1 / f noise model theory, transistors exhibit 1 / f noise because the carriers absorbed by the silicon-silicon dioxide interface layer traps are periodically released, with the distribution pattern ranging from a few nanoseconds to several days. The source follower transistor used in this invention is a P-type transistor. This is because P-type transistors have lower noise than N-type transistors, and the substrate potential of a P-type transistor can be easily adjusted through the electrical contacts of the N-well, allowing the inversion region under the channel to switch between inversion and non-inversion states. The switching frequency can typically be set to tens to hundreds of kHz. This process causes the silicon-silicon dioxide interface layer traps to be rapidly filled with electrons, and the repeated operation of the device causes these traps to be frequently refreshed, losing their characteristic of long-period carrier release, thus superficially reducing the 1 / f noise of the corresponding transistor.

[0060] Finally, the column gate will be activated during the exposure cycle, and the subsequent analog-to-digital converter circuit will periodically sample and quantize the output signal when the source follower transistor is in an inverted state, according to the substrate potential switching frequency. The number of sampling and quantization cycles of the output signal is consistent with the number of substrate potential switching cycles, and can generally be selected in the range of 100-1000.

[0061] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

Claims

1. An injection stage circuit for an infrared detector, characterized by It includes a photodiode PD, a reset transistor Mrst, a source follower transistor Msf, a column gating transistor Msel, a first substrate potential switching transistor Msp, and a second substrate potential switching transistor Msn; The positive terminal of the photodiode PD is connected to the reverse bias voltage Vdet of the infrared detector, and the negative terminal is connected to the drain of the reset transistor Mrst and the gate of the source follower transistor Msf. The source of the reset transistor Mrst is connected to the drain of the source follower transistor Msf and connected to ground potential Vss. The gate of the reset transistor Mrst is connected to the reset control signal Vrst. The source of the source follower transistor Msf is connected to the drain of the column gating transistor Msel. The source of the column gating transistor Msel is connected to the column output bus of the infrared detector. The gate of the column gating transistor Msel is connected to the column gating control voltage signal Vsel. The substrate potential of the source follower transistor Msf can be switched between the power supply VDD and the ground VSS. The substrate terminal of the source follower transistor Msf is connected to the drain of the second substrate potential switching transistor Msn and the drain of the first substrate potential switching transistor Msp, respectively; the source of the first substrate potential switching transistor Msp is connected to the power supply Vdd. The source of the second substrate potential switching transistor Msn is connected to ground Vss; The gates of the first substrate potential switching transistor Msp and the second substrate potential switching transistor Msn are controlled by the potential switching voltage signal Vsb. When the potential switching voltage signal Vsb is low, the first substrate potential switching transistor Msp is turned on, and vice versa.

2. An injection stage circuit for an infrared detector as claimed in claim 1, characterized in that The column select transistor Msel and the source follower transistor Msf are P-type transistors, and the reset transistor Mrst is an N-type transistor.

3. An injection stage circuit for an infrared detector as claimed in claim 1, characterized in that The first substrate potential switching transistor Msp is a P-type transistor, and the second substrate potential switching transistor Msn is an N-type transistor.

4. An injection stage circuit for an infrared detector according to any one of claims 1 to 3, characterized in that The voltage of the power supply Vdd is 3.3V or 5V.

5. A method for controlling the readout timing of an infrared detector based on the injection stage circuit of claim 1, characterized in that Each readout operation of the detector includes the following steps: S1. Set the reset control signal Vrst to control the reset transistor Mrst to turn on, so that the gate node of the source follower transistor Msf is reset to the ground potential Vss. S2. The control reset transistor Vrst is turned off, and the photodiode PD starts the exposure integration process. During this period, photogenerated carriers will be stored in the integration capacitor Cint of the injection stage circuit. The gate node voltage of the source follower transistor Msf will gradually decrease. After the exposure time reaches the system set time, the process proceeds to step S3. S3. Turn on the column gating transistor Msel and output the source voltage signal of the source follower transistor Msf to the column output bus of the total infrared detector. S4. The first substrate potential switching transistor Msp and the second substrate potential switching transistor Msn are turned on alternately by the potential switching voltage signal Vsb, and the substrate potential of the source follower transistor Msf is switched repeatedly, so that the channel of the source follower transistor Msf is alternately in the inversion state and the non-inversion state. When the channel of the source follower transistor Msf enters the inversion state, the analog-to-digital converter D of the detector quantizes the voltage on the column output bus of the infrared detector; when the channel of the transistor Msf enters the non-inversion state, the source follower transistor Msf enters a new channel charge refresh cycle, and the analog-to-digital converter D does not quantize the voltage on the column output bus of the infrared detector. S5. The column strobe control voltage signal Vsel is set, turning off the column strobe transistor Msel, completing one readout operation.

6. The method of readout timing control for an infrared detector of claim 5, wherein The frequency at which the first substrate potential switching transistor Msp and the second substrate potential switching transistor Msn alternately conduct is set to tens to hundreds of kHz.

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