Chiplet core particle and interface multiplexing method based on PCIE standard interface interconnection
By using a chiplet design based on the PCIe standard interface and utilizing PIU and CIU modules to achieve protocol packet multiplexing, the high requirements for inter-chiplet interconnection are solved, enabling high-bandwidth, low-cost interconnection, supporting multiple packaging forms, and saving chip area and cost.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- WUXI ADVANCED TECH RES INST
- Filing Date
- 2022-10-27
- Publication Date
- 2026-07-24
AI Technical Summary
Existing chip interconnect technologies have high requirements in terms of transmission delay, bandwidth and cost, which are difficult to achieve, especially under the conditions of domestic process technology. Furthermore, I/O and direct connection interfaces occupy a large chip area, have many high-speed pins and high costs.
It adopts a chiplet design based on the PCIe standard interface, realizes protocol packet multiplexing through PIU and CIU modules, and uses the PCIe interface as both an I/O interface and a direct connection interface between dies, supports multiple packaging forms, and saves chip area and cost.
It achieves high-bandwidth interconnect without increasing chip pins and area, reduces process requirements, supports multiple package types, saves cost and area, and is flexible enough to support the expansion of standard PCIe devices.
Smart Images
Figure CN115576894B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a chiplet based on PCIe standard interface interconnection and an interface reuse method, belonging to the field of integrated circuit chip technology. Background Technology
[0002] Currently, the main die-to-die direct connection technologies are: (1) Intel’s chiplet technology based on silicon substrates involves interconnecting dies using dedicated “interconnect dies”—silicon substrates—and then bumping them onto a package substrate, thereby enabling the packaging of multiple dies of different types and processes into a single chip. Due to the identical transmission medium and extremely short transmission distance, silicon substrate-based die interconnects are most likely to achieve the performance requirements of ultra-low latency and ultra-high bandwidth, but they also have extremely high requirements for the manufacturing process.
[0003] ②Custom Serdes (serializers): Infinity Fabric (IF) is a general interconnect architecture used by AMD CPUs. For serial interconnects, it employs two custom SerDes: IFOP (IF On-Package) SerDes for direct connections between dies within the package, and IFIS (IF Inter-Socket) SerDes for direct connections between chips. Due to the different transmission media and distances, the two custom SerDes use different transmission methods and design approaches to achieve optimal performance and minimum power consumption.
[0004] While Intel's silicon-based die interconnect technology offers ultra-low latency and ultra-high bandwidth, it places extremely high demands on manufacturing processes. Custom SerDes, on the other hand, can tailor different transmission protocols and implementations to meet the interconnect requirements of different layers, media, and distances, achieving optimal cost-effectiveness and power efficiency. However, it also places extremely high demands on manufacturing processes, design capabilities, and cost. Both approaches require exceptional chip design and manufacturing processes, which are particularly difficult to achieve with current domestic manufacturing capabilities. Summary of the Invention
[0005] The purpose of this invention is to provide a chiplet and interface multiplexing method based on PCIe standard interface interconnection, which realizes the multiplexing of PCIe standard interface and chiplet interconnection interface, and solves the problems of large chip area, many high-speed pins and high cost of separate IO and direct connection ports.
[0006] A chiplet based on a PCIe standard interface interconnect, comprising: At least one die core, and multiple die cores are directly connected to each other via a PCIe interface; The die core includes a central module, a selection module, a PIU module, a CIU module, and an RC module. The selection module is used to select the physical link to be used by the CIU module or the PIU module, based on the head and data packets sent by the central module or received from the RC module. The RC module is used to package the head and data packets into a protocol packet or separate the protocol packet into head and data packets. The RC module enables receiving or sending with external devices or the die core through the PCIE PHY. When the selection module selects the CIU module, the head and data packets are placed as a whole into a data packet. The RC module communicates with other die cores according to the PCIE packet format requirements, realizing PCIE interface multiplexing.
[0007] Furthermore, the die includes four 8X PCIe 4.0 interfaces.
[0008] Furthermore, all four paths of the PCIe 4.0 interface are multiplexed paths.
[0009] Furthermore, when the selection module selects the PIU module, it assembles the head packets into a head' packet and the data packets into a data' packet, and sends them to the RC module to be converted into PICE protocol packets to communicate with external devices through the PCIE interface.
[0010] Furthermore, when the selection module selects the CIU module, the dies are directly connected. The CIU module puts the head packet and data packet as a whole into the data' packet and sends it to the RC module to be converted into a PICE protocol packet and sent to the die directly connected to it through the PCIE interface.
[0011] Furthermore, the die cores are directly connected via a PCIe interface to form various die core forms such as single die, 2-die, 3-die, and 4-die.
[0012] A chiplet interface multiplexing method based on PCIe standard interface interconnection, the method comprising: When connecting to external devices, the selection module converts the head and data packets sent by the central module or the head and data packets received from the RC module into RC module protocol requirements through the PIU module. The RC module and PCIE PHY, according to the PCIE interface protocol, assemble the packets received from the PIU module into PICE protocol packets and send them to the external device for high-speed communication. When directly connected to the die chip, the selection module packages the head packet and data packet sent by the central module into a whole data packet through the CIU module, and sends it to the RC module according to the PCIE protocol packet format. The RC module and PCIE PHY connect to the corresponding PCIE interface of the die chip according to the PCIE interface protocol for high-speed communication.
[0013] Furthermore, the method also includes: The receiving die chip separates the head packet and data packet through the RC module and sends them to the CIU module. Then, based on the head packet, the head packet and data packet are parsed from the data packet and handed over to the central module.
[0014] Compared with the prior art, the beneficial effects achieved by the present invention are as follows: This invention achieves both general-purpose I / O interface and direct inter-die connection by reusing the physical path of the PCIe interface and processing transport layer protocol packets separately, occupying only one set of high-speed chip pins. This greatly saves area and cost, while also providing considerable flexibility. It can not only support interconnection between chips via organic substrate in multi-chip packaging, but also support interconnection between chips via printed lines, as well as the expansion of standard PCIe devices. It saves chip pins and reduces process requirements while providing high-bandwidth interconnection. Attached Figure Description
[0015] Figure 1 This is a schematic diagram of the multi-die form of the 4E chip of the present invention with different numbers of cores; Figure 2 This is a schematic diagram of the PIU and CIU modules of the present invention; Figure 3 This is a schematic diagram of the PCIE protocol packet format of the present invention; Figure 4 This is a schematic diagram of the direct transmission packet format of the present invention; Figure 5 This is a flowchart illustrating the communication between the present invention and external devices; Figure 6 This is a flowchart of inter-DIE communication in this invention; Figure 7 This is a flowchart illustrating the conversion of various packets when the present invention communicates with external devices; Figure 8 This is a flowchart illustrating the conversion of various packets during inter-DIE communication in this invention; Figure 9 This is a schematic diagram of the components of each stage of the present invention. Detailed Implementation
[0016] To make the technical means, creative features, objectives and effects of this invention easier to understand, the invention will be further described below in conjunction with specific embodiments.
[0017] Example 1 like Figures 1-6 As shown, a chiplet based on a PCIe standard interface interconnect is disclosed, comprising: At least one die core, and multiple die cores are directly connected to each other via a PCIe interface; Figure 1 The product showcases how each die chip implements four 8X PCIe 4.0 interfaces, and how the product forms of single-die, 2-die, 3-die, and 4-die chips are formed through PCIe die direct connection technology, which can cover the performance requirements of different fields.
[0018] In the specific design, all four 8x PCIe 4.0 paths of each die chip are multiplexed paths, and the multiplexing layer is at the TLP layer (transaction layer), that is, above the RC (root complex port) controller.
[0019] In this invention, the above-mentioned multiplexing function is mainly achieved through the PIU module and the CIU module, see Figure 2 : The die core includes a central module, a selection module, a PIU module, a CIU module, and an RC module. The selection module is used to select the physical link to be used by the CIU module or the PIU module, based on the head and data packets sent by the central module or received from the RC module. The RC module is used to package the head and data packets into a protocol packet or separate the protocol packet into head and data packets. The RC module enables receiving or sending with external devices or the die core through the PCIE PHY. When the selection module selects the CIU module, the head and data packets are placed as a whole into a data packet. The RC module communicates with other die cores according to the PCIE packet format requirements, realizing PCIE interface multiplexing. PIU (PCIe Interface Unit): When used as an I / O device interface, it processes PCIe device packets and completes the conversion between the PCIe protocol and the kernel protocol by communicating with the crossbar switch to handle device I / O, DMA (Direct Memory Access), and interrupt packets.
[0020] CIU (Connection Interface Unit) module: As a direct connection interface, it communicates with the crossbar switch to complete the conversion between the custom inter-chip direct connection protocol packet format and the PCIe protocol packet format. Details are as follows: The packets generated by the central module consist of a header and data. The PIU / CIU module's communication path is also divided into a header path and a data path. Communication with external devices is handled by the PIU. Due to protocol differences, the packet format needs to be reassembled. According to the RC module's protocol requirements, header packets are combined into header' packets, and data packets are combined into data' packets and sent to the RC module. The RC module and the PCIe PHY will then assemble the packets received from the PIU module into PICE protocol packets according to the PCIe interface protocol. At this point, the header and data information can be considered packaged together and sent to the external device for high-speed communication. Figure 5 ; The CIU module needs to control and manage the sending and receiving of packets when the PCIe interface is used as a direct connection interface, as detailed below: (1) Selection of Direct Connection Transmission Packet Type. For the RC module, the CIU only provides one packet type: PCIE Memory Write Packet (MMWr). That is, all packet types passing through the direct connection interface are converted into MMWr() packets in the PCIE protocol and transmitted on the PCIE link after passing through the CIU. The reason for choosing this packet type is that the MMWr packet is a Post type. For the sending end, it is considered complete as long as it is sent out, and no response is required. In the RC module, there is no logic such as request hanging or timeout, so it can be selected as the transmission channel without considering the support of the protocol itself.
[0021] (2) Format of direct-connect transmission packets. The 64-bit MMWr packet format of PCIE is as follows: Figure 3 As shown. The MMWr packet is used as a direct transmission packet. Besides the 4DW (Double Word) header, it must include at least one 128-bit data packet (4DW) as control information for the direct transmission packet. The actual data starts from the 5th DW and can be up to 128 bytes. Specifically, Fmt[1:0] needs to be fixed at 2'b11, Type[4:0] at 5'b00000, and Address[63:0] can be fixed but is unrelated to the actual spatial address; it just needs to fall outside the default range of the peer RC. Length is the DW length of the packet data, which must be at least 4, i.e., the length of one control information packet. Therefore, for protocol packets without data, Length = 4; for protocol packets with data, Length = data DW length + 4.
[0022] When the CIU module is working, the DIE chips are directly connected. Details are as follows: like Figure 6For example, when DIE1 sends a packet to DIE2, the packet generated by the central module consists of a head and data. The CIU will combine the core's head and data packets into a single data' packet, which is then sent to DIE2. The head' packet sent to the RC will be processed according to the PCIe packet format requirements. The CIU will generate control information based on the data and hand it over to the RC. This control information is generated to meet the PCIe protocol specification requirements and is necessary for transmission. However, for the core of DIE2, this head' packet is useless; it only needs the data packet. This is different from external communication, where the information in the head' packet is also required by the device. When the PCIe protocol packet reaches the PCIe interface corresponding to DIE2, it is re-unpacked by the RC, and the head' and data' packets are separated and then handed over to the CIU. The CIU, based on the head' packet, parses the head and data packets from the data' packet and then hands them over to the core.
[0023] Example 2 A chiplet interface multiplexing method based on PCIe standard interface interconnection, the method comprising: When connecting to external devices, the selection module converts the head and data packets sent by the central module or the head and data packets received from the RC module into RC module protocol requirements through the PIU module. The RC module and PCIE PHY, according to the PCIE interface protocol, assemble the packets received from the PIU module into PICE protocol packets and send them to the external device for high-speed communication. When directly connected to the die chip, the selection module packages the head packet and data packet sent by the central module into a whole data packet through the CIU module, and sends it to the RC module according to the PCIE protocol packet format. The RC module and PCIE PHY connect to the corresponding PCIE interface of the die chip according to the PCIE interface protocol for high-speed communication.
[0024] Based on the method described above, it also includes: The receiving die chip separates the head packet and data packet through the RC module and sends them to the CIU module. Then, based on the head packet, the head packet and data packet are parsed from the data packet and handed over to the central module.
[0025] This invention achieves the multiplexing of the PCIe standard interface and die interconnect interface by supporting a specific direct-connect transmission protocol above the standard PCIe interface transport layer. This solves the problems of large chip area, numerous high-speed pins, and high cost associated with separate I / O and direct-connect ports. It significantly saves area and cost by multiplexing the PCIe interface, enabling the reuse of die-to-die direct-connect ports and PCIe high-speed I / O interfaces. In other words, the PCIe interface can be used both as a high-speed I / O interface and as a die-to-die direct-connect port in multi-die configurations. Without increasing chip pins and chip area, it greatly reduces process requirements and supports various package types.
[0026] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A chiplet based on PCIe standard interface interconnect, characterized in that, include: At least one die core, and multiple die cores are directly connected to each other via a PCIe interface; The die core includes a central module, a selection module, a PIU module, a CIU module, and an RC module. The selection module is used to select the physical link to be used by the CIU module or the PIU module, based on the head and data packets sent by the central module or received from the RC module. The RC module is used to package the head and data packets into a protocol packet or separate the protocol packet into head and data packets. The RC module enables receiving or sending with external devices or the die core through the PCIE PHY. When the selection module selects the CIU module, the head and data packets are placed as a whole into a data packet. The RC module communicates with other die cores according to the PCIE packet format requirements, realizing PCIE interface multiplexing. The PIU module, when used as an I / O device interface, processes PCIE device packets and, through communication with the crossbar switch, completes the conversion of device I / O, DMA, and interrupt packets between the PCIE protocol and the core protocol. The CIU module, acting as a direct connection interface, communicates with the crossbar switch to complete the conversion between the custom inter-chip direct connection protocol packet format and the PCIE protocol packet format. When connecting to external devices, the selection module converts the head and data packets sent by the central module or the head and data packets received from the RC module into RC module protocol requirements through the PIU module. The RC module and PCIE PHY, according to the PCIE interface protocol, assemble the packets received from the PIU module into PICE protocol packets and send them to the external device for high-speed communication. When directly connected to the die chip, the selection module packages the head packet and data packet sent by the central module into a whole data packet through the CIU module, and sends it to the RC module according to the PCIE protocol packet format. The RC module and PCIE PHY connect to the corresponding PCIE interface of the die chip according to the PCIE interface protocol for high-speed communication.
2. The chiplet based on PCIe standard interface interconnect according to claim 1, characterized in that, The die includes four 8X PCIe 4.0 interfaces.
3. The chiplet based on PCIe standard interface interconnect according to claim 2, characterized in that, All four paths of the PCIe 4.0 interface are multiplexed paths.
4. The chiplet based on PCIe standard interface interconnect according to claim 1, characterized in that, When the selection module selects the PIU module, it combines the head packets into a head' packet and the data packets into a data' packet, and sends them to the RC module to be converted into PICE protocol packets to communicate with external devices through the PCIE interface.
5. The chiplet based on PCIe standard interface interconnect according to claim 1, characterized in that, When the selection module selects the CIU module, the dies are directly connected. The CIU module puts the head packet and data packet as a whole into the data' packet and sends it to the RC module to be converted into a PICE protocol packet and sent to the die directly connected to it through the PCIE interface.
6. The chiplet based on PCIe standard interface interconnect according to claim 1, characterized in that, The die cores are directly connected via PCIe interfaces to form various die core forms such as single-die, 2-die, 3-die, and 4-die.
7. The chiplet based on PCIe standard interface interconnect according to claim 1, characterized in that, The receiving die chip separates the head packet and data packet through the RC module and sends them to the CIU module. Then, based on the head packet, the head packet and data packet are parsed from the data packet and handed over to the central module.