Method for adaptive multiple programming of memory and applications

Abstract

This invention discloses a method and application for adaptive multiple programming of a memory. The method includes: dividing the internal address space of the memory into a validity identifier area, an addressing information area, and a load area, wherein the load area includes multiple load address spaces; storing the current program into the load address space of the memory; updating the validity identifier corresponding to the current program in the validity identifier area and updating the addressing information corresponding to the load address space where the current program is located in the addressing information area; and determining, based on the updated validity identifier, whether to address the load address space where the current program is located through the updated addressing information to load the current program. This method, by dividing the internal address space of the memory into multiple load address spaces, allows the revised or supplemented program to be stored in an unprogrammed load address space when the program stored in the programmed load address space needs to be revised or supplemented, thereby achieving adaptive multiple programming of the memory.

Description

Technical Field

[0001] This invention relates to the field of microcontroller technology, and in particular to a method and application of adaptive multiple programming of memory. Background Technology

[0002] In chip development, external storage devices are frequently used to carry programs to improve the success rate of chip design. Compared to reprogrammable memory devices, one-time programmable (OTP) memory cannot be modified or erased once programmed. This makes OTP memory difficult to use in situations where programs need patching or where different packages have different programming requirements. However, due to its lower cost, OTP memory is still favored by many chip design companies.

[0003] In view of this, there is an urgent need to design a method or device that enables commercially viable multiple programming on a one-time programmable memory in order to solve the above problems. Summary of the Invention

[0004] The purpose of this invention is to provide a method and application for adaptive multiple programming of memory, which solves the problem that once a one-time programmable memory is programmed, it cannot be modified or cleared again, making it unsuitable for applications where the program needs to be patched or where different packages have different programming requirements.

[0005] To achieve the above objectives, embodiments of the present invention provide a method for adaptive multiple programming of a memory, the method comprising:

[0006] The internal address space of the memory is divided into a validity identification area, an addressing information area, and a payload area, wherein the payload area includes multiple payload address spaces;

[0007] Store the current program into the payload address space of the memory;

[0008] The legitimacy identifier corresponding to the current program is updated in the legitimacy identifier area, and the addressing information corresponding to the payload address space where the current program is located is updated in the addressing information area;

[0009] Based on the updated validity identifier, determine whether to address the payload address space where the current program is located through the updated addressing information, so as to load the current program.

[0010] In one or more embodiments of the present invention, based on the updated validity identifier, determining whether to address the payload address space where the current program resides through the updated addressing information in order to load the current program specifically includes:

[0011] Based on the updated validity identifier, determine whether the current program corresponding to the updated validity identifier is valid; if so,

[0012] The updated addressing information is used to address the payload address space where the current program is located, and the current program is loaded.

[0013] In one or more embodiments of the present invention, the method specifically includes:

[0014] During the current programming phase, only the current program is loaded, wherein the current program includes all register configurations required for the current programming phase.

[0015] In one or more embodiments of the present invention, the method specifically includes:

[0016] During the current programming, the first historical program and the current program are loaded sequentially, wherein the current program includes updates to the register configurations in the first historical program, and the current program and the first historical program are stored in different payload address spaces.

[0017] In one or more embodiments of the present invention, the method specifically includes:

[0018] During the current programming, the first historical program, the second historical program, and the current program are loaded sequentially, wherein the current program includes updates to the register configurations in the second historical program, the second historical program includes updates to the register configurations in the first historical program, and the current program, the first historical program, and the second historical program are stored in different payload address spaces.

[0019] In one or more embodiments of the present invention, updating the addressing information corresponding to the payload address space where the current program is located in the addressing information area specifically includes:

[0020] Based on the payload address space stored in the current program, update the addressing information of the payload address space, wherein the addressing information includes the address information of the payload address space in the payload area and the length of bytes occupied.

[0021] In one or more embodiments of the present invention, determining whether the current program corresponding to the updated legality identifier is legal based on the updated legality identifier specifically includes:

[0022] The updated validity identifier is parsed using a spatial mapping algorithm to determine whether the current program corresponding to the updated validity identifier is valid.

[0023] In another aspect of the invention, an adaptive multiple programming apparatus for a memory is provided, the apparatus comprising:

[0024] The partitioning module is used to divide the internal address space of the memory into a validity identification area, an addressing information area, and a payload area, wherein the payload area includes multiple payload address spaces.

[0025] A storage module is used to store the current program into the payload address space of the memory;

[0026] The update module is used to update the legality identifier corresponding to the current program in the legality identifier area, and to update the addressing information corresponding to the payload address space where the current program is located in the addressing information area;

[0027] The loading module is used to determine, based on the updated validity identifier, whether to address the payload address space where the current program is located through the updated addressing information, so as to load the current program.

[0028] The update module is also used to: update the addressing information of the payload address space according to the payload address space stored in the current program, wherein the addressing information includes the address information of the payload address space in the payload area and the length of bytes occupied.

[0029] The loading module is further configured to: determine whether the current program corresponding to the updated legality identifier is legal based on the updated legality identifier; if so, address the payload address space where the current program is located through the updated addressing information, and load the current program.

[0030] The loading module is also used to: parse the updated legality identifier using a spatial mapping algorithm to determine whether the current program corresponding to the updated legality identifier is legal.

[0031] The method further includes: during the current programming phase, loading only the current program, wherein the current program includes all register configurations required for the current programming phase.

[0032] The method further includes: during current programming, sequentially loading a first historical program and the current program, wherein the current program includes updates to the register configurations in the first historical program, and the current program and the first historical program are stored in different payload address spaces.

[0033] The method further includes: during current programming, sequentially loading a first historical program, a second historical program, and the current program, wherein the current program includes updates to the register configurations in the second historical program, the second historical program includes updates to the register configurations in the first historical program, and the current program, the first historical program, and the second historical program are stored in different payload address spaces.

[0034] In another aspect of the invention, an electronic device is also provided, the electronic device comprising:

[0035] At least one processor; and

[0036] A memory that stores instructions, when executed by the at least one processor, cause the at least one processor to perform the adaptive multiple programming method of the memory as described above.

[0037] In another aspect of the invention, a computer-readable storage medium is also provided, on which a computer program is stored, which, when executed by a processor, implements the method of adaptive multiple programming of a memory as described above.

[0038] Compared with the prior art, the adaptive multiple programming method and application of memory according to the present invention divides the internal address space of the memory into multiple payload address spaces. When the program stored in the programmed payload address space needs to be revised or supplemented, the revised or supplemented program can be stored in the unprogrammed payload address space, thereby realizing adaptive multiple programming of the memory, meeting the needs of program revision or supplementation, and meeting the needs of different programming for different packages. Moreover, the multiple programming of the memory does not increase the time for loading the program of the microcontroller chip. Attached Figure Description

[0039] Figure 1 This is a flowchart of an adaptive multiple programming method for a memory according to an embodiment of the present invention;

[0040] Figure 2 This is a schematic diagram of the internal address space structure of a memory according to an embodiment of the present invention;

[0041] Figure 3 This is a schematic diagram of the load address space of a memory according to an embodiment of the present invention;

[0042] Figure 4 This is a schematic diagram of the Slice format in the payload address space of a memory according to an embodiment of the present invention;

[0043] Figure 5This is a structural diagram of an adaptive multiple programming apparatus for a memory according to an embodiment of the present invention;

[0044] Figure 6 This is a hardware structure diagram of an electronic device for adaptive multiple programming of memory according to an embodiment of the present invention. Detailed Implementation

[0045] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings, but it should be understood that the scope of protection of the present invention is not limited to the specific embodiments.

[0046] Unless otherwise expressly stated, throughout the specification and claims, the term "comprising" or its variations such as "including" or "comprises" shall be understood to include the stated elements or components without excluding other elements or other components.

[0047] The programmable memory embedded in microcontroller chips is divided into one-time programmable (OTP) memory and multiple-time programmable (MTP) memory. The programming process of one-time programmable (OTP) memory is an irreversible destructive activity, allowing data to be written only once. Generally, before programming, all bits in an OTP memory have the same logical state (e.g., all bits are logic "1"). After programming, the state of some bits is inverted (e.g., originally "1", becomes "0" after programming), and these inverted bits cannot be returned to their original default logical state. MTP memory typically includes erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), and flash memory.

[0048] This invention aims to provide a method and application for adaptive multiple programming of memory, which is applicable to multiple programming of OTP memory and OTP program hardware loading process, and is also applicable to memory such as FLASH / EEPROM / NVM.

[0049] In this invention, adaptive multiple programming of the memory is achieved by re-partitioning the internal address space of the memory.

[0050] like Figure 1 As shown, an adaptive multiple programming method for a memory according to an embodiment of the present invention is described, which specifically includes the following steps.

[0051] S101, the internal address space of the memory is divided into a validity identification area, an addressing information area, and a payload area, wherein the payload area includes multiple payload address spaces.

[0052] For Figure 2 , in this embodiment, taking the OTP memory as an example, the internal address space of the memory is divided into a legality identification area, an addressing information area, and a payload area. Among them, the payload area includes multiple payload address spaces Payload, and all the multiple payload address spaces Payload are used to store programming programs.

[0053] S102, Store the current program into the payload address space of the memory.

[0054] For a programming program, there is a legality identification ID for identifying the legality of the program. The legality identification area includes multiple ID storage spaces for storing legality identifications, and the legality identification ID corresponding to each program can be stored in the corresponding ID storage space.

[0055] The addressing information area includes multiple addressing information spaces HB. Each addressing information space HB corresponds to each payload address space Payload one by one, and each addressing information space HB is respectively used to store the addressing information corresponding to each payload address space. The addressing information includes the initial address of each payload address space in the payload area and the occupied byte length.

[0056] Exemplarily, let the set of payload address spaces in the payload area be P = {Payload0, Payload1,... PayloadX}, that is, it contains (X + 1) payload address spaces Payload and can store (X + 1) groups of programming programs. Among them, X is an integer greater than zero. The set of addressing information spaces HB corresponding to each payload address space Payload is H = {HB_0_0, HB_0_1,... HB_X_1}, where HB_0_0 and HB_0_1 are used to store the addressing information of Payload0, HB_1_0 and HB_1_1 are used to store the addressing information of Payload1, and so on, HB_X_0 and HB_X_1 are used to store the addressing information of PayloadX.

[0057] Thus, based on the above internal address space structure of the memory, the microcontroller chip applying this memory can achieve a maximum of (X + 1) programming times.

[0058] S103, Update the legality identification corresponding to the current program in the legality identification area.

[0059] Specifically, each programming program has a unique legitimacy identifier (ID). When a programming program is stored in the payload address space, its corresponding legitimacy identifier (ID) is stored in the corresponding ID storage space within the legitimacy identifier area. Updating the legitimacy identifier involves updating the legitimacy identifier corresponding to the current program in its corresponding ID storage space.

[0060] When the current program is the first program to be programmed, each ID storage space in the validity identifier area is null, i.e., empty value. At this time, assuming that the validity identifier of the first program to be programmed is ID_0, the validity identifier ID_0 corresponding to the current first program to be updated to the first ID storage space in the validity identifier area; when the current program is the second program to be programmed, let the validity identifier of the second program to be programmed be ID_1, the validity identifier ID_1 corresponding to the current second program to be updated to the second ID storage space in the validity identifier area, and so on, to complete the update of the validity identifier ID of the current program in the subsequent programming process.

[0061] At the same time, the addressing information corresponding to the payload address space where the current program is located is updated in the addressing information area.

[0062] Specifically, during programming, the addressing information of the payload address space can be updated according to the payload address space stored in the current program, and the updated addressing information can be stored in the addressing information space HB corresponding to the payload address space where the current program resides. This update of the addressing information includes updating the address information of the payload in the payload area and updating its byte length.

[0063] S104, based on the updated validity identifier, determine whether to address the payload address space where the current program is located through the updated addressing information, so as to load the current program.

[0064] In this embodiment, determining whether to address the payload address space where the current program is located through the updated addressing information based on the updated legitimacy identifier ID in order to load the current program specifically includes: determining whether the current program corresponding to the updated legitimacy identifier ID is legitimate based on the updated legitimacy identifier ID; if so, addressing the payload address space where the current program is located through the updated addressing information and loading the current program.

[0065] In the above process, the microcontroller chip using this memory can use a space mapping algorithm to parse the updated validity identifier ID to determine the validity of the corresponding current program. If the current program is valid, the microcontroller chip can address the payload address space where the current program is located through the updated addressing information and load the current program.

[0066] In this embodiment, the storage order of the programming program can be stored sequentially according to the setting order of each payload address space in the payload area. That is, the program programmed for the first time is stored in the first payload address space Payload0 in the payload area, the program programmed for the second time is stored in the second payload address space Payload1 in the payload area, and so on.

[0067] The process of storing a programming program in each payload address space means that the payload address space is programmed once, and correspondingly, the addressing information space HB corresponding to that payload address space is also programmed once. Furthermore, each payload address space and its corresponding addressing information space HB can be programmed at most once.

[0068] Specifically, when the current program is the first program programmed, the microcontroller chip only loads the current program during the current programming process. That is, when the microcontroller chip has only been programmed once, only the first payload address space Payload0 and the corresponding first addressing information spaces HB_0_0 and HB_0_1 are programmed. If the programming program is valid, the microcontroller chip only loads the program within the first payload address space Payload0. This current program includes all register configurations required for the current programming.

[0069] When the current program is the second program to be programmed, and the first program to be programmed is the first historical program, then during the current programming process, the first historical program and the current program are loaded sequentially. The current program includes updates to the register configurations in the first historical program. Furthermore, the current program and the first historical program are stored in different payload address spaces.

[0070] When the current program is the third program to be programmed, the first program to be programmed is the first historical program, and the second program to be programmed is the second historical program. During the current programming process, the first historical program, the second historical program, and the current program are loaded sequentially. The current program includes updates to the register configurations in the second historical program, and the second historical program includes updates to the register configurations in the first historical program. Furthermore, the current program, the first historical program, and the second historical program are stored in different payload address spaces.

[0071] Based on the above loading rule, when the current program is the program for the Nth (0 < N ≤ X, N) programming, during the current programming process, the previous (N - 1) historical programs and the current program are loaded in sequence, where N is an integer greater than 1. And during these N programming processes, each subsequent programming program is an update of the previous programming program, so that the program finally loaded and retained in the microcontroller chip is the program for the Nth programming, that is, only the latest programming program in PayloadN is retained. When the value of HB_N_0 in the microcontroller chip is queried as 0x00ffffff, the program loading stops.

[0072] Further, referring Figure 3 , when programming each address in each payload address space Payload, to make full use of all byte spaces of each address and avoid byte space waste, each payload address space Payload can be designed as Figure 3 shown in the structure. Specifically, when traversing the software program, programs with the same rule are placed in the same slice in units of bytes (Byte) in real time. The number of Byte bytes occupied by different slices is completely random. After the slices are divided, they are placed continuously in the storage body according to the time order of the slice division, which can perfectly solve the space waste caused by the mapping process from bytes (Byte) to words (4 * Byte) in the storage body and make full use of the storage body space.

[0073] In this embodiment, CRC check is used to protect the programs in each payload address space Payload, effectively preventing abnormal errors during the program loading process.

[0074] Referring Figure 4 , the format of each slice in each payload address space Payload is designed as Figure 4As shown, bits 7 to 5 of Byte0 are designed as 3 bits, and the type of the current Slice can be parsed as a single data mode or a continuous data mode by using the major voting method. Specifically, a single data mode slice is used to store the operation code of a single instruction, which fixedly occupies 3 byte spaces. Byte1 is used to represent the instruction operation address, and Byte2 is used to represent the instruction operation data. A continuous data mode slice is used to store multiple instruction operation codes, which occupies "N + 3" byte spaces. Byte1 is used to represent the starting address of the multiple instruction operation codes, Byte2 is used to represent the number of the multiple instruction operation codes, and Byte3 to ByteK represent the operation data of the multiple instruction operation codes. For N instructions, the space occupied by using a single data mode slice is "3 * N" Byte, and the space occupied by using a continuous data mode slice is "N + 3" Bytes. It can be seen that for N instructions, using a continuous data mode slice can save "2 * N - 3" Bytes of storage space.

[0075] See Figure 5 , an adaptive multi-programming device of a memory according to a preferred embodiment of the present invention is introduced.

[0076] In an embodiment of the present invention, an adaptive multi-programming device of a memory includes a partitioning module 201, a storage module 202, an update module 203, and a loading module 204.

[0077] The partitioning module 201 is configured to partition the internal address space of the memory into a legality identification area, an addressing information area, and a payload area, and the payload area includes multiple payload address spaces;

[0078] The storage module 202 is configured to store the current program into the payload address space of the memory;

[0079] The update module 203 is configured to update the legality identification corresponding to the current program in the legality identification area and update the addressing information corresponding to the payload address space where the current program is located in the addressing information area;

[0080] The loading module 204 is configured to determine whether to address the payload address space where the current program is located through the updated addressing information based on the updated legality identification, so as to load the current program.

[0081] The update module 203 is further configured to: update the addressing information of the payload address space according to the payload address space where the current program is stored, where the addressing information includes the address information of the payload address space in the payload area and the byte length occupied.

[0082] The loading module 204 is further configured to: determine whether the current program corresponding to the updated legality identifier is legal based on the updated legality identifier; if so, address the payload address space where the current program is located through the updated addressing information, and load the current program.

[0083] The loading module 204 is further configured to: use a spatial mapping algorithm to parse the updated legality identifier in order to determine whether the current program corresponding to the updated legality identifier is legal.

[0084] The method further includes: during the current programming phase, loading only the current program, wherein the current program includes all register configurations required for the current programming phase.

[0085] The method further includes: during current programming, sequentially loading a first historical program and the current program, wherein the current program includes updates to the register configurations in the first historical program, and the current program and the first historical program are stored in different payload address spaces.

[0086] The method further includes: during current programming, sequentially loading a first historical program, a second historical program, and the current program, wherein the current program includes updates to the register configurations in the second historical program, the second historical program includes updates to the register configurations in the first historical program, and the current program, the first historical program, and the second historical program are stored in different payload address spaces.

[0087] Figure 6 A hardware structure diagram of an electronic device 30 with adaptive multiple programming of memory according to an embodiment of this specification is shown. Figure 6 As shown, the electronic device 30 may include at least one processor 301, a memory 302 (e.g., non-volatile memory), a RAM 303, and a communication interface 304, and the at least one processor 301, memory 302, RAM 303, and communication interface 304 are connected together via a bus 305. At least one processor 301 executes at least one computer-readable instruction stored or encoded in the memory 302.

[0088] It should be understood that the computer-executable instructions stored in memory 302, when executed, cause at least one processor 301 to perform the above-described combinations in the various embodiments of this specification. Figure 1-4 The description includes various operations and functions.

[0089] In the embodiments of this specification, electronic device 30 may include, but is not limited to: personal computer, server computer, workstation, desktop computer, laptop computer, notebook computer, mobile computing device, smartphone, tablet computer, cellular phone, personal digital assistant (PDA), handheld device, messaging device, wearable computing device, consumer electronic device, etc.

[0090] According to one embodiment, a program product, such as a computer-readable storage medium, is provided. The computer-readable storage medium may have instructions (i.e., the elements implemented in software as described above), which, when executed by a computer, cause the computer to perform the above-described combinations of the various embodiments of this specification. Figure 1-4 The various operations and functions described. Specifically, a system or apparatus equipped with a readable storage medium storing software program code that implements the functions of any of the embodiments described above, and enabling the computer or processor of the system or apparatus to read and execute the instructions stored in the readable storage medium.

[0091] The adaptive multiple programming method and application of memory according to embodiments of the present invention divides the internal address space of the memory into multiple payload address spaces. When the program stored in the programmed payload address space needs to be revised or supplemented, the revised or supplemented program can be stored in the unprogrammed payload address space, thereby realizing adaptive multiple programming of the memory, meeting the needs of program revision or supplementation, and meeting the needs of different packages with different programming requirements. Moreover, the multiple programming of the memory does not increase the time for loading the program of the microcontroller chip.

[0092] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0093] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0094] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0095] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0096] The foregoing description of specific exemplary embodiments of the invention is for illustrative and explanatory purposes. These descriptions are not intended to limit the invention to the precise forms disclosed, and it will be apparent that many changes and variations can be made in accordance with the foregoing teachings. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application, thereby enabling those skilled in the art to implement and utilize various different exemplary embodiments of the invention, as well as various different choices and variations. The scope of the invention is intended to be defined by the claims and their equivalents.

Claims

1. A method for adaptive multiple programming of a memory, characterized in that, The method includes: The internal address space of the memory is divided into a validity identification area, an addressing information area, and a payload area, wherein the payload area includes multiple payload address spaces; Store the current program into the payload address space of the memory; The legitimacy identifier corresponding to the current program is updated in the legitimacy identifier area, and the addressing information corresponding to the payload address space where the current program is located is updated in the addressing information area; Based on the updated validity identifier, determine whether to address the payload address space where the current program is located through the updated addressing information, so as to load the current program; Wherein, the memory is a one-time programmable memory, the current program is the program programmed for the Nth time, the previous (N-1) historical programs and the current program are stored in different payload address spaces, and in the N programming process, the subsequent programming program is an update of the previous programming program, including the update of the register configuration in the previous programming program; The methods for loading the current program include: Load the previous (N-1) historical programs and the current program in sequence.

2. The adaptive multiple programming method for memory as described in claim 1, characterized in that, Based on the updated validity identifier, determine whether to address the payload address space where the current program is located through the updated addressing information in order to load the current program, specifically including: Based on the updated validity identifier, determine whether the current program corresponding to the updated validity identifier is valid; if so, The updated addressing information is used to address the payload address space where the current program is located, and the current program is loaded.

3. The adaptive multiple programming method for memory as described in claim 2, characterized in that, The method specifically includes: During the current programming phase, only the current program is loaded, wherein the current program includes all register configurations required for the current programming phase.

4. The adaptive multiple programming method for memory as described in claim 2, characterized in that, The method specifically includes: During the current programming, the first historical program and the current program are loaded sequentially, wherein the current program includes updates to the register configurations in the first historical program, and the current program and the first historical program are stored in different payload address spaces.

5. The adaptive multiple programming method for memory as described in claim 2, characterized in that, The method specifically includes: During the current programming, the first historical program, the second historical program, and the current program are loaded sequentially, wherein the current program includes updates to the register configurations in the second historical program, the second historical program includes updates to the register configurations in the first historical program, and the current program, the first historical program, and the second historical program are stored in different payload address spaces.

6. The method for adaptive multiple programming of a memory as described in claim 1, characterized in that, Updating the addressing information in the addressing information area corresponding to the address space of the current program's payload specifically includes: Based on the payload address space stored in the current program, update the addressing information of the payload address space, wherein the addressing information includes the address information of the payload address space in the payload area and the length of bytes occupied.

7. The adaptive multiple programming method for memory as described in claim 2, characterized in that, Based on the updated validity identifier, determine whether the current program corresponding to the updated validity identifier is valid, specifically including: The updated validity identifier is parsed using a spatial mapping algorithm to determine whether the current program corresponding to the updated validity identifier is valid.

8. An adaptive multiple programming device for a memory, characterized in that, The device includes: The partitioning module is used to divide the internal address space of the memory into a validity identification area, an addressing information area, and a payload area, wherein the payload area includes multiple payload address spaces. A storage module is used to store the current program into the payload address space of the memory; The update module is used to update the legality identifier corresponding to the current program in the legality identifier area, and to update the addressing information corresponding to the payload address space where the current program is located in the addressing information area; The loading module is used to determine, based on the updated validity identifier, whether to address the payload address space where the current program is located through the updated addressing information, so as to load the current program; The current program is the program programmed for the Nth time. The previous (N-1) historical programs and the current program are stored in different payload address spaces. In the N programming process, each subsequent programming program is an update of the previous programming program, including the update of the register configuration in the previous programming program. The methods for loading the current program include: Load the previous (N-1) historical programs and the current program in sequence.

9. An electronic device, characterized in that, The electronic device includes: At least one processor; and A memory that stores instructions, when executed by the at least one processor, cause the at least one processor to perform an adaptive multiple programming method of the memory as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the method of adaptive multiple programming of the memory as described in any one of claims 1 to 7.

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