Gate driving circuit and display device including the same

Abstract

Provided is a gate driving circuit and a display device including the gate driving circuit. The gate driving circuit includes: a plurality of signal transmitters; and a plurality of first buffers, each connected to one of the plurality of signal transmitters and including: a first transistor; and a second transistor connected to the first transistor, wherein a first output node for outputting a gate pulse is provided between the first and second transistors, wherein the plurality of signal transmitters includes: a first controller that controls a first control node to serve as a pull-up control node for turning on the first transistor when an activation clock is input to the first controller in a first unit time, and is disabled when an inactivation clock is input to the first controller in a second unit time; and a second controller that controls a second control node to serve as a pull-up control node for turning on the second transistor when an activation clock is input to the second controller in the second unit time, and is disabled when an inactivation clock is input to the second controller in the first unit time.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority and the benefit of Korean Patent Application No. 10 - 2021 - 0089994, filed on July 8, 2021, and Korean Patent Application No. 10 - 2021 - 0170668, filed on December 2, 2021, the entire disclosures of which are incorporated herein by reference. Technical field

[0003] The present invention relates to a gate driving circuit and a display device including the gate driving circuit. Background art

[0004] According to the material of the light - emitting layer, an electroluminescent display device can be classified into an inorganic light - emitting display device and an organic light - emitting display device. An active - matrix organic light - emitting display device includes an organic light - emitting diode (OLED) that generates light by itself and has advantages such as a fast response speed, high luminous efficiency, high brightness, and a wide viewing angle. In an organic light - emitting display device, an OLED is formed in each pixel. The organic light - emitting display device has a fast response speed, high luminous efficiency, high brightness, and a wide viewing angle, and can display black grayscale with perfect black, thereby achieving high contrast and high color reproducibility.

[0005] The pixel circuit of a field - emitting display device includes a light - emitting element, a driving element for driving the light - emitting element, and one or more switching elements. The switching element conducts or cuts off according to the gate voltage to connect or disconnect the main node of the pixel circuit. The driving element and the switching element can be implemented together as one transistor.

[0006] The gate driving circuit generates gate signal pulses to be applied to the gate of the switching element to control the switching element. The gate driving circuit includes a plurality of transistors. The degradation of the transistor is accelerated by gate bias stress as the driving time increases. In the gate driving circuit, since the buffer transistor is applied with a relatively higher voltage and has a relatively longer driving time compared to other transistors, the buffer transistor is applied with higher stress. This is a main factor leading to a reduction in the reliability of the gate driving circuit. Summary of the invention

[0007] An object of the present invention is to meet the needs and / or solve the above - mentioned problems.

[0008] The present invention provides a gate driving circuit capable of reducing the stress applied to a buffer transistor and a display device including the gate driving circuit.

[0009] Aspects of the present invention are not limited thereto, and those of ordinary skill in the art will clearly understand other aspects not described herein according to the following description.

[0010] A gate driving circuit according to an embodiment of the present invention includes: a plurality of signal transmitters, to which a start signal and a shift clock are input, and the signal transmitters are configured to charge or discharge a first control node and a second control node; and a plurality of first buffers, each first buffer being connected to one of the plurality of signal transmitters.

[0011] Each first buffer includes: a first transistor configured to be driven by the voltage of the first control node; and a second transistor configured to be driven by the voltage of the second control node and connected to the first transistor, and a first output node for outputting a gate pulse is provided between the first transistor and the second transistor.

[0012] The plurality of signal transmitters includes: a first controller configured to control the first control node to serve as a pull-up control node for turning on the first transistor when an activation clock is input to the first controller in a first unit time, and to be disabled when an inactivation clock is input to the first controller in a second unit time; and a second controller configured to control the second control node to serve as a pull-up control node for turning on the second transistor when the activation clock is input to the second controller in the second unit time, and to be disabled when the inactivation clock is input to the second controller in the first unit time.

[0013] According to another embodiment of the present invention, a gate driving circuit includes a plurality of signal transmitters configured to charge or discharge a first pull-up control node, a second pull-up control node, and a pull-down control node, to which a start signal and a shift clock are input; and a plurality of first buffers, each first buffer being connected to one of the plurality of signal transmitters,

[0014] Each first buffer of the gate driving circuit includes: a 1-1 pull-up transistor configured to be driven by the voltage of the first pull-up control node; a 1-2 pull-up transistor configured to be driven by the voltage of the second pull-up control node; and a first pull-down transistor configured to be driven by the voltage of the pull-down control node.

[0015] The plurality of signal transmitters includes: a first Q logic generation unit configured to charge a first pull-up control node when an activation clock is input to the first Q logic generation unit at a first pull-up time to turn on the 1-1 pull-up transistor, and to be disabled when an inactivation clock is input to the first Q logic generation unit at a second pull-up time; a second Q logic generation unit configured to charge a second pull-up control node when the activation clock is input to the second Q logic generation unit at the second pull-up time to turn on the 1-2 pull-up transistor, and to be disabled when the inactivation clock is input to the second Q logic generation unit at the first pull-up time; and a QB logic generation unit configured to charge a pull-down control node during a pull-down time when the first pull-up control node and the second pull-up control node are discharged to turn on the first pull-down transistor.

[0016] A display device according to an embodiment of the present invention includes: a display panel on which a plurality of data lines to which data voltages are applied, a plurality of gate lines intersecting the plurality of data lines and to which gate signals are applied, and a plurality of pixels connected to a plurality of power supply lines are provided; a data driving circuit configured to receive pixel data and output the data voltage; and a gate driving circuit configured to output the gate signal using a shift register, wherein the shift register of the gate driving circuit includes: a plurality of signal transmitters configured to charge or discharge a first control node and a second control node, wherein a start signal and a shift clock are input to the plurality of signal transmitters; and a plurality of buffers, each buffer being connected to one of the plurality of signal transmitters, wherein each buffer includes: a first transistor configured to be driven by a voltage of the first control node; and a second transistor configured to be driven by a voltage of the second control node and connected to the first transistor, wherein a first output node is provided between the first transistor and the second transistor, and wherein the plurality of signal transmitters includes: a first controller configured to: control the first control node to serve as a pull-up control node for turning on the first transistor when an activation clock is input to the first controller at a first unit time, and to be disabled when an inactivation clock is input to the first controller at a second unit time; and a second controller configured to: control the second control node to serve as a pull-up control node for turning on the second transistor when the activation clock is input to the second controller at the second unit time, and to be disabled when the inactivation clock is input to the second controller at the first unit time.

[0017] According to another embodiment of the present invention, a display device includes: a display panel on which a plurality of data lines to which a data voltage is applied, a plurality of gate lines intersecting the plurality of data lines and to which a gate signal is applied, and a plurality of pixels connected to a plurality of power supply lines are provided; a data driving circuit configured to receive pixel data and output the data voltage; and a gate driving circuit configured to output the gate signal using a shift register, wherein the shift register of the gate driving circuit includes: a plurality of signal transmitters configured to charge or discharge a first pull-up control node, a second pull-up control node, and a pull-down control node, wherein a start signal and a shift clock are input to the plurality of signal transmitters; and a plurality of first buffers, each first buffer being connected to one of the plurality of signal transmitters, wherein each first buffer includes: a 1-1 pull-up transistor configured to be driven by the voltage of the first pull-up control node; a 1-2 pull-up transistor configured to be driven by the voltage of the second pull-up control node; and a first pull-down transistor configured to be driven by the voltage of the pull-down control node, the plurality of signal transmitters including: a first Q logic generation unit configured to charge the first pull-up control node when an activation clock is input to the first Q logic generation unit at a first pull-up time to turn on the 1-1 pull-up transistor, and to be disabled when an inactivation clock is input to the first Q logic generation unit at a second pull-up time; a second Q logic generation unit configured to charge the second pull-up control node when the activation clock is input to the second Q logic generation unit at the second pull-up time to turn on the 1-2 pull-up transistor, and to be disabled when the inactivation clock is input to the second Q logic generation unit at the first pull-up time; and a QB logic generation unit configured to charge the pull-down control node during a pull-down time when the first pull-up control node and the second pull-up control node are discharged to turn on the first pull-down transistor.

[0018] The display device of the present invention includes the above-mentioned gate driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and other objects, features, and advantages of the present invention will become more apparent to those of ordinary skill in the art by referring to the exemplary embodiments described in detail with reference to the accompanying drawings. In the drawings:

[0020] Figure 1 is a schematic diagram of a shift register of a gate driving circuit according to an embodiment of the present invention;

[0021] Figure 2 is input to Figure 1Waveform diagrams of the shift clock, gate pulse, and carry signal of the shift register;

[0022] Figure 3 Is an exemplary diagram illustrating the gate driving circuits provided on both sides of the display panel;

[0023] Figure 4A And 4B Is a diagram illustrating the driving method of the gate driving circuit according to the first embodiment of the present invention;

[0024] Figure 5 Is Figure 4A And 4B Detailed circuit diagrams of the signal transmitter and buffer shown;

[0025] Figure 6A And 6B Is the waveform diagram of the signals input to / output from the circuit of Figure 5 And the voltage of the main node;

[0026] Figure 7A And 7B Is a diagram illustrating Figure 5 The operation of the circuit in the first unit time and the second unit time;

[0027] Figures 8A to 8F Illustrates based on by Figure 6A And Figure 6B The signals are input to the circuit of Figure 5 The waveform of the simulation performed;

[0028] Figure 9A And 9B Is a diagram illustrating the driving method of the gate driving circuit according to the second embodiment of the present invention;

[0029] Figure 10A And 10B Is a diagram illustrating Figure 9A And Figure 9B The operation of the circuit shown in the first pull-up time and the second pull-up time;

[0030] Figure 11 Is a block diagram of a display device according to an embodiment of the present invention;

[0031] Figure 12 Is Figure 11 A cross-sectional view of the display panel; and

[0032] Figure 13 Is a circuit diagram of a pixel circuit according to an embodiment of the present invention. Detailed implementation mode

[0033] The advantages and features of the present invention and the method for realizing the same will be more clearly understood through the embodiments described with reference to the accompanying drawings below. However, the present invention is not limited to the following embodiments, but can be implemented in various different forms. The embodiments of the present invention will make the disclosure of the present invention complete and enable those skilled in the art to fully understand the scope of the present invention. The present invention is only defined within the scope of the appended claims.

[0034] The shapes, sizes, proportions, angles, quantities, etc. shown in the drawings for describing the embodiments of the present invention are only examples, and the present invention is not limited thereto. Similar reference numerals generally denote similar elements throughout the specification. In addition, in the process of describing the present invention, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present invention.

[0035] Terms such as "comprising", "including", "having" used herein generally intend to allow the addition of other components, unless these terms are used together with the term "only".

[0036] Even if not explicitly described, components are interpreted as including the usual error ranges.

[0037] When using terms such as "on", "above", "below", and "after" to describe the positional relationship between two components, one or more components may be located between these two components, unless these terms are used together with the terms "immediately" or "directly".

[0038] Terms such as "first", "second", etc. may be used to distinguish components from each other, but the functions or structures of the components are not limited by the serial numbers or component names in front of these components.

[0039] Throughout this application, the same reference numerals may represent substantially the same elements.

[0040] The following embodiments may be partially or wholly combined or combined with each other and may be associated and operated in various ways technically. These embodiments may be implemented independently of each other or in association with each other.

[0041] Each pixel may include: a plurality of sub-pixels having different colors to reproduce image colors on the screen of the display panel. Each sub-pixel includes a transistor serving as a switching element or a driving element. Such a transistor can be implemented as a TFT (Thin Film Transistor).

[0042] The driving circuit of the display device writes the pixel data of the input image to the pixels on the display panel. To this end, the driving circuit of the display device may include: a data driving circuit configured to provide a data signal to the data line, a gate driving circuit configured to provide a gate signal to the gate line, etc.

[0043] In the display device of the present invention, the pixel circuit and the gate driving circuit may include a plurality of transistors. The transistors may be implemented as oxide thin film transistors (oxide TFTs) including oxide semiconductors, low temperature polysilicon (LTPS) TFTs including low temperature polysilicon, and the like. In an embodiment, a description will be given based on an example in which the transistors of the pixel circuit are implemented as n-channel oxide TFTs, but the present invention is not limited thereto.

[0044] A transistor is a three-electrode element including a gate, a source, and a drain. The source is an electrode that supplies carriers to the transistor. In the transistor, carriers start to flow from the source. The drain is an electrode from which carriers flow out of the transistor. In the transistor, carriers flow from the source to the drain. In the case of an n-channel transistor, since the carriers are electrons, the source voltage is a voltage lower than the drain voltage, so that electrons can flow from the source to the drain. The n-channel transistor has a current direction from the drain to the source. In the case of a p-channel transistor (p-channel metal oxide semiconductor (PMOS)), since the carriers are holes, the source voltage is higher than the drain voltage, so that holes can flow from the source to the drain. In the p-channel transistor, since holes flow from the source to the drain, the current flows from the source to the drain. It should be noted that the source and drain of the transistor are not fixed. For example, the source and drain may change according to the applied voltage. Therefore, the present invention is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as the first electrode and the second electrode.

[0045] The gate signal swings between a gate-on voltage and a gate-off voltage. The gate-on voltage is set to a voltage higher than the threshold voltage of the transistor, and the gate-off voltage is set to a voltage lower than the threshold voltage of the transistor.

[0046] The transistor conducts in response to the gate-on voltage and cuts off in response to the gate-off voltage. In the case of an n-channel transistor, the gate-on voltage may be a gate high voltage VGH and VEH, and the gate-off voltage may be a gate low voltage VGL and VEH.

[0047] Hereinafter, various embodiments of the present invention will be described in detail with reference to the drawings. In the following embodiments, the display device will be mainly described with respect to an organic light emitting display device, but the present invention is not limited thereto.

[0048] Refer to Figure 1 and Figure 2 , the gate driving circuit includes a shift register that sequentially outputs pulses GOUT(n - 1) to GOUT(n + 2) of the gate signal (hereinafter referred to as "gate pulses") in synchronization with a shift clock CLK.

[0049] The shift register includes a plurality of signal transmitters ST(n-1) to ST(n+2) connected to each other in a subordinate relationship. Each of the signal transmitters ST(n-1) to ST(n+2) includes: a VST node to which a start signal VST is input, a CLK node to which shift clocks CLK1 to CLK4 are input, a first control node and a second control node that alternately drive buffer transistors TR1 and TR2, and so on.

[0050] Generally, the start signal VST is input to the first signal transmitter. In Figure 1 this case, the (n-1)th signal transmitter ST(n-1) may be the first signal transmitter to which the start signal VST is input. The shift clocks CLK1 to CLK4 may be k-phase clocks, but are not limited thereto (k is a natural number).

[0051] When a carry signal CAR is input as the start signal from a previous signal transmitter, the signal transmitters ST(n) to ST(n+2) connected to the (n-1)th signal transmitter ST(n-1) in a subordinate relationship start to be driven. Each of the signal transmitters ST(n-1) to ST(n+2) may output a carry signal CAR through a second output node while outputting gate pulses GOUT(n-1) to GOUT(n+2) through a first output node.

[0052] Figure 1 The shown buffer transistors TR1 and TR2 include a first transistor TR1 and a second transistor TR2 connected to the first output node, which output gate pulses GOUT(n-1) to GOUT(n+2) through the first output node. The first output node is connected to the gate line of a display panel on which an input image is reproduced.

[0053] In at least one of the signal transmitters ST(n-1) to ST(n+2), the first transistor TR1 and the second transistor TR2 alternately serve as pull-up transistors that supply a gate driving voltage GVDD to the first output node at a predetermined time interval, thereby raising the voltage of the first output node. The first transistor TR1 and the second transistor TR2 may be driven at a predetermined time interval as pull-down transistors that discharge the first output node, thereby reducing the gate pulses GOUT(n-1) to GOUT(n+2). The gate driving voltage GVDD may be higher than the gate reference voltage GVSS. The gate driving voltage GVDD may be set as the gate conduction voltage, and the gate reference voltage GVSS may be set as the gate cut-off voltage.

[0054] The predetermined time may be j frame periods (j is a natural number) or a unit time set in seconds (sec).

[0055] In at least one of signal transmitters ST(n - 1) to ST(n + 2), the first transistor TR1 and the second transistor TR2 are alternately used as pull-up transistors at a predetermined time interval. When one of the first transistor TR1 and the second transistor TR2 is used as a pull-up transistor, the other is used as a pull-down transistor and outputs a gate pulse through a first output node.

[0056] Each of the signal transmitters ST(n - 1) to ST(n + 2) alternately charges or discharges a first control node for controlling the first transistor TR1 and a second control node for controlling the second transistor TR2 at a predetermined time interval.

[0057] The first transistor TR1 can be driven as a pull-up transistor in odd unit times and as a pull-down transistor in even unit times. The second transistor TR2 can be driven as a pull-up transistor in even unit times and as a pull-down transistor in odd unit times. Hereinafter, the first unit time can be understood as an odd unit time, and the second unit time can be understood as an even unit time.

[0058] Figure 3 is an example diagram of a shift register of a gate driving circuit mounted on a display panel, which reproduces an input image on the display panel. The gate driving circuit may include a first gate driving unit located in a left border region of the display panel and a second gate driving unit located in a right border region of the display panel. The first gate driving unit and the second gate driving unit may be disposed on opposite sides of the screen, and an input image is displayed on the screen through a pixel array AA located between the first gate driving unit and the second gate driving unit. Each of the first gate driving unit and the second gate driving unit includes Figure 1 the shift register shown. To reduce the border region of the display panel, at least some circuit components of the first gate driving unit and the second gate driving unit may be disposed on the pixel array AA.

[0059] The gate pulses GOUT(n - 1) to GOUT(n + 2) sequentially output by the shift register of the gate driving circuit may include a scan pulse and a light emission control pulse (hereinafter referred to as an "EM pulse").

[0060] In the present invention, the transistors TR1 and TR2 connected to one signal transmitter can be alternately driven at a predetermined time interval to reduce the stress on the transistors TR1 and TR2. In another embodiment, according to the present invention, a plurality of transistors connected to one signal transmitter are alternately driven to reduce the stress thereon.

[0061] As Figure 4A and 4BAs shown, it can drive the buffer BUF that is connected to at least one of the signal transmitters ST(n - 1) to ST(n + 2).

[0062] Figure 4A and 4B is a diagram illustrating a driving method of a first buffer transistor TR1 and a second buffer transistor TR2 according to a first embodiment of the present invention.

[0063] The first transistor TR1 is driven as a pull - up transistor in a first unit time and as a pull - down transistor in a second unit time. As Figure 4A shown, the first transistor TR1 serves as a first pull - up transistor in the first unit time in response to the voltage of a first control node Q / QB (which is controlled to serve as a pull - up control node Q(n)). In this case, the gate drive voltage GVDD is applied to a first power node and the gate reference voltage GVSS is applied to a second power node. The second control node QB / Q is controlled to serve as a pull - down control node QB(n) in the first unit time to use the second transistor TR2 as a pull - down transistor.

[0064] The second transistor TR2 and the first transistor TR1 are driven alternately. For example, the second transistor TR2 serves as a pull - down transistor in the first unit time according to the second control node QB / Q that is controlled to serve as a pull - down control node QB(n), and then serves as a pull - up transistor in the second unit time in response to the voltage of the second control node QB / Q that is controlled to serve as a pull - up control node Q(n). Thus, the first transistor TR1 and the second transistor TR2 are alternately driven as pull - up transistors at a predetermined time interval to disperse stress.

[0065] As Figure 4B shown, the second transistor TR2 serves as a second pull - up transistor in the second unit time when the second control node QB / Q is controlled to serve as a pull - up control node Q(n). In this case, the gate drive voltage GVDD is applied to the second power node and the gate reference voltage GVSS is applied to the first power node. For the second unit time when the second control node QB / Q is controlled to serve as a pull - up control node Q(n), the first control node Q / QB is controlled to serve as a pull - down control node QB(n) to use the first transistor TR1 as a pull - down transistor.

[0066] The signal transmitter ST(n) includes: a first controller CTR1 for controlling the voltage of the first control node Q / QB; and a second controller CTR2 for controlling the voltage of the second control node QB / Q. The first controller CTR1 charges the first control node Q / QB (ON state) in a first unit time when an activation clock is input to control the first transistor TR1 as a pull-up transistor, and is disabled (OFF state) in a second unit time when a deactivation clock is input. The second controller CTR2 charges the second control node QB / Q in a second unit time when an activation clock is input to control the second transistor TR2 as a pull-up transistor, and is disabled in the first unit time when a deactivation clock is input. In Figure 1 either one of the two shift clocks input to the signal transmitter can be an activation clock and the other can be a deactivation clock.

[0067] The activation clock includes a plurality of pulses that swing between a high voltage and a low voltage during a unit time. The deactivation clock can be held at a low voltage during a unit time. The pulse voltage of the activation clock, i.e., the high voltage, can be set as the gate turn-on voltage. The low voltage can be set as the gate cut-off voltage.

[0068] The first transistor TR1 serves as a pull-up transistor during the first unit time when the first control node Q / QB is controlled to serve as a pull-up control node Q(n). During the first unit time, the second control node QB / Q can be controlled by the first controller CTR1 to serve as a pull-down control node QB(n). During the first unit time, the second control node QB / Q is held at the gate reference voltage GVSS. In this case, the second transistor TR2 serves as a pull-down transistor.

[0069] The second transistor TR2 serves as a pull-up transistor during the second unit time when the second control node QB / Q is controlled to serve as a pull-up control node Q(n). During the second unit time, the first control node Q / QB can be controlled by the second controller CTR2 to serve as a pull-down control node QB(n). During the second unit time, the first control node Q / QB is held at the gate reference voltage GVSS. In this case, the first transistor TR1 serves as a pull-down transistor.

[0070] Figure 5 is Figure 4A and Figure 4B the detailed circuit diagrams of the signal transmitter ST(n) and the buffer BUF shown. In Figure 5In the embodiment, a circuit example of the n-th signal transmitter ST(n) that outputs an EM pulse and a buffer BUF connected to the n-th signal transmitter ST(n) is shown, but the present invention is not limited thereto. For example, a circuit substantially the same as the Figure 5 circuit can be used and a clock applicable to a scan pulse can be used as a shift clock to generate a scan pulse. Signal transmitters other than the n-th signal transmitter ST(n) can be implemented as a circuit substantially the same as the n-th signal transmitter ST(n). All transistors constituting the shift register can be implemented as n-channel oxide thin film transistors (TFTs).

[0071] Figure 6A and 6B are waveform diagrams of signals input to / output from the Figure 5 circuit and the voltage of the main node. Figure 6A Illustrates the first control node voltage and the second control node voltage charged or discharged by the first controller CTR1 activated in the first unit time. Figure 6B Illustrates the first control node voltage and the second control node voltage charged or discharged by the second controller CTR2 activated in the second unit time. In Figure 6A and 6B , VDD represents a high voltage and VSS represents a low voltage. Figure 7A and 7B are circuit diagrams illustrating the operation of the Figure 5 circuit in the first unit time and the second unit time. Figure 7A Illustrates the current flow when the first control node Q / QB is controlled to be used as a pull-up control node Q(n) and the second control node QB / Q is controlled to be used as a pull-down control node QB(n) by the first controller CTR1 activated in the first unit time. Figure 7B Illustrates the current flow when the second control node QB / Q is controlled to be used as a pull-up control node Q(n) and the first control node Q / QB is controlled to be used as a pull-down control node QB(n) by the second controller CTR2 activated in the second unit time.

[0072] Referring to Figures 5 to 7B , the n-th signal transmitter ST(n) includes a first controller CTR1 and a second controller CTR2, and is connected to a first buffer BUF1 and a second buffer BUF2.

[0073] In Figure 5 , the gate drive voltages GVDD1 and GVDD2 can be set to different voltages, but are not limited thereto. The gate reference voltages GVSS, GVSS0, and GVSS2 can be set to different voltages, but are not limited thereto.

[0074] The first buffer BUF1 charges or discharges the first output node according to the voltages of the first control node Q / QB and the second control node QB / Q, and outputs an EM pulse EMOUT(n). The first buffer BUF1 includes a first transistor TR1 and a second transistor TR2. The first transistor TR1 includes a gate connected to the first control node Q / QB, a first electrode connected to the first power supply node, and a second electrode connected to the first output node. The second transistor TR2 is connected to the first transistor TR1 and has the first output node therebetween. The second transistor TR2 includes a gate connected to the second control node QB / Q, a first electrode connected to the first output node, and a second electrode connected to the second power supply node. The voltages applied to the first power supply node and the second power supply node are switched between the gate drive voltage GVDD2 and the gate reference voltage GVSS0 at a predetermined time interval. For example, the gate drive voltage GVDD2 may be applied to the first power supply node for a first unit time, and thereafter, the gate reference voltage GVSS0 may be applied to the first power supply node for a second unit time. In contrast, the gate reference voltage GVSS0 may be applied to the second power supply node for a first unit time, and thereafter, the gate drive voltage GVDD2 may be applied to the second power supply node for a second unit time.

[0075] A third capacitor C3 may be connected between the gate and the second electrode of the first transistor TR1. A fourth capacitor C4 is connected between the gate and the first electrode of the second transistor TR2.

[0076] The second buffer BUF2 charges or discharges the second output node according to the voltages of the first control nodes Q / QB and QB / Q, and outputs a carry pulse CAR(n). The second buffer BUF2 includes a third transistor TR3 and a fourth transistor TR4. The third transistor TR3 includes a gate connected to the first control node Q / QB, a first electrode connected to the third power supply node, and a second electrode connected to the second output node. The fourth transistor TR4 is connected to the third transistor TR3 and has the second output node therebetween. The fourth transistor TR4 includes a gate connected to the second control node QB / Q, a first electrode connected to the second output node, and a second electrode connected to the fourth power supply node. The voltages applied to the third power supply node and the fourth power supply node are switched between the gate drive voltage GVDD1 and the gate reference voltage GVSS2. For example, the gate drive voltage GVDD1 may be applied to the third power supply node in a first unit time, and thereafter, the gate reference voltage GVSS2 may be applied to the third power supply node in a second unit time. In contrast, the gate reference voltage GVSS2 may be applied to the fourth power supply node in the first unit time, and thereafter, the gate drive voltage GVDD1 may be applied to the fourth power supply node in the second unit time.

[0077] In at least one first buffer BUF1, the power supply voltages applied to the first transistor TR1 and the second transistor TR2 may be switched periodically. In at least one second buffer BUF2, the power supply voltages applied to the third transistor TR3 and the fourth transistor TR4 may be switched periodically.

[0078] The first controller CTR1 includes a first Q logic generation unit (Q generation logic unit) QG1 and a first QB logic generation unit QBG1.

[0079] As Figure 6A and Figure 7A shown, when the active clock ECLK is input to the first CLK node in the first unit time to charge the first control node Q / QB, the first Q logic generation unit QG1 controls the first control node Q / QB and the second control node QB / Q to serve as the pull-up control node Q(n) and the pull-down control node QB(n), respectively. The first Q logic generation unit QG1 is disabled during the second unit time when the inactive clock ECLKB is input to the first CLK node.

[0080] The first Q logic generation unit QG1 may include fifth to eighth transistors T5 to T8.

[0081] The fifth transistor T5 conducts in a first unit time when an active clock ECLK is input to the first CLK node, thereby connecting the carry signal node to the first buffer node Qh. A carry pulse CAR(n - 1) is applied to the carry signal node. The carry pulse CAR(n - 1) is output from a second output node of a previous signal transmitter, such as the (n - 1)th signal transmitter ST(n - 1). The fifth transistor T5 includes a gate connected to the first CLK node, a first electrode connected to the carry signal node, and a second electrode connected to the first buffer node Qh. An inactive clock ECLKB is input to the first CLK node in a second unit time.

[0082] The sixth transistor T6 conducts in a first unit time when an active clock ECLK is input to the first CLK node, thereby connecting the first buffer node Qh to the first control node Q / QB. The sixth transistor T6 includes a gate connected to the first CLK node, a first electrode connected to the first buffer node Qh, and a second electrode connected to the first control node Q / QB.

[0083] The fifth transistor T5 and the sixth transistor T6 conduct according to a high voltage VDD of the active clock ECLK in a first unit time when the active clock ECLK is applied to the first CLK node, thereby charging the first buffer node Qh and the first control node Q / QB. In this case, the first control node Q / QB serves as a pull-up control node Q(n). The fifth transistor T5 and the sixth transistor T6 remain in a cut-off state in a second unit time when an inactive clock ECLKB is input to the first CLK node.

[0084] When the first control node Q / QB is charged with the high voltage VDD, the seventh transistor T7 conducts to connect the fifth power supply node to the first buffer node Qh, thereby charging or discharging the first buffer node Qh. A gate drive voltage GVDD1 is applied to the fifth power supply node in the first unit time, as Figure 7A shown; a gate reference voltage GVSS0 is applied to the fifth power supply node in the second unit time, as Figure 7B shown. The seventh transistor T7 includes a gate connected to the first control node Q / QB, a first electrode connected to the fifth power supply node, and a second electrode connected to the first buffer node Qh.

[0085] When the voltage of the second buffer node QhB is the high voltage VDD, the eighth transistor T8 conducts to connect the sixth power supply node to the first control node Q / QB, thereby discharging the first control node Q / QB. A gate reference voltage GVSS2 is applied to the sixth power supply node. The eighth transistor T8 includes a gate connected to the second buffer node QhB, a first electrode connected to the sixth power supply node, and a second electrode connected to the first control node Q / QB.

[0086] As Figure 6A and Figure 7A shown, when the first control node Q / QB is discharged to a low voltage VSS in the first unit time, the first QB logic generation unit QBG1 charges the second control node QB / Q to control the second control node QB / Q to be used as a pull-down control node QB(n).

[0087] The first QB logic generation unit QBG1 may include ninth to eleventh transistors T9, T10, T11.

[0088] When the voltage of the second control node QB / Q of a previous signal transmitter, such as the (n - 1)th signal transmitter ST(n - 1), is a high voltage VDD, the ninth transistor T9 conducts to connect the seventh power supply node to the gate of the eleventh transistor T11. The gate drive voltage GVDD1 is applied to the seventh power supply node in the first unit time, as Figure 7A shown; the gate reference voltage GVSS is applied to the seventh power supply node in the second unit time, as Figure 7B shown. The ninth transistor T9 includes a gate connected to the second control node QB / Q of the previous signal transmitter, a first electrode connected to the seventh power supply node, and a second electrode connected to the gate of the eleventh transistor T11.

[0089] When the voltage of the first buffer node Qh is a high voltage VDD, the tenth transistor T10 conducts to connect the gate of the eleventh transistor T11 to the tenth power supply node. The gate reference voltage GVSS1 is applied to the tenth power supply node. The tenth transistor T10 includes a gate connected to the first buffer node Qh, a first electrode connected to the gate of the eleventh transistor T11, and a second electrode connected to the tenth power supply node.

[0090] When the gate voltage is a high voltage VDD, the eleventh transistor T11 conducts to connect the eleventh power supply node to the second control node QB / Q. The gate drive voltage GVDD1 is applied to the eleventh power supply node. The eleventh transistor T11 includes a gate connected to the second electrode of the ninth transistor T9 and the first electrode of the tenth transistor T10, a first electrode connected to the eleventh power supply node, and a second electrode connected to the second control node QB / Q. A first capacitor C1 may be connected between the gate and the second electrode of the eleventh transistor T11.

[0091] The second controller CTR2 includes a second Q logic generation unit QG2 and a second QB logic generation unit QBG2.

[0092] As Figure 6B and 7BAs shown, when the second control node QB / Q is charged in the second unit time when the active clock ECLK is input to the second CLK node, the second Q logic generation unit QG2 controls the second control node QB / Q and the first control node Q / QB to respectively serve as the pull-up control node Q(n) and the pull-down control node QB(n). The second Q logic generation unit QG2 is disabled during the second unit time when the inactive clock ECLKB is input to the second CLK node.

[0093] The second Q logic generation unit QG2 may include the twelfth to fifteenth transistors T12 to T15.

[0094] The twelfth transistor T12 is turned on in the second unit time when the active clock ECLK is input to the second CLK node, thereby connecting the carry signal node to the second buffer node QhB. The carry pulse CAR(n - 1) is applied to the carry signal node. The carry pulse CAR(n - 1) is output from the second output node of the previous signal transmitter, such as the (n - 1)th signal transmitter ST(n - 1). The twelfth transistor T12 includes a gate connected to the second CLK node, a first electrode connected to the carry signal node, and a second electrode connected to the second buffer node QhB.

[0095] The thirteenth transistor T13 is turned on in the second unit time when the active clock ECLK is input to the second CLK node, thereby connecting the second buffer node QhB to the second control node QB / Q. The thirteenth transistor T13 includes a gate connected to the second CLK node, a first electrode connected to the second buffer node QhB, and a second electrode connected to the second control node QB / Q.

[0096] The twelfth transistor T12 and the thirteenth transistor T13 are turned on according to the high voltage VDD of the active clock ECLK in the second unit time when the active clock ECLK is applied to the second CLK node, thereby charging the second buffer node QhB and the second control node QB / Q. In this case, the second control node QB / Q serves as the pull-up control node Q(n). The twelfth transistor T12 and the thirteenth transistor T13 remain in the cut-off state in the first unit time when the inactive clock ECLKB is input to the second CLK node.

[0097] When the second control node QB / Q is charged with the high voltage VDD, the fourteenth transistor T14 is turned on to connect the twelfth power supply node to the second buffer node QhB, thereby charging or discharging the second buffer node QhB. The gate drive voltage GVDD1 is applied to the twelfth power supply node in the second unit time, as Figure 7B shown; the gate reference voltage GVSS0 is applied to the twelfth power supply node in the first unit time, as Figure 7AAs shown, the fourteenth transistor T14 includes a gate connected to the second control node QB / Q, a first electrode connected to the twelfth power supply node, and a second electrode connected to the second buffer node QhB.

[0098] When the voltage of the first buffer node Qh is the high voltage VDD, the fifteenth transistor T15 is turned on to connect the sixth power supply node to the second control node QB / Q, thereby discharging the second control node QB / Q. The gate reference voltage GVSS2 is applied to the sixth power supply node. The fifteenth transistor T15 includes a gate connected to the first buffer node Qh, a first electrode connected to the sixth power supply node, and a second electrode connected to the second control node QB / Q.

[0099] As Figure 6B and Figure 7B shown, when the second control node QB / Q is discharged to the low voltage VSS in the second unit time, the second QB logic generation unit QBG2 charges the first control node Q / QB to control the first control node Q / QB to be used as the pull-down control node QB(n).

[0100] The second QB logic generation unit QBG2 may include the sixteenth to eighteenth transistors T16, T17, T18.

[0101] When the voltage of the first control node Q / QB of the previous signal transmitter, such as the (n - 1)th signal transmitter ST(n - 1), is the high voltage VDD, the sixteenth transistor T16 is turned on to connect the thirteenth power supply node to the gate of the eighteenth transistor T18. The gate reference voltage GVSS is applied to the thirteenth power supply node in the first unit time, as Figure 7A shown; the gate drive voltage GVDD1 is applied to the thirteenth power supply node in the second unit time, as Figure 7B shown. The sixteenth transistor T16 includes a gate connected to the first control node Q / QB of the previous signal transmitter, a first electrode connected to the thirteenth power supply node, and a second electrode connected to the gate of the eighteenth transistor T18.

[0102] When the voltage of the second buffer node QhB is the high voltage VDD, the seventeenth transistor T17 is turned on to connect the gate of the eighteenth transistor T18 to the tenth power supply node. The gate reference voltage GVSS1 is applied to the tenth power supply node. The seventeenth transistor T17 includes a gate connected to the second buffer node QhB, a first electrode connected to the gate of the eighteenth transistor T18, and a second electrode connected to the tenth power supply node.

[0103] When the gate voltage is the high voltage VDD, the eighteenth transistor T18 conducts to connect the eleventh power supply node to the first control node Q / QB. The gate drive voltage GVDD1 is applied to the eleventh power supply node. The eighteenth transistor T18 includes a gate connected to the second electrode of the sixteenth transistor T16 and the first electrode of the seventeenth transistor T17, a first electrode connected to the eleventh power supply node, and a second electrode connected to the first control node Q / QB. The second capacitor C2 may be connected between the gate and the second electrode of the eighteenth transistor T18.

[0104] Figures 8A to 8F illustrates the simulation waveforms based on the circuit by inputting the Figure 6A and Figure 6B signals into the Figure 5 . In Figure 8D , Q(n) represents the waveform of the voltage of the pull-up control node corresponding to the first control node Q / QB in the first unit time and the waveform of the voltage of the pull-up control node corresponding to the second control node QB / Q in the second unit time. In Figure 8E , QB(n) represents the waveform of the voltage of the pull-down control node corresponding to the second control node QB / Q in the first unit time and the waveform of the voltage of the pull-down control node corresponding to the first control node Q / QB in the second unit time.

[0105] In the gate drive circuit of another embodiment, two pull-up transistors are alternately driven to disperse the stress thereon, as Figures 9A to 10B shows. This embodiment is applicable to at least one of the first and second Q logic generation units as described above and the buffer connected to at least one Q logic generation unit, or can be applied alone. For example, in the present invention, Figures 4A to 5 at least one of the first controller CTR1 and the second controller CTR2 of the gate drive circuit shown can be configured as the Q logic generation unit of 10A and Figure 10B the first and second Q logic generation units shown. In this case, each buffer transistor may include two transistors that are alternately driven. The first unit time may be divided into a first and a second pull-up time. The first Q logic generation unit may drive one of the two pull-up transistors in the first pull-up time, and the second Q logic generation unit may drive the other pull-up transistor in the second pull-up time.

[0106] Figure 9A and 9B are diagrams illustrating the driving method of the buffer transistor according to the second embodiment of the present invention. In FIGS. 9 and 10, the gate drive voltages GVDD, GVDD1, and GVDD2 may be set to different voltages, but are not limited thereto. The gate reference voltages GVSS0, GVSS1, and GVSS2 may be set to different voltages, but are not limited thereto. Figure 10A and10B is a diagram Figure 9A and 9B the circuit diagram showing the operations at the first pull-up time and the second pull-up time.

[0107] Referring to Figures 9A to 10B , the n-th signal transmitter ST(n) includes a first Q logic generation unit QG11, a second Q logic generation unit QG12, and a QB logic generation unit QBG.

[0108] The first Q logic generation unit QG11 drives the 1-1 pull-up transistor TR11 (ON state) of the first buffer BUF1 by charging the first pull-up control node Q1(n) at the first pull-up time of the input active clock ECLK. The first Q logic generation unit QG11 can further drive the 3-1 pull-up transistor TR31 of the second buffer BUF2 at the first pull-up time, as Figure 10A shown. The first Q logic generation unit QG11 can be disabled (OFF state) at the second pull-up time by being input with the inactive clock ECLKB, as Figure 10B shown.

[0109] The second Q logic generation unit QG12 and the first Q logic generation unit QG11 are alternately activated to charge the second pull-up control node Q2(n), thereby driving the 1-2 pull-up transistor TR12. The second Q logic generation unit QG12 drives the 1-2 pull-up transistor TR12 of the first buffer BUF1 at the second pull-up time of the input active clock ECLK, as Figure 10A shown. The second Q logic generation unit QG12 can further drive the 3-2 pull-up transistor TR32 of the second buffer BUF2 at the second pull-up time. The second Q logic generation unit QG12 can be disabled at the first pull-up time by being input with the inactive clock ECLKB, as Figure 10B shown.

[0110] The active clock ECLK includes a plurality of pulses that swing between a high voltage and a low voltage in a unit time. The inactive clock ECLKB remains at a low voltage during the unit time.

[0111] The QB logic generation unit QBG drives the pull-down transistors TR20 and TR40 by charging the pull-down control node QB(n) at the pull-down time when the first pull-up control node Q1(n) and the second pull-up control node Q2(n) are discharged. The QB logic generation unit QBG can drive the pull-down transistors TR20 and TR40 of the first buffer BUF1 in response to the voltage of the pull-up control node of the previous signal transmitter, for example, the (n-1)-th signal transmitter ST(n-1).

[0112] The first buffer BUF1 charges or discharges the first output node and outputs an EM pulse EMOUT(n). The first buffer BUF1 includes a 1-1 pull-up transistor TR11 and a 1-2 pull-up transistor TR12 that are alternately driven by a first Q logic generation unit QG11 and a second Q logic generation unit QG12, and a first pull-down transistor TR20 that is driven by a QB logic generation unit QBG.

[0113] The 1-1 pull-up transistor TR11 includes a gate connected to a first pull-up control node Q1(n), a first electrode connected to a first power supply node, and a second electrode connected to the first output node. The second electrode of the 1-1 pull-up transistor TR11 can be connected to the first output node via a second capacitor C6. The 1-2 pull-up transistor TR12 includes a gate connected to a second pull-up control node Q2(n), a first electrode connected to the first power supply node, and a second electrode connected to the first output node. A gate drive voltage GVDD2 is applied to the first power supply node. The second capacitor C6 can be connected between the second electrode of the 1-1 pull-up transistor TR11 and the first output node. A third capacitor C7 can be connected between the gate and the second electrode of the 1-2 pull-up transistor TR12.

[0114] The first pull-down transistor TR20 is connected to the 1-1 pull-up transistor TR11 and the 1-2 pull-up transistor TR12, and the first output node is located between the first pull-down transistor TR20 and the 1-1 pull-up transistor TR11 and the 1-2 pull-up transistor TR12. The first pull-down transistor TR20 includes a gate connected to a pull-down control node QB(n), a first electrode connected to the first output node, and a second electrode connected to a second power supply node. A gate reference voltage GVSS0 is applied to the second power supply node.

[0115] The second buffer BUF2 charges or discharges the second output node and outputs a carry pulse CAR(n). The second buffer BUF2 includes a 3-1 pull-up transistor TR31 and a 3-2 pull-up transistor TR32 that are alternately driven by a first Q logic generation unit QG11 and a second Q logic generation unit QG12, and a second pull-down transistor TR40 that is driven by a QB logic generation unit QBG.

[0116] The 3-1 pull-up transistor TR31 includes a gate connected to a first pull-up control node Q1(n), a first electrode connected to a first power supply node, and a second electrode connected to the second output node. The 3-2 pull-up transistor TR32 includes a gate connected to a second pull-up control node Q2(n), a first electrode connected to a first power supply node, and a second electrode connected to the second output node.

[0117] The second pull-down transistor TR40 is connected to the 3-1 pull-up transistor TR31 and the 3-2 pull-up transistor TR32, and the second output node is located between the second pull-down transistor TR40 and the 3-1 pull-up transistor TR31 and the 3-2 pull-up transistor TR32. The second pull-down transistor TR40 includes a gate connected to the pull-down control node QB(n), a first electrode connected to the second output node, and a second electrode connected to the second power supply node.

[0118] The first Q logic generation unit QG11 may include fourth to sixth transistors T25 to T27, as Figure 10A and 10B shown. The first Q logic generation unit QG11 may further include a seventh transistor T28 shared with the second Q logic generation unit QG12.

[0119] The fourth transistor T25 conducts during a first pull-up time when an active clock ECLK is input to the first CLK node, thereby connecting the carry signal node to the first buffer node Qh1. A carry pulse CAR(n - 1) from a previous signal transmitter is applied to the carry signal node. The carry pulse CAR(n - 1) is output from a second output node of a previous signal transmitter, such as the (n - 1)th signal transmitter ST(n - 1). The fourth transistor T25 includes a gate connected to the first CLK node, a first electrode connected to the carry signal node, and a second electrode connected to the first buffer node Qh1. An inactive clock ECLKB is input to the first CLK node during a second pull-up time.

[0120] The fifth transistor T26 conducts during a first pull-up time when an active clock ECLK is input to the first CLK node, thereby connecting the first buffer node Qh1 to the first pull-up control node Q1(n). The fifth transistor T26 includes a gate connected to the first CLK node, a first electrode connected to the first buffer node Qh1, and a second electrode connected to the first pull-up control node Q1(n).

[0121] The fourth transistor T25 and the fifth transistor T26 conduct according to a high voltage VDD of the active clock ECLK during a first pull-up time when the active clock ECLK is applied to the first CLK node, thereby charging the first buffer node Qh1 and the first pull-up control node Q1(n). The fourth transistor T25 and the fifth transistor T26 remain in a cut-off state during a second pull-up time when an inactive clock ECLKB is input to the first CLK node and during a pull-down time.

[0122] When charging the first pull-up control node Q1(n) with the high voltage VDD, the sixth transistor T27 is turned on to connect the third power supply node to the first buffer node Qh1, thereby charging the first buffer node Qh1. The gate drive voltage GVDD is applied to the third power supply node. The sixth transistor T27 includes a gate connected to the first pull-up control node Q1(n), a first electrode connected to the third power supply node, and a second electrode connected to the first buffer node Qh1.

[0123] When the voltage of the first buffer node QH1 or the voltage of the second buffer node Qh2 is a high voltage, the seventh transistor T28 is turned on to connect the pull-down control node QB(n) to the fourth power supply node, thereby discharging the pull-down control node QB(n). The gate reference voltage GVSS2 is applied to the fourth power supply node. The seventh transistor T28 includes a gate connected to the first buffer node Qh1 and the second buffer node Qh2, a first electrode connected to the pull-down control node QB(n), and a second electrode connected to the fourth power supply node.

[0124] The second Q logic generation unit QG12 may include eighth to tenth transistors T29 to T31, as Figure 10A and 10B shown.

[0125] The eighth transistor T29 is turned on during the second pull-up time when the active clock ECLK is input to the second CLK node, thereby connecting the carry signal node to the first buffer node Qh1. The carry pulse CAR(n - 1) from the previous signal transmitter is applied to the carry signal node. The eighth transistor T29 includes a gate connected to the second CLK node, a first electrode connected to the carry signal node, and a second electrode connected to the second buffer node Qh2. The inactive clock ECLKB is input to the second CLK node during the first pull-up time.

[0126] The ninth transistor T30 is turned on during the second pull-up time when the active clock ECLK is input to the second CLK node, thereby connecting the second buffer node Qh2 to the second pull-up control node Q2(n). The ninth transistor T30 includes a gate connected to the second CLK node, a first electrode connected to the second buffer node Qh2, and a second electrode connected to the second pull-up control node Q2(n).

[0127] The eighth transistor T29 and the ninth transistor T30 are turned on according to the high voltage of the active clock ECLK during the second pull-up time when the active clock ECLK is applied to the second CLK node, thereby charging the second buffer node Qh2 and the second pull-up control node Q2(n). The eighth transistor T29 and the ninth transistor T30 remain in the cut-off state during the first pull-up time and the pull-down time when the inactive clock ECLKB is input to the second CLK node.

[0128] When charging the second pull-up control node Q2(n) with a high voltage, the tenth transistor T31 is turned on to connect the third power supply node to the second buffer node Qh2, thereby charging the second buffer node Qh2. The gate drive voltage GVDD is applied to the third power supply node. The tenth transistor T31 includes a gate connected to the second pull-up control node Q2(n), a first electrode connected to the third power supply node, and a second electrode connected to the second buffer node Qh2.

[0129] In response to the voltages of the first pull-up control node Q1(n) and the second pull-up control node Q2(n) that are alternately charged during the first and second pull-up times, the pull-up transistors TR11, TR12, TR31, and TR32 are turned on, thereby charging the output node.

[0130] The QB logic generation unit QBG charges the pull-down control node QB(n) during the pull-down time. When charging the pull-down control node QB(n) with a high voltage, the pull-down transistors TR20 and TR40 are turned on to discharge the output node to the gate reference voltages GVSS0 and GVSS2, respectively.

[0131] The QB logic generation unit QBG may include the eleventh to fourteenth transistors T32 to T35.

[0132] When the voltage of the pull-down control node QB(n - 1) of the previous signal transmitter, such as the (n - 1)th signal transmitter ST(n - 1), is a high voltage, that is, during the pull-down time, the eleventh transistor T32 is turned on to connect the fifth power supply node to the gate of the fourteenth transistor T35. The gate drive voltage GVDD1 is applied to the fifth power supply node. The eleventh transistor T32 includes a gate connected to the pull-down control node QB(n - 1) of the previous signal transmitter, a first electrode connected to the fifth power supply node, and a second electrode connected to the gate of the fourteenth transistor T35.

[0133] When the voltage of the first buffer node Qh1 is a high voltage, that is, during the first pull-up time, the twelfth transistor T33 is turned on to connect the gate of the fourteenth transistor T35 to the sixth power supply node. The gate reference voltage GVSS1 is applied to the sixth power supply node. The twelfth transistor T33 includes a gate connected to the first buffer node Qh1, a first electrode connected to the gate of the fourteenth transistor T35, and a second electrode connected to the sixth power supply node.

[0134] When the voltage of the second buffer node Qh2 is a high voltage, i.e., during the second pull-up time, the thirteenth transistor T34 is turned on to connect the gate of the fourteenth transistor T35 to the sixth power supply node. The thirteenth transistor T34 includes a gate connected to the second buffer node Qh2, a first electrode connected to the gate of the fourteenth transistor T35, and a second electrode connected to the sixth power supply node.

[0135] During the pull-down time when the gate voltage is a high voltage, the fourteenth transistor T35 is turned on to connect the fifth power supply node to the pull-down control node QB(n), thereby charging the pull-down control node QB(n). The fourteenth transistor T35 includes: a gate connected to the second electrode of the eleventh transistor T32, the first electrode of the twelfth transistor T33, and the first electrode of the thirteenth transistor T34; a first electrode connected to the fifth power supply node; and a second electrode connected to the pull-down control node QB(n). A first capacitor C5 may be connected between the gate and the second electrode of the fourteenth transistor T35.

[0136] Figure 11 is a block diagram of a display device according to an embodiment of the present invention. Figure 12 is Figure 11 a cross-sectional view of the display panel of

[0137] Referring to Figure 11 and 12 According to an embodiment of the present invention, a display device includes: a display panel 100; a display panel driver for writing pixel data to pixels of the display panel 100; and a power supply 140 for generating power required to drive the pixels and the display panel driver.

[0138] The display panel 100 may be a display panel having a rectangular structure with a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. The display panel 100 includes a pixel array for displaying an input image on a screen. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 intersecting the plurality of data lines 102, and a plurality of pixels arranged in a matrix. The display panel 100 may further include a power supply line commonly connected to the pixels. The power supply line may include a power supply line for applying a pixel driving voltage ELVDD, a power supply line for applying an initialization voltage Vinit1, and a power supply line for applying a low-potential power supply voltage ELVSS.

[0139] The cross-sectional structure of the display panel 100 includes a circuit layer 12, a light-emitting element layer 14, and a packaging layer 16 stacked on a substrate 10, as Figure 12 shown.

[0140] The circuit layer 12 may include thin film transistors (TFTs) having pixel circuits, a demultiplexer array 112, a gate driver 120, etc., where the pixel circuits are connected to interconnect structures such as data lines, gate lines, power supply lines, etc. The interconnect structures and circuit elements of the circuit layer 12 may include a plurality of insulating layers, two or more metal layers separated from each other and having insulating layers therebetween, and an active layer including a semiconductor material. All transistors formed in the circuit layer 12 may be implemented as n-channel oxide TFTs.

[0141] The light-emitting element layer 14 may include light-emitting elements EL driven by the pixel circuits. The light-emitting elements EL may include red (R) light-emitting elements, green (G) light-emitting elements, and blue (B) light-emitting elements. In another embodiment, the light-emitting element layer 14 may include white light-emitting elements and color filters. The light-emitting elements EL of the light-emitting element layer 14 may be covered by a multi-layer protective layer including organic films and inorganic films.

[0142] The encapsulation layer 16 covers the light-emitting element layer 14 to seal the circuit layer 12 and the light-emitting element layer 14. The encapsulation layer 16 may be a multi-insulating film structure in which organic films and inorganic films are alternately stacked. The inorganic film blocks the penetration of moisture or oxygen. The organic film planarizes the surface of the inorganic film. When the organic film and the inorganic film are stacked in multiple layers, the moving path of moisture or oxygen is longer than that in the case of a single layer, so the penetration of moisture and oxygen that can affect the light-emitting element layer 14 can be effectively blocked.

[0143] Although not shown, a touch sensor layer is formed on the encapsulation layer 16, and a polarizing plate or a color filter layer may be provided on the touch sensor layer. The touch sensor layer may include a capacitive touch sensor that senses a touch input based on capacitance changes before and after the touch input is performed. The touch sensor layer may include an insulating film and a metal interconnect pattern that form the capacitance of the touch sensor. The insulating film may insulate the crossing portions of the metal interconnect pattern and planarize the surface of the touch sensor layer. The polarizing plate may convert the polarization of external light reflected from the metals of the touch sensor layer and the circuit layer to improve visibility and contrast. The polarizing plate may be implemented as a polarizing plate or a circular polarizing plate in which a linear polarizing plate and a phase retardation film are joined to each other. A cover glass may be bonded to the polarizing plate. The color filter layer may include red, green, and blue color filters. The color filter layer may further include a black matrix pattern. The color filter layer may absorb a part of the light reflected from the circuit layer and the touch sensor layer rather than from the polarizing plate and increase the color purity of the image reproduced on the pixel array.

[0144] The pixel array includes a plurality of pixel rows L1 to Ln. Each of the pixel rows L1 to Ln includes a row of pixels arranged in the row direction (X-axis direction) on the pixel array of the display panel 100. The pixels arranged in one pixel row share the gate line 103. The pixels arranged in the column direction Y along the data line direction share the same data line 102. One horizontal period is the time obtained by dividing the first frame period by the total number of the pixel rows L1 to Ln.

[0145] The display panel 100 can be implemented as a non-transmissive display panel or a transmissive display panel. The transmissive display panel is applicable to a transparent display device, where an image is displayed on the screen and the real background is visible. The display panel 100 can be manufactured as a flexible display panel.

[0146] Each pixel 101 can be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel to achieve color. Each pixel 101 can further include a white sub-pixel. Each sub-pixel includes a pixel circuit. Hereinafter, "pixel" can be understood to have the same meaning as "sub-pixel". Each pixel circuit is connected to a data line, a gate line, and a power line.

[0147] The pixels can be arranged in the form of actual color pixels and Pentile pixels. In the case of Pentile pixels, two sub-pixels of different colors are driven together as one pixel 101 using a predetermined pixel rendering algorithm, so as to achieve a higher resolution than that of the actual color pixels. The pixel rendering algorithm can utilize the colors of the light emitted from adjacent pixels to compensate for the insufficient color reproduction of each pixel.

[0148] The power supply 140 uses a DC-DC converter to generate the direct current (DC) power required to drive the pixel array of the display panel 100 and the display panel driver. The DC-DC converter can include a charge pump, a rectifier, a buck converter, a boost converter, etc. The power supply 140 can adjust the level of the input DC voltage applied from a host system (not shown) to generate a DC voltage (or a constant voltage), such as a gamma reference voltage VGMA, a gate-on voltage VGH, a gate-off voltage VGL, a pixel driving voltage ELVDD, a low-potential power supply voltage ELVSS, or an initialization voltage Vinit1. The gamma reference voltage VGMA is provided to the data driver 110. The gate-on voltage VGH and the gate-off voltage VGL are provided to the gate driver 120. The pixel driving voltage ELVDD, the low-potential power supply voltage ELVSS, and the initialization voltage Vinit1 are commonly applied to the pixel 101.

[0149] The display panel driver writes the pixel data of the input image to the pixels of the display panel 100 under the control of the timing controller 130.

[0150] The display panel driver includes a data driver 110 and a gate driver 120. The display panel driver may further include a demultiplexer array 112 located between the data driver 110 and the data lines 102.

[0151] The demultiplexer array 112 sequentially applies the data voltages output from the channels of the data driver 110 to the data lines 102 by using a plurality of demultiplexers (DEMUX). The DEMUX may include a plurality of switching elements located on the display panel 100. When the DEMUX is disposed between the output terminals of the data driver 110 and the data lines 102, the number of channels of the data driver 110 can be reduced. The demultiplexer array 112 may be omitted.

[0152] The display panel driver may further include a touch sensor driver for driving a touch sensor. The touch sensor driver is omitted in Figure 11 The data driver 110 and the touch sensor driver may be integrated into one driving integrated circuit (IC). In a mobile device or a wearable device, the timing controller 130, the power supply 140, the data driver 110, etc. may be integrated into one driving IC.

[0153] The display panel driver may operate in a low-speed driving mode under the control of the timing controller 130. The low-speed driving mode may be set to analyze the input image and reduce the power consumption of the display device when the degree of change of the input image is lower than a predetermined number of frames. In the low-speed driving mode, when a still image is input for a specific period or a longer period, the refresh rate of the pixels can be reduced to reduce the power consumption of the display panel driver and the display panel 100. The low-speed driving mode is not limited to the case of inputting a still image. For example, when the display device operates in a standby mode or when no user command or input image is input to the display panel driver within a specific time, the display panel driver may operate in the low-speed driving mode.

[0154] The data driver 110 receives the pixel data of the input image in the form of a digital signal from the timing controller 130 and outputs a data voltage. The data driver 110 generates a data voltage by converting the pixel data of the input image into a gamma-compensated voltage using a digital-to-analog converter (DAC) in each frame period. The gamma reference voltage VGMA is divided into gamma-compensated voltages for each gray level by a voltage dividing circuit. The gamma-compensated voltages for each gray level are provided to the DAC of the data driver 110. The data voltage is output through an output buffer in each channel of the data driver 110.

[0155] The gate driver 120, together with the interconnect structure of the TFT array and the pixel array, can be implemented as an in-panel gate (GIP) circuit formed on the circuit layer 12 of the display panel 100. The gate driver 120 can be disposed on the bezel area BZ (which is the non-display area of the display panel 100) or dispersed thereon and reproduced in the pixel array of the input image. The gate driver 120 sequentially outputs gate signals to the gate lines 103 under the control of the timing controller 130. The gate driver 120 can shift the gate signals by using a shift register and sequentially provide the obtained signals to the gate lines 103. In the organic light-emitting display device, the gate signals can include a scan pulse, an EM pulse, an initialization pulse, and the like.

[0156] The gate driver 120 can include a first shift register 121 for outputting a scan pulse, a second shift register 122 for outputting an EM pulse, and a third shift register 123 for outputting an initialization pulse. At least one of the shift registers 121, 122, and 123 can be implemented as the gate driving circuit described in the above embodiment.

[0157] The timing controller 130 receives the digital video data DATA of the input image and the timing signals synchronized with the digital video data DATA from the host system. The timing signals can include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock CLK, a data enable signal DE, and the like. The vertical period and the horizontal period can be identified by a method of counting the data enable signal DE, so the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The data enable signal DE has a time period of one horizontal cycle 1H.

[0158] The host system can be a television system, a tablet computer, a laptop computer, a navigation system, a personal computer (PC), a home theater system, a mobile device, a wearable device, or a vehicle system. The host system can scale the image signal from the video source to match the resolution of the display panel 100 and transmit the obtained image signal and timing signals to the timing controller 130.

[0159] In the low-speed driving mode, compared with the normal driving mode, the timing controller 130 reduces the frequency of the frame rate at which pixel data is written to the pixels. For example, in the normal driving mode, the data refresh frame frequency for writing pixel data to the pixels can occur at a refresh rate of 60 Hz or higher, such as 60 Hz, 120 Hz, or 144 Hz; in the low-speed driving mode, the data refresh frame DRF can occur at a refresh rate lower than the frequency in the normal driving mode. The timing controller 130 can reduce the driving frequency of the display panel driver by reducing the frame frequency to between 1 Hz and 30 Hz, thereby reducing the refresh rate of the pixels in the low-speed driving mode.

[0160] Based on the timing signals Vsync, Hsync, and DE received from the host system, the timing controller 130 generates a data timing control signal for controlling the operation timing of the data driver 110, a control signal for controlling the operation timing of the demultiplexer array 112, and a gate control signal for controlling the operation timing of the gate driver 120. The timing controller 130 controls the operation timing of the display panel driver to synchronize the data driver 110, the demultiplexer array 112, the touch sensor driver, and the gate driver 120 with each other.

[0161] The gate timing control signal generated by the timing controller 130 may be input to the shift registers 121, 122, and 123 of the gate driver 120 through a level shifter (not shown). The level shifter may receive the gate timing control signal, generate a start pulse and a shift clock, and supply the start pulse and the shift clock to the shift registers 121, 122, and 123.

[0162] Due to device characteristic deviations and process deviations in the manufacturing process of the display panel 100, the electrical characteristics of the driving elements may vary for pixels, and the variations increase as the driving time of the pixels increases. To compensate for the deviations between the electrical characteristics of the driving elements of the pixels, an internal compensation technique or an external compensation technique may be applied to the organic light-emitting display device. In the internal compensation technique, the threshold voltage of the driving element of each sub-pixel is sampled using an internal compensation circuit of each pixel circuit, and the gate-source voltage Vgs of the driving element is compensated by the threshold voltage. In the external compensation technique, the current or voltage of the driving element that changes based on the electrical characteristics of the driving element is sensed in real time using an external compensation circuit. In the external compensation technique, the pixel data (digital data) of the input image is modified based on the electrical characteristic deviations (or changes) of the driving elements sensed in pixel units to compensate for the electrical characteristic deviations (or changes) of the driving elements of each pixel in real time. The display panel driver may drive the pixels using the external compensation technique and / or the internal compensation technique.

[0163] Figure 13 is a circuit diagram of a pixel circuit according to an embodiment of the present invention. The pixel circuit of the present invention may be implemented as a pixel circuit having an internal compensation circuit, as Figure 13 shown, but is not limited thereto.

[0164] Referring to Figure 13 , the pixel circuit includes a light-emitting element EL, a driving element DT, first to fifth switching elements M1 to M5, and a capacitor Cst. The driving element DT and the switching elements M1 to M5 may be implemented together as an n-channel oxide TFT.

[0165] The light-emitting element EL may include an anode, a cathode, and an organic compound layer connected between the anode and the cathode. The organic compound layer may include a hole injection layer (HIL), a hole transport layer (HTL), a light-emitting layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL), but is not limited thereto. When a voltage is applied to the anode and the cathode, holes passing through the HTL and electrons passing through the ETL move to the EML, thereby generating excitons, and thus visible light is emitted from the EML. The OLED used as the light-emitting element EL may have a tandem structure in which a plurality of light-emitting layers are stacked. The tandem structure of the OLED may improve the brightness and lifetime of the pixel.

[0166] The driving element DT generates a current for driving the light-emitting element EL according to the gate-source voltage Vgs. The driving element DT includes a gate connected to the first node DRG, a first electrode connected to the second node DRD, and a second electrode connected to the third node DRS. The capacitor Cst may be connected between the first node DRG and the anode of the light-emitting element EL.

[0167] The first switching element M1 includes a gate to which the n-th scan pulse SCAN(n) is applied, a first electrode connected to the first node DRG, and a second electrode connected to the second node DRD. The first switching element M1 is turned on by the gate conduction voltage of the n-th scan pulse SCAN(n) to connect the first node DRG and the second node DRD, thereby connecting the electrodes of the driving element DT in a diode-connected structure.

[0168] The second switching element M2 includes a gate to which the n-th scan pulse SCAN(n) is applied, a first electrode connected to the third node DRS, and a second electrode connected to the data line to which the data voltage Vdata is applied. The second switching element M2 is turned on by the gate conduction voltage of the n-th scan pulse SCAN(n) to supply the data voltage Vdata to the third node DRS.

[0169] The third switching element M3 includes a gate to which the first EM pulse EM1(n) is applied, a first electrode to which the pixel driving voltage ELVDD is applied, and a second electrode connected to the second node DRD. The third switching element M3 is turned on by the gate conduction voltage of the first EM pulse EM1(n) to supply the pixel driving voltage ELVDD to the second node DRD.

[0170] The fourth switching element M4 includes a gate to which the second EM pulse EM2(n) is applied, a first electrode connected to the third node DRS, and a second electrode connected to the anode of the light-emitting element EL. The fourth switching element M4 is turned on by the gate conduction voltage of the second EM pulse EM2(n) to connect the third node DRS to the anode of the light-emitting element EL.

[0171] The fifth switching element M5 includes a gate to which the (n - 1)-th scan pulse SCAN(n - 1) is applied, a first electrode connected to a power supply node to which an initialization voltage Vinit1 is applied, and a second electrode connected to an anode of the light-emitting element EL. The fifth switching element M5 is turned on by the gate-on voltage of the (n - 1)-th scan pulse SCAN(n - 1) to supply the initialization voltage Vinit1 to the anode of the light-emitting element EL.

[0172] According to the present invention, the first control node and the second control node can be alternately controlled to serve as a pull-up control node and a pull-down control node, or two pull-up control nodes can be alternately activated to achieve a narrow border of the display device and reduce stress on buffer transistors of the gate driving circuit.

[0173] The effects of the present invention are not limited thereto, and other effects not described herein can be clearly understood by those of ordinary skill in the art from the appended claims.

[0174] The objects to be achieved by the present invention as described above, the means for achieving these objects, and the effects of the present invention do not specify the essential features of the claims, and thus the scope of the claims is not limited to these specific descriptions of the present invention.

[0175] Although the embodiments of the present invention have been described in more detail with reference to the accompanying drawings, the present invention is not limited thereto, and the present invention can be implemented in many different forms without departing from the technical concept of the present invention. Therefore, the embodiments disclosed in the present invention are provided for illustrative purposes only, and these embodiments are not intended to limit the technical concept of the present invention. The scope of the technical concept of the present invention is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all respects and do not limit the present invention. The protection scope of the present invention should be interpreted based on the appended claims, and all technical concepts within the equivalent scope should be interpreted as falling within the scope of the present invention.

Claims

1. A gate driving circuit, comprising: A plurality of signal transmitters configured to charge or discharge a first control node and a second control node, wherein a start signal and a shift clock are input to the plurality of signal transmitters; And A plurality of first buffers, each first buffer being connected to one of the plurality of signal transmitters, Wherein each first buffer comprises: A first transistor configured to be driven by the voltage of the first control node; and A second transistor configured to be driven by the voltage of the second control node and connected to the first transistor, wherein there is a first output node for outputting a gate pulse between the first transistor and the second transistor, Wherein the plurality of signal transmitters comprises: A first controller configured to: control the first control node to serve as a pull-up control node for turning on the first transistor when an activation clock is input to the first controller in a first unit time, and disable it when an inactivation clock is input to the first controller in a second unit time; and A second controller configured to: control the second control node to serve as a pull-up control node for turning on the second transistor when the activation clock is input to the second controller in the second unit time, and disable it when the inactivation clock is input to the second controller in the first unit time, Wherein the first transistor comprises a gate connected to the first control node, a first electrode connected to a first power node, and a second electrode connected to the first output node, The second transistor comprises a gate connected to the second control node, a first electrode connected to the first output node, and a second electrode connected to a second power node, Wherein the voltages applied to the first power node and the second power node are switched between a gate driving voltage and a gate reference voltage at a predetermined time interval.

2. The gate driving circuit according to claim 1, further comprising a plurality of second buffers, each second buffer being connected to one of the plurality of signal transmitters, Wherein each second buffer comprises: A third transistor configured to be driven by the voltage of the first control node; And A fourth transistor configured to be driven by the voltage of the second control node and connected to the third transistor, wherein there is a second output node for outputting a carry pulse between the third transistor and the fourth transistor, Wherein in at least one of the first buffers, the power supply voltages applied to the first transistor and the second transistor are periodically switched, Wherein in at least one of the second buffers, the power supply voltages applied to the third transistor and the fourth transistor are periodically switched.

3. The gate driving circuit according to claim 1, wherein the gate driving voltage is applied to the first power node in the first unit time, and the gate reference voltage is applied to the first power node in the second unit time, The gate reference voltage is applied to the second power supply node in the first unit time, and the gate driving voltage is applied to the second power supply node in the second unit time. In the first unit time, the first transistor serves as a pull-up transistor and the second transistor serves as a pull-down transistor. In the second unit time, the second transistor serves as a pull-up transistor and the first transistor serves as a pull-down transistor.

4. The gate driving circuit according to claim 1, wherein the activation clock includes a plurality of pulses that swing between a high voltage and a low voltage during a unit time. The inactivation clock remains at the low voltage during the unit time.

5. The gate driving circuit according to claim 4, wherein the first controller includes: A first Q logic generation unit configured to control the first control node to serve as the pull-up control node by charging the first control node in the first unit time. And A first QB logic generation unit configured to control the second control node to serve as the pull-down control node by charging the second control node when discharging the first control node in the first unit time. The second controller includes: A second Q logic generation unit configured to control the second control node to serve as the pull-up control node by charging the second control node in the second unit time. And A second QB logic generation unit configured to control the first control node to serve as the pull-down control node by charging the first control node when discharging the second control node in the second unit time.

6. The gate driving circuit according to claim 5, wherein the first Q logic generation unit includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The fifth transistor includes a gate connected to the first CLK node, a first electrode connected to the carry signal node, and a second electrode connected to the first buffer node. The activation clock is applied to the first CLK node in the first unit time and the inactivation clock is applied to the first CLK node in the second unit time, and a carry pulse from a previous signal transmitter is input to the carry signal node. The sixth transistor includes a gate connected to the first CLK node, a first electrode connected to the first buffer node, and a second electrode connected to the first control node. The seventh transistor includes a gate connected to the first control node, a first electrode connected to the fifth power supply node, and a second electrode connected to the first buffer node. The gate driving voltage is applied to the fifth power supply node in the first unit time and the gate reference voltage is applied to the fifth power supply node in the second unit time. The eighth transistor includes a gate connected to the second buffer node, a first electrode connected to the sixth power supply node, and a second electrode connected to the first control node, wherein the gate reference voltage is applied to the sixth power supply node. The first QB logic generation unit includes a ninth transistor, a tenth transistor, and an eleventh transistor. The ninth transistor includes a gate connected to the second control node of the previous signal transmitter, a first electrode connected to the seventh power supply node, and a second electrode connected to the gate of the eleventh transistor, wherein the gate drive voltage is applied to the seventh power supply node in the first unit time and the gate reference voltage is applied to the seventh power supply node in the second unit time. The tenth transistor includes a gate connected to the first buffer node, a first electrode connected to the gate of the eleventh transistor, and a second electrode connected to the tenth power supply node, wherein the gate reference voltage is applied to the tenth power supply node. The eleventh transistor includes a gate connected to the second electrode of the ninth transistor and the first electrode of the tenth transistor, a first electrode connected to the eleventh power supply node, and a second electrode connected to the second control node, wherein the gate drive voltage is applied to the eleventh power supply node.

7. The gate driving circuit according to claim 6, wherein the second Q logic generation unit includes a twelfth transistor, a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor. The twelfth transistor includes a gate connected to the second CLK node, a first electrode connected to the carry signal node, and a second electrode connected to the second buffer node, wherein the inactive clock is input to the second CLK node in the first unit time and the active clock is input to the second CLK node in the second unit time. The thirteenth transistor includes a gate connected to the second CLK node, a first electrode connected to the second buffer node, and a second electrode connected to the second control node. The fourteenth transistor includes a gate connected to the second control node, a first electrode connected to the twelfth power supply node, and a second electrode connected to the second buffer node, wherein the gate reference voltage is applied to the twelfth power supply node in the first unit time and the gate drive voltage is applied to the twelfth power supply node in the second unit time. The fifteenth transistor includes a gate connected to the first buffer node, a first electrode connected to the sixth power supply node, and a second electrode connected to the second control node. The second QB logic generation unit includes a sixteenth transistor, a seventeenth transistor, and an eighteenth transistor. The sixteenth transistor includes a gate connected to the first control node of the foregoing signal transmitter, a first electrode connected to the thirteenth power supply node, and a second electrode connected to the gate of the eighteenth transistor, wherein the gate reference voltage is applied to the thirteenth power supply node in the first unit time and the gate drive voltage is applied to the thirteenth power supply node in the second unit time. The seventeenth transistor includes a gate connected to the second buffer node, a first electrode connected to the gate of the eighteenth transistor, and a second electrode connected to the tenth power supply node. The eighteenth transistor includes a gate connected to the second electrode of the sixteenth transistor and the first electrode of the seventeenth transistor, a first electrode connected to the eleventh power supply node, and a second electrode connected to the first control node.

8. The gate drive circuit according to claim 1, wherein the first unit time is an odd unit time and the second unit time is an even unit time.

9. The gate drive circuit according to claim 1, wherein a third capacitor is connected between the gate of the first transistor and the second electrode of the first transistor, and a fourth capacitor is connected between the gate of the second transistor and the first electrode of the second transistor.

10. The gate drive circuit according to claim 6, wherein a first capacitor is connected between the gate of the eleventh transistor and the second electrode of the eleventh transistor.

11. The gate drive circuit according to claim 7, wherein a second capacitor is connected between the gate of the eighteenth transistor and the second electrode of the eighteenth transistor.

12. A gate drive circuit, comprising: a plurality of signal transmitters configured to charge or discharge a first pull-up control node, a second pull-up control node, and a pull-down control node, wherein a start signal and a shift clock are input to the plurality of signal transmitters; and a plurality of first buffers, each first buffer connected to one of the plurality of signal transmitters, wherein each first buffer includes: a 1-1 pull-up transistor configured to be driven by the voltage of the first pull-up control node; a 1-2 pull-up transistor configured to be driven by the voltage of the second pull-up control node; and a first pull-down transistor configured to be driven by the voltage of the pull-down control node, the plurality of signal transmitters includes: a first Q logic generation unit configured to: charge the first pull-up control node when an activation clock is input to the first Q logic generation unit in a first pull-up time to turn on the 1-1 pull-up transistor, and disable when an inactivation clock is input to the first Q logic generation unit in a second pull-up time; A second Q logic generation unit, the second Q logic generation unit being configured to: charge the second pull-up control node when the activation clock is input to the second Q logic generation unit at the second pull-up time to turn on the 1-2 pull-up transistor, and disable when the inactivation clock is input to the second Q logic generation unit at the first pull-up time; and A QB logic generation unit, the QB logic generation unit being configured to: charge the pull-down control node during a pull-down time when the first pull-up control node and the second pull-up control node are discharged to turn on the first pull-down transistor.

13. The gate drive circuit according to claim 12, further comprising a plurality of second buffers, each second buffer being connected to one of the plurality of signal transmitters, wherein each second buffer includes: A 3-1 pull-up transistor configured to be driven by the voltage of the first pull-up control node; A 3-2 pull-up transistor configured to be driven by the voltage of the second pull-up control node; And A second pull-down transistor configured to be controlled by the voltage of the pull-down control node.

14. The gate drive circuit according to claim 13, wherein the first Q logic generation unit includes a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor, wherein the fourth transistor includes a gate connected to a first CLK node, a first electrode connected to a carry signal node, and a second electrode connected to a first buffer node, wherein the activation clock is applied to the first CLK node at the first pull-up time and the inactivation clock is applied to the first CLK node at the second pull-up time, and a carry pulse from a previous signal transmitter is input to the carry signal node, The fifth transistor includes a gate connected to the first CLK node, a first electrode connected to the first buffer node, and a second electrode connected to the first pull-up control node, The sixth transistor includes a gate connected to the first pull-up control node, a first electrode connected to a third power supply node, and a second electrode connected to the first buffer node, wherein a gate drive voltage is applied to the third power supply node, The seventh transistor includes a gate connected to the first buffer node and a second buffer node, a first electrode connected to the pull-down control node, and a second electrode connected to a fourth power supply node, wherein a gate reference voltage is applied to the fourth power supply node, wherein the second Q logic generation unit includes an eighth transistor, a ninth transistor, and a tenth transistor, wherein the eighth transistor includes a gate connected to a second CLK node, a first electrode connected to the carry signal node, and a second electrode connected to the second buffer node, wherein the activation clock is input to the second CLK node at the second pull-up time and the inactivation clock is input to the second CLK node at the first pull-up time, The ninth transistor includes a gate connected to the second CLK node, a first electrode connected to the second buffer node, and a second electrode connected to the second pull-up control node. The tenth transistor includes a gate connected to the second pull-up control node, a first electrode connected to the third power supply node, and a second electrode connected to the second buffer node.

15. The gate driving circuit according to claim 14, wherein the QB logic generating unit includes an eleventh transistor, a twelfth transistor, a thirteenth transistor, and a fourteenth transistor. The eleventh transistor includes a gate connected to the pull-down control node of the previous signal transmitter, a first electrode connected to the fifth power supply node, and a second electrode connected to the gate of the fourteenth transistor, wherein the gate driving voltage is applied to the fifth power supply node. The twelfth transistor includes a gate connected to the first buffer node, a first electrode connected to the gate of the fourteenth transistor, and a second electrode connected to the sixth power supply node, wherein the gate reference voltage is applied to the sixth power supply node. The thirteenth transistor includes a gate connected to the second buffer node, a first electrode connected to the gate of the fourteenth transistor, and a second electrode connected to the sixth power supply node. The fourteenth transistor includes: A gate connected to the second electrode of the eleventh transistor, the first electrodes of the twelfth transistor and the thirteenth transistor. A first electrode connected to the fifth power supply node. And a second electrode connected to the pull-down control node.

16. The gate driving circuit according to claim 13, wherein the 1-1 pull-up transistor includes a gate connected to the first pull-up control node, a first electrode connected to the first power supply node, and a second electrode connected to the first output node. The 1-2 pull-up transistor includes a gate connected to the second pull-up control node, a first electrode connected to the first power supply node, and a second electrode connected to the first output node. The first pull-down transistor includes a gate connected to the pull-down control node, a first electrode connected to the first output node, and a second electrode connected to the second power supply node. Wherein the gate driving voltage is applied to the first power supply node, and the gate reference voltage is applied to the second power supply node.

17. The gate driving circuit according to claim 16, wherein a second capacitor is connected between the second electrode of the 1-1 pull-up transistor and the first output node, and a third capacitor is connected between the gate of the 1-2 pull-up transistor and the second electrode of the 1-2 pull-up transistor.

18. The gate driving circuit according to claim 15, wherein a first capacitor is connected between the gate of the fourteenth transistor and the second electrode of the fourteenth transistor.

19. The gate driving circuit according to claim 16, wherein the 3-1 pull-up transistor includes a gate connected to the first pull-up control node, a first electrode connected to the first power supply node, and a second electrode connected to the second output node. The 3-2 pull-up transistor includes a gate connected to the second pull-up control node, a first electrode connected to the first power supply node, and a second electrode connected to the second output node. The second pull-down transistor includes a gate connected to the pull-down control node, a first electrode connected to the second output node, and a second electrode connected to the second power supply node.

20. A display device, comprising: A display panel, on which a plurality of data lines to which data voltages are applied, a plurality of gate lines intersecting with the plurality of data lines and to which gate signals are applied, and a plurality of pixels connected to a plurality of power supply lines are provided; A data driving circuit configured to receive pixel data and output the data voltage; And A gate driving circuit configured to output the gate signal using a shift register, wherein the shift register of the gate driving circuit includes: A plurality of signal transmitters configured to charge or discharge a first control node and a second control node, wherein a start signal and a shift clock are input to the signal transmitters; and A plurality of buffers, each buffer being connected to one of the plurality of signal transmitters, wherein each buffer includes: A first transistor configured to be driven by the voltage of the first control node; and A second transistor configured to be driven by the voltage of the second control node and connected to the first transistor, wherein a first output node is provided between the first transistor and the second transistor, wherein the plurality of signal transmitters includes: A first controller configured to: control the first control node to serve as a pull-up control node for turning on the first transistor when an activation clock is input to the first controller in a first unit time, and disable it when an inactivation clock is input to the first controller in a second unit time; and A second controller configured to: control the second control node to serve as a pull-up control node for turning on the second transistor when the activation clock is input to the second controller in the second unit time, and disable it when the inactivation clock is input to the second controller in the first unit time, wherein the first transistor includes a gate connected to the first control node, a first electrode connected to the first power supply node, and a second electrode connected to the first output node, The second transistor includes a gate connected to the second control node, a first electrode connected to the first output node, and a second electrode connected to the second power supply node, wherein the voltages applied to the first power supply node and the second power supply node are switched between a gate driving voltage and a gate reference voltage at a predetermined time interval.

21. A display device, comprising: A display panel, on which a plurality of data lines to which data voltages are applied, a plurality of gate lines intersecting the plurality of data lines and to which gate signals are applied, and a plurality of pixels connected to a plurality of power supply lines are provided; A data driving circuit configured to receive pixel data and output the data voltage; And A gate driving circuit configured to output the gate signal using a shift register, Wherein the shift register of the gate driving circuit includes: A plurality of signal transmitters configured to charge or discharge a first pull-up control node, a second pull-up control node, and a pull-down control node, wherein a start signal and a shift clock are input to the plurality of signal transmitters; and A plurality of first buffers, each first buffer being connected to one of the plurality of signal transmitters, Wherein each first buffer includes: A 1-1 pull-up transistor configured to be driven by the voltage of the first pull-up control node; A 1-2 pull-up transistor configured to be driven by the voltage of the second pull-up control node; and A first pull-down transistor configured to be driven by the voltage of the pull-down control node, The plurality of signal transmitters include: A first Q logic generation unit configured to charge the first pull-up control node when an activation clock is input to the first Q logic generation unit at a first pull-up time to turn on the 1-1 pull-up transistor, and to be disabled when an inactivation clock is input to the first Q logic generation unit at a second pull-up time; A second Q logic generation unit configured to charge the second pull-up control node when the activation clock is input to the second Q logic generation unit at the second pull-up time to turn on the 1-2 pull-up transistor, and to be disabled when the inactivation clock is input to the second Q logic generation unit at the first pull-up time; and A QB logic generation unit configured to charge the pull-down control node during a pull-down time when the first pull-up control node and the second pull-up control node are discharged to turn on the first pull-down transistor.

22. A display device, including the gate driving circuit according to any one of claims 1-19.

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