A method to improve STI chemical mechanical polishing-induced pitting

Abstract

This invention provides a method for improving depressions caused by STI chemical mechanical polishing (CMP). The method involves providing a stack comprising, from bottom to top, a silicon layer, a silicon nitride layer, and an amorphous silicon layer. The stack is etched to form multiple spaced grooves with the bottom layer located within the silicon layer. A dielectric layer is deposited to fill the grooves, while the upper surface of the amorphous silicon layer is covered by the dielectric layer. The dielectric layer is then chemically mechanically polished until the upper surface of the amorphous silicon layer is exposed. The dielectric layer is further polished and the amorphous silicon layer is removed until the upper surface of the silicon nitride layer is exposed, thus planarizing the upper surface of the dielectric layer. This invention uses an amorphous silicon layer as a buffer layer during the STI filler polishing process. By utilizing the fact that the polishing rate of the amorphous silicon is greater than that of the filler, it can effectively improve the formation of depressions in the STI filler during CMP, resulting in a smoother surface after polishing.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for improving depressions caused by STI chemical mechanical polishing. Background Technology

[0002] Shallow trench isolation (STI) is a key technology for 40 / 28nm processes. Trench oxide CMP depressions are typically observed after CMP, especially for wide trenches. This leads to a degradation in device performance.

[0003] Therefore, a new method is needed to solve the above problems. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method to improve the pitting caused by STI chemical mechanical polishing, which solves the problem of pitting of groove oxides caused by CMP in the prior art.

[0005] To achieve the above and other related objectives, the present invention provides a method for improving depressions caused by STI chemical mechanical polishing, comprising at least:

[0006] Step 1: Provide a stack, the stack comprising a silicon layer, a silicon nitride layer, and an amorphous silicon layer stacked sequentially from bottom to top;

[0007] Step 2: Etch the stacked layers to form multiple spaced grooves with their bottoms located in the silicon layer;

[0008] Step 3: Deposit a dielectric layer to fill the groove, while the upper surface of the amorphous silicon layer is covered by the dielectric layer;

[0009] Step 4: Perform chemical mechanical polishing on the dielectric layer until the upper surface of the amorphous silicon layer is exposed;

[0010] Step 5: Continue grinding the dielectric layer and remove the amorphous silicon layer until the upper surface of the silicon nitride layer is exposed, so as to planarize the upper surface of the dielectric layer.

[0011] Preferably, the stacked layer in step one further includes a silicon oxide layer between the silicon layer and the silicon nitride layer.

[0012] Preferably, the stacked layer in step one further includes an APF layer and an NF DARC layer stacked on the amorphous silicon layer.

[0013] Preferably, the thickness of the silicon nitride layer in step one is 550 angstroms.

[0014] Preferably, the thickness of the amorphous silicon layer is 50 angstroms.

[0015] Preferably, the thickness of the APF layer in step one is 2000 angstroms.

[0016] Preferably, the thickness of the NF DARC layer in step one is 250 angstroms.

[0017] Preferably, during the etching process of the stack in step two, the APF layer and the NF DARC layer are removed, exposing the upper surface of the amorphous silicon.

[0018] Preferably, before depositing the dielectric layer in step three, a silicon oxide layer is formed on the surface of the groove.

[0019] Preferably, the dielectric layer in step three is a dielectric layer filled under the HARP process.

[0020] Preferably, the dielectric layer in step three is silicon dioxide.

[0021] Preferably, during the chemical mechanical polishing process in step five, the polishing rate of the amorphous silicon is 260 Å / min; and the polishing rate of the dielectric layer is 90 Å / min.

[0022] Preferably, this method is applicable to STI process technology nodes of 40nm or 28nm.

[0023] As described above, the method of the present invention for improving the depressions caused by STI chemical mechanical polishing has the following beneficial effects: the present invention uses an amorphous silicon layer as a buffer layer during the polishing process of STI filler, and utilizes the fact that the polishing rate of amorphous silicon is greater than that of filler, thereby effectively improving the formation of depressions in STI filler during CMP, making the polished surface flatter. Attached Figure Description

[0024] Figure 1 The diagram shown is a cross-sectional view of the stacked structure in this invention.

[0025] Figure 2 The diagram shows a cross-sectional structure of the groove after the medium layer is filled in the groove according to the present invention.

[0026] Figure 3 The diagram shows a cross-sectional view of the amorphous silicon layer exposed by chemical mechanical polishing in this invention.

[0027] Figure 4 The diagram shows a cross-sectional structure of the dielectric layer in the groove after grinding and removing the amorphous silicon layer in this invention, which flattens the upper surface of the dielectric layer in the groove.

[0028] Figure 5 The diagram shows a flowchart of the method for improving STI chemical mechanical polishing-induced depressions according to the present invention. Detailed Implementation

[0029] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0030] Please refer to the image. Figures 1 to 5 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0031] This invention provides a method for improving depressions caused by STI chemical mechanical polishing, such as... Figure 5 As shown, Figure 5 The flowchart shown is a method for improving STI (chemical mechanical polishing)-induced indentations according to the present invention, which includes at least the following steps:

[0032] Step 1: Provide a stack, the stack comprising a silicon layer, a silicon nitride layer, and an amorphous silicon layer stacked sequentially from bottom to top;

[0033] like Figure 1 As shown, Figure 1 The diagram shown is a cross-sectional view of the stacked structure in this invention. Step one provides the stacked structure, which includes a silicon layer 01, a silicon nitride layer 02, and an amorphous silicon layer 03 stacked sequentially from bottom to top.

[0034] Furthermore, in step one of this embodiment, a silicon oxide layer is also provided between the silicon layer and the silicon nitride layer in the stacked layer.

[0035] Furthermore, in step one of this embodiment, the stacked layer also includes an APF layer 04 and an NF DARC layer 05 stacked on the amorphous silicon layer.

[0036] Furthermore, in this embodiment, the thickness of the silicon nitride layer O2 in step one is 550 angstroms.

[0037] Furthermore, in this embodiment, the thickness of the amorphous silicon layer 03 in step one is 50 angstroms.

[0038] Furthermore, in this embodiment, the thickness of the APF layer 05 in step one is 2000 angstroms.

[0039] Furthermore, in this embodiment, the thickness of the NF DARC layer 05 in step one is 250 angstroms.

[0040] Step 2: Etch the stacked layers to form multiple spaced grooves with their bottoms located in the silicon layer;

[0041] like Figure 2 As shown, Figure 2 The diagram shows a cross-sectional structure after the dielectric layer is filled in the grooves in this invention. In step two, the stacked layers are etched to form multiple mutually spaced grooves with their bottoms located in the silicon layer.

[0042] Furthermore, in step two of this embodiment, during the etching process of the stacked layers, the APF layer and the NF DARC layer are removed, exposing the upper surface of the amorphous silicon.

[0043] Step 3: Deposit a dielectric layer to fill the groove, while the upper surface of the amorphous silicon layer is covered by the dielectric layer; as shown Figure 2 As shown, in step three, a dielectric layer 04 is deposited to fill the groove, while the upper surface of the amorphous silicon layer 03 is covered by the dielectric layer.

[0044] In a further step of this invention, before depositing the dielectric layer 04 in step three of this embodiment, a silicon oxide layer is formed on the surface of the groove.

[0045] Furthermore, in this embodiment, the dielectric layer in step three is a dielectric layer filled using the HARP process. That is, the HARP process is a high aspect ratio process, under which the dielectric layer is filled into the groove.

[0046] Furthermore, in this embodiment, the dielectric layer in step three is silicon dioxide.

[0047] Step 4: Perform chemical mechanical polishing on the dielectric layer until the upper surface of the amorphous silicon layer is exposed; for example... Figure 3 As shown, Figure 3 The diagram shows a cross-sectional structure of the amorphous silicon layer exposed by chemical mechanical polishing in this invention. Step four involves chemical mechanical polishing of the dielectric layer until the upper surface of the amorphous silicon layer 03 is exposed.

[0048] Step 5: Continue grinding the dielectric layer and removing the amorphous silicon layer until the upper surface of the silicon nitride layer is exposed, thus planarizing the upper surface of the dielectric layer. Figure 4 As shown, Figure 4The diagram shows a cross-sectional view of the dielectric layer in the groove after grinding and removing the amorphous silicon layer in this invention, thus planarizing the upper surface of the dielectric layer 04. Step five continues grinding the dielectric layer 04 and removing the amorphous silicon layer until the upper surface of the silicon nitride layer 02 is exposed, thereby planarizing the upper surface of the dielectric layer 04.

[0049] Furthermore, in step five of this embodiment, during the chemical mechanical polishing process, the polishing rate of the amorphous silicon is 260 Å / min; and the polishing rate of the dielectric layer is 90 Å / min.

[0050] Furthermore, the method of this embodiment is applicable to STI process technology nodes of 40nm or 28nm.

[0051] In summary, this invention uses an amorphous silicon layer as a buffer layer during the STI filler polishing process. By utilizing the fact that the polishing rate of the amorphous silicon is greater than that of the filler, it effectively reduces the formation of depressions in the STI filler during CMP, resulting in a smoother surface after polishing. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0052] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for improving depressions caused by STI chemical mechanical polishing, characterized in that, At least including: Step 1: Provide a stack, the stack comprising a silicon layer, a silicon nitride layer, and an amorphous silicon layer stacked sequentially from bottom to top; Step 2: Etch the stacked layers to form multiple spaced grooves with their bottoms located in the silicon layer; Step 3: Deposit a dielectric layer to fill the groove, while the upper surface of the amorphous silicon layer is covered by the dielectric layer; Step 4: Perform chemical mechanical polishing on the dielectric layer until the upper surface of the amorphous silicon layer is exposed; Step 5: Continue grinding the dielectric layer and remove the amorphous silicon layer until the upper surface of the silicon nitride layer is exposed, so that the upper surface of the dielectric layer is planarized; during the chemical mechanical polishing process, the grinding rate of the amorphous silicon is 260 Å / min; the grinding rate of the dielectric layer is 90 Å / min.

2. The method for improving STI-induced indentations according to claim 1, characterized in that: In step one, a silicon oxide layer is also provided between the silicon layer and the silicon nitride layer in the stacked layer.

3. The method for improving STI-induced indentations according to claim 2, characterized in that: The stacked layer in step one also includes an APF layer and an NF DARC layer stacked on the amorphous silicon layer.

4. The method for improving STI-induced indentations according to claim 3, characterized in that: The thickness of the silicon nitride layer in step one is 550 angstroms.

5. The method for improving STI-induced indentations according to claim 1, characterized in that: The thickness of the amorphous silicon layer in step one is 50 angstroms.

6. The method for improving STI-induced indentations according to claim 3, characterized in that: The thickness of the APF layer in step one is 2000 angstroms.

7. The method for improving STI-induced indentations according to claim 3, characterized in that: The thickness of the NF DARC layer in step one is 250 angstroms.

8. The method for improving STI-induced indentations according to claim 3, characterized in that: During the etching process of the stack in step two, the APF layer and the NF DARC layer are removed, exposing the upper surface of the amorphous silicon.

9. The method for improving STI-induced indentations according to claim 3, characterized in that: Before depositing the dielectric layer in step three, a silicon oxide layer is formed on the surface of the groove.

10. The method for improving STI-induced indentations according to claim 3, characterized in that: The dielectric layer mentioned in step three is a dielectric layer filled under the HARP process.

11. The method for improving STI-induced depressions according to claim 10, characterized in that: The dielectric layer in step three is silicon dioxide.

12. The method for improving STI-induced depressions according to claim 1, characterized in that: This method is applicable to STI process technology nodes of 40nm or 28nm.

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