Display device

Abstract

A display device capable of realizing appropriate display characteristics is provided. The display device includes a substrate, a plurality of first light emitting elements and a plurality of second light emitting elements provided in a display region of the substrate, a first lens having a first diameter in a plan view observed from a direction perpendicular to the substrate, which is provided so as to overlap each of the plurality of first light emitting elements, and a second lens having a second diameter smaller than the first diameter in the plan view observed from the direction perpendicular to the substrate, which is provided so as to overlap each of the plurality of second light emitting elements.

Description

TECHNICAL FIELD

[0001] The present application relates to a display device. BACKGROUND

[0002] Currently, attention is paid to a light emitting diode of a micro size (micro LED) used as a display element (for example, refer to Patent Literature 1). In Patent Literature 1, a technology of changing an emission light distribution in a display region by tilting a light emitting element to be mounted on an array substrate is described. In Patent Literature 2, a plurality of micro lenses arranged on a prescribed curved surface opposite to each pixel of a display device are provided.

[0003] PRIOR ART DOCUMENTS

[0004] Patent Literature 1: JP Patent Publication No. 2021-56380

[0005] Patent Literature 2: JP Patent Publication No. 2007-86500 SUMMARY

[0006] In a display using a light emitting diode of a micro size, appropriate display characteristics such as a high viewing angle and a high brightness are required. In Patent Literature 1, it can be difficult to implement a process of transferring a light emitting element to an array substrate. In Patent Literature 2, since light emitted from a plurality of micro lenses is configured to be concentrated on an eye portion, a great brightness can be obtained in a front direction, but brightnesses other than the front direction can be reduced.

[0007] An object of the present application is to provide a display device capable of implementing appropriate display characteristics.

[0008] A display device of one aspect of the present application includes: a substrate; a plurality of first light emitting elements and a plurality of second light emitting elements provided in a display region of the substrate; a first lens having a first diameter in a plan view observed from a direction perpendicular to the substrate, which is provided to overlap with each of the plurality of first light emitting elements; and a second lens having a second diameter smaller than the first diameter in the plan view observed from the direction perpendicular to the substrate, which is provided to overlap with each of the plurality of second light emitting elements. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a plan view schematically showing a display device of the first embodiment.

[0010] Figure 2 is a plan view showing a plurality of pixels.

[0011] Figure 3 is a circuit diagram showing a pixel circuit.

[0012] Figure 4is Figure 2 a cross-sectional view of IV-IV'.

[0013] Figure 5 is a plan view schematically showing the first light emitting element, the first lens, the second light emitting element, and the second lens.

[0014] Figure 6 is a cross-sectional view schematically showing the first light emitting element, the first lens, the second light emitting element, and the second lens.

[0015] Figure 7 is a cross-sectional view schematically showing the first light emitting element, the first lens, the second light emitting element, and the second lens of the first modification of the first embodiment.

[0016] Figure 8 is a perspective view schematically showing an array substrate possessed by the display device of the second modification of the first embodiment.

[0017] Figure 9 is a plan view schematically showing the first light emitting element, the first lens, the second light emitting element, and the second lens possessed by one pixel of the display device of the second embodiment.

[0018] Figure 10 is a cross-sectional view schematically showing the first light emitting element, the first lens, the second light emitting element, and the second lens possessed by one pixel of the display device of the second embodiment.

[0019] Figure 11 is a circuit diagram showing a pixel circuit of the second embodiment.

[0020] Figure 12 is a plan view showing a pixel of the third modification of the second embodiment.

[0021] Figure 13 is a perspective view schematically showing the display device of the third embodiment.

[0022] In the drawings, the following signs are used:

[0023] 1, 1A, 1B, 1C, 1D, 1E display device

[0024] 2, 2A array substrate

[0025] 3, 3R, 3G, 3B light emitting element

[0026] 3-1, 3R-1, 3G-1, 3B-1 first light emitting element

[0027] 3-2, 3R-2, 3G-2, 3B-2 second light emitting element

[0028] 12 drive circuit

[0029] 21 substrate

[0030] 22 Opposed Cathode Electrodes

[0031] 23 Anode Connection Electrode

[0032] 24 Install electrodes

[0033] 25 opposing electrodes

[0034] 28 joint components

[0035] 31 semiconductor layers

[0036] 32 Cathode Electrode

[0037] 33 Anode electrode

[0038] 71, 71A First Lens

[0039] 72 Second Lens

[0040] 98 component insulating film

[0041] AA display area

[0042] AAs1, AAc1, AAd1 area 1

[0043] Region 2 of AAs2, AAc2, AAD2

[0044] GA surrounding area Detailed Implementation

[0045] Referring to the accompanying drawings, the embodiments for carrying out the present invention are described in detail. The invention is not limited by the content described in the following embodiments. Furthermore, the constituent elements described below include substantially the same constituent elements that are readily conceived by those skilled in the art. Moreover, the constituent elements described below can be appropriately combined. Furthermore, this disclosure is merely an example, and appropriate modifications that maintain the spirit of the invention and are readily conceived by those skilled in the art are naturally included within the scope of the invention. Additionally, to make the description clearer, the width, thickness, shape, etc., of various parts in the drawings are sometimes schematically shown compared to the actual form, but this is merely an example and does not limit the interpretation of the invention. Furthermore, in this specification and the drawings, the same reference numerals are used for the same elements as those described with respect to the already presented drawings, and detailed descriptions are sometimes appropriately omitted.

[0046] In the present specification and the scope of the patent, in the case where the form in which another structure is arranged on a certain structure is expressed as only "on", unless particularly limited, both the case where another structure is arranged directly on the certain structure and the case where another structure is arranged above the certain structure with another structure interposed are included.

[0047] (First Embodiment)

[0048] Figure 1 is a plan view schematically showing a display device of the first embodiment. As shown in Figure 1 , the display device 1 includes an array substrate 2, a pixel PX, a drive circuit 12, a drive IC (Integrated Circuit) 210, and a cathode wiring 60. The array substrate 2 is a drive circuit substrate for driving each pixel PX, and is also called a backplane or an active matrix substrate. The array substrate 2 has a substrate 21, a plurality of transistors, a plurality of capacitors, and various wirings, and the like.

[0049] As shown in Figure 1 , the display device 1 has a display region AA and a peripheral region GA. The display region AA is a region in which a plurality of pixels PX are arranged so as to overlap and display an image. The peripheral region GA is a region which does not overlap with the plurality of pixels PX, and is arranged outside the display region AA.

[0050] The plurality of pixels PX are arranged in the display region AA of the substrate 21 in a first direction Dx and a second direction Dy. Further, the first direction Dx and the second direction Dy are directions parallel with respect to the surface of the substrate 21. The first direction Dx is orthogonal to the second direction Dy. However, the first direction Dx can not be orthogonal to the second direction Dy but can intersect. A third direction Dz is a direction orthogonal to the first direction Dx and the second direction Dy. The third direction Dz corresponds to, for example, the normal direction of the substrate 21. Further, hereinafter, plan view means showing the positional relationship in the case of being observed from the third direction Dz.

[0051] In the display device 1 of the first embodiment, the display region AA includes a first region AAs1 and a plurality of second regions AAs2. The first region AAs1 is located at the central portion of the display region AA in the first direction Dx. The plurality of second regions AAs2 are located at the outer edge portion of the display region AA in the first direction Dx, and are provided along the edge extending in the second direction Dy of the display region AA. The first region AAs1 is provided between the plurality of second regions AAs2 in the first direction Dx. The display region AA is arranged in the order of the second region AAs2, the first region AAs1, and the second region AAs2 in the first direction Dx.

[0052] Further, Figure 1The configuration of the first region AAs1 and the second region AAs2 shown is merely an example, and can be appropriately changed according to display characteristics (viewing angle, luminance, and the like) required of the display device 1. For example, the second region AAs2 can be provided along one side of the display region AA, or can be provided so as to surround the first region AAs1 along four sides of the display region AA. In addition, in Figure 1 , only a part of the display region AA is shown as pixels PX, but a plurality of pixels PX are arranged in a matrix shape throughout the first region AAs1 and the second region AAs2.

[0053] The drive circuit 12 is a circuit that drives a plurality of gate lines (for example, a reset control signal line L5, an output control signal line L6, a pixel control signal line L7, an initialization control signal line L8 (refer to Figure 3 )) based on various control signals supplied via a wiring drawn from the drive IC 210. The drive circuit 12 sequentially or simultaneously selects a plurality of gate lines, and supplies a gate drive signal to the selected gate line. Thereby, the drive circuit 12 selects a plurality of pixels PX connected to the gate line.

[0054] The drive IC 210 is a circuit that controls display of the display device 1. A plurality of wirings (for example, an image signal line L2, a reset power supply line L3, and an initialization power supply line L4 (refer to Figure 3 )) are drawn from the drive IC 210 toward a plurality of pixels PX. The drive IC 210 is mounted on the COG (Chip On Glass) as the peripheral region GA of the substrate 21. However, the drive IC 210 can also be mounted on a flexible printed substrate or a rigid substrate connected to the peripheral region GA of the substrate 21.

[0055] The cathode wiring 60 is provided in the peripheral region GA of the substrate 21. The cathode wiring 60 is provided so as to surround a plurality of pixels PX of the display region AA and the drive circuit 12 of the peripheral region GA. The cathodes of a plurality of light emitting elements 3 are connected to the common cathode wiring 60, and are supplied with a fixed potential (for example, a ground potential). More specifically, the cathode electrode 32 (refer to Figure 4 ) of the light emitting element 3 is connected to the cathode wiring 60 via the opposing cathode electrode 22 (refer to Figure 4 ) formed in the array substrate 2.

[0056] Figure 2 is a plan view showing a plurality of pixels. As shown in Figure 2 , one pixel PX includes a plurality of sub-pixels 49. For example, the pixel PX has a sub-pixel 49R, a sub-pixel 49G, and a sub-pixel 49B. The sub-pixel 49R displays red as a primary color of a first color. The sub-pixel 49G displays green as a primary color of a second color. The sub-pixel 49B displays blue as a primary color of a third color. As shown in Figure 2As shown, in one pixel PX, the sub-pixel 49R and the sub-pixel 49B are arranged in the first direction Dx. In addition, the sub-pixel 49B and the sub-pixel 49G are arranged in the second direction Dy. Further, the first color, the second color, and the third color are each not limited to red, green, and blue, and an arbitrary color such as a complementary color can be selected. Hereinafter, in a case where it is not necessary to distinguish the sub-pixel 49R, the sub-pixel 49G, and the sub-pixel 49B, only the sub-pixel 49 is referred to.

[0057] The sub-pixel 49 has the light emitting element 3 and the anode connection electrode 23, respectively. The first lens 71 (or the second lens 72 (refer to Figure 5 )) is provided so as to overlap the light emitting element 3. The display device 1 emits different light from each of the light emitting elements 3R, 3G, and 3B in the sub-pixel 49R, the sub-pixel 49G, and the sub-pixel 49B, respectively, and thereby displays an image. The light emitting element 3 is an inorganic light emitting diode (LED: Light Emitting Diode) chip having a size of 3 μm or more and 300 μm or less in plan view, and is referred to as a micro LED. The display device 1 in which each pixel has a micro LED is also referred to as a micro LED display device. Further, the micro of the micro LED does not limit the size of the light emitting element 3.

[0058] Further, the detailed configuration of the light emitting element 3 and the first lens 71 will be described later. In addition, the plurality of light emitting elements 3 can emit different light of four or more colors. In addition, the arrangement of the plurality of sub-pixels 49 is not limited to Figure 2 the configuration shown. For example, the sub-pixel 49R can be adjacent to the sub-pixel 49G in the second direction Dy. In addition, the sub-pixel 49R, the sub-pixel 49G, and the sub-pixel 49B can be repeatedly arranged in the first direction Dx in this order.

[0059] Figure 3 is a circuit diagram showing a pixel circuit. Figure 3 A pixel circuit PICA provided in one sub-pixel 49 is shown, and the pixel circuit PICA is provided in each of the plurality of sub-pixels 49. As shown, Figure 3 the pixel circuit PICA includes the light emitting element 3, five transistors, and two capacitors. Specifically, the pixel circuit PICA includes a drive transistor DRT, an output transistor BCT, an initialization transistor IST, a pixel selection transistor SST, and a reset transistor RST. The drive transistor DRT, the output transistor BCT, the initialization transistor IST, the pixel selection transistor SST, and the reset transistor RST are each configured of an n-type TFT (Thin Film Transistor). In addition, the pixel circuit PICA includes a first capacitor Cs1 and a second capacitor Cs2.

[0060] The cathode (cathode electrode 32) of the light emitting element 3 is connected to the cathode power supply line L10, and the anode (anode electrode 33) of the light emitting element 3 is connected to the anode power supply line Ll via the anode connecting electrode 23, the drive transistor DRT, and the output transistor BCT, and the anode power supply line Ll is supplied with an anode power supply potential PVDD. The cathode power supply line L10 is supplied with a cathode power supply potential PVSS via the cathode wiring 60 and the cathode electrode 32. The anode power supply potential PVDD is a potential higher than the cathode power supply potential PVSS.

[0061] The anode power supply line Ll supplies the sub-pixel 49 with the anode power supply potential PVDD as a drive potential. Specifically, the light emitting element 3 is supplied with a forward current (drive current) by the potential difference (PVDD-PVSS) between the anode power supply potential PVDD and the cathode power supply potential PVSS, and emits light. That is, the anode power supply potential PVDD has a potential difference with respect to the cathode power supply potential PVSS that causes the light emitting element 3 to emit light. The anode electrode 33 of the light emitting element 3 is electrically connected to the anode connecting electrode 23, and the second capacitor Cs2 is formed between the anode connecting electrode 23 and the anode power supply line Ll.

[0062] The source electrode of the drive transistor DRT is connected to the anode electrode 33 of the light emitting element 3 via the anode connecting electrode 23, the drain electrode is connected to the source electrode of the output transistor BCT, and the gate electrode of the drive transistor DRT is connected to the first capacitor Csl, the drain electrode of the pixel selection transistor SST, and the drain electrode of the initialization transistor IST.

[0063] The gate electrode of the output transistor BCT is connected to the output control signal line L6, and the output control signal line L6 is supplied with the output control signal BG. The drain electrode of the output transistor BCT is connected to the anode power supply line Ll.

[0064] The source electrode of the initialization transistor IST is connected to the initialization power supply line L4, and the initialization power supply line L4 is supplied with the initialization potential Vini. The gate electrode of the initialization transistor IST is connected to the initialization control signal line L8, and the initialization control signal line L8 is supplied with the initialization control signal IG. That is, when the initialization transistor IST is turned on, the initialization power supply line L4 is connected to the gate electrode of the drive transistor DRT via the initialization transistor IST.

[0065] The source electrode of the pixel selection transistor SST is connected to the image signal line L2, and the image signal line L2 is supplied with the image signal Vsig. The pixel control signal line L7 is connected to the gate electrode of the pixel selection transistor SST. The pixel control signal line L7 is supplied with the pixel control signal SG.

[0066] The source electrode of the reset transistor RST is connected to the reset power supply line L3, and a reset power supply potential Vrst is supplied to the reset power supply line L3. The gate electrode of the reset transistor RST is connected to the reset control signal line L5, and a reset control signal RG is supplied to the reset control signal line L5. The drain electrode of the reset transistor RST is connected to the anode connection electrode 23 (the anode electrode 33 of the light emitting element 3) and the source electrode of the drive transistor DRT, and the voltage held by the first capacitor Cs1 and the second capacitor Cs2 is reset by the reset operation of the reset transistor RST.

[0067] The first capacitor Cs1 is formed between the drain electrode of the reset transistor RST and the gate electrode of the drive transistor DRT. The pixel circuit PICA can suppress the variation of the gate voltage due to the parasitic capacitance and the drain current of the drive transistor DRT, using the first capacitor Cs1 and the second capacitor Cs2.

[0068] Further, in the following description, the anode power supply line L1 and the cathode power supply line L10 are sometimes simply referred to as power supply lines. The image signal line L2, the reset power supply line L3, and the initialization power supply line L4 are sometimes referred to as signal lines. The reset control signal line L5, the output control signal line L6, the pixel control signal line L7, and the initialization control signal line L8 are sometimes referred to as gate lines.

[0069] The gate electrode of the drive transistor DRT is supplied with a potential corresponding to the image signal Vsig (or the gradation signal). That is, the drive transistor DRT supplies a current corresponding to the image signal Vsig to the light emitting element 3, based on the anode power supply potential PVDD supplied via the output transistor BCT. In this way, the anode power supply potential PVDD supplied to the anode power supply line L1 is lowered by the drive transistor DRT and the output transistor BCT, and thus a potential lower than the anode power supply potential PVDD is supplied to the anode electrode 33 of the light emitting element 3.

[0070] The anode power supply potential PVDD is supplied to one electrode of the second capacitor Cs2 via the anode power supply line L1, and a potential lower than the anode power supply potential PVDD is supplied to the other electrode of the second capacitor Cs2. That is, a higher potential than the other electrode of the second capacitor Cs2 is supplied to one electrode of the second capacitor Cs2. One electrode of the second capacitor Cs2 is, for example, the counter electrode 25 connected to the anode power supply line L1 shown in FIG. 1, and the other electrode of the second capacitor Cs2 is, for example, the anode connection electrode 23 connected to the source electrode of the drive transistor DRT shown in FIG. 1. Figure 4 The anode power supply potential PVDD is supplied to one electrode of the second capacitor Cs2 via the anode power supply line L1, and a potential lower than the anode power supply potential PVDD is supplied to the other electrode of the second capacitor Cs2. That is, a higher potential than the other electrode of the second capacitor Cs2 is supplied to one electrode of the second capacitor Cs2. One electrode of the second capacitor Cs2 is, for example, the counter electrode 25 connected to the anode power supply line L1 shown in FIG. 1, and the other electrode of the second capacitor Cs2 is, for example, the anode connection electrode 23 connected to the source electrode of the drive transistor DRT shown in FIG. 1. Figure 4 The anode power supply potential PVDD is supplied to one electrode of the second capacitor Cs2 via the anode power supply line L1, and a potential lower than the anode power supply potential PVDD is supplied to the other electrode of the second capacitor Cs2. That is, a higher potential than the other electrode of the second capacitor Cs2 is supplied to one electrode of the second capacitor Cs2. One electrode of the second capacitor Cs2 is, for example, the counter electrode 25 connected to the anode power supply line L1 shown in FIG. 1, and the other electrode of the second capacitor Cs2 is, for example, the anode connection electrode 23 connected to the source electrode of the drive transistor DRT shown in FIG. 1.

[0071] In the display device 1, the drive circuit 12 (see Figure 1 ) supplies the image signal Vsig to the image signal line L2 from the first row (for example, the first row in the first column in FIG. 1) to the (m-1)th row (for example, the (m-1)th row in the first column in FIG. 1) in the first column. Figure 1The display device 1 sequentially selects multiple pixel rows (the topmost pixel row in the display area AA). The driver IC 210 writes an image signal Vsig (image write potential) to the sub-pixels 49 of the selected pixel rows, causing the light-emitting element 3 to emit light. During each horizontal scan, the driver IC 210 supplies the image signal Vsig to the image signal line L2, the reset power potential Vrst to the reset power line L3, and the initialization potential Vini to the initialization power line L4. The display device 1 repeats these actions for each frame of the image.

[0072] Next, the cross-sectional configuration of display device 1 will be described. Figure 4 yes Figure 2 Sectional view of IV-IV'. (See also...) Figure 4 As shown, the light-emitting element 3 is disposed on the array substrate 2. The array substrate 2 has a substrate 21, various transistors, various wirings, and various insulating films. The substrate 21 is an insulating substrate, such as a glass substrate, a resin substrate, or a resin film.

[0073] In this specification, the direction perpendicular to the surface of the substrate 21 is designated as "upper side" or simply "upper". Conversely, the direction from the light-emitting element 3 towards the substrate 21 is designated as "lower side" or simply "lower".

[0074] A base coating film 91 is provided on the substrate 21. The base coating film 91 is, for example, a three-layer stacked structure having insulating films 91a, 91b, and 91c. The insulating film 91a is a silicon oxide film, the insulating film 91b is a silicon nitride film, and the insulating film 91c is a silicon oxide film.

[0075] The composition of the primer film 91 is not limited to Figure 4 The configuration is shown. For example, the base coating film 91 can be a single-layer film, a two-layer film, or a film with four or more layers. In addition, when the substrate 21 is a glass substrate, the silicon nitride film has better adhesion, so the silicon nitride film can be formed directly on the substrate 21.

[0076] A light-shielding film 65 is disposed on top of an insulating film 91a. The light-shielding film 65 is located between the semiconductor layer 61 and the substrate 21. The light-shielding film 65 can suppress the intrusion of light from the substrate 21 side into the channel region 61a of the semiconductor layer 61. Alternatively, a conductive material can be used to form the light-shielding film 65 to supply a predetermined potential, thereby enabling the back-gate effect of the driving transistor DRT. Furthermore, the light-shielding film 65 can be disposed on the substrate 21, with an insulating film 91a covering the light-shielding film 65.

[0077] The driving transistor DRT is disposed on the main surface of the substrate 21 on the undercoat 91. Furthermore, in Figure 4In the diagram, a driving transistor DRT is shown corresponding to the light-emitting element 3, but the pixel circuit PICA also includes an output transistor BCT, an initialization transistor IST, a pixel selection transistor SST, and a reset transistor RST (see reference). Figure 3 It is also formed using the same stacked structure as the driving transistor DRT.

[0078] A semiconductor layer 61 is disposed on top of a base coating film 91. The semiconductor layer 61 has a channel region 61a, a source region 61b, a drain region 61c, and a low-concentration impurity region 61d. The low-concentration impurity region 61d is disposed between the channel region 61a and the source region 61b, and also between the channel region 61a and the drain region 61c.

[0079] A gate insulating film 92 is disposed on top of a semiconductor layer 61, covering the base coating film 91. The gate insulating film 92 is, for example, a silicon oxide film. A gate electrode 64 is disposed on top of the gate insulating film 92. In addition, a first wiring 66 is provided on the same layer as the gate electrode 64. The gate electrode 64 and the first wiring 66 are, for example, made of molybdenum tungsten (MoW).

[0080] exist Figure 4 In the example shown, the driving transistor DRT is a top-gate structure with the gate electrode 64 located on the upper side of the semiconductor layer 61. However, it is not limited to this; the driving transistor DRT can be a bottom-gate structure with the gate electrode 64 located on the lower side of the semiconductor layer 61, or it can be a dual-gate structure with the gate electrode 64 located on both the upper and lower sides of the semiconductor layer 61.

[0081] An interlayer insulating film 93 is disposed on top of a gate insulating film 92, covering the gate electrode 64. The interlayer insulating film 93 may have, for example, a stacked structure of silicon nitride and silicon oxide films. A source electrode 62 and a drain electrode 63 are disposed on the interlayer insulating film 93. The source electrode 62 is connected to the source region 61b via contact holes in the gate insulating film 92 and the interlayer insulating film 93, and the drain electrode 63 is connected to the drain region 61c via contact holes in the gate insulating film 92 and the interlayer insulating film 93. A second wiring 67, serving as a lead-in wiring, is connected to the source electrode 62. The source electrode 62, drain electrode 63, and second wiring 67 may, for example, employ a three-layer stacked structure of titanium (Ti), aluminum (Al), and titanium (Ti).

[0082] A portion of the second wiring 67 is formed in the region overlapping with the first wiring 66. A first capacitor Cs1 is formed using the first wiring 66 and the second wiring 67, which are opposed to each other with an interlayer insulating film 93 in between. Additionally, the first wiring 66 is formed in the region overlapping with a portion of the semiconductor layer 61. The first capacitor Cs1 also includes a capacitor formed using the semiconductor layer 61 and the first wiring 66, which are opposed to each other with a gate insulating film 92 in between.

[0083] The first organic insulating film 94 is provided on the interlayer insulating film 93 so as to cover the drive transistor DRT and the second wiring 67. As the first organic insulating film 94, a photosensitive acrylic or the like is used. The photosensitive acrylic or the like has more superior coverage of the wiring layer or surface flatness than inorganic insulating materials formed by CVD or the like.

[0084] On the first organic insulating film 94, a counter electrode 25, a capacitor insulating film 95, and an anode connecting electrode 23 are stacked in this order. The counter electrode 25 is composed of a light-transmissive conductive material such as ITO (Indium Tin Oxide). Although not shown, the counter electrode 25 is connected to the anode power supply line LI (see FIG. 1) at the bottom of a contact hole provided in the first organic insulating film 94. Figure 3 The connecting electrode 26a is provided in the same layer as the counter electrode 25. The connecting electrode 26a is provided so as to cover the inside of the contact hole HI provided in the first organic insulating film 94, and is connected to the second wiring 67 at the bottom of the contact hole HI.

[0085] The capacitor insulating film 95 is provided so as to cover the counter electrode 25 and the connecting electrode 26a, and has an opening in a region overlapping the contact hole HI. The capacitor insulating film 95 is, for example, a silicon nitride film. The anode connecting electrode 23 faces the counter electrode 25 with the capacitor insulating film 95 interposed therebetween. The anode connecting electrode 23 is electrically connected to the connecting electrode 26a and the second wiring 67 via the contact hole HI, and thus the anode connecting electrode 23 is electrically connected to the drive transistor DRT.

[0086] The anode connecting electrode 23 is, for example, a laminated structure of titanium (Ti) and aluminum (Al). However, the anode connecting electrode 23 is not limited to this, and can be composed of one or more of metals including molybdenum and titanium. Alternatively, the anode connecting electrode 23 can be an alloy including one or more of molybdenum and titanium, or a light-transmissive conductive material. Further, the second capacitor Cs2 is formed between the anode connecting electrode 23 and the counter electrode 25 facing each other with the capacitor insulating film 95 interposed therebetween.

[0087] The second organic insulating film 97 is provided on the anode connecting electrode 23. The second organic insulating film 97 uses the same organic material as the first organic insulating film 94. The mounting electrode 24 is provided on the second organic insulating film 97, and is electrically connected to the anode connecting electrode 23 via the contact hole H2. The mounting electrode 24 is also a laminated structure of titanium and aluminum, like the anode connecting electrode 23. However, the mounting electrode 24 can use a conductive material different from the anode connecting electrode 23. Further, the second organic insulating film 97 can use an organic material different from the first organic insulating film 94.

[0088] Light-emitting elements 3R, 3G, and 3B are mounted on their respective mounting electrodes 24. Each light-emitting element 3 is mounted such that its anode electrode 33 is connected to the mounting electrode 24. The bonding member 28 between the anode electrode 33 and the mounting electrode 24 of each light-emitting element 3 is not particularly limited, as long as it ensures good conductivity between them and does not damage the formation on the array substrate 2. The bonding member 28 is, for example, solder or conductive paste. Examples of bonding methods between the anode electrode 33 and the mounting electrode 24 include a reflow process using low-temperature melting solder material and a sintering method after placing the light-emitting element 3 on the array substrate 2 using conductive paste.

[0089] The light-emitting element 3 includes a semiconductor layer 31, a cathode electrode 32, and an anode electrode 33. The semiconductor layer 31 can be constructed by stacking an n-type cladding layer, an active layer, and a p-type cladding layer. The semiconductor layer 31 can be a compound semiconductor such as gallium nitride (GaN), indium aluminum phosphide (AlInP), or indium gallium nitride (InGaN). Different materials can be used for the semiconductor layer 31 for each light-emitting element 3R, 3G, and 3B. In addition, as the active layer, a multiple quantum well (MQW) structure can be adopted, in which a well layer and a barrier layer composed of multiple atomic layers are periodically stacked for high efficiency.

[0090] An insulating film 98 is provided between multiple light-emitting elements 3. The insulating film 98 is formed of resin material. The insulating film 98 covers at least the side surfaces of the light-emitting elements 3, and the cathode electrode 32 of the light-emitting elements 3 protrudes from the insulating film 98. The insulating film 98 is formed flatly such that the upper surface of the insulating film 98 is flush with the upper surface of the cathode electrode 32. However, the position of the upper surface of the insulating film 98 may differ from the position of the upper surface of the cathode electrode 32.

[0091] The opposing cathode electrode 22 covers multiple light-emitting elements 3 and element insulating film 98, and is electrically connected to the multiple light-emitting elements 3. The opposing cathode electrode 22 uses a conductive material with light transmittance, such as ITO. This allows for efficient emission of light from the light-emitting elements 3 to the outside. The opposing cathode electrode 22 is electrically connected to the cathode electrodes 32 of the multiple light-emitting elements 3 mounted in the display area AA. The opposing cathode electrode 22 utilizes a contact portion located on the outer side of the display area AA to connect with the cathode wiring 60 (see reference 60) located on the array substrate 2 side. Figure 1 )connect.

[0092] A first lens 71 is disposed overlapping each of the plurality of light-emitting elements 3. The first lens 71 and the second lens 72 (see reference) Figure 5 This is an optical component used to adjust the illuminance distribution of light emitted from multiple light-emitting elements 3, also known as a microlens. Furthermore, the configuration of the multiple light-emitting elements 3, the first lens 71, and the second lens 72 is as follows:Figure 5 The following description will be given.

[0093] As described above, the display device 1 is configured as a display element using the light emitting element 3. In addition, the display device 1 can have an overcoat layer or a cover sheet stacked on the upper side of the opposing cathode electrode 22, the first lens 71, and the second lens 72, as needed. Furthermore, the display device 1 can have a circularly polarizing plate or a touch panel or the like provided on the upper side of the opposing cathode electrode 22.

[0094] In addition, in Figure 4 a face-up configuration in which the upper portion of the light emitting element 3 is connected to the opposing cathode electrode 22 is shown. However, the light emitting element 3 can be a flip chip type light emitting element in which the anode electrode 33 (p-type electrode) and the cathode electrode 32 (n-type electrode) are provided on the same side opposite to the array substrate 2.

[0095] Figure 5 is a plan view schematically showing the first light emitting element, the first lens, the second light emitting element, and the second lens. Figure 6 is a cross-sectional view schematically showing the first light emitting element, the first lens, the second light emitting element, and the second lens. Figure 5 and Figure 6 is a schematic view that shows a part of the second region AAs2, the first region AAs1, and the second region AAs2 arranged in the first direction Dx in the display region AA of the substrate 21, respectively. Figure 5 and Figure 6 shows the light emitting element 3R of the light emitting elements 3R, 3G, 3B included in the pixel PX, but the description of the light emitting element 3R can also be applied to the light emitting elements 3G, 3B. In addition, in Figure 6 , the detailed configuration of the array substrate 2 is omitted.

[0096] As Figure 5 and Figure 6 shown, the first light emitting element 3-1 (first light emitting element 3R-1) and the first lens 71 are provided in the first region AAs1. The second light emitting element 3-2 (second light emitting element 3R-2) and the second lens 72 are provided in the second region AAs2. In addition, in the following description, the light emitting element 3 of the plurality of light emitting elements 3 mounted in the first region AAs1 is denoted as the first light emitting element 3-1, and the light emitting element mounted in the second region AAs2 is denoted as the second light emitting element 3-2. Here, the first light emitting element 3-1 and the second light emitting element 3-2 are elements formed using the same material and the same stacked configuration.

[0097] The first lens 71 is disposed overlapping the first light emitting element 3-1. The second lens 72 is disposed overlapping the second light emitting element 3-2. The first lens 71 and the second lens 72 are provided above the element insulating film 98 and the opposing cathode electrode 22 that cover the first light emitting element 3-1 and the second light emitting element 3-2. The first lens 71 and the second lens 72 are provided in the same layer. Here, a protective film or the like formed of an insulating material can be provided between the first lens 71 and the second lens 72 and the opposing cathode electrode 22.

[0098] As shown in FIG. 1, in the first region AAs1, the first lens 71 has a first diameter D1 in plan view. The first diameter D1 of the first lens 71 is larger than a first width W1 of the first light emitting element 3-1 in the first direction Dx. One first lens 71 is provided overlapping one first light emitting element 3-1. The center (optical axis) of the first lens 71 overlaps the geometric center in plan view of the first light emitting element 3-1. Figure 5

[0099] In the second region AAs2, the second lens 72 has a second diameter D2 in plan view. The second diameter D2 of the second lens 72 is smaller than a second width W2 of the second light emitting element 3-2 in the first direction Dx. In addition, the second diameter D2 of the second lens 72 is smaller than the first diameter D1 of the first lens 71. Four second lenses 72 are provided overlapping one second light emitting element 3-2. The centers (optical axes) of the four second lenses 72 are arranged so as to surround the geometric center in plan view of the second light emitting element 3-2.

[0100] In addition, the first width W1 of the first light emitting element 3-1 and the second width W2 of the second light emitting element 3-2 are, for example, set to the width in the first direction Dx of the upper surface (the surface opposing the first lens 71 and the second lens 72) of the respective semiconductor layers 31.

[0101] As shown in FIG. 1, in the first region AAs1, the light emitted from the first light emitting element 3-1 is condensed by the first lens 71, and the intensity of the light Lz traveling in the third direction Dz becomes greater than the intensity of the light Lxy traveling in a direction other than the third direction Dz. In the first region AAs1, the first lens 71 is provided overlapping the respective first light emitting elements 3-1. Thus, in the first region AAs1, the luminance in the third direction Dz, that is, the front direction of the display device 1, is improved as a whole. Figure 6

[0102] ​​In region AAs2, light emitted from the second light-emitting element 3-2 is collected by multiple second lenses 72. The intensity of light Lz traveling from the multiple second lenses 72 towards the third direction Dz is less than the intensity of light Lz traveling from the first lens 71 towards the third direction Dz in region AAs1. On the other hand, the intensity of light Lxy traveling from the second lenses 72 in directions other than the third direction Dz becomes greater than that of the first lens 71. Therefore, in region AAs2, the overall brightness in the direction tilted relative to the third direction Dz is increased, ensuring a good viewing angle.

[0103] As described above, the display device 1 of this embodiment includes: a substrate 21; a plurality of first light-emitting elements 3-1 and a plurality of second light-emitting elements 3-2 disposed in a display area AA of the substrate 21; a first lens 71 having a first diameter D1 when viewed from a direction perpendicular to the substrate 21, which overlaps with the plurality of first light-emitting elements 3-1 respectively; and a second lens 72 having a second diameter D2 smaller than the first diameter D1 when viewed from a direction perpendicular to the substrate 21, which overlaps with the plurality of second light-emitting elements 3-2 respectively.

[0104] In this way, in the display device 1 of the first embodiment, the first diameter D1 (radius of curvature) of the first lens 71 and the second diameter D2 (radius of curvature) of the second lens 72 are different in the first region AAs1 and the second region AAs2. Furthermore, the number of first lenses 71 overlapping with the first light-emitting element 3-1 and the number of second lenses 72 overlapping with the second light-emitting element 3-2 are different. Therefore, within the display region AA, the distribution of light emitted from the light-emitting element 3 can be different for each region. Specifically, the display device 1 can ensure brightness in the frontal direction in the first region AAs1 and can ensure a viewing angle in the second region AAs2.

[0105] In addition, such as Figure 5 As shown, the semiconductor layer 31 of the light-emitting element 3 has a quadrilateral shape when viewed from above. However, it is not limited to this; the semiconductor layer 31 can have other shapes when viewed from above, such as rectangular, polygonal, or circular. In addition, the number of second lenses 72 overlapping with one second light-emitting element 3-2 is not limited to four; it can be two, three, or more than five.

[0106] (First variation of the first embodiment)

[0107] Figure 7 This is a schematic cross-sectional view illustrating the first light-emitting element, the first lens, the second light-emitting element, and the second lens of the first embodiment, a first modification of the first embodiment. Furthermore, in the following description, the same reference numerals are used to denote the same constituent elements as those described in the above embodiments, and repeated descriptions are omitted.

[0108] As Figure 7 shown in FIG. 1A, in the display device 1A of the first modification of the first embodiment, the light emitting elements 3 are flip chip type light emitting elements. The anode electrodes 33 (p-type electrodes) and the cathode electrodes 32 (n-type electrodes) are arranged on a surface opposite to the array substrate 2 of the semiconductor layer 31.

[0109] The anode electrodes 33 are connected to the first mounting electrodes 24A provided on the array substrate 2 by the bonding members 28A. Also, the cathode electrodes 32 are connected to the first mounting electrodes 24A provided on the array substrate 2 by the bonding members 28A.

[0110] In the first region AAs1, the first lens 71A is provided so as to cover the upper surface and the side surface of the first light emitting element 3-1. The first lens 71A is also provided so as to cover the bonding members 28A and 28B. In other words, the first lens 71A also functions as the element insulating film 98.

[0111] In the second region AAs2, the element insulating film 98 is provided so as to cover the second light emitting element 3-2. A plurality of second lenses 72 are provided on the element insulating film 98 so as to overlap the second light emitting element 3-2. In the present modification, the first diameter D1 (refer to FIG. 1A) of the first lens 71A is larger than the second diameter D2 (refer to FIG. 1A) of the second lens 72 in plan view. Figure 5 Figure 5 In addition, in cross section, the radius of curvature (height) of the first lens 71A is larger than the radius of curvature (height) of the second lens 72 and is larger than the height of the first light emitting element 3-1.

[0112] As such, the first lens 71A and the second lens 72 can be provided in different layers. By providing the first lens 71A having a large radius of curvature on the array substrate 2 (more specifically, on the first mounting electrodes 24A and the second mounting electrodes 24B), thinning of the display device 1A can be achieved compared to the first embodiment.

[0113] (Second Modification of the First Embodiment)

[0114] Figure 8 is a perspective view schematically showing an array substrate provided in the display device of the second modification of the first embodiment. In the above-described first embodiment and the first modification, an example in which the substrate 21 is a flat plate is shown, but the present application is not limited to this. As shown in FIG. 2A, the display device 1B of the second modification of the first embodiment is a curved display. Figure 8

[0115] ​​The array substrate 2A of the display device 1B has a shape curved in the first direction Dx, and has a shape curved in an S-letter shape when viewed from the second direction Dy. The array substrate 2A includes a first curved surface region TA, a second curved surface region CA, and a low curvature region FA.

[0116] The first curved surface region TA has a curved surface curved in a convex shape toward the display surface side. The second curved surface region CA has a curved surface curved in a concave shape on the side opposite to the first curved surface region TA. The first curved surface region TA and the second curved surface region CA are curved with a certain curvature. The first curved surface region TA and the second curved surface region CA can have the same curvature, or can have different curvatures. In addition, the first curved surface region TA and the second curved surface region CA are each not limited to the case where the curvature is constant, and can have different curvatures along the first direction Dx.

[0117] The low curvature region FA is disposed between the first curved surface region TA and the second curved surface region CA in the first direction Dx. The low curvature region FA is a region having a curvature smaller than the first curved surface region TA and the second curved surface region CA. In other words, the low curvature region FA is a region having no inflection portion, and smoothly connecting the first curved surface region TA and the second curved surface region CA together.

[0118] The display region AA has a first display region AA-1 and a second display region AA-2. The first display region AA-1 and the second display region AA-2 are disposed adjacent to each other in the first direction Dx. Specifically, the first display region AA-1 is a region overlapping a portion of the first curved surface region TA and the low curvature region FA adjacent to the first curved surface region TA. The second display region AA-2 is a region overlapping a portion of the second curved surface region CA and the low curvature region FA adjacent to the second curved surface region CA.

[0119] The display region AA has a substantially quadrangular shape when viewed from the third direction Dz, but the shape of the outer shape of the display region AA is not particularly limited. For example, the display region AA can have a cutout portion, or the display region AA can have other polygonal shapes, or the display region AA can have other shapes such as a circular shape or an elliptical shape. In addition, the first display region AA-1 and the second display region AA-2 are continuously provided, and are not limited to the case where one image is displayed, and can be separately provided to display different images.

[0120] The first display region AA-1 includes a first region AAc1 and a second region AAc2. The first region AAc1 is located in a central portion of the first display region AA-1 in the first direction Dx. The first region AAc1 is provided between a plurality of the second regions AAc2 in the first direction Dx. The first display region AA-1 is arranged in the order of the second region AAc2, the first region AAc1, and the second region AAc2 in the first direction Dx.

[0121] The second display region AA-2 includes a third region AAc3 and a fourth region AAc4. The third region AAc3 is located in a central portion of the second display region AA-2 in the first direction Dx. The third region AAc3 is provided between a plurality of the fourth regions AAc4 in the first direction Dx. The second display region AA-2 is arranged in the order of the fourth region AAc4, the third region AAc3, and the fourth region AAc4 in the first direction Dx. The fourth region AAc4 is arranged adjacent to the second region AAc2 in the low-curvature region FA.

[0122] The first region AAc1 and the third region AAc3 are regions in which the normal direction of the array substrate 2A (the substrate 21A) faces the front direction, and the plurality of first light emitting elements 3-1 and the first lens 71 (or the first lens 71A) described above are provided. The second region AAc2 and the fourth region AAc4 are regions in which the normal direction of the array substrate 2A (the substrate 21A) faces a direction inclined with respect to the front direction, and the plurality of second light emitting elements 3-2 and the second lens 72 described above are provided.

[0123] Thus, in the first region AAc1 and the third region AAc3, light emitted from the plurality of first light emitting elements 3-1 is condensed by the first lens 71 (or the first lens 71A), and the luminance in the front direction is improved. In addition, in the second region AAc2 and the fourth region AAc4, a part of light emitted from the plurality of second light emitting elements 3-2 travels toward the front direction from the second lens 72. Thus, compared to a case where the second lens 72 is not provided, the luminance in the front direction in the second region AAc2 and the fourth region AAc4 is improved.

[0124] The array substrate 2A has a first gate line GLA, a second gate line GLB, a first signal line SLA, a second signal line SLB, a first gate line drive circuit 12A, a second gate line drive circuit 12B, a first signal line drive circuit 14A, a second signal line drive circuit 14B, a first drive IC 210A, and a second drive IC 210B.

[0125] The first gate line GLA and the first signal line SLA are provided in the first display region AA-1. The first gate line GLA is curved in a convex shape in accordance with the shape of the first curved region TA and the low curvature region FA. The first gate line GLA is connected to the first gate line driver circuit 12A, and the first signal line SLA extends in the second direction Dy and is connected to the first signal line driver circuit 14A. The first drive IC 210A is mounted in a region between the first signal line driver circuit 14A and the end portion of the array substrate 2A.

[0126] The second gate line GLB and the second signal line SLB are provided in the second display region AA-2. The second gate line GLB is curved in a concave shape in accordance with the shape of the second curved region CA and the low curvature region FA. The second gate line GLB is connected to the second gate line driver circuit 12B, and the second signal line SLB extends in the second direction Dy and is connected to the second signal line driver circuit 14B. The second drive IC 210B is mounted in a region between the second signal line driver circuit 14B and the end portion of the array substrate 2A.

[0127] Further, the configurations of the first gate line GLA, the second gate line GLB, the first signal line SLA, the second signal line SLB, and various peripheral circuits are merely examples and can be appropriately changed. For example, the first gate line GLA and the second gate line GLB can be continuously formed throughout the first display region AA-1 and the second display region AA-2. In addition, the array substrate 2A (the substrate 21A) is not limited to the shape curved in an S shape, and can be a shape curved in only a convex shape or a concave shape.

[0128] (Second Embodiment)

[0129] Figure 9 is a plan view schematically showing the first light emitting element, the first lens, the second light emitting element, and the second lens that one pixel has of the display device of the second embodiment. Figure 10 is a cross-sectional view schematically showing the first light emitting element, the first lens, the second light emitting element, and the second lens that one pixel has of the display device of the second embodiment. Further, in Figure 10 , the first light emitting element 3R-1 and the second light emitting element 3R-2 arranged in the second direction Dy are schematically shown side by side.

[0130] In the above first embodiment, a configuration in which the first light emitting element 3-1 and the first lens 71 (or the first lens 71A) are arranged in the first region AAs1 and the second light emitting element 3-2 and the second lens 72 are arranged in the second region AAs2 in the display region AA is shown, but is not limited thereto.

[0131] As shown in Figure 9 and Figure 10As shown in the display device 1C of the second embodiment, one pixel PXA includes the first light emitting elements 3R-1, 3G-1, 3B-1 and the second light emitting elements 3R-2, 3G-2, 3B-2. The first light emitting elements 3R-1, 3G-1, 3B-1 are arranged in the first direction Dx. In addition, the second light emitting elements 3R-2, 3G-2, 3B-2 are arranged in the first direction Dx, and are arranged adjacent to the first light emitting elements 3R-1, 3G-1, 3B-1 in the second direction Dy. In Figure 9 In the second embodiment, the first light emitting element 3-1 (for example, the first light emitting element 3R-1) and the second light emitting element 3-2 (for example, the second light emitting element 3R-2) that emit light of the same color are arranged adjacent to each other in the second direction Dy.

[0132] In plan view, the first lens 71 is provided so as to overlap each of the first light emitting elements 3R-1, 3G-1, 3B-1. In addition, a plurality of second lenses 72 are provided so as to overlap each of the second light emitting elements 3R-2, 3G-2, 3B-2. That is, one first lens 71 and a plurality of second lenses 72 are arranged adjacent to each other in the second direction Dy.

[0133] In other words, in the present embodiment, within one pixel PXA, the first sub-pixel 49-1 having the first light emitting element 3-1 and the first lens 71 and the second sub-pixel 49-2 having the second light emitting element 3-2 and the second lens 72 are arranged adjacent to each other in the second direction Dy. The first sub-pixel 49-1 and the second sub-pixel 49-2, which are six in total, are arranged as one group in a matrix shape on the display region AA.

[0134] The stacked structure of the first light emitting element 3R-1, the first lens 71, the second light emitting element 3R-2, and the second lens 72 is the same as that of the first embodiment described above, and the repeated description is omitted. In addition, the relationship of the first diameter D1 of the first lens 71, the second diameter D2 of the second lens 72, and the width of each light emitting element 3 is also the same as that of the first embodiment.

[0135] Figure 11 is a circuit diagram showing the pixel circuit of the second embodiment. As shown in Figure 11 The first pixel circuit PICA-1 is provided corresponding to the first light emitting element 3R-1. The second pixel circuit PICA-2 is provided corresponding to the second light emitting element 3R-2. The first pixel circuit PICA-1 and the second pixel circuit PICA-2 are arranged adjacent to each other, and share a part of the wiring. In addition, in Figure 11 In the second embodiment, the first light emitting element 3-1 and the second light emitting element 3-2 are shown as the pixel circuit PICA, but respective pixel circuits PICA are also provided for the other first light emitting elements 3G-1, 3B-1 and the second light emitting elements 3G-2, 3B-2.

[0136] Specifically, the reset power line L3, the reset control signal line L5, the output control signal line L6, the pixel control signal line L7, the initialization control signal line L8, and the cathode power line L10 are connected to the first pixel circuit PICA-1 and the second pixel circuit PICA-2, respectively. Further, the first pixel circuit PICA-1 and the second pixel circuit PICA-2 have the same configuration as the pixel circuit PICA shown in Figure 3 the first pixel circuit PICA-1 and the second pixel circuit PICA-2, the reset transistor RST is connected between the output transistor BCT and the drive transistor DRT.

[0137] According to this configuration, in the display device 1C of the second embodiment, in one pixel PXA, the luminance in the front direction can be increased by the first light emitting element 3-1 and the first lens 71 of the first sub-pixel 49-1, and a wide viewing angle can be ensured by the second light emitting element 3-2 and the second lens 72 of the second sub-pixel 49-2. In addition, the display device 1C can control the lighting and the extinguishing of the first light emitting element 3-1 and the second light emitting element 3-2 for each region with respect to the pixels PXA arranged in a matrix in the display region AA.

[0138] (Third Modification of the Second Embodiment)

[0139] Figure 12 is a plan view schematically showing a pixel of the third modification of the second embodiment. As shown in Figure 12 In the display device 1D of the third modification of the second embodiment, the pixel PXA further includes a first drive IC 211 and a second drive IC 212. The first drive IC 211 and the second drive IC 212 are also referred to as micro ICs.

[0140] The first drive IC 211 is a circuit that drives the first light emitting elements 3R-1, 3G-1, 3B-1. The second drive IC 212 is a circuit that drives the second light emitting elements 3R-2, 3G-2, 3B-2. The first drive IC 211 and the second drive IC 212 are mounted on each of a plurality of pixels PXA. That is, the first drive IC 211 and the second drive IC 212 respectively have the functions of the first pixel circuit PICA-1 and the second pixel circuit PICA-2 shown in Figure 11 Further, the first drive IC 211 and the second drive IC 212 can have a part of the functions of the first pixel circuit PICA-1 and the second pixel circuit PICA-2 shown in Figure 11 Further, the first drive IC 211 and the second drive IC 212 can have a part of the functions of the first pixel circuit PICA-1 and the second pixel circuit PICA-2 shown in

[0141] According to the third modification of the second embodiment, it is possible to reduce the number of transistors of the array substrate 2.

[0142] (Third Embodiment)

[0143] Figure 13 FIG. 1E is a perspective view schematically showing a display device of the third embodiment. As shown in FIG. 1E, in the display device 1E of the third embodiment, the main surface of the substrate 21 on which the light emitting elements 3 are mounted has a curved shape that is convexly curved. More specifically, the array substrate 2 (substrate 21) of the display device 1E has a cross-sectional configuration in the first direction Dx that has a curved shape that is convexly curved, and also has a cross-sectional configuration in the second direction Dy that intersects the first direction Dx, which also has a curved shape that is convexly curved. Figure 13

[0144] In the present embodiment, the configurations of the above-described embodiments and modifications can also be employed. For example, the display region AA of the substrate 21 includes a first region AAdl provided at a central portion of the display region AA, and a second region AAd2 provided at an outer edge portion of the display region AA. A plurality of first light emitting elements 3-1 and a plurality of first lenses 71 are provided in the first region AAdl. A plurality of second light emitting elements 3-2 and a plurality of second lenses 72 are provided in the second region AAd2.

[0145] Alternatively, the configuration of the array substrate 2 (substrate 21) of the third embodiment and the configuration of the pixel PXA of the second embodiment can be combined.

[0146] The above describes a suitable embodiment of the present application, but the present application is not limited to this embodiment. The content disclosed in the embodiments is merely an example, and various modifications can be made within a scope that does not depart from the gist of the present application. A suitable modification made within a scope that does not depart from the gist of the present application is of course within the technical scope of the present application. Within a scope that does not depart from the gist of the above-described embodiments and modifications, at least one of various omissions, substitutions, and modifications of the configuration elements can be made.​

Claims

1. A display device comprising: a substrate; a plurality of first light emitting elements and a plurality of second light emitting elements provided in a display region of the substrate; a first lens having a first diameter in a plan view from a direction perpendicular to the substrate, the first lens being provided so as to overlap each of the plurality of first light emitting elements; and a second lens having a second diameter smaller than the first diameter in the plan view from the direction perpendicular to the substrate, the second lens being provided so as to overlap each of the plurality of second light emitting elements, one of the first lens is provided so as to overlap one of the first light emitting elements, a plurality of the second lens is provided so as to overlap one of the second light emitting elements, the display region of the substrate includes a first region in which the plurality of first light emitting elements and the plurality of first lens are provided, and a second region in which the plurality of second light emitting elements and the plurality of second lens are provided, in a first direction, the first region is provided in a central portion of the display region, and the second region is provided in a peripheral portion of the display region.

2. The display device according to claim 1, wherein the first diameter of the first lens is larger than a first width of the first light emitting element, and the second diameter of the second lens is smaller than a second width of the second light emitting element.

3. The display device according to claim 1 or 2, wherein a plurality of pixels are arranged on the substrate, one of the pixels includes the plurality of first light emitting elements and the plurality of second light emitting elements, and in a plan view from a direction perpendicular to the substrate, the first light emitting element and the first lens, and the second light emitting element and the plurality of second lens are arranged adjacently.

4. The display device according to claim 3, wherein in one of the pixels, the first light emitting element and the second light emitting element which are adjacent to each other emit light of the same color.

5. The display device according to claim 3, wherein one of the pixels has a first driving IC which drives the first light emitting element, and a second driving IC which drives the second light emitting element.

6. The display device according to claim 4, wherein one of the pixels has a first driving IC which drives the first light emitting element, and a second driving IC which drives the second light emitting element.

7. The display device according to claim 1 or 2, wherein an element insulating film which covers side surfaces of the plurality of first light emitting elements and the plurality of second light emitting elements is provided, and the first lens and the second lens are provided on the element insulating film.

8. The display device according to claim 1 or 2, wherein an element insulating film which covers side surfaces of the plurality of second light emitting elements is provided, the first lens is provided on the substrate so as to cover an upper surface and side surfaces of the first light emitting element, and the second lens is provided on the element insulating film.

9. The display device according to claim 1 or 2, wherein a main surface of the substrate on which the plurality of first light emitting elements and the plurality of second light emitting elements are mounted has a curved shape which is curved in a convex shape. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The display region of the substrate includes a first region provided with a plurality of the first light emitting elements and a plurality of the first lenses, and a second region provided with a plurality of the second light emitting elements and a plurality of the second lenses, The first region is provided at a central portion of the display region of the substrate, The second region is provided at an outer edge portion of the display region of the substrate.

Images