A method for establishing a six-dimensional clutter map based on a multi-core DSP architecture

Abstract

This invention relates to a method for establishing multi-dimensional clutter maps based on a multi-core DSP architecture. It utilizes a 4XSRIO high-speed data transmission serial port to transmit MTD data from the FPGA to six cores, meeting the requirement of parallel processing of clutter maps for different elevation beams by the six cores. It leverages the powerful data storage capabilities of DDR3 SDRAM to establish a six-dimensional clutter map including range, frequency, azimuth, elevation, PRI, and mode information. Using the DDR3 SDRAM's page-turning function, clutter maps for different modes are partitioned and managed. During mode switching, the clutter space under the corresponding zone number is updated according to the current mode, while the clutter space of other zones retains its previous state, ensuring that the clutter map for each mode is always real-time and effective. This invention is applicable to most current complex search radar systems, enabling real-time acquisition of complex clutter maps with high partitioning accuracy, wide coverage, and adaptability to various environments.

Description

Technical Field

[0001] This invention belongs to the field of radar technology and relates to the establishment of a six-dimensional clutter map based on a multi-core DSP architecture. It can be applied to the clutter processing needs of different radar signal processors, meet the real-time establishment and updating of clutter maps in various scenarios and working modes, and can establish more flexible and efficient refined clutter maps, reducing false alarms. Background Technology

[0002] A clutter map is a distribution map of clutter intensity stored in memory within the radar's effective range. With the increasing complexity of the electromagnetic environment, modern radar systems are becoming more complex, requiring sufficiently long operating ranges and wide beam coverage. Modern radars demand that signal processing can record as comprehensive as possible clutter information in real time, process clutter, and analyze real-time clutter changes to promptly address clutter interference with effective targets. Therefore, many new requirements have been placed on clutter maps: sufficiently large storage capacity, fast clutter update speed, and the ability to adjust clutter update states and iteration coefficients in real time according to changes in the type of detected target and the application environment. Although integrated circuit technology has developed rapidly, with high-performance single-core DSP chips reaching core frequencies of 1GHz and above, multiple DSPs are typically integrated on the signal processing board to meet system requirements for processing speed and data throughput. Some even use multiple signal processing boards for simultaneous processing, although this design improves overall processing performance. However, the integration density of multiple DSPs on signal processing circuit boards is increasing, limiting board space. Using multiple processing boards further increases system size, making product design, debugging, and manufacturing increasingly difficult. Simultaneously, the increased number of DSP devices leads to higher system power consumption and heat dissipation challenges, resulting in a sharp decline in overall system reliability and stability. Recently developed multi-core DSPs integrate multiple cores onto a single chip, significantly increasing the chip's operating frequency. Compared to discrete single-core DSPs with the same number of cores, they reduce cost and power consumption by more than half. Furthermore, the KeyStone multi-core architecture, high-performance floating-point arithmetic capabilities, numerous high-speed interfaces, and rich external storage devices give multi-core DSPs advantages such as flexibility, high speed, low power consumption, fast processing speed, and abundant external interfaces.

[0003] On the other hand, in order to accomplish complex search tasks and simultaneously search for long-range aerial targets and low, small, and slow targets, modern radars have added alternating modes, that is, alternating between two search modes throughout the week. The signal processing of search radars generally adopts a sliding window method. Due to the difference in timing during mode switching, the data of the first few frames of the switch are disordered. Traditional search radars need to re-establish clutter maps when switching modes. Thus, when the modes are frequently alternating, invalid data is used, causing the clutter map to fail, increasing false alarm points, and seriously affecting target detection and track formation. Therefore, the traditional method cannot meet the requirements of this new type of radar system with real-time changes in search modes. Summary of the Invention

[0004] Technical problems to be solved

[0005] To overcome the shortcomings of existing technologies, this invention proposes a method for constructing six-dimensional clutter maps based on a multi-core DSP architecture. The main technical problems it addresses include:

[0006] 1. Real-time creation and updating of fine clutter maps were achieved based on a multi-core DSP architecture;

[0007] 2. Establish a six-dimensional clutter map to solve the problem of increased false alarms caused by clutter map failure in alternating search mode.

[0008] Technical solution

[0009] A method for establishing a six-dimensional clutter map based on a multi-core DSP architecture, characterized by the following steps:

[0010] Step 1: After the system powers on, the main core configures the SRIO interface and DDR3, partitions the DDR3 space, associates the mode number with the zone number, performs page turning operations on the DDR3 in sequence, calculates the storage capacity of the mode, and allocates the corresponding size of noise space.

[0011] Step Two: The main core enters the CPI-based cyclic operation phase, receiving commands from the host computer in real time, parsing control parameters, obtaining the current operating mode, and retrieving the clutter diagram parameter vector table [R_NUM, F_NUM, EL_NUM, AZ_NO, PRI_NO, MODE_NO, K] based on the mode. IOC R_NUM, F_NUM, and EL_NUM represent the number of range points, frequency points, and elevation beams, respectively; AZ_NO, PRI_NO, and MODE_NO represent the location zone number, PRI stagger number, and mode zone number corresponding to the current cycle, respectively; K IOC These are the clutter map iteration coefficients; once the parameter table is ready, it is placed in the L2 cache of each core at the address (SHARED_LL2+No). core×0X1000000),SHARED_LL2=0X1087FF00,No core For the verification number;

[0012] Step 3: The master core controls the processing mode of the slave cores based on the working status. First, it determines whether the current mode is the first operation after power-on. If so, the master core sets the clutter initial state flag of the corresponding clutter block to ENABLE, indicating that the slave core performs a single-cycle rapid clutter map establishment for that clutter block. Otherwise, it sets it to DISABLE, and the slave core performs routine clutter map updates. Second, the master core determines whether the radar system is currently in a silent state. If silent, it opens the clutter map silence switch; otherwise, it closes it. Finally, it compares the current mode with the previous cycle mode. If there is a change, the mode counter starts counting from 0 according to the CPI cycle, and the clutter map silence switch is opened to prevent invalid data from being used for clutter map updates during the initial mode switching, thus destroying the original valid clutter map. When the counter reaches 2, 3, 4, or 5, the clutter map silence switch is closed, and the clutter map update process restarts. The clutter initial state flag and silence state flag are stored in the L2 of each core at address (SHARED_LL2+No). core ×0X1000000+0X00000040), SHARED_LL2=0X1087FF00, No core For the verification number;

[0013] Step 4: First, from cores 1 to 6, retrieve the corresponding addresses SHARED_LL2+No. core ×0X1000000+0X00000040 reads the working status word, queries the clutter silence status word, and determines that it is ENABLE. The slave core does not receive data from the FPGA and enters the idle state; otherwise, the slave core works normally. Next, the slave core determines whether the initial status flag word is ENABLE. If it is, the slave core initializes the clutter map single-cycle enable matrix. The size of this matrix is ​​EL_NUM×AZ_NUM, where EL_NUM is the number of elevation beams and AZ_NUM is the number of azimuth blocks. The value range of this matrix is ​​{0,1}, where 0 represents non-single-cycle update and 1 represents single-cycle update. During initialization, all values ​​of the matrix are set to 1.

[0014] Step 5: From cores 1 to 6, the CPI cycle begins. First, the core starts from the corresponding address SHARED_LL2+No. core ×0X1000000 Read the clutter parameter vector table. Based on the parameter vector table, obtain the elevation beam number and azimuth area number of the clutter block to be processed from core 1 to 6 respectively. Determine whether the single-cycle enable matrix of the current clutter map is 1. If it is 1, proceed to step five; otherwise, proceed to step six.

[0015] Step Six: In each CPI cycle, the FPGA sends data for all elevation beams with azimuth number AZ_NO. Assuming there are K elevation beams, corex receives the data for the (x+6*n)th beam, where n = (0, 1, 2…), x is the core number, and x+6*n <= K. After receiving the data, the core flips to the corresponding page in DDR3 based on MODE_NO, finds the clutter start address, and calculates the offset address of the clutter block for the current core's processed beam as R_NUM*F_NUM*(x+6*n)*AZ_NO*PRI_NO*4. The received data is then quickly sent to the corresponding position in DDR3 via EDMA, and the current block position corresponding to the single-cycle clutter map enable matrix is ​​set to 0. In one CPI cycle, the initial clutter map construction for all elevation beams is completed in parallel from cores 1 to 6. After the antenna completes one revolution, all azimuth area numbers are traversed, thus completing the initial clutter map construction.

[0016] Step 7: After the initial clutter map is built, the system enters a stable update phase. Data is received from the core as in Step 5. The absolute address and offset address are obtained according to the parameter vector table. The previous clutter data is read from the corresponding address in DDR3. The clutter data is iteratively updated according to the following formula:

[0017] D(k)=K IOC ×D_fpga+(1-K IOC )×D(k-1)

[0018] Where k represents the iteration number, and D_fpga is the clutter block data sent by the FPGA; the iterated data is quickly sent to the corresponding position in DDR3 via EDMA; one iteration update of the clutter map is completed; during operation, the slave core works in CPI cycle under the control of the master core, repeatedly iterating and updating the clutter map to meet the needs of target detection in real time.

[0019] A computer system is characterized by comprising: one or more processors, and a computer-readable storage medium for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors cause the one or more processors to implement the method described above.

[0020] A computer-readable storage medium is characterized by storing computer-executable instructions, which, when executed, are used to implement the above-described method.

[0021] Beneficial effects

[0022] This invention proposes a six-dimensional clutter map creation method based on a multi-core DSP architecture. For the first time, a six-dimensional clutter map is created and updated in real-time using a multi-core DSP architecture. For real-time changing search modes such as alternating modes, it can quickly complete clutter map switching and updates, effectively avoiding the phenomenon of a surge in false alarm points during mode switching. The invention also achieves modular and parametric design of the clutter map software, which can meet the clutter map processing needs of different radar signal processors.

[0023] This invention is based on a multi-core DSP architecture, where the entire operation is completed collaboratively by one master core and six slave cores. The master core controls the operation of the slave cores in real time, and the slave cores respond to system requirements in real time. The entire design adopts a modular and parametric approach, which can meet the clutter processing needs of different radar signal processors. Attached Figure Description

[0024] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.

[0025] Figure 1 Schematic diagram of clutter plot operation;

[0026] Figure 2 Schematic diagram of clutter data pipeline;

[0027] Figure 3 Schematic diagram of clutter address distribution. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0029] This invention employs a multi-core DSP architecture. After the system powers on, the main core first completes the interface initialization configuration, calculates the clutter map storage space based on the prior information of all modes, and allocates a space of corresponding size. The space size for each working mode is calculated according to the following formula: R N ×F M ×EL K ×AZ L ×3 PRI ×4Byte, the variables represent the number of distance points, the number of frequency points, the number of elevation beams, the number of azimuth blocks, and the PRI three-parameter, respectively, and the data type is 4-byte Float. For details on the address distribution of the clutter diagram, please refer to... Figure 3Next, the slave cores are activated. Slave cores 1 through 6 enter a periodic working state, with a cycle of one CPI. The master core parses the host computer commands and configures working parameters according to the CPI. Slave cores 1 through 6 receive the master core's working parameters and, based on the commands, establish and iteratively update the clutter diagram. The clutter diagram functional block diagram is shown below. Figure 1 As shown, a set of range-Doppler two-dimensional data after MTD is used as the smallest clutter block. In one CPI cycle, cores 1 to 6 process clutter information from all elevation beams in parallel. To ensure real-time performance, a 5G 4XSRIO high-speed serial port is used with the FPGA. Clutter data from different beams is received sequentially from cores 1 to 6. Internal data transfer uses EDMA, processing data while receiving. To address the issues in the alternating search mode, this invention adds a mode dimension to the original five-dimensional clutter map, transforming it into a six-dimensional clutter map. Utilizing the powerful data storage capacity and page-turning function of DDR3 SDRAM, clutter maps under different modes are partitioned for management. Each mode has a corresponding fixed space. The clutter space under the corresponding zone number is updated according to the current mode, while the previous state of the clutter space under other zones is retained, ensuring that a valid clutter map is always available in real-time during mode switching. A clutter silence switch is set up. During the initial stage of mode switching or when the radar is silent, the slave core can be controlled by the main core to enter a silent state and stop receiving data to update the clutter map, thus preventing invalid data from contaminating the original valid clutter map.

[0030] This invention comprises the following parts:

[0031] 1. The main core parses the control commands from the host computer, including working modes and status control, and controls the operation of the slave cores according to system requirements.

[0032] 2. Cores 1 through 6 perform their respective tasks according to the work control words sent by the main core. If the main core enables the silent state flag, the cores enter the idle working state; otherwise, they work normally.

[0033] 3. During the periodic operation of the core, the changes in the control status word are continuously queried, and the latest iteration coefficients and clutter parameter vector table are always used for clutter update and iteration.

[0034] The detailed steps are as follows:

[0035] Step 1: After the system powers on, the main core configures the SRIO interface and DDR3, partitions the DDR3 space, associates the mode number with the zone number, performs page flipping operations on the DDR3 sequentially, calculates the storage capacity for that mode, and allocates a corresponding size of clutter space. This completes the initialization of the clutter map.

[0036] Step Two: The main core enters the CPI-based cyclic operation phase, receiving commands from the host computer in real time, parsing control parameters, obtaining the current operating mode, and retrieving the clutter diagram parameter vector table [R_NUM, F_NUM, EL_NUM, AZ_NO, PRI_NO, MODE_NO, K] based on the mode. IOC R_NUM, F_NUM, and EL_NUM represent the number of range points, frequency points, and elevation beams, respectively; AZ_NO, PRI_NO, and MODE_NO represent the azimuth zone number (azimuth is a weekly scan, dividing one week into 256 regions, numbered from 0 to 255), PRI stagger number (0, 1, 2), and the zone number corresponding to the mode (0, 1, 2 correspond to normal search mode, low-altitude search mode, and high-altitude search mode, respectively), K IOC (Iteration On Coefficient) Clutter map iteration coefficients (iteration coefficient values ​​are greater than 0 and less than 1, applicable to various situations such as mobile operation, low-speed target detection, hovering helicopters, and radar silence). Once the parameter table is ready, it is placed in the L2 cache of each core at address (SHARED_LL2+No). core ×0X1000000),SHARED_LL2=0X1087FF00,No core For the nuclear number.

[0037] Step 3: The master core controls the processing mode of the slave cores based on the working status. First, it determines whether the current mode is the first operation after power-on. If so, the master core sets the clutter initial state flag of the corresponding clutter block to ENABLE, indicating that the slave core performs a single-cycle rapid clutter map establishment for that clutter block. Otherwise, it sets it to DISABLE, and the slave core performs routine clutter map updates. Second, the master core determines whether the radar system is currently in a silent state. If silent, it opens the clutter map silence switch; otherwise, it closes it. Finally, it compares the current mode with the previous cycle mode. If there is a change, the mode counter starts counting from 0 according to the CPI cycle, and the clutter map silence switch is opened to prevent invalid data from being used for clutter map updates during the initial mode switching, thus destroying the original valid clutter map. When the counter reaches n (n = 2, 3, 4, 5), the clutter map silence switch is closed, and the clutter map update process restarts. The clutter initial state flag and silence state flag are stored in the L2 of each core at address (SHARED_LL2 + No). core ×0X1000000+0X00000040),SHARED_LL2=0X1087FF00,No core For the nuclear number.

[0038] Step 4: First, from cores 1 to 6, retrieve the corresponding addresses SHARED_LL2+No. core×0X1000000+0X00000040 reads the working status word, queries the clutter silence status word, and determines that the slave core does not receive data from the FPGA and enters the idle state if it is ENABLE; otherwise, the slave core works normally. Next, the slave core determines whether the initial status identifier word is ENABLE. If it is, the slave core initializes the clutter map single-cycle enable matrix. The size of this matrix is ​​EL_NUM×AZ_NUM, where EL_NUM is the number of elevation beams and AZ_NUM is the number of azimuth blocks. The value range of this matrix is ​​{0,1}, where 0 represents non-single-cycle update and 1 represents single-cycle update. During initialization, all values ​​of the matrix are set to 1.

[0039] Step 5: From cores 1 to 6, the CPI cycle begins. First, the core starts from the corresponding address SHARED_LL2+No. core ×0X1000000 Read the clutter parameter vector table. Based on the parameter vector table, obtain the elevation beam number and azimuth area number of the clutter block to be processed from core 1 to 6 respectively. Determine whether the single-cycle enable matrix of the current clutter map is 1. If it is 1, proceed to step five; otherwise, proceed to step six.

[0040] Step Six: In each CPI cycle, the FPGA sends data for all elevation beams with azimuth number AZ_NO. As shown in the figure, assuming the number of elevation beams is K, corex receives the data for the (x+6*n)th beam, where n = (0, 1, 2…), x is the core number, and x+6*n <= K. After receiving the data, the core flips to the corresponding page in DDR3 based on MODE_NO, finds the clutter start address, and calculates the offset address of the clutter block for the current core's processed beam as R_NUM*F_NUM*(x+6*n)*AZ_NO*PRI_NO*4. The received data is then quickly sent to the corresponding location in DDR3 via EDMA, and the current block position corresponding to the single-cycle clutter map enable matrix is ​​set to 0. In one CPI cycle, the initial clutter map construction for all elevation beams is completed in parallel from cores 1 to 6. After the antenna completes one revolution, all azimuth area numbers are traversed, thus completing the initial clutter map construction. Since the PRI update is completed once per lap, it takes at least three laps to initially build the clutter map for all PRIs. It takes at least nine laps to initially build the clutter map for all modes. The initial clutter map construction is now complete.

[0041] Step 7: After the initial clutter map is built, the system enters a stable update phase. Following the method in Step 5, data is received from the core. The absolute address and offset address are obtained according to the parameter vector table. The previous clutter data is read from the corresponding address in DDR3. The clutter data is iteratively updated according to the following formula.

[0042] D(k)=K IOC ×D_fpga+(1-K IOC )×D(k-1)

[0043] Where K IOC Here, k represents the iteration coefficient, D_fpga represents the clutter block data sent by the FPGA, and the iterated data is quickly sent to the corresponding location in DDR3 via EDMA. This completes one iteration update of the clutter map. During operation, the slave core works under the control of the master core at CPI cycles, repeatedly iterating and updating the clutter map to meet the real-time requirements of target detection.

[0044] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the scope of the technology disclosed in the present invention, and such modifications or substitutions should all be covered within the scope of protection of the present invention.

Claims

1. A method for establishing a six-dimensional clutter map based on a multi-core DSP architecture, characterized in that... The steps are as follows: Step 1: After the system powers on, the main core configures the SRIO interface and DDR3, partitions the DDR3 space, associates the mode number with the zone number, performs page turning operations on the DDR3 in sequence, calculates the storage capacity of the mode, and allocates the corresponding size of noise space. Step Two: The main core enters the CPI-cycle working phase, receives commands from the host computer in real time, parses control parameters, obtains the current working mode, and obtains the clutter diagram parameter vector table [R_NUM, F_NUM, EL_NUM, AZ_NO, PRI_NO, MODE_NO, ...] based on the mode. R_NUM, F_NUM, and EL_NUM represent the number of range points, frequency points, and elevation beams, respectively; AZ_NO, PRI_NO, and MODE_NO represent the location zone number, PRI stagger number, and mode zone number corresponding to the current cycle, respectively. These are the clutter map iteration coefficients; once the parameter table is ready, it is placed in L2 of each core at address ( ), , For the verification number; Step 3: The master core controls the processing mode of the slave core according to the working status. First, it determines whether the current mode is the first working after power-on. If so, the master core sets the clutter initial state flag of the corresponding clutter block to ENABLE, indicating that the slave core performs a single-cycle fast clutter map establishment for the clutter block. Otherwise, it sets it to DISABLE, and the slave core performs the regular clutter map update. Secondly, the main core determines whether the radar system is currently in a silent state. If it is silent, the clutter map silence switch is turned on; otherwise, it is turned off. Finally, the current mode is compared with the previous cycle mode. If there is a change, the mode counter starts counting from 0 according to the CPI cycle, and the clutter map silence switch is turned on to prevent invalid data from being used for clutter map updates during the initial mode switching, thus destroying the original valid clutter map. When the counter reaches 2, 3, 4, or 5, the clutter map silence switch is turned off, and the clutter map update process restarts. The initial clutter state identifier and the silence state word are stored in the L2 of each core, at address ( ), , For the verification number; Step 4: First, start from the corresponding addresses of cores 1 to 6. Read the working status word, query the noise silence status word, and if it is ENABLE, the slave core will not receive data from the FPGA and will enter the idle state; otherwise, the slave core will work normally. Next, the kernel checks if the initial state identifier is ENABLE. If so, it initializes the clutter map single-cycle enable matrix from the kernel. The size of this matrix is... , The number of pitch beams, The matrix is ​​used to divide the area into blocks, and its range is... 0 represents non-single-cycle update, 1 represents single-cycle update, and the matrix is ​​initialized with all values ​​of 1. Step 5: From cores 1 to 6, the CPI cycle begins, starting from the corresponding address on each core. Read the clutter parameter vector table, and obtain the elevation beam number and azimuth area number of the clutter block to be processed from kernel 1 to 6 according to the parameter vector table. Determine whether the single-cycle enable matrix of the current clutter map is 1. If it is 1, proceed to step five; otherwise, proceed to step six. Step Six: In each CPI cycle, the FPGA sends data for all elevation beams with azimuth number AZ_NO. The number of elevation beams is K. CoreX receives the data for the (x+6*n)th beam, where n = 0, 1, 2, ..., x is the core number, and x+6*n <= K. After receiving the data, the core flips to the corresponding page in DDR3 according to MODE_NO, finds the clutter start address, and calculates the offset address of the clutter block for the current core's processed beam as R_NUM* F_NUM*(x+6*n)* AZ_NO* PRI_NO*4. The received data is then quickly sent to the corresponding position in DDR3 via EDMA, and the current block position corresponding to the single-cycle clutter map enable matrix is ​​set to 0. In one CPI cycle, the initial clutter map construction for all elevation beams is completed in parallel from cores 1 to 6. After the antenna completes one revolution, all azimuth area numbers are traversed, thus completing the initial clutter map construction. Step 7: After the initial clutter map is built, the system enters a stable update phase. Data is received from the core as in Step 5. The absolute address and offset address are obtained according to the parameter vector table. The previous clutter data is read from the corresponding address in DDR3. The clutter data is iteratively updated according to the following formula: in To identify the number of iterations, The clutter block data is sent to the FPGA; the iteratively completed data is quickly sent to the corresponding location in DDR3 via EDMA; one iteration update of the clutter map is completed; during operation, the slave core works in CPI cycle under the control of the master core, repeatedly iterating and updating the clutter map to meet the needs of target detection in real time.

2. A computer system, characterized in that... include: One or more processors, a computer-readable storage medium for storing one or more programs, wherein, when the one or more programs are executed by the one or more processors, the one or more processors cause the one or more processors to implement the method of claim 1.

3. A computer-readable storage medium, characterized in that... The device stores computer-executable instructions, which, when executed, are used to implement the method of claim 1.

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