FPGA-based camera link data encryption and detection repair device
The FPGA-based CameraLink data encryption, detection, and repair device solves the timing deviation problem after CameraLink data encryption, achieves accurate data stream restoration and decryption, and supports long-distance transmission.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING INST OF ENVIRONMENTAL FEATURES
- Filing Date
- 2022-10-31
- Publication Date
- 2026-06-23
Smart Images
Figure CN115630383B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of long-distance data transmission technology for CameraLink, and in particular to a CameraLink data encryption, detection and repair device and method based on FPGA. Background Technology
[0002] Currently, the CameraLink interface is the mainstream image output interface for industrial digital cameras, widely used in aerospace, medical, military, and security fields. In certain special application scenarios, there are high security requirements for digital images, thus necessitating the encryption of transmitted CameraLink data. Encryption methods are generally divided into two types: hardware encryption and software encryption. Hardware encryption implements the encryption process through hardware circuitry on embedded devices, while software encryption implements the encryption process through software on a computer. Hardware encryption has the advantage of strong resistance to brute-force attacks, and therefore is widely used in fields with high security requirements.
[0003] FPGAs, as programmable logic devices, are widely used in the field of hardware encryption. However, during the actual operation of FPGAs, timing violations or timing jitter may occur, which can cause deviations between the timing of the encrypted data stream and the timing of the data stream before encryption. In this case, after the encrypted data stream is transmitted and decrypted, it will be impossible to accurately restore the actual data stream, and it may even be unable to be decrypted normally. Summary of the Invention
[0004] In view of at least some of the above-mentioned shortcomings, the purpose of this invention is to provide an FPGA-based cameralink data encryption and detection repair device and method, which can quickly realize cameralink data encryption and perform timing detection and repair on the encrypted data stream.
[0005] In a first aspect, embodiments of the present invention provide a CameraLink data encryption and detection repair device based on FPGA, comprising:
[0006] The input module is used to receive the cameralink differential data output from the cameralink interface and convert it into a single-ended signal; the single-ended signal includes pixel clock C, image data, and line and field signals;
[0007] The stable clock module is used to obtain a stable clock C1 with the same phase and stable period based on the pixel clock C;
[0008] The sampling module is used to sample the acquired image data and line and field signals based on a stable clock C1 to obtain timing parameters T;
[0009] The encryption module is used to encrypt the acquired image data based on the pixel clock C, generate the encryption sequence D1, and call the sampling module to sample the encryption sequence D1 based on the stable clock C1 to obtain the timing parameter T1.
[0010] The comparison module is used to compare and determine the timing parameter T and timing parameter T1. If the timing parameter T and timing parameter T1 are exactly the same, the encrypted sequence D1 is used as the image encryption data and the output module is called; otherwise, the repair module is called.
[0011] The repair module is used to correct the encrypted sequence D1 based on the difference between the timing parameter T and the timing parameter T1, to obtain the encrypted sequence D3 that conforms to the timing parameter T, which is then used as image encryption data and the output module is called.
[0012] The output module is used to generate and output a CameraLink differential signal based on the pixel clock C and the image encryption data.
[0013] Optionally, the repair module includes an address generation module, on-chip RAM1, and on-chip RAM2; wherein, on-chip RAM1 is used to cache the encrypted sequence D1, and on-chip RAM2 is used to cache the encrypted sequence D3;
[0014] The repair module corrects the encrypted sequence D1 based on the difference between timing parameter T and timing parameter T1, including performing the following operations:
[0015] The address generation module determines the missing and / or redundant parts of the encryption sequence D1 based on the difference between the timing parameter T and the timing parameter T1.
[0016] The address generation module generates a read address and, based on the read address, reads the cached encryption sequence D1 from the on-chip RAM1 to obtain the data sequence D2; in the read address, for the missing part of the encryption sequence D1, the address of the previous data is repeated.
[0017] The address generation module generates a write address and writes the read data sequence D2 into the on-chip RAM2 based on the write address to cache the encrypted sequence D3 that conforms to the timing parameter T; in the write address, no write address is set for the redundant part of the encrypted sequence D1.
[0018] Optionally, the encryption module includes: an 8x frequency multiplication module, a random number generation module, and a data encryption operation module;
[0019] The encryption module encrypts the acquired image data based on the pixel clock C, generating an encryption sequence D1, including performing the following operations:
[0020] The 8x frequency multiplier module obtains an 8x frequency multiplier clock C2 based on the pixel clock C;
[0021] The random number generation module generates random binary encryption sequences based on an 8x clock frequency C2.
[0022] The data encryption operation module encrypts the acquired image data based on the binary encryption sequence to generate an encryption sequence D1.
[0023] Optionally, the data encryption operation module encrypts the acquired image data based on the binary encryption sequence, including:
[0024] The data encryption operation module performs bitwise XOR processing on the acquired image data based on the binary encryption sequence to achieve encryption.
[0025] Optionally, the stable clock module includes a phase-locked loop (PLL), with the input terminal of the PLL connected to the input module and the output terminal connected to the sampling module.
[0026] Secondly, embodiments of the present invention also provide a method for encrypting, detecting, and repairing CameraLink data, including:
[0027] Acquire the cameralink differential data output from the cameralink interface and convert it into a single-ended signal; the single-ended signal includes pixel clock C, image data, and line and field signals;
[0028] A stable clock C1 with the same phase and stable period is obtained based on the pixel clock C;
[0029] Based on a stable clock C1, the acquired image data and line and field signals are sampled to obtain timing parameters T;
[0030] The acquired image data is encrypted based on pixel clock C to generate encrypted sequence D1;
[0031] The encrypted sequence D1 is sampled based on a stable clock C1 to obtain the timing parameters T1;
[0032] Compare and determine the timing parameter T and timing parameter T1. If timing parameter T and timing parameter T1 are exactly the same, then use the encryption sequence D1 as the image encryption data; otherwise, continue execution.
[0033] Based on the difference between the timing parameter T and the timing parameter T1, the encryption sequence D1 is corrected to obtain the encryption sequence D3 that conforms to the timing parameter T, which is used as the image encryption data;
[0034] Based on the pixel clock C and the image encryption data, a CameraLink differential signal is generated and output.
[0035] Optionally, the step of correcting the encrypted sequence D1 based on the difference between the timing parameter T and the timing parameter T1 to obtain the encrypted sequence D3 that conforms to the timing parameter T includes:
[0036] Based on the difference between timing parameter T and timing parameter T1, the missing and / or redundant parts of the encrypted sequence D1 are determined;
[0037] Generate a read address, and based on the read address, read the cached encrypted sequence D1 to obtain the data sequence D2; in the read address, for the missing part of the encrypted sequence D1, repeat the address of the previous data.
[0038] Generate a write address, and write the read data sequence D2 into the buffer based on the write address; for the redundant part of the encrypted sequence D1, no write address is set;
[0039] Read the cached encrypted sequence D3 that conforms to the timing parameter T.
[0040] Optionally, the step of encrypting the acquired image data based on the pixel clock C to generate an encrypted sequence D1 includes:
[0041] The 8x clock C2 is obtained based on the pixel clock C;
[0042] A random binary encryption sequence is obtained using an RS flip-flop based on an 8x clock C2.
[0043] The acquired image data is encrypted based on the binary encryption sequence to generate an encryption sequence D1.
[0044] Optionally, encrypting the acquired image data based on the binary encryption sequence to generate an encryption sequence D1 includes:
[0045] Based on the binary encryption sequence, the acquired image data is XORed bitwise to achieve encryption.
[0046] Optionally, obtaining a stable clock C1 with the same phase and stable period based on the pixel clock C includes:
[0047] Based on the pixel clock C, a stable clock C1 with the same phase and stable period is obtained through a phase-locked loop.
[0048] This invention provides an FPGA-based CameraLink data encryption, detection, and repair device and method. The invention encrypts acquired image data and uses timing parameters obtained from stable pixel clock sampling for detection. If the timing parameters of the encrypted data differ from those of the data before encryption, the encrypted data is time-corrected based on these differences, thereby obtaining accurate and decryptable data and providing technical support for long-distance CameraLink data transmission. Attached Figure Description
[0049] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0050] Figure 1 This is a schematic diagram of a CameraLink data encryption, detection and repair device based on FPGA provided in an embodiment of the present invention;
[0051] Figure 2 This is a flowchart of a CameraLink data encryption, detection and repair method based on FPGA provided in an embodiment of the present invention. Detailed Implementation
[0052] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.
[0053] As mentioned earlier, when using FPGA to encrypt CameraLink data, timing violations or jitter may occur during actual operation. This can lead to a discrepancy between the timing of the encrypted data stream and the timing of the unencrypted data stream. In such cases, after transmission and decryption, the encrypted data stream cannot accurately reconstruct the actual data stream, and may even fail to decrypt properly. Therefore, a technical solution is needed that can detect and repair the timing of the encrypted data stream while encrypting it, in order to output accurate encrypted data. Currently, there is a lack of research on encrypting CameraLink data on an FPGA platform and performing timing detection and repair on the encrypted data stream. In view of this, this invention provides an FPGA-based CameraLink data encryption and timing detection and repair device and method.
[0054] Please refer to Figure 1 This invention provides an FPGA-based CameraLink data encryption, detection, and repair device, comprising: an input module, a stable clock module, a sampling module, an encryption module, a comparison module, a repair module, and an output module; specifically, wherein,
[0055] The input module is used to receive the CameraLink differential data output from the CameraLink interface and convert it into a single-ended signal; the single-ended signal includes pixel clock C, image data, and line and field signals;
[0056] The stable clock module is connected to the input module and is used to obtain a stable clock C1 with the same phase and stable period based on the pixel clock C.
[0057] The sampling module is connected to the input module and the stabilizing clock module. It is used to sample the acquired image data and line and field signals based on the stabilizing clock C1 to obtain the timing parameters T.
[0058] The encryption module is connected to the input module and the sampling module. It is used to encrypt the acquired image data based on the pixel clock C, generate the encryption sequence D1, and call the sampling module to sample the encryption sequence D1 based on the stable clock C1 to obtain the timing parameter T1.
[0059] The comparison module is connected to the sampling module and the encryption module. It is used to compare the timing parameter T and the timing parameter T1 and make a judgment based on the comparison result. If the timing parameter T and the timing parameter T1 are completely the same, that is, all the data in the two are the same, then the encryption sequence D1 is used as the image encryption data and the output module is called. Otherwise, it is considered that a timing error has occurred and the repair module is called.
[0060] The repair module is connected to the comparison module and is used to correct the encrypted sequence D1 based on the difference between the timing parameter T and the timing parameter T1 to obtain the encrypted sequence D3 that conforms to the timing parameter T. This D3 is then used as image encryption data and the output module is called.
[0061] The output module is connected to the repair module and is used to generate and output a CameraLink differential signal based on the pixel clock C and image encryption data.
[0062] Currently, there is a lack of research on encrypting CameraLink data on an FPGA platform and performing timing detection and repair on the encrypted data stream. This results in the inability to promptly verify and repair potentially timing errors in encrypted CameraLink data, affecting its transmission and use. This invention provides an FPGA-based CameraLink data encryption, detection, and repair device. It can not only quickly encrypt CameraLink data but also perform timing detection and repair on the encrypted image data, promptly identifying timing problems that arise after encryption. This invention encrypts the acquired image data and uses timing parameters sampled by a stable pixel clock (i.e., stable clock C1) for detection. If the timing parameters of the encrypted data differ from those of the unencrypted data, timing correction is performed on the encrypted data based on these differences, thereby obtaining accurate and decryptable data and providing technical support for long-distance CameraLink data transmission.
[0063] Alternatively, the input and output modules can be implemented using a CameraLink interface chip.
[0064] Optionally, the stable clock module includes a phase-locked loop (PLL), with its input connected to the input module and its output connected to the sampling module.
[0065] By inputting the pixel clock C into the phase-locked loop, a stable clock C1 with the same phase and stable period can be obtained. The stable clock C1 is also a pixel clock, but it is more stable and reliable than the pixel clock C.
[0066] Optionally, the sampling module samples the acquired image data and line and field signals to obtain timing parameters T. Timing parameters T may include line blanking length, line front shoulder length, line back shoulder length, line effective length, field blanking length, and field effective length. The sampling module samples the encrypted sequence D1 based on a stable clock C1 to obtain timing parameters T1. Timing parameters T1 correspond to timing parameters T and also include line blanking length, line front shoulder length, line back shoulder length, line effective length, field blanking length, and field effective length.
[0067] The above parameters can be used to effectively measure whether the sampled data have the same time sequence.
[0068] Optionally, the encryption module includes: an 8x frequency multiplication module, a random number generation module, and a data encryption operation module;
[0069] The encryption module encrypts the acquired image data based on the pixel clock C, generating an encryption sequence D1, including performing the following operations:
[0070] The 8x frequency multiplier module obtains an 8x frequency multiplier clock C2 based on the pixel clock C;
[0071] The random number generation module generates random binary encryption sequences based on an 8x clock frequency C2.
[0072] The data encryption operation module encrypts the acquired image data based on the binary encryption sequence to generate an encryption sequence D1.
[0073] The random number generation module can optionally use an RS flip-flop. By connecting an 8x clock C2 to the R, S, and CP terminals of the constructed RS flip-flop, the RS flip-flop operates in a metastable state. In this state, the Q terminal of the RS flip-flop generates a random binary sequence, which can be used as a binary encryption sequence. The pixel clock C corresponds to an 8-bit data stream. The binary encryption sequence obtained through the 8x clock C2 corresponds bit-by-bit with the image data and can be directly used to encrypt the image data.
[0074] Furthermore, the data encryption operation module encrypts the acquired image data based on the binary encryption sequence, including:
[0075] The data encryption operation module performs bitwise XOR processing on the acquired image data based on the binary encryption sequence to achieve encryption.
[0076] The above embodiments use XOR processing to encrypt image data, which is fast, resistant to brute-force attacks, and easy to decrypt given the binary encrypted sequence. Of course, other computational methods can also be used to achieve encryption in other embodiments.
[0077] Optionally, the repair module includes an address generation module, on-chip RAM1, and on-chip RAM2; wherein, on-chip RAM1 is used to cache the encrypted sequence D1, and on-chip RAM2 is used to cache the encrypted sequence D3;
[0078] The repair module corrects the encrypted sequence D1 based on the difference between timing parameter T and timing parameter T1, including performing the following operations:
[0079] The address generation module determines the missing and / or redundant parts of the encryption sequence D1 based on the difference between the timing parameter T and the timing parameter T1.
[0080] The address generation module generates a read address and, based on the read address, reads the cached encryption sequence D1 from the on-chip RAM1 to obtain the data sequence D2. In the read address, for the missing part of the encryption sequence D1, the address of the previous data is repeated. That is, for the missing part of the encryption sequence D1, the data of the previous address is read continuously, thereby completing the missing data of the encryption sequence D1 in the reading stage.
[0081] The address generation module generates a write address and writes the read data sequence D2 into the on-chip RAM2 based on the write address to cache the encrypted sequence D3 that conforms to the timing parameter T. In the write address, no write address is set for the redundant part of the encrypted sequence D1. That is, no data is written to the on-chip RAM2 for the redundant part of the encrypted sequence D1, thereby removing the redundant data of the encrypted sequence D1 in the writing process, so that the encrypted sequence D3 cached in the on-chip RAM2 conforms to the timing parameter T.
[0082] The above embodiment completes the missing parts of the encrypted sequence D1 and removes the redundant parts by reading and writing data between on-chip RAM1 and on-chip RAM2. The processing speed is fast and it can be used for implementation.
[0083] In a specific embodiment, an address signal A and a status control signal S are generated based on the difference between timing parameter T and timing parameter T1. The generation mechanism of address signal A and status control signal S is as follows: When there is a portion where timing parameter T is greater than timing parameter T1, i.e., there is a missing part in the encrypted sequence D1, the address signal A for the corresponding portion (i.e., the missing part) remains unchanged, and the status control signal S is set to a high level, meaning that data from the previous address is continuously read to complete the missing data in the encrypted sequence D1. When there is a portion where timing parameter T is less than timing parameter T1, i.e., there is a redundant part in the encrypted sequence D1, the address signal A for the corresponding portion (i.e., the redundant part) increments, and the status control signal S is set to a low level. When writing the read data to on-chip RAM2, an address write signal A1 is generated based on the status control signal S. When the status control signal S is low, the address write signal A1 is 0, and no data is written, thereby removing redundant data from the encrypted sequence D1 during the writing process. During invocation, an address read signal A2 is generated based on timing parameter T, and the on-chip RAM2 is read to obtain the encrypted sequence D3 that conforms to timing parameter T.
[0084] Optionally, the device further includes a verification module, which connects the repair module and the output module. The verification module is used to call the sampling module to sample the encrypted sequence D3 based on a stable clock C1 to obtain timing parameters T2, and to call the comparison module to compare timing parameters T and T2 and make a judgment. If timing parameters T and T2 are exactly the same, then the encrypted sequence D3 is used as the image encryption data; otherwise, the output is stopped.
[0085] The above embodiments perform a second verification on the output encrypted sequence D3 to ensure that the output image encrypted data remains stable.
[0086] like Figure 2 As shown, the present invention also provides a CameraLink data encryption and detection repair method based on FPGA, including:
[0087] Step 200: Obtain the cameralink differential data output from the cameralink interface and convert it into a single-ended signal; the single-ended signal includes pixel clock C, image data, and line and field signals;
[0088] Step 202: Obtain a stable clock C1 with the same phase and stable period based on the pixel clock C;
[0089] Step 204: Based on the stable clock C1, sample the acquired image data and line and field signals to obtain timing parameters T;
[0090] Step 206: Encrypt the acquired image data based on the pixel clock C to generate an encrypted sequence D1;
[0091] Step 208: Sample the encrypted sequence D1 based on the stable clock C1 to obtain the timing parameters T1;
[0092] Step 210: Compare and determine the timing parameter T and timing parameter T1. If the timing parameter T and timing parameter T1 are exactly the same, use the encryption sequence D1 as the image encryption data and skip step 212; otherwise, continue to execute step 212.
[0093] Step 212: Based on the difference between the timing parameter T and the timing parameter T1, the encryption sequence D1 is corrected to obtain the encryption sequence D3 that conforms to the timing parameter T, which is used as the image encryption data;
[0094] Step 214: Based on the pixel clock C and the image encryption data, generate and output the CameraLink differential signal.
[0095] The above embodiments provide a cameralink data encryption, detection and repair method based on FPGA, which can encrypt cameralink data on the FPGA platform and perform timing detection and repair on the encrypted data stream, so as to promptly check and repair the cameralink data in the event of timing errors after encryption, and provide technical support for cameralink data transmission.
[0096] Optionally, step 202 includes:
[0097] Based on the pixel clock C, a stable clock C1 with the same phase and stable period is obtained through a phase-locked loop.
[0098] A phase-locked loop (PLL) can quickly provide a more stable and in-phase pixel clock.
[0099] Optionally, step 206 includes:
[0100] The 8x clock C2 is obtained based on the pixel clock C;
[0101] A random binary encryption sequence is obtained using an RS flip-flop based on an 8x clock C2.
[0102] The acquired image data is encrypted based on the binary encryption sequence to generate an encryption sequence D1.
[0103] Further, the step of encrypting the acquired image data based on the binary encryption sequence to generate an encryption sequence D1 includes:
[0104] Based on the binary encryption sequence, the acquired image data is XORed bitwise to achieve encryption.
[0105] Using the above method, a brute-force resistant encrypted sequence can be obtained quickly.
[0106] Optionally, step 212 includes:
[0107] Based on the difference between timing parameter T and timing parameter T1, the missing and / or redundant parts of the encrypted sequence D1 are determined;
[0108] Generate a read address, and based on the read address, read the cached encrypted sequence D1 to obtain the data sequence D2; in the read address, for the missing part of the encrypted sequence D1, repeat the address of the previous data.
[0109] Generate a write address, and write the read data sequence D2 into the buffer based on the write address; for the redundant part of the encrypted sequence D1, no write address is set;
[0110] Read the cached encrypted sequence D3 that conforms to the timing parameter T, and use it as the image encryption data.
[0111] The aforementioned FPGA-based CameraLink data encryption, detection, and repair method can be implemented based on any of the FPGA-based CameraLink data encryption, detection, and repair devices described above.
[0112] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0113] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as ROM, RAM, magnetic disk, or optical disk.
[0114] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A CameraLink data encryption, detection, and repair device based on FPGA, characterized in that, include: The input module is used to receive the cameralink differential data output from the cameralink interface and convert it into a single-ended signal; the single-ended signal includes pixel clock C, image data, and line and field signals; The stable clock module is used to obtain a stable clock C1 with the same phase and stable period based on the pixel clock C; The sampling module is used to sample the acquired image data and line and field signals based on a stable clock C1 to obtain timing parameters T; The encryption module is used to encrypt the acquired image data based on the pixel clock C, generate the encryption sequence D1, and call the sampling module to sample the encryption sequence D1 based on the stable clock C1 to obtain the timing parameter T1. The comparison module is used to compare and determine the timing parameter T and timing parameter T1. If the timing parameter T and timing parameter T1 are exactly the same, the encrypted sequence D1 is used as the image encryption data and the output module is called; otherwise, the repair module is called. The repair module is used to correct the encrypted sequence D1 based on the difference between the timing parameter T and the timing parameter T1, to obtain the encrypted sequence D3 that conforms to the timing parameter T, which is then used as image encryption data and the output module is called. The repair module includes an address generation module, on-chip RAM1, and on-chip RAM2; wherein, on-chip RAM1 is used to cache encrypted sequence D1, and on-chip RAM2 is used to cache encrypted sequence D3; The repair module corrects the encrypted sequence D1 based on the difference between timing parameter T and timing parameter T1, including performing the following operations: The address generation module determines the missing and / or redundant parts of the encryption sequence D1 based on the difference between the timing parameter T and the timing parameter T1. The address generation module generates a read address and, based on the read address, reads the cached encryption sequence D1 from the on-chip RAM1 to obtain the data sequence D2; in the read address, for the missing part of the encryption sequence D1, the address of the previous data is repeated. The address generation module generates a write address and writes the read data sequence D2 into the on-chip RAM2 based on the write address to cache the encrypted sequence D3 that conforms to the timing parameter T; in the write address, no write address is set for the redundant part of the encrypted sequence D1; The output module is used to generate and output a CameraLink differential signal based on the pixel clock C and the image encryption data.
2. The apparatus according to claim 1, characterized in that, The encryption module includes: an 8x frequency multiplication module, a random number generation module, and a data encryption calculation module; The encryption module encrypts the acquired image data based on the pixel clock C, generating an encryption sequence D1, including performing the following operations: The 8x frequency multiplier module obtains an 8x frequency multiplier clock C2 based on the pixel clock C; The random number generation module generates random binary encryption sequences based on an 8x clock frequency C2. The data encryption operation module encrypts the acquired image data based on the binary encryption sequence to generate an encryption sequence D1.
3. The apparatus according to claim 2, characterized in that, The data encryption operation module encrypts the acquired image data based on the binary encryption sequence, including: The data encryption operation module performs bitwise XOR processing on the acquired image data based on the binary encryption sequence to achieve encryption.
4. The apparatus according to claim 1, characterized in that, The stable clock module includes a phase-locked loop (PLL), with its input connected to the input module and its output connected to the sampling module.
5. A method for encrypting, detecting, and repairing CameraLink data based on FPGA, characterized in that, The method, applied to the apparatus as described in any one of claims 1-4, comprises: Acquire the cameralink differential data output from the cameralink interface and convert it into a single-ended signal; the single-ended signal includes pixel clock C, image data, and line and field signals; A stable clock C1 with the same phase and stable period is obtained based on the pixel clock C; Based on a stable clock C1, the acquired image data and line and field signals are sampled to obtain timing parameters T; The acquired image data is encrypted based on pixel clock C to generate encrypted sequence D1; The encrypted sequence D1 is sampled based on a stable clock C1 to obtain the timing parameters T1; Compare and determine the timing parameter T and timing parameter T1. If timing parameter T and timing parameter T1 are exactly the same, then use the encryption sequence D1 as the image encryption data; otherwise, continue execution. Based on the difference between the timing parameter T and the timing parameter T1, the encryption sequence D1 is corrected to obtain the encryption sequence D3 that conforms to the timing parameter T, which is used as the image encryption data; Based on the pixel clock C and the image encryption data, a CameraLink differential signal is generated and output.
6. The method according to claim 5, characterized in that, The step of correcting the encrypted sequence D1 based on the difference between the timing parameter T and the timing parameter T1 to obtain the encrypted sequence D3 that conforms to the timing parameter T includes: Based on the difference between timing parameter T and timing parameter T1, the missing and / or redundant parts of the encrypted sequence D1 are determined; Generate a read address, and based on the read address, read the cached encrypted sequence D1 to obtain the data sequence D2; in the read address, for the missing part of the encrypted sequence D1, repeat the address of the previous data. Generate a write address, and write the read data sequence D2 into the buffer based on the write address; for the redundant part of the encrypted sequence D1, no write address is set; Read the cached encrypted sequence D3 that conforms to the timing parameter T.
7. The method according to claim 5, characterized in that, The process of encrypting the acquired image data based on pixel clock C to generate an encryption sequence D1 includes: The 8x clock C2 is obtained based on the pixel clock C; A random binary encryption sequence is obtained using an RS flip-flop based on an 8x clock C2. The acquired image data is encrypted based on the binary encryption sequence to generate an encryption sequence D1.
8. The method according to claim 7, characterized in that, The step of encrypting the acquired image data based on the binary encryption sequence to generate an encryption sequence D1 includes: Based on the binary encryption sequence, the acquired image data is XORed bitwise to achieve encryption.
9. The method according to claim 5, characterized in that, The process of obtaining a stable clock C1 with the same phase and stable period based on the pixel clock C includes: Based on the pixel clock C, a stable clock C1 with the same phase and stable period is obtained through a phase-locked loop.