Layout pattern of static random access memory
By employing a stepped gate structure design with finned or planar transistors in SRAM devices, spanning more finned structures, the problem of difficult pattern exposure in existing SRAM devices is solved, improving the read speed and space utilization efficiency of pull-down devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- UNITED MICROELECTRONICS CORP
- Filing Date
- 2016-08-01
- Publication Date
- 2026-06-16
AI Technical Summary
The fabrication of existing SRAM devices is difficult to achieve using existing architectures for pattern exposure, resulting in poor exposure quality and affecting device performance.
Static random access memory layout patterns using finned transistors or planar transistors are employed. The gate structure of the pull-down element is designed to be stepped or other non-elongated, spanning more finned structures to increase the gate width and thus increase the current.
Within a limited space, the read speed and efficiency of pull-down elements were improved, thereby enhancing the overall processing speed of the static random access memory.
Smart Images
Figure CN115666126B_ABST
Abstract
Description
[0001] This application is a divisional application of Chinese invention patent application (application number: 201610616761.9, application date: August 1, 2016, invention title: layout pattern of static random access memory). Technical Field
[0002] This invention relates to a static random access memory (SRAM), and more particularly to a layout pattern for a static random access memory (SRAM) that increases yield and improves read speed. Background Technology
[0003] An embedded static random access memory (SRAM) contains logic circuitry and SRAM connected to the logic circuitry. SRAM itself is a volatile memory cell, meaning that the stored data is erased when the power supply to the SRAM is lost. SRAM stores data using the conductivity state of transistors within the memory cells. SRAM is designed based on intercoupled transistors, eliminating the need for capacitor discharge and continuous charging to prevent data loss; in other words, it does not require memory updates. This differs from Dynamic Random Access Memory (DRAM), which also uses capacitors for data storage. SRAM offers very fast access speeds and is therefore used in computer systems as cache memory.
[0004] However, with the reduction in linewidth and exposure spacing in manufacturing processes, it is now difficult to expose the desired patterns using existing SRAM device architectures. Therefore, improving the architecture of existing SRAM devices to enhance exposure quality has become an important issue. Summary of the Invention
[0005] This invention provides a layout pattern for a static random access memory (SRAM) comprising at least two inverters coupled together to store data. The two inverters include a first inverter and a second inverter. Each inverter includes at least one pull-up element (PLs) and at least one pull-down element (PDs). At least two access elements (PGs) are respectively connected to the outputs of the two coupled inverters. Each pull-up element (PLs), each pull-down element (PDs), and each access element (PGs) includes a finned transistor (FIT). An nFET (internal field-effect transistor) is provided, wherein multiple fin structures are located on the substrate, and the fin structures include at least one first fin structure, at least one second fin structure, at least one third fin structure, at least one fourth fin structure, and at least one fifth fin structure. Each inverter includes a stepped gate structure, the stepped gate structure including a first portion and a second portion arranged along a first direction, and a bridging portion connecting the first portion and the second portion, the bridging portion being arranged along a second direction, wherein the first direction and the second direction are perpendicular to each other. The first portion spans the at least one first fin structure, and the second portion spans the at least one second fin structure and forms the at least one pull-down element (PDs). The first portion spans the at least one third fin structure and forms the at least one pull-up element (PLs). Each inverter includes a first access gate structure and a second access gate structure, located on the substrate. The first access gate structure and the first portion of the stepped gate structure are aligned in the same direction, and the first access gate structure and the first portion have the same axis of symmetry. The second access gate structure is aligned in the same direction as the second portion of the stepped gate structure, and the second access gate structure and the second portion have the same other axis of symmetry. The first access gate structure spans the at least one fourth fin structure and forms one of the at least two access elements (PGs). The second access gate structure spans the at least one fifth fin structure and forms the other of the at least two access elements (PGs). There is also at least one first extended contact structure spanning the at least one first fin structure and the at least one second fin structure.
[0006] The present invention further provides a layout pattern for a static random access memory (SRAM) comprising at least two inverters coupled together to store data. The two inverters include a first inverter and a second inverter. Each inverter includes at least one pull-up element (PLs) and at least one pull-down element (PDs). At least two access elements (PGs) are respectively connected to the output terminals of the two coupled inverters. Each pull-up element (PLs), each pull-down element (PDs), and each access element (PGs) includes a planar transistor. The transistor comprises multiple diffusion regions located on the substrate, the diffusion regions including at least one first diffusion region, at least one second diffusion region, and at least one third diffusion region. Each inverter includes a stepped gate structure, the stepped gate structure including a first portion and a second portion arranged along a first direction, and a bridging portion connecting the first portion and the second portion, the bridging portion being arranged along a second direction, wherein the first direction and the second direction are perpendicular to each other, wherein the first portion spans the at least one first diffusion region and the second portion spans the at least one second diffusion region and forms the at least one pull-down element (PDs), wherein the first portion spans the at least one third diffusion region and forms the at least one pull-up element (PLs), and each inverter includes a first storage... A first access gate structure and a second access gate structure are located on the substrate, wherein the first access gate structure and the first portion of the stepped gate structure are aligned in the same direction and have the same axis of symmetry, the second access gate structure and the second portion are aligned in the same direction and have the same axis of symmetry, wherein the first access gate structure spans the at least one first diffusion region and forms one of the at least two access elements (PGs), wherein the second access gate structure spans the at least one second diffusion region and forms the other of the at least two access elements (PGs), and at least one first extended contact structure spans the at least one first diffusion region and the at least one second diffusion region.
[0007] The present invention is characterized in that the gate structure of the pull-down element PDs is not limited to a long strip structure, but can be designed as a stepped or other shape to achieve the purpose of spanning a greater number of fin structures. In this way, the limited space can be utilized more efficiently and the read speed of the pull-down element PDs can be further improved. Attached Figure Description
[0008] Figure 1 This is a circuit diagram of a group of eight-transistor static random access memory (8T-SRAM) storage cells in the static random access memory of the present invention.
[0009] Figure 2 This is a layout diagram of a static random access memory according to a first preferred embodiment of the present invention;
[0010] Figure 3 Draw Figure 2 A sectional view obtained along section line A-A';
[0011] Figure 4 This is a layout diagram of a static random access memory according to another preferred embodiment of the present invention;
[0012] Figure 5 Draw Figure 4 A sectional view obtained along section line B-B';
[0013] Figure 6 Draw Figure 4 A sectional view obtained along section line C-C';
[0014] Figure 7 This is a layout diagram of a static random access memory according to a second preferred embodiment of the present invention;
[0015] Figure 8 This is a layout diagram of a static random access memory according to another preferred embodiment of the present invention.
[0016] Symbol Explanation
[0017] 10 8T-SRAM memory cells
[0018] 10' 8T-SRAM memory cell
[0019] 11 Specific range
[0020] 11A Boundary
[0021] 24 storage nodes
[0022] 26 storage nodes
[0023] 28 Series circuit
[0024] 30 Series circuit
[0025] 52 base
[0026] 54 Fin-like structures
[0027] 54A First fin structure
[0028] 54B Second Fin Structure
[0029] 54C Third fin structure
[0030] 54D Fourth Fin Structure
[0031] 54E Fifth fin structure
[0032] 54F Sixth Fin Structure
[0033] 54A' Fin-like structure
[0034] 54B' Fin-like structure
[0035] 54D' fin structure
[0036] 54E' Fin-like structure
[0037] 55A and 55B stepped gate structure
[0038] 56A Part 1
[0039] 56B Part Two
[0040] 56C Bridging Section
[0041] 57 Contact Structure
[0042] 58A First Diffusion Region
[0043] 58B Second Diffusion Region
[0044] 58C Third Diffusion Region
[0045] 58D Fourth Diffusion Region
[0046] 58E Fifth Diffusion Region
[0047] 58F Sixth Diffusion Zone
[0048] 60A, 60B First Access Gate Structure
[0049] 62A, 62B Second Access Gate Structure
[0050] 72A, 72B Extended Contact Structure
[0051] 72A-1, 72A-2 Extended Contact Structure
[0052] 72B-1, 72B-2 Extended Contact Structure
[0053] 73A and 73B contact structures
[0054] 74A and 74B contact structures
[0055] 76A and 76B contact structures
[0056] 78A and 78B contact structures
[0057] 80A and 80B contact structures
[0058] 82A, 80B contact structure
[0059] 84A and 84B contact structures
[0060] 86A and 86B contact structures
[0061] 88A and 88B contact structures
[0062] PL1 First Pull-up Component
[0063] PD1 First pull-down element
[0064] PL2 Second Pull-up Component
[0065] PD2 Second Pull-down Component
[0066] PG1 First Access Element
[0067] PG2 Second Access Element
[0068] PG3 Third Access Element
[0069] PG4 Fourth Access Element
[0070] Vcc voltage source
[0071] Vss voltage source
[0072] BL1 bit line
[0073] BL2 bit line
[0074] BL3 bit line
[0075] BL4 bit line
[0076] WL character line
[0077] WL1 character line
[0078] WL2 character line
[0079] O Center
[0080] A-A' section line
[0081] B-B' section line
[0082] C-C' section line Detailed Implementation
[0083] To enable those skilled in the art to further understand the present invention, preferred embodiments of the present invention are described below, and the composition and desired effects of the present invention are explained in detail with reference to the accompanying drawings.
[0084] For ease of explanation, the accompanying drawings are merely illustrative to facilitate understanding of the invention, and their detailed proportions can be adjusted according to design requirements. The vertical relationships of relative elements in the drawings described herein should be understood by those skilled in the art to refer to the relative positions of objects; therefore, all can be flipped to present the same components, and this should all fall within the scope of this specification, as stated herein.
[0085] Please refer to Figure 1 and Figure 2 , Figure 1 This is a circuit diagram of a group of eight-transistor SRAM (8T-SRAM) memory cells in the static random access memory of the present invention. Figure 2 This is a layout diagram of a static random access memory according to a preferred embodiment of the present invention.
[0086] like Figure 1 and Figure 2 As shown, the static random access memory of the present invention preferably includes at least one set of static random access memory cells, wherein each static random access memory cell includes an eight-transistor static random access memory cell (8T-SRAM) 10.
[0087] Please refer to Figure 1 In this embodiment, each 8T-SRAM memory cell 10 preferably consists of a first pull-up device PL1, a second pull-up device PL2, a first pull-down transistor PD1, a second pull-down transistor PD2, a first pass gate device PG1, a second pass gate device PG2, a third pass gate device PG3, and a fourth pass gate device PG4 forming a flip-flop. The first pull-up device PL1 and the second pull-up device PL2, and the first pull-down device PD1 and the second pull-down device PD2 form a latch circuit, allowing data to be latched to storage nodes 24 or 26. Furthermore, the first pull-up device PL1 and the second pull-up device PL2 serve as active loads; they can also be replaced by ordinary resistors as pull-up devices, in which case it becomes a four-transistor static random access memory (4T-SRAM). In this embodiment, a source region of each of the first pull-up element PL1 and the second pull-up element PL2 is electrically connected to a voltage source Vcc, and a source region of each of the first pull-down element PD1 and the second pull-down element PD2 is electrically connected to a voltage source Vss.
[0088] In one embodiment, the first pull-up element PL1 and the second pull-up element PL2 of the 8T-SRAM memory cell 10 are composed of P-type metal oxide semiconductor (PMOS) transistors, while the first pull-down element PD1, the second pull-down element PD2, the first access element PG1, the second access element PG2, the third access element PG3, and the fourth access element PG4 are composed of N-type metal oxide semiconductor (NMOS) transistors. However, the present invention is not limited thereto. The first pull-up element PL1 and the first pull-down element PD1 together constitute an inverter, and the two ends of the series circuit 28 formed by these two elements are respectively coupled to a voltage source Vcc and a voltage source Vss. Similarly, the second pull-up element PL2 and the second pull-down element PD2 constitute another inverter, and the two ends of the series circuit 30 formed by these two elements are also respectively coupled to a voltage source Vcc and a voltage source Vss. Each of the above access elements (including the first access element PG1, the second access element PG2, the third access element PG3 and the fourth access element PG4) is connected to the output terminal of the two mutually coupled inverters, wherein each pull-up element, each pull-down element and each access element includes a finned transistor (FinFET).
[0089] Furthermore, at memory node 24, the gates of the second pull-down element PD2 and the second pull-up element PL2 are electrically connected, as are the drains of the first pull-down element PD1, the first pull-up element PL1, the first access element PG1, and the second access element PG2. Similarly, at memory node 26, the gates of the first pull-down element PD1 and the first pull-up element PL1 are electrically connected, as are the drains of the second pull-down element PD2, the second pull-up element PL2, the third access element PG3, and the fourth access element PG4. The gates of the first access element PG1 and the third access element PG3 are respectively coupled to a word line WL1, the gates of the second access element PG2 and the fourth access element PG4 are respectively coupled to a word line WL2, the source of the first access element PG1 is coupled to the corresponding bit line BL1, the source of the second access element PG2 is coupled to the corresponding bit line BL2, the source of the third access element PG3 is coupled to the corresponding bit line BL3, and the source of the fourth access element PG4 is coupled to the corresponding bit line BL4.
[0090] Please refer to Figure 2In this embodiment, the 8T-SRAM memory cell 10 is disposed on a substrate 52, such as a silicon substrate or a silicon-on-insulator (SOI) substrate. The substrate 52 is provided with a plurality of parallel fin structures 54, and each fin structure 54 is surrounded by a shallow trench isolation (not shown).
[0091] In this invention, the same gate structure spans multiple parallel fin structures simultaneously, which helps to increase the gate width of the fin transistor. In other words, in the equivalent circuit, it is equivalent to multiple transistors connected in parallel. Therefore, within a limited fixed space, the read current value (Iread) of the fin transistor can be increased, and the overall SRAM operation speed can be accelerated.
[0092] The present invention is characterized in that each inverter includes at least one stepped gate structure 55A, 55B located on the substrate 52, that is, both stepped gate structures 55A and 55B have a stepped layout pattern (appearing stepped in the top view). The two stepped gate structures 55A and 55B are symmetrically arranged (to... Figure 2 (The center points O on the top are symmetrically arranged). To simplify the explanation, only one of the stepped gate structures 55A is described in this embodiment. The two stepped gate structures 55A and 55B are completely identical except for their symmetrical structure.
[0093] Both the stepped gate structure 55A and the stepped gate structure 55B include a first portion 56A, a second portion 56B, and a bridging portion 56C connecting the first portion 56A and the second portion 56B. More specifically, both the first portion 56A and the second portion 56B are arranged along a first direction (e.g., ...). Figure 2 The bridging portion 56C is located between the first portion 56A and the second portion 56B, and electrically connects the first portion 56A and the second portion 56B. Furthermore, the bridging portion 56C is preferably arranged along a second direction (e.g., the X direction in the first part of the first part). Figure 2 The first and second directions are preferably perpendicular to each other, but not limited to this. In addition, the first part 56A and the second part 56B contain different axes of symmetry, that is, the shortest distance between the first part 56A and the second part 56B is approximately equal to the length of the bridging part 56C (if the bridging part 56C is perpendicular to the first part 56A or the second part 56B).
[0094] It is worth noting that in this embodiment, the 8T-SRAM memory cell 10 is located within a specific range 11, meaning that the specific range 11 contains only one set of 8T-SRAM memory cells 10. The second part 56B is adjacent to one boundary of the aforementioned specific range 11. Figure 2 The Chinese standard designation is 11A.
[0095] The aforementioned stepped gate structures 55A and 55B span multiple fin structures 54. For example, the fin structures 54 are designated as first fin structure 54A, second fin structure 54B, third fin structure 54C, fourth fin structure 54D, fifth fin structure 54E, and sixth fin structure 54F. Additionally, fin structures 54A', 54B', 54D', and 54E' are located on the substrate 52. The stepped gate structure 55A spans the first fin structure 54A, second fin structure 54B, and third fin structure 54C, while the stepped gate structure 55B spans the fourth fin structure 54D, fifth fin structure 54E, and sixth fin structure 54F. It is worth noting that in this embodiment, the number of the first fin structure 54A, the second fin structure 54B, the fourth fin structure 54D, and the fifth fin structure 54E is greater than 1. This includes four parallel first fin structures 54A, two parallel second fin structures 54B, one third fin structure 54C, four parallel fourth fin structures 54D, two parallel fifth fin structures 54E, and one sixth fin structure 54F. However, the number of each of the above fin structures (including the first to sixth fin structures and fin structures 54A', 54B', 54D', and 54E') is not limited to this; it can be any integer greater than or equal to 1, and can be adjusted according to actual needs.
[0096] In this embodiment, the first portion 56A of the stepped gate structure 55A spans the first fin structure 54A and the third fin structure 54C, while the second portion 56B spans the second fin structure 54B. The portion of the first portion 56A that spans the third fin structure 54C forms the gate of the first pull-up element PL1; the portion of the first portion 56A that spans the first fin structure 54A, and the portion of the second portion 56B that spans the second fin structure 54B, together constitute the gate of the first pull-down element PD1. Figure 2 The area within the dashed line represents the range of the first pull-down element PD1.
[0097] Therefore, the first pull-down element PD1 includes a stepped gate structure 55A that spans a total of 6 fin structures (including the four first fin structures 54A spanned by the first part 56A and the two second fin structures 54B spanned by the second part 56B). Thus, within a limited space, the number of fin structures spanned by the gate structure is increased, thereby increasing the gate width (channel width) of the first pull-down element PD1, further increasing the current through the first pull-down element PD1, and accelerating the read speed of the first pull-down element PD1.
[0098] In addition to the stepped gate structure described above, each inverter in this embodiment includes a first access gate structure and a second access gate structure, that is, it also includes at least two mutually symmetrical first access gate structures 60A and 60B and two mutually symmetrical second access gate structures 62A and 62B located on the substrate 52. For the sake of simplicity, only the first access gate structure 60A and the second access gate structure 62A will be described here. The two first access gate structures 60A and 60B and the two second access gate structures 62A and 62B are completely identical except for their structural symmetry.
[0099] Preferably, the first access gate structure 60A is arranged along a first direction and is located in the extension direction of the first portion 56A. In other words, the first portion 56A and the first access gate structure 60 have the same axis of symmetry S1. The first access gate structure 60A spans the fin structure 54B' and forms the gate of the first access element PG1. Furthermore, the bridging portion 56C is located between the first access gate structure 60 and the first portion 56A. Similarly, the first access gate structure 60B spans the fin structure 54E' and forms the gate of the third access element PG3, with the remaining features being the same.
[0100] The second access gate structure 62A is also arranged along the first direction and is located in the extension direction of the second portion 56B. In other words, the second portion 56B and the second access gate structure 62A share the same axis of symmetry S2. The second access gate structure 62A spans the fin structure 54A' and forms the gate of the second access element PG2. Furthermore, the bridging portion 56C is located between the second access gate structure 62A and the second portion 56B. Similarly, the second access gate structure 62B spans the fin structure 54D' and forms the gate of the fourth access element PG4.
[0101] Therefore, from Figure 2 As can be seen, the stepped gate structure 55A in this embodiment presents a stepped or Z-shaped form, while the first access gate structure 60A and the second access gate structure 62A are located on both sides of the stepped gate structure 55A. For example, the first access gate structure 60A is located on the lower left side of the stepped gate structure 55A, while the second access gate structure 62A is located on the upper right side of the stepped gate structure 55A.
[0102] In addition to the aforementioned fin structure and gate structure, the 8T-SRAM memory cell 10 in this embodiment also includes a plurality of contact structures. These include at least two symmetrically arranged extending contact structures 72A and 72B, wherein extending contact structure 72A spans across each of the first fin structures 54A, each of the second fin structures 54B, and the third fin structure 54C, and extending contact structure 72B spans across each of the fourth fin structures 54D, each of the fifth fin structures 54E, and the sixth fin structure 54F, electrically connecting the parallel fin structures to each other. Figure 1 As seen in the view, the extended contact structure 72A connects the drains of the first pull-down element PD1, the first pull-up element PL1, the first access element PG1, and the second access element PG2. Furthermore, as seen in the top view, the extended contact structures 72A and 72B may be elongated or have other shapes (e.g., L-shaped), and the invention is not limited to these. In addition, for a cross-sectional view, please refer to... Figure 3 Its illustration Figure 2 The cross-sectional view obtained along section line A-A'. The aforementioned bridging portion 56C and the extended contact structure 72A or extended contact structure 72B are located in different layers of the structure. Figure 3 (Only the extended contact structure 72A is shown as an example). The bridging portion 56C preferably spans over the extended contact structure 72A or the extended contact structure 72B, but is not electrically connected to the extended contact structures 72A and 72B. In addition, a contact structure 57 may also be included between the bridging portion 56C and the first portion 56A and the second portion 56B.
[0103] In another embodiment of the present invention, each stepped gate structure 55A, 55B is an integrally formed structure, that is, the first portion 56A, the second portion 56B, and the bridging portion 56C are all located in the same layer and fabricated simultaneously. In this embodiment, the extended contact structures 72A, 72B extend over the bridging portion 56C but are not electrically connected to the bridging portion 56C. For more detailed description, please refer to... Figure 4 , Figure 4 This is a layout diagram of a static random access memory (SRAM) according to another preferred embodiment of the present invention. Each stepped gate structure 55A and 55B is integrally formed, and the extended contact structure 72A includes extended contact structure 72A-1 and extended contact structure 72A-2, respectively located on both sides of the bridging portion 56C of the stepped gate structure 55A. Similarly, the extended contact structure 72B includes extended contact structure 72B-1 and extended contact structure 72B-2, respectively located on both sides of the bridging portion 56C of the stepped gate structure 55B. This embodiment also includes two bridging structures 73A and 73B, which should be referred to accordingly. Figure 5 and Figure 6 , Figure 5 Draw Figure 4The sectional view obtained along section line B-B'. Figure 6 Draw Figure 4 The cross-sectional view obtained along section line C-C' shows that bridging structure 73A spans the bridging portion 56C of stepped gate structure 55A and is electrically connected to extended contact structures 72A-1 and 72A-2; bridging structure 73B spans the bridging portion 56C of stepped gate structure 55B and is electrically connected to extended contact structures 72B-1 and 72B-2. Furthermore, a contact structure 75 may be included between bridging structure 73A and extended contact structures 72A-1 and 72A-2.
[0104] In addition to the extended contact structures 72A and 72B mentioned above, other contact structures located on the substrate 52 include:
[0105] Contact structures 74A and 74B are used, where contact structure 74A connects to each of the third fin structures 54C and is also connected to the voltage source Vcc; contact structure 74B connects to each of the sixth fin structures 54F and is also connected to the voltage source Vcc. (Please refer to the diagram.) Figure 1 Contact structures 74A and 74B connect the source of the first pull-up element PL1 and the second pull-up element PL2 to the voltage source Vcc.
[0106] Contact structures 76A and 76B are provided, wherein contact structure 76A spans across each of the first fin structures 54A and is connected to the voltage source Vss, and contact structure 76B spans across each of the fourth fin structures 54D and is connected to the voltage source Vss. (Please refer to the diagram.) Figure 1 Contact structures 76A and 76B connect the source of the first pull-down element PD1 and the second pull-down element PD2 to the voltage source Vss.
[0107] Contact structures 78A and 78B, wherein contact structure 78A spans across each of the second fin structures 54B and is connected to the voltage source Vss, and contact structure 78B spans across each of the fifth fin structures 54E and is connected to the voltage source Vss (please refer to...). Figure 1 Contact structures 78A and 78B connect the source of the first pull-down element PD1 and the second pull-down element PD2 to the voltage source Vss.
[0108] Contact structures 80A and 80B, wherein contact structure 80A spans across each of the second fin structures 54B and connects to bit line BL1, and contact structure 80B spans across each of the fifth fin structures 54E and connects to bit line BL3 (please refer to...). Figure 1 Contact structure 80A connects the first access element PG1 to bit line BL1, and contact structure 80B connects the third access element PG3 to bit line BL3.
[0109] Contact structures 82A and 82B, wherein contact structure 82A spans each of the first fin structures 54A and connects to bit line BL2, and contact structure 82B spans each of the fourth fin structures 54D and connects to bit line BL4 (please refer to the diagram). Figure 1 Contact structure 82A connects the second access element PG2 to bit line BL2, and contact structure 82B connects the fourth access element PG4 to bit line BL4.
[0110] Contact structures 84A and 84B are provided, wherein contact structure 84A is located on each of the first access gate structures 60A and is connected to the character line WL1, and contact structure 84B is located on each of the first access gate structures 60B and is connected to the character line WL1 (please refer to the diagram). Figure 1 Contact structure 84A connects the gates of the first access element PG1 and the third access element PG3 to the character line WL1.
[0111] Contact structures 86A and 86B are provided, wherein contact structure 86A is located on each of the second access gate structures 62A and is connected to the character line WL2, and contact structure 86B is located on each of the second access gate structures 62B and is connected to the character line WL2 (please refer to the diagram). Figure 1 Contact structure 86A connects the gates of the second access element PG2 and the fourth access element PG4 to the character line WL2.
[0112] Contact structures 88A and 88B are provided, wherein contact structure 88B is located on each of the third fin structures 54C and connects to the stepped gate structure 55A and the extended contact structure 72A; contact structure 88A is located on each of the sixth fin structures 54F and connects to the stepped gate structure 55B and the extended contact structure 72B. (Please refer to the diagram.) Figure 1 Contact structure 84A connects the gate of the first pull-up element PL1 to the storage node 26, and contact structure 88B connects the gate of the second pull-up element PL2 to the storage node 24. It is worth noting that contact structure 88B and extended contact structure 72A may be located on the same layer and in direct contact with each other; therefore, contact structure 88B and extended contact structure 72A may be a single-piece structure. Similarly, contact structure 88A and extended contact structure 72B may also be a single-piece structure. Furthermore, the above contact structures are arranged symmetrically, which will not be elaborated further here.
[0113] The feature of this embodiment is that the first portion 56A and the second portion 56B of the stepped gate structure 55A or 55B have different axes of symmetry, but they respectively span the first fin structure 54A and the second fin structure 54B, together forming the gate of the first pull-down element PD1. Therefore, for the first pull-down element PD1, its gate structure spans a total of 6 fin structures (including the four first fin structures 54A spanned by the first portion 56A, and the two second fin structures 54B spanned by the second portion 56B). That is to say, the gate structure of the first pull-down element PD1 of the present invention is not limited to a long strip structure, but can be designed as a stepped shape or other shapes as described in this case, so as to span a greater number of fin structures. In this way, the limited space can be utilized more efficiently, and the read speed of the first pull-down element PD1 can be further improved.
[0114] The following description will focus on different embodiments of the static random access memory of the present invention. For the sake of simplicity, the description will mainly focus on the differences between the embodiments, and will not repeat the same points. In addition, the same elements in the various embodiments of the present invention are identified by the same reference numerals to facilitate comparison between the embodiments.
[0115] In the above embodiments, a fin structure 54 is formed on the substrate 52. However, in other embodiments of the present invention, the fin structure may not be formed on the substrate; instead, only an ion doping step may be performed on the substrate to form multiple diffusion regions. Then, the aforementioned stepped gate structure, first access gate structure, and contact structure are formed. That is, in the following embodiments, a planar transistor is used instead of the fin transistor in the above embodiments. Please refer to... Figure 7 , Figure 7 This is a layout diagram of an 8-transistor static random access memory (SRAM) according to another preferred embodiment of the present invention. In this embodiment, an 8T-SRAM memory cell 10' is formed. Notably, this embodiment does not form a fin structure, but instead forms a first diffusion region 58A, a second diffusion region 58B, a third diffusion region 58C, a fourth diffusion region 58D, a fifth diffusion region 58E, and a sixth diffusion region 58F in the substrate 52 by means of ion implantation or the like. Then, stepped gate structures 55A and 55B, first access gate structures 60A and 60B, second access gate structures 62A and 62B, extended contact structures 72A and 72B, and multiple contact structures (including contact structures 74A, 74B, 76A, 76B, 78A, 78B, 80A, 80B, 82A, 82B, 84A, 84B, 86A, 86B, and 88A, 88B) are formed.
[0116] The main difference between this embodiment and the first preferred embodiment described above is that, in this embodiment, a fin-like structure is not formed. Instead, multiple diffusion regions (including a first diffusion region 58A, a second diffusion region 58B, a third diffusion region 58C, a fourth diffusion region 58D, a fifth diffusion region 58E, and a sixth diffusion region 58F) are formed in the substrate 10, and then a gate structure and a contact structure are formed to form a planar transistor. Apart from this, the features and structures of the remaining components are generally the same as those described in the first preferred embodiment.
[0117] The circuit diagram in this embodiment is the same as that in the first preferred embodiment (please refer to...). Figure 1 The device comprises two mutually coupled inverters, each inverter including at least one pull-up element, at least one pull-down element, and at least two access elements. More specifically, it includes a first pull-up device PL1, a second pull-up device PL2, a first pull-down device PD1, a second pull-down device PD2, a first access element PG1, a second access element PG2, a third access element PG3, and a fourth access element PG4.
[0118] Each inverter includes a stepped gate structure, specifically stepped gate structures 55A and 55B spanning multiple diffusion regions. Similar to the embodiments described above, the stepped gate structure 55A includes a first portion 56A, a second portion 56B, and a bridging portion 56C. The first portion 56A and the second portion 56B are arranged along a first direction (e.g., the X direction), and the bridging portion 56C is arranged along a second direction (e.g., the Y direction). Preferably, the first and second directions are perpendicular to each other.
[0119] The stepped gate structure 55A spans the first diffusion region 58A, the second diffusion region 58B and the third diffusion region 58C, while the stepped gate structure 55B spans the fourth diffusion region 58D, the fifth diffusion region 58E and the sixth diffusion region 58F.
[0120] In this embodiment, the first portion 56A of the stepped gate structure 55A spans the first diffusion region 58A and the third diffusion region 58C, while the second portion 56B spans the second diffusion region 58B. The portion of the first portion 56A that spans the third diffusion region 58C forms the gate of the first pull-up element PL1; the portion of the first portion 56A that spans the first diffusion region 58A and the portion of the second portion 56B that spans the second diffusion region 58B together constitute the gate of the first pull-down element PD1. Figure 3 The area within the dashed line represents the range of the first pull-down element PD1.
[0121] Furthermore, in this embodiment, the 8T-SRAM memory cell 10' is located within a specific range 11, meaning that the specific range 11 contains only one set of 8T-SRAM memory cells 10'. The second part 56B is adjacent to one boundary of the aforementioned specific range 11. Figure 3 The Chinese standard designation is 11A.
[0122] In addition to the stepped gate structure described above, each inverter in this embodiment also includes at least one first access gate structure and at least one second access gate structure, that is, at least two mutually symmetrical first access gate structures 60A and 60B and two mutually symmetrical second access gate structures 62A and 62B are located on the substrate 52. Preferably, the first access gate structure 60A is arranged along a first direction (e.g., the X-axis) and is located in the extension direction of the first portion 56A. In other words, the first portion 56A and the first access gate structure 60A have the same axis of symmetry S1. The first access gate structure 60A is located on the second diffusion region 58B and forms the gate of the first access element PG1. Furthermore, the bridging portion 56C is located between the first access gate structure 60A and the first portion 56A. Similarly, the first access gate structure 60B spans the fifth diffusion region 58E and forms the gate of the third access element PG3, with the other features being the same.
[0123] The second access gate structure 62A is also arranged along the first direction and is located in the extension direction of the second portion 56B. In other words, the second portion 56B and the second access gate structure 62 share the same axis of symmetry S2. The second access gate structure 62A spans the first diffusion region 58A and forms the gate of the second access element PG2. Furthermore, the bridging portion 56C is located between the second access gate structure 62 and the second portion 56B. Similarly, the second access gate structure 62B spans the fourth diffusion region 58D and forms the gate of the fourth access element PG4.
[0124] In addition to the aforementioned diffusion regions and gate structures, the 8T-SRAM memory cell 10 in this embodiment also includes a plurality of contact structures. These include at least two symmetrically arranged extended contact structures 72A and 72B, wherein the extended contact structure 72A spans across each of the first diffusion regions 58A, each of the second diffusion regions 58B, and the third diffusion region 58C, and the extended contact structure 72B spans across each of the fourth diffusion region 58D, each of the fifth diffusion region 58E, and the sixth diffusion region 58F, connecting the diffusion regions to each other. Figure 1 As can be seen from the top view, the extended contact structure 72A connects the drains of the first pull-down element PD1, the first pull-up element PL1, the first access element PG1, and the second access element PG2. Furthermore, as can be seen from the top view, the extended contact structures 72A and 72B may be elongated or have other shapes (e.g., L-shaped), and the present invention is not limited thereto.
[0125] In this embodiment, the bridging portion 56C of the stepped gate structure 55A spans over the extended contact structure 72A (see the cross-sectional view above). Figure 3 In addition, in other embodiments of the present invention, please refer to Figure 8 , Figure 8 This is a layout diagram of a static random access memory (SRAM) according to another preferred embodiment of the present invention. Each stepped gate structure 55A and 55B is integrally formed, and the extended contact structure 72A includes extended contact structure 72A-1 and extended contact structure 72A-2, respectively located on both sides of the bridging portion 56C of the stepped gate structure 55A. Similarly, the extended contact structure 72B includes extended contact structure 72B-1 and extended contact structure 72B-2, respectively located on both sides of the bridging portion 56C of the stepped gate structure 55B. It also includes a bridging structure 73A spanning the bridging portion 56C of the stepped gate structure 55A and electrically connected to the extended contact structures 72A-1 and 72A-2; and a bridging structure 73B spanning the bridging portion 56C of the stepped gate structure 55B and electrically connected to the extended contact structures 72B-1 and 72B-2 (cross-sectional view can be found above). Figure 5 and Figure 6 ,but Figure 6 The fin-like structures 54A and 54B shown in this embodiment do not appear in this embodiment.
[0126] In addition to the extended contact structures 72A and 72B described above, the other contact structures located on the substrate 52 (including contact structures 74A, 74B, 76A, 76B, 78A, 78B, 80A, 80B, 82A, 82B, 84A, 84B, 86A, 86B, and 88A, 88B) correspond in position to the contact structures described in the first preferred embodiment. The difference lies in that some of the contact structures in the first preferred embodiment are located on the fin-like structure, while in this embodiment they are located on the diffusion region. Apart from the features described above, the other features are the same and will not be elaborated further here.
[0127] The feature of this embodiment is that the gate structure of the first pull-down element PD1 (or the second pull-down element PD2) is not limited to a long strip structure, but can be designed as a stepped shape or other shapes as described in this case, so as to span more diffusion regions. In this way, the limited space can be utilized more efficiently, and the read speed of the first pull-down element PD1 (or the second pull-down element PD2) can be further improved.
[0128] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.
Claims
1. A layout pattern for a static random access memory (SRAM), comprising at least: Two inverters are coupled to each other to store data. The two inverters include a first inverter and a second inverter. Each inverter includes at least one pull-up element (PLs) and at least one pull-down element (PDs). At least two access elements (PGs) are respectively connected to the output terminals of the two mutually coupled inverters, wherein each of the pull-up elements (PLs), each of the pull-down elements (PDs) and each of the access elements (PGs) includes a fin-field transistor (FinFET); Multiple fin-like structures are located on the substrate, and these fin-like structures include at least one first fin-like structure, at least one second fin-like structure, at least one third fin-like structure, at least one fourth fin-like structure and at least one fifth fin-like structure. Each inverter includes a stepped gate structure, the stepped gate structure including a first portion and a second portion arranged along a first direction, and a bridging portion connecting the first portion and the second portion, the bridging portion being arranged along a second direction, wherein the first direction and the second direction are perpendicular to each other, wherein the first portion spans the at least one first fin structure and the second portion spans the at least one second fin structure and forms the at least one pull-down element (PDs), wherein the first portion spans the at least one third fin structure and forms the at least one pull-up element (PLs); Each inverter includes a first access gate structure and a second access gate structure located on the substrate. The first access gate structure and the first portion of the stepped gate structure are aligned in the same direction and share the same axis of symmetry. The second access gate structure and the second portion of the stepped gate structure are aligned in the same direction and share the same axis of symmetry. The first access gate structure spans the at least one fourth fin structure and forms one of the at least two access elements (PGs). The second access gate structure spans the at least one fifth fin structure and forms the other of the at least two access elements (PGs). At least one first extended contact structure spans the at least one first fin-like structure and the at least one second fin-like structure. The length of the first part is greater than the length of the second part.
2. The layout pattern as claimed in claim 1, wherein the first portion and the second portion of the stepped gate structure have different axes of symmetry.
3. The layout pattern as claimed in claim 1, wherein the at least first extended contact structure further extends beyond the at least one third fin structure.
4. The layout pattern as described in claim 1, further comprising at least one character line electrically connected to the first access gate structure.
5. The layout pattern of claim 1, wherein the bridging portion is located between the first portion and the first access gate.
6. The layout pattern of claim 1, wherein the bridging portion is located between the second portion and the second access gate structure.
7. The layout pattern of claim 1, wherein the layout pattern of the static random access memory is located within a specific range having a boundary, wherein the second portion is adjacent to the first access gate at the boundary.
8. The layout pattern as described in claim 1, further comprising a second stepped gate structure symmetrically arranged with respect to the stepped gate structure.
9. The layout pattern of claim 1, wherein the bridging portion of the stepped gate structure spans over the at least one first extended contact structure.
10. The layout pattern as claimed in claim 1, wherein the first portion, the second portion, and the bridging portion of the stepped gate structure are integrally formed, and further includes a second bridging structure spanning over the bridging portion of the stepped gate structure.
11. The layout pattern as described in claim 1, wherein, The length of the first part is greater than the length of the bridging part.
12. The layout pattern as described in claim 1, further comprising: A first contact structure is located on the at least one third fin structure, wherein the first contact structure is electrically connected to a first voltage source.
13. The layout pattern as described in claim 1, further comprising: A second contact structure is located on the at least one first fin structure, wherein the second contact structure is electrically connected to a second voltage source.
14. The layout pattern as described in claim 1, further comprising: A third contact structure is located on the at least one second fin structure, wherein the third contact structure is electrically connected to a second voltage source.
15. The layout pattern as described in claim 1, further comprising: The fourth contact structure electrically connects the first extended contact structure and the first portion of the second inverter.
16. The layout pattern as described in claim 1, wherein, The number of at least one first fin structure is greater than the number of at least one second fin structure.
17. The layout pattern as described in claim 1, wherein, The number of at least one first fin structure is greater than the number of at least one third fin structure.
18. The layout pattern as described in claim 1, wherein, The number of at least one second fin structure is equal to the number of at least one fourth fin structure.
19. The layout pattern as described in claim 1, wherein, The number of at least one second fin structure is equal to the number of at least one fifth fin structure.
20. The layout pattern as described in claim 10, wherein, The at least one first extended contact structure includes: a first-side first extended contact structure and a second-side first extended contact structure located on opposite sides of the bridging portion, respectively, and the second bridging structure electrically connects the first-side first extended contact structure and the second-side first extended contact structure.
21. The layout pattern as described in claim 20, wherein, The area of the first extended contact structure on the second side is larger than the area of the first extended contact structure on the first side.
22. The layout pattern as described in claim 20, wherein, The second side first extended contact structure is formed by the at least one first fin structure, the at least one third fin structure and the at least one fifth fin structure.
23. The layout pattern as described in claim 20, wherein, The first extended contact structure on the first side is through the at least one second fin structure and the at least one fourth fin structure.
24. The layout pattern as described in claim 20, further comprising: The fifth contact structure is located between the first extended contact structure on the first side and the second bridging structure, or between the first extended contact structure on the second side and the second bridging structure.
25. A layout pattern for a static random access memory (SRAM), comprising at least: Two inverters are coupled to each other to store data. The two inverters include a first inverter and a second inverter. Each inverter includes at least one pull-up element (PLs) and at least one pull-down element (PDs). At least two access elements (PGs) are respectively connected to the output terminals of the two mutually coupled inverters, wherein each of the pull-up elements (PLs), each of the pull-down elements (PDs) and each of the access elements (PGs) includes a planar transistor. Multiple diffusion regions are located on the substrate, and these diffusion regions include at least one first diffusion region, at least one second diffusion region, and at least one third diffusion region; Each inverter includes a stepped gate structure, the stepped gate structure including a first portion and a second portion arranged along a first direction, and a bridging portion connecting the first portion and the second portion, the bridging portion being arranged along a second direction, wherein the first direction and the second direction are perpendicular to each other, wherein the first portion spans the at least one first diffusion region and the second portion spans the at least one second diffusion region and forms the at least one pull-down element (PDs), wherein the first portion spans the at least one third diffusion region and forms the at least one pull-up element (PLs); Each inverter includes a first access gate structure and a second access gate structure located on the substrate. The first access gate structure and the first portion of the stepped gate structure are aligned in the same direction and share the same axis of symmetry. The second access gate structure and the second portion of the stepped gate structure are aligned in the same direction and share the same axis of symmetry. The first access gate structure spans the at least one first diffusion region and forms one of the at least two access elements (PGs). The second access gate structure spans the at least one second diffusion region and forms the other of the at least two access elements (PGs). At least one first extended contact structure spans the at least one first diffusion region and the at least one second diffusion region. The length of the first part is greater than the length of the second part.
26. The layout pattern of claim 25, wherein the first portion and the second portion of the stepped gate structure have different axes of symmetry.
27. The layout pattern of claim 25, wherein the at least first extended contact structure further extends across the at least one third diffusion region.
28. The layout pattern of claim 25, further comprising at least one character line electrically connected to the first access gate structure.
29. The layout pattern of claim 25, wherein the bridging portion is located between the first portion and the first access gate.
30. The layout pattern of claim 25, wherein the bridging portion is located between the second portion and the second access gate structure.
31. The layout pattern of claim 25, wherein the layout pattern of the static random access memory is located within a specific range having a boundary, wherein the second portion is adjacent to the first access gate at the boundary.
32. The layout pattern of claim 25, further comprising a second stepped gate structure symmetrically arranged with respect to the stepped gate structure.
33. The layout pattern of claim 25, wherein the bridging portion of the stepped gate structure spans over the at least one first extended contact structure.
34. The layout pattern of claim 25, wherein the first portion, the second portion, and the bridging portion of the stepped gate structure are integrally formed, and further includes a second bridging structure spanning over the bridging portion of the stepped gate structure.
35. The layout pattern as described in claim 25, wherein, The length of the first part is greater than the length of the bridging part.
36. The layout pattern as described in claim 25, further comprising: A first contact structure is located on the at least one third diffusion region, wherein the first contact structure is electrically connected to a first voltage source.
37. The layout pattern as described in claim 25, further comprising: A second contact structure is located on the at least one first diffusion region, wherein the second contact structure is electrically connected to a second voltage source.
38. The layout pattern as described in claim 25, further comprising: A third contact structure is located on the at least one second diffusion region, wherein the third contact structure is electrically connected to a second voltage source.
39. The layout pattern as described in claim 25, further comprising: The fourth contact structure electrically connects the first extended contact structure and the first portion of the second inverter.
40. The layout pattern as described in claim 34, wherein, The at least one first extended contact structure includes: a first-side first extended contact structure and a second-side first extended contact structure located on opposite sides of the bridging portion, respectively, and the second bridging structure electrically connects the first-side first extended contact structure and the second-side first extended contact structure.
41. The layout pattern as described in claim 40, wherein, The area of the first extended contact structure on the second side is larger than the area of the first extended contact structure on the first side.
42. The layout pattern as described in claim 40, wherein, The second side first extended contact structure passes through the at least one first diffusion region.
43. The layout pattern as described in claim 40, wherein, The first extended contact structure on the first side passes through the at least one second diffusion region.
44. The layout pattern as described in claim 40, further comprising: The fifth contact structure is located between the first extended contact structure on the first side and the second bridging structure, or between the first extended contact structure on the second side and the second bridging structure.