Status polling based on die-generated pulse signals

Abstract

This application relates to state polling based on pulse signals generated by a die. A memory system includes a plurality of dies having a plurality of planes. A processing device is coupled to the dies and conducts controller operations including receiving a status indicator signal comprising a pulse validated by one or more planes of the plurality of dies. In response to receiving the pulse, the processing device conducts at least one of: a first status check of a die operation conducted by the plurality of dies upon expiration of a polling delay period; or a second status check of the die operation in response to detecting that the pulse is invalidated. The processing device terminates the conducting of status checks while the status indicator signal remains invalidated.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically to state polling based on pulse signals generated by the die. Background Technology

[0002] A memory subsystem may include one or more memory devices for storing data. These memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize a memory subsystem to store data at memory devices and retrieve data from memory devices. Summary of the Invention

[0003] According to one aspect of this application, a memory system is provided. The memory system includes: a plurality of dies having multiple planes; and a processing means coupled to the plurality of dies, the processing means being configured to perform controller operation, the controller operation including: receiving a status indicator signal comprising a pulse validated by one or more planes of the plurality of dies; in response to detecting the pulse, performing at least one of the following: a first status check of a die operation performed by the plurality of dies upon expiration of a polling delay period; or a second status check of the die operation in response to detecting that the pulse is invalidated; and terminating the state check while the status indicator signal remains invalidated.

[0004] According to another aspect of this application, a method is provided. The method includes: receiving, by a processing device coupled to a plurality of dies comprising a plurality of planes, a status indicator signal including a pulse valid by one or more planes of the plurality of dies; in response to detecting the pulse, the processing device performing at least one of the following: a first status check of die operation performed by the plurality of dies upon expiration of a polling delay period; or a second status check of the die operation in response to detecting that the pulse is invalidated; and the processing device terminating the status check while the status indicator signal remains invalid.

[0005] According to another aspect of this application, a method is provided. The method includes: a processing device coupled to a plurality of dies of one or more memory devices waiting to perform any state check until after a pulse on a state indicator signal is valid; the processing device detecting the pulse validated by one or more of the plurality of dies; and in response to detecting the pulse: the processing device performing an initial state check associated with die operations performed by the plurality of dies upon the expiration of a polling delay period; and the processing device performing one or more additional state checks associated with the die operations during a polling interval after the expiration of the polling delay period and before the pulse is invalidated. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed descriptions given below and from the accompanying drawings of some embodiments thereof.

[0007] Figure 1A An exemplary computing system including a memory subsystem is shown according to some embodiments.

[0008] Figure 1B This is a block diagram of a memory device communicating with a memory subsystem controller of a memory subsystem according to one embodiment.

[0009] Figure 2A This is a schematic block diagram of an example of a memory device comprising multiple dies and other sensor hardware that provides indicator pulses to control logic, according to some embodiments.

[0010] Figure 2B This is a schematic block diagram illustrating a multiplane memory device configured for noise reduction during parallel plane access according to some embodiments of the present disclosure.

[0011] Figure 3 This is a diagram of a status indicator signal comprising pulses generated by a plane of multiple dies of a memory device, according to some embodiments.

[0012] Figure 4A It is a diagram according to one embodiment of a status indicator signal comprising pulses generated by a plane of multiple dies of a memory device and a timing diagram for performing status checks.

[0013] Figure 4B It is a diagram according to another embodiment containing a status indicator signal of pulses generated by a plane of multiple dies of a memory device and a timing diagram of a status check.

[0014] Figure 5 This is a flowchart of an exemplary method for state checking based on a plane-generated pulse signal according to an exemplary embodiment.

[0015] Figure 6 This is a flowchart of an exemplary method for performing a status check based on a pulse signal generated by the die, according to an exemplary embodiment.

[0016] Figure 7 This is a block diagram of an exemplary computer system in which embodiments of the present disclosure can be operated. Detailed Implementation

[0017] Embodiments of this disclosure relate to state polling based on pulse signals generated by the die. Some memory subsystems include a memory subsystem controller that determines when and at what frequency to poll the state of multiple dies of the memory device. Polling is necessary because the controller needs to know which dies are available for the next memory operation, such as an erase operation, read operation, or program operation. The controller polls multiple dies and receives state updates in response to know when one or more of the dies are ready for the next operation.

[0018] For example, in some memory subsystems, the memory subsystem controller waits for a polling delay after each operation begins to make an initial state request, followed by subsequent state requests at polling intervals. The controller blindly triggers these state requests on a per-operation basis, resulting in a frequency of pending state checks exceeding what is necessary. This repetitive state requests between the controller and the memory device cause congestion on the communication bus and / or interface between them, consuming significant overhead that could otherwise be used for other control signals and data. This overhead slows down and impacts the performance of the memory subsystem.

[0019] Various aspects of this disclosure address the aforementioned and other deficiencies by enabling the memory subsystem controller to perform state checks based on pulses on state indicator signals received from multiple dies. In some embodiments, the pulses are generated from a set of planes across multiple dies and communicated via a Ready Busy (RB) pin coupled to the multiple dies and the controller (e.g., a processing device). More specifically, the state indicator signals may remain invalid (e.g., logic 0 or 1 in various embodiments) and may be validated by pulses from the planes and dies (e.g., logic values ​​opposite to invalidation) to indicate state changes, such as indicating the completion of memory operations (programming, erasing, reading), and other information, such as reaching a temperature trigger, error detection, security event detection, etc., which will be discussed in more detail. In some embodiments, pulses from different planes and dies may be validated in a partially overlapping manner, thus extending the pulses for state checking over a period of time. Furthermore, no state check is performed when the state indicator signal is invalidated. In this way, the controller performs state checks in response to state changes and when new state information is pending.

[0020] In at least some embodiments, the memory subsystem controller performs an operation including receiving a status indicator signal with a pulse, the pulse being determined by one or more planes of a plurality of dies or simply by one or more of the plurality of dies. In response to detecting a pulse, the operation includes performing at least one of the following: a first status check of a die operation performed by a die when a polling delay period expires, or a second status check of a die operation in response to detecting that the pulse has been invalidated. If the pulse is longer than the polling delay period, the controller performs both the first and second status checks. In some embodiments, the polling delay period is set to be greater than or equal to the pulse width of the pulse received from the die, thereby minimizing the status checks for a single completion. In the case of generating an extended pulse of status pulses overlapping the status indicator signal, the operation further includes performing one or more additional status checks of the die operation during the polling interval after the polling delay period expires and before the pulse is detected to be invalidated. The operation further includes terminating the status checks while the status indicator signal remains invalidated.

[0021] Therefore, the advantages of the systems and methods implemented according to some embodiments of this disclosure include, but are not limited to, that the controller only polls the state when an operation on the memory device has been completed or the state has changed. This approach by the controller improves polling efficiency, particularly for programming and erasing operations, and reduces bus (or other communication interface) congestion caused by polling. The controller hardware is also simplified because there is no need to track timers for each executing operation. Other advantages will be apparent to those skilled in the art, as discussed below.

[0022] Figure 1A An exemplary computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure is illustrated. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., one or more memory devices 130), or combinations of such media or memory devices. The memory subsystem 110 may be a storage device, a memory module, or a mixture of storage devices and memory modules.

[0023] Memory device 130 may be a non-volatile memory device. An example of a non-volatile memory device is a NOT AND (NAND) memory device. A non-volatile memory device is a package of one or more dies or logic units (LUNs). Therefore, each memory device 130 may be a die (or LUN) or may be a multi-die package containing multiple dies (or LUNs) on a chip, such as a die integrated circuit package. Each die may contain one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane contains a set of physical blocks. Each block contains a set of pages. Each page contains a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logic states associated with the number of bits stored. Logic states may be represented by binary values, such as “0” and “1” or combinations of these values.

[0024] Each memory device 130 may consist of bits arranged in a two-dimensional or three-dimensional grid, also known as a memory array. Memory cells are formed on a silicon wafer in an array of columns (hereinafter also referred to as bit lines) and rows (hereinafter also referred to as word lines). A word line may refer to one or more rows of memory cells in a memory device, which are used in conjunction with one or more bit lines to generate the address of each memory cell. The intersection of bit lines and word lines constitutes the address of the memory cell.

[0025] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0026] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capabilities, embedded computer (e.g., an embedded computer contained in a vehicle, industrial equipment or networked business device), or such computing device containing memory and processing power.

[0027] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to multiple memory subsystems 110 of different types. Figure 1AAn example of a host system 120 coupled to a memory subsystem 110 is shown. The host system 120 can provide data to be stored at the memory subsystem 110 and can request retrieval of data from the memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without an intermediate component), whether wired or wireless, and includes connections such as electrical, optical, magnetic, etc.

[0028] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses, for example, memory subsystem 110 to write data to and read data from memory subsystem 110.

[0029] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Double Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Double Data Rate (DDR)), etc. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access components (e.g., one or more memory devices 130). The physical host interface can provide an interface for passing control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1A The memory subsystem 110 is shown as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0030] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0031] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as a three-dimensional crosspoint (“3D crosspoint”) memory device, which is a crosspoint array of non-volatile memory cells. The non-volatile memory cell crosspoint array can perform bit storage based on changes in volume resistance, together with a stackable cross-grid data access array. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory allows for in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0032] Each memory device 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell, for example, through an additional threshold voltage range. In some embodiments, each memory device 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion, an MLC portion, a TLC portion, a QLC portion, or a PLC portion of memory cells. The memory cells of the memory device 130 may be grouped into multiple pages, where a page may refer to a logical unit of the memory device used to store data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0033] Although non-volatile memory components, such as non-volatile memory cell 3D cross-dot arrays and NAND flash memory (e.g., 2D NAND, 3D NAND), are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0034] The memory subsystem controller 115 (or simply, controller 115 or processing device) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0035] The memory subsystem controller 115 may include a processing device comprising one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0036] In some embodiments, local memory 119 may include memory registers storing memory pointers, acquired data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1A The exemplary memory subsystem 110 has been shown to include a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0037] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and correction coding (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access the memory device 130 and translate responses associated with the memory device 130 into information for the host system 120.

[0038] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., row decoder and column decoder) that can receive and decode addresses from the memory subsystem controller 115 to access the memory device 130.

[0039] In some embodiments, memory device 130 includes a local media controller 135 that operates together with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device that is a raw memory device having on-die control logic (e.g., local media controller 135) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0040] In some embodiments, each memory device 130 further includes a plurality of die-coupled to the memory device 130 and a ready busy pin 152 (or RB pin 152) coupled to the memory subsystem controller 115, for example, via a communication bus 125. In various embodiments, the communication bus 125 is or includes an Open NAND Flash Interface (ONFI). The communication bus 125 may also include other command, address, and data interfaces, including, but not limited to, a shared bus polled therethrough, configurable channels, and separate command / address bus schemes.

[0041] In these embodiments, controller 115 further includes a status polling component 113. The status polling component 113 can monitor a status indicator signal received via RB pin 152 (or other status input / output (I / O) pins discussed herein) to detect pulses that are validated and invalidated on the status indicator signal by one or more planes and / or dies of memory device 130. The status polling component 113 can manage polling of multiple planes and / or dies based on the detection of these pulses that are validated and invalidated throughout operation, as will be referred to... Figure 2A-3 , Figures 4A-4B and Figure 5-6 For more details, in some embodiments, the state polling component is wholly or partially integrated within the host system 120.

[0042] Figure 1B It is a first device and memory subsystem in the form of one or more memory devices 130 according to one embodiment (e.g., Figure 1A A simplified block diagram of communication between a second device and a memory subsystem controller 115 in the form of a memory subsystem 110. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical appliances, vehicles, wireless devices, mobile phones, etc. The memory subsystem controller 115 (e.g., a controller external to each memory device 130) may be a memory controller or other external host device.

[0043] Each memory device 130 includes an array 104 of memory cells logically arranged in rows and columns. Memory cells in logical rows are typically connected to the same access lines (e.g., word lines), while memory cells in logical columns are typically selectively connected to the same data lines (e.g., bit lines). A single access line may be associated with more than one logical row of memory cells, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in the memory cell array 104 ( Figure 1B (not shown) can be programmed as one of at least two target data states.

[0044] Row decoding circuitry 108 and column decoding circuitry 111 are provided to decode address signals. Address signals are received and decoded to access memory cell array 104. Each memory device 130 also includes input / output (I / O) control circuitry 112 to manage the input of commands, addresses, and data to memory device 130, as well as the output of data and status information from each memory device 130. Address register 114 communicates with I / O control circuitry 112, row decoding circuitry 108, and column decoding circuitry 111 to latch address signals before decoding. Command register 124 communicates with I / O control circuitry 112 and local media controller 135 to latch incoming commands.

[0045] A controller (e.g., a local media controller 135 within each memory device 130) responds to commands to control access to the memory cell array 104 and generates status information for the external storage subsystem controller 115, i.e., the local media controller 135 is configured to perform access operations (e.g., read operations, programming operations, and / or erase operations) on the memory cell array 104. The local media controller 135 communicates with the row decoding circuitry 108 and the column decoding circuitry 111 in response to address control of the row decoding circuitry 108 and the column decoding circuitry 111.

[0046] The local media controller 135 also communicates with cache register 118 and data register 121. Cache register 118 latches incoming or outgoing data under the direction of the local media controller 135 to temporarily store data while the memory cell array 104 is busy writing or reading other data. During programming operations (e.g., write operations), data can be transferred from cache register 118 to data register 121 to the memory cell array 104; new data can then be latched from I / O control circuitry 112 into cache register 118. During read operations, data can be transferred from cache register 118 to I / O control circuitry 112 for output to memory subsystem controller 115; new data can then be transferred from data register 121 to cache register 118. Cache register 118 and / or data register 121 may form a page buffer for each memory device 130 (e.g., at least a portion thereof). The page buffer may further include sensing devices, such as a sensing amplifier, to sense the data state of the memory cells, for example, by sensing the state of the data lines connected to the memory cells of the memory cell array 104. The status register 122 may communicate with the I / O control circuitry system 112 and the local memory controller 135 to latch status information for output to the memory subsystem controller 115.

[0047] Each memory device 130 receives control signals from the local media controller 135 at the memory subsystem controller 115 via control link 132. For example, the control signals may include a chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE#, a read enable signal RE#, and a write protection signal WP#. Depending on the nature of each memory device 130, additional or alternative control signals (not shown) may be received further via control link 132. In one embodiment, each memory device 130 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from the memory subsystem controller 115 via a multiplexed input / output (I / O) bus 134, and outputs data to the memory subsystem controller 115 via the I / O bus 134.

[0048] For example, commands can be received at I / O control circuitry 112 via the input / output (I / O) pins [7:0] of I / O bus 134, and then written to command register 124. Addresses can be received at I / O control circuitry 112 via the input / output (I / O) pins [7:0] of I / O bus 134, and then written to address register 114. Data can be received at I / O control circuitry 112 via the input / output (I / O) pins [7:0] of an 8-bit device or the input / output (I / O) pins [15:0] of a 16-bit device, and then written to cache register 118. The data can then be written to data register 121 for programming memory cell array 104.

[0049] In one embodiment, cache register 118 can be omitted, and data can be written directly to data register 121. Data can also be output via input / output (I / O) pins [7:0] of an 8-bit device or input / output (I / O) pins [15:0] of a 16-bit device. Although references to I / O pins are possible, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that provide electrical connection to each memory device 130 via an external device, such as a memory subsystem controller 115.

[0050] Those skilled in the art will understand that alternative circuit systems and signals can be provided, and Figure 1B Each memory device 130 has been simplified. It should be recognized that the reference... Figure 1B The functions of the described individual block components may not need to be separated into different components or component portions of the integrated circuit device. For example, a single component or component portion of the integrated circuit device may be adapted to perform... Figure 1BThe functionality of more than one block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 1B The functionality of a single block component. Additionally, while specific I / O pins are described according to popular conventions for receiving and outputting various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0051] Figure 2A This is a schematic block diagram of an example of a memory device 130, such as memory device 130A, according to some embodiments, which includes a plurality of dies 230 (e.g., die_0, die_1, die_2, ... die_N) and other sensor hardware that provides indicator pulses to control logic. In addition to a Ready Busy (RB) pin 152 coupled to the plurality of dies 230 and the local media controller 135, memory device 130A may further include one or more status I / O pins 252 coupled between die sensor hardware 256 and the local media controller 135. Thus, each die and / or plane of the plurality of dies 230 (see...) Figure 2B The pulse can be enabled at RB pin 152 to indicate that the die / plane has completed its operation and is ready, or the status indicator signal sent through RB pin 152 can be disabled to indicate that the die / plane is busy.

[0052] Similarly, in at least some embodiments, other hardware and / or control logic of the memory device 130A may pulse at one or more state I / O pins 252 to indicate the completion or triggering of a specific device state that may not be directly related to programming / erasing / read operations performed at multiple dies but is still associated with die functionality. For example, a specific state may be associated with a state directly tracked by die sensor hardware 256 or by the local media controller 135. These specific states received from die sensor hardware 256 may include, but are not limited to, temperature states (e.g., thermocouple reaching a specific temperature threshold limit), power events or power states (e.g., power supply voltage out of range, power supply noise out of specification), or security events (e.g., unauthorized access, secure area access, authentication failure, etc.). Furthermore, specific states received from the local media controller 135 may include paused completion of die operation, error states (e.g., programming failure, erase failure, or read error exceeding the threshold bit error rate (BER)), or similar types of operational states other than memory operation completion.

[0053] Therefore, in various embodiments, the operation may further include receiving a second state indicator signal with a second pulse, the second pulse being activated by the sensor hardware of the memory device, such as device sensor hardware 256. In response to detecting the second pulse, the operation further includes performing at least one of the following: a third state check of the device operation performed by the memory device 130 when the polling delay period expires, or a fourth state check of the device operation in response to detecting that the second pulse has been invalidated. The operation may further include terminating the state check while the second state indicator signal remains invalid. In some embodiments, the device operation includes one of a pause completion of memory operation associated with the memory device, a power event state, a security event state, or a temperature state.

[0054] Figure 2B This is a schematic block diagram illustrating a multiplane memory device 130B configured for noise reduction during parallel plane access according to some embodiments of the present disclosure. Memory planes 272(0)-272(3) can each be divided into data blocks, wherein different relative data blocks from two or more memory planes 272(0)-272(3) can be accessed simultaneously during a memory access operation. For example, during a memory access operation, two or more of the following can be accessed simultaneously: data block 282 of memory plane 272(0), data block 283 of memory plane 272(1), data block 284 of memory plane 272(2), and data block 285 of memory plane 272(3).

[0055] Memory device 130B includes a memory array 270 divided into memory planes 272(0)-272(3), each memory plane containing a corresponding number of memory cells. In various embodiments, the memory array 270 is contained in one or more of a plurality of dies 230. Figure 2A The multiplane memory device 130B may further include a local media controller 135, which includes power control circuitry and access control circuitry for simultaneously performing memory access operations on different memory planes 272(0)-272(3). The memory cells may be non-volatile memory cells, such as NAND flash memory cells, or may generally be any type of memory cell.

[0056] Each of memory planes 272(0)-272(3) can be divided into data blocks, wherein different relative data blocks from each of memory planes 272(0)-272(3) can be accessed simultaneously during a memory access operation. For example, during a memory access operation, data block 282 of memory plane 272(0), data block 283 of memory plane 272(1), data block 284 of memory plane 272(2), and data block 285 of memory plane 272(3) can each be accessed simultaneously.

[0057] Each memory plane 272(0)-272(3) can be coupled to a corresponding page buffer 276(0)-276(3). Each page buffer 276(0)-276(3) can be configured to provide data to or receive data from the corresponding memory plane 272(0)-272(3). Page buffers 276(0)-276(3) can be controlled by a local media controller 135. Data received from the corresponding memory planes 272(0)-272(3) can be latched at page buffers 276(0)-276(3) respectively and retrieved by the local media controller 135, and provided to the memory subsystem controller 115 via an NVMe interface.

[0058] Each memory plane 272(0)-272(3) may be further coupled to a corresponding access driver circuit 274(0)-274(3), such as an access line driver circuit. The driver circuits 274(0)-274(3) may be configured to regulate pages of the corresponding blocks of the associated memory planes 272(0)-272(3) for memory access operations, such as programming data (i.e., writing data), reading data, or erasing data. Each driver circuit 274(0)-274(3) may be coupled to a corresponding global access line associated with the corresponding memory plane 272(0)-272(3). Each global access line may be selectively coupled to a corresponding local access line within the block during memory access operations associated with pages within the block of the plane. The driver circuits 274(0)-274(3) may be controlled based on signals from the local media controller 135. Each driver circuit 274(0)-274(3) may include or be coupled to a corresponding power supply circuit and may supply voltage to the corresponding access line based on the voltage provided by the corresponding power supply circuit. The voltage provided by the power supply circuit may be based on a signal received from the local media controller 135.

[0059] The local media controller 135 can control driver circuits 274(0)-274(3) and page buffers 276(0)-276(3) to perform memory access operations simultaneously with each of a set of memory command and address pairs (e.g., received from memory subsystem controller 115). For example, the local media controller 135 can control driver circuits 274(0)-274(3) and page buffers 376(0)-376(3) to perform parallel memory access operations. The local media controller 135 may include power control circuitry and access control circuitry, wherein the power control circuitry serially configures two or more driver circuits 274(0)-274(3) for parallel memory access operations, and the access control circuitry is configured to control two or more page buffers 276(0)-276(3) to sense and latch data from the respective memory planes 272(0)-272(3), or to program data to the respective memory planes 272(0)-272(3) for parallel memory access operations.

[0060] In operation, the local media controller 135 may receive a set of memory command and address pairs via an NVMe interface, each pair arriving in parallel or serially. In some instances, the set of memory command and address pairs may each be associated with a different corresponding memory plane 272(0)-272(3) of the memory array 270. The local media controller 135 may be configured to perform parallel memory access operations (e.g., read operations or programming operations) for the different memory planes 272(0)-272(3) of the memory array 270 in response to the set of memory command and address pairs. For example, the power control circuitry of the local media controller 135 may serially configure driver circuitry 274(0)-274(3) of two or more memory planes 272(0)-272(3) associated with the set of memory command and address pairs for parallel memory access operations based on corresponding page types (e.g., up page (UP), middle page (MP), down page (LP), extra page (XP), SLC / MLC / TLC / QLC pages). After the access line driver circuits 274(0)-274(3) have been configured, the access control circuitry of the local media controller 135 can simultaneously control the page buffers 276(0)-276(3) to access the corresponding pages of each of the two or more memory planes 272(0)-272(3) associated with the set of memory command and address pairs during parallel memory access operations, for example, to retrieve or write data. For example, the access control circuitry can simultaneously (e.g., in parallel and / or concurrently) control the page buffers 276(0)-276(3) to charge / discharge bit lines, sense data from the two or more memory planes 272(0)-272(3), and / or latch data.

[0061] Based on signals received from the local media controller 135, driver circuits 274(0)-274(3) coupled to memory planes 272(0)-272(3) associated with the set of memory command and address pairs can select memory blocks or memory cells from the associated memory planes 272(0)-272(3) for memory operations, such as read, program, and / or erase operations. Driver circuits 274(0)-274(3) can drive different corresponding global access lines associated with the respective memory planes 272(0)-272(3). As an example, driver circuit 274(0) can drive a first voltage on a first global access line associated with memory plane 272(0), driver circuit 274(1) can drive a second voltage on a third global access line associated with memory plane 272(1), driver circuit 274(2) can drive a third voltage on a seventh global access line associated with memory plane 272(2), and so on, and other voltages can be driven on each of the remaining global access lines. In some instances, voltage can be provided on all access lines except for the access lines associated with the pages of the memory planes 272(0)-272(3) to be accessed. Driver circuits 274(0)-274(3) and page buffers 276(0)-276(3) can allow access to different corresponding pages within different corresponding blocks of memory cells to be accessed simultaneously. For example, the first page of the first block of the first memory plane can be accessed simultaneously with the second page of the second block of the second memory plane, regardless of the page type.

[0062] Page buffers 276(0)-276(3) can provide data to or receive data from the local media controller 135 during memory access operations in response to signals from the local media controller 135 and the corresponding memory planes 272(0)-272(3). The local media controller 135 can provide the received data to the memory subsystem controller 115.

[0063] It will be understood that memory device 130B may include more or fewer than four memory planes, driver circuitry, and page buffers. It will also be understood that the corresponding global access lines may include 8, 16, 32, 64, 128, etc., global access lines. In another embodiment, memory device 130B may include fewer driver circuitry than the number of planes. In such embodiments, memory device 130B may further include plane selection circuitry (e.g., multiple bidirectional multiplexer circuits) controlled by control signals received from local media controller 135. The plane selection circuitry allows any driver circuitry to be selectively coupled to any memory plane in memory device 130B. In this way, there is no fixed association between any driver circuitry and any plane.

[0064] Furthermore, in at least some embodiments, each processor 254(0)-254(3) may receive instructions from the plane driver manager 260, such as whether to allow, pause, or resume quiet or high-noise events during operations performed by a corresponding driver circuit 274(0)-274(3), to manage the execution timing of such operations, such as programming, erasing, or reading operations at memory planes 272(0)-272(3); and / or the handling of errors detected in such memory operations. For example, each processor 254(0)-254(3) may monitor the status of operations performed by a corresponding driver circuit 274(0)-274(3) and report the status to the plane driver manager 260.

[0065] In at least some embodiments, each processor 254(0)-254(3) also detects when a particular plane in the memory planes 272(0)-272(3) becomes available due to the completion of a previous operation, such as an erase operation, programming operation, or read operation at a plane driven by a particular driver circuit 274(0)-274(3) coupled to one of the processors 254(0)-254(3), respectively. Thus, each processor 254(0)-254(3) can detect the activity of the corresponding driver circuit 274(0)-274(3) to determine, for example, a completion state. In response to detecting the completion of a memory operation, the corresponding processor 254(0)-254(3) or the plane driver manager 260 can validate a pulse on the status indicator signal of the RB pin 152. In this way, the local media controller 135 can provide plane-specific status pulses to the memory subsystem controller 115, which include validate and invalidate pulses to indicate a ready / busy state associated with the completion or continuation of a memory operation.

[0066] Figure 3This is a diagram of a status indicator signal comprising pulses generated by a plane of multiple dies of a memory device, according to some embodiments. In various embodiments, the duration is approximately the width of the ready-to-work signal pulse. The ready state transition from logic 1 (RDY) to logic 0 within the system can now pulse the ready busy signal (RB#) low (e.g., activate). Therefore, in some embodiments, the pulse indicates a transition to the ready state. In at least some embodiments, there is a cross-reference... Figure 2A-2B The multiple dies 230 discussed share a common ready busy signal (e.g., on ready busy pin 152). Therefore, each pulse on the ready busy signal (generally referred to herein as the status indicator signal) can correspond to 1 to N dies per channel multiplied by the number of independent word line threads, thus providing the ability to track the status of any plane / die, a group of planes / dies, or any individual die (regardless of the plane).

[0067] refer to Figure 3 The first operation 302 is completed first, followed by the second operation 304 and the third operation 306. All operations are performed at the first die (die 0), but simultaneously at different planes, plane _0 (P0) and plane _1 (P1). Finally, a set of operations 308, performed simultaneously at the second die (DIE1), is completed. Although the status indicator signal (e.g., RB#) is invalidated (e.g., at a logic high value in this example), the state of these operations does not change. However, after the first operation 302 is completed, the control logic (e.g., the local media controller 135) validates the pulse on the status indicator signal. As shown, this is a standard pulse with a standard pulse width (~tRBPW).

[0068] In response to the completion of the second operation 304 and the third operation 306, the corresponding control logic for each plane (P1, P3) validates a separate pulse to indicate the completion of the corresponding operation. Because these separate pulses partially overlap, the pulse transmitted via the status indicator signal is an extended pulse, for example, whose length is a standard pulse (~tRBPW) plus the time difference between the completion of the second and third operations (tP3-tP1). Therefore, when the operations of different planes / dies are completed close to each other, the aggregation validation of their corresponding pulses may have pulses of variable length. Furthermore, when the set of operations 308 of the second die is completed, the control logic again validates a pulse of standard width (~tRBPW) and then invalidates the status indicator signal again.

[0069] Figure 4AThis is a diagram illustrating the timing of a status indicator signal containing pulses generated by the planes of a plurality of dies of the memory device 130, according to one embodiment, and the timing of status checks. A polling delay period can be set so that the controller 115 waits after detecting that a pulse has been validated on the status indicator signal before initiating status checks on the plurality of planes and dies of the memory device 130. To minimize the status check for a single completion, the polling delay period can be set to be greater than or equal to the standard pulse width of the pulses validated by the plurality of dies 230.

[0070] In these embodiments, once a status check begins after the polling delay period, the controller 115 can perform additional status checks during the polling interval, as long as the pulse remains valid, for example, in the case of extended pulses. Furthermore, the controller 115 can perform a final status check when it detects that the status indicator signal has been deactivated. This final status check can be performed to ensure that all completion transitions from the plurality of dies 230 are captured before terminating status checks, while the status indicator signal remains deactivated. Although the illustrated embodiments show a pulse being validated as a transition from a high value to a low value and a pulse being deactivated as a transition from a low value to a high value, the reverse can be implemented in alternative embodiments.

[0071] Therefore, refer to Figure 4A In this embodiment, the first operation 402 is completed first, followed by the second operation 404 and the third operation 406, which are completed later. When the controller 115 detects that the first pulse 452 is valid on the status indicator signal, the controller begins to wait for the polling delay period. However, since the first pulse 450 is invalidated earlier (e.g., in the case where the pulse width of the standard pulse is shorter than the polling delay period), the controller 115 performs only one status check (ST) in response to detecting that the first pulse 450 is invalidated.

[0072] Furthermore, the second operation 404 and the third operation 406 are completed close to each other, and their corresponding pulses are aggregated to generate the extended pulse 454. Therefore, in this embodiment, the controller 115 begins a state check after the polling delay period expires, which is triggered when the extended pulse 454 begins to be validated. Finally, shortly thereafter, the controller 115 detects that the extended pulse 454 has been invalidated and thus performs a final state check.

[0073] Figure 4BThis is a diagram according to another embodiment of a status indicator signal comprising pulses generated by the planes of a plurality of dies of a memory device and a timing sequence for status checks. In some embodiments, this diagram may also represent cases where the dies generate these pulses, with each operation performed by a different die. However, as shown, the first operation 412 completes earlier, followed by the third operation 416, then the second operation 414, then the fifth operation 424, and finally the fourth operation 420, wherein, for simplicity, the operations are marked in order of comparison of the start time of the operation with the start times of the other operations. The fifth operation is being performed by die 1 when the plane of die 0 is particularly active. Similarly, each pulse indicates that the state of at least one operation has changed, for example, it has been completed, and thus indicates that the plane / die performing the operation is now ready to perform another operation.

[0074] In this embodiment, because the first pulse 462, which is validated by the first die and plane (die OP0), has the width of a polling delay period, only a single state check (ST) is required in response to the expiration of the polling delay period or the detection that the first pulse 462 has been invalidated. Clearly, the second pulse 464 is an extended pulse significantly longer than the first pulse 462 on the status indicator signal (RB#). As each of the remaining operations completes, the corresponding die / plane pulses to the status indicator signal, resulting in the aggregation of multiple overlapping pulses, which generates the extended pulse. Therefore, the controller 115 can perform (e.g., initiate) multiple state checks, one after the polling delay period expires, and then four additional state checks at the polling interval. As mentioned, each polling delay period and each polling interval can be set to a pulse width greater than or equal to the pulse width.

[0075] Furthermore, controller 115 may perform a sixth (and final) state check in response to detecting that the second pulse 464 has been invalidated, for example, returning to a high value. Thus, although multiple state checks are performed, some of these checks gather additional state information because many operations complete close together. For example, the first state check determines that both the second operation 414 and the third operation 416 have completed. Furthermore, the fourth state check determines that both the fourth operation 420 and the fifth operation 424 have completed. Although the sixth state check does not obtain additional information, its performance ensures that any final state of any active operation is guaranteed in response to the invalidation of the second pulse 464, and thus terminates the initiation of any further state checks.

[0076] Figure 5This is a flowchart of an exemplary method 500 for state checking based on a plane-generated pulse signal according to an exemplary embodiment. Method 500 can be performed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 500 is performed by, for example... Figure 1A The processing means of the memory subsystem controller 115 is used. In one embodiment, method 500 is performed by the state polling component 113 of the memory subsystem controller 115. Although shown in a specific order or sequence, the order of processes may be modified unless otherwise stated. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0077] In operation 510, a signal is received. For example, processing logic (e.g., status polling component 113) receives a signal, such as a status indicator signal having a pulse of one or more planes of multiple dies 230.

[0078] In operation 520, a status check is performed. For example, the processing logic performs at least one status check in response to the detection of a pulse. For example, in operation 525, the processing logic performs a first status check on die operations performed by multiple dies when the polling delay period expires. Alternatively, in operation 530, the processing logic performs a second status check on die operations in response to the detection that a pulse has been invalidated.

[0079] If the pulse is longer than the polling delay period, additional status checks are performed in operation 540. For example, the processing logic also performs zero or more additional status checks on the die operation during the polling interval after the polling delay period expires and before the pulse is detected as invalid. If the longer pulse does not reach at least one polling interval, no additional status checks are performed, and if the longer pulse exceeds the duration of the polling delay period plus at least one polling interval, at least one additional status check is performed. If zero or more additional status checks are required, they can be performed before initiating the second status check in operation 530.

[0080] In operation 540, the received status indicator signal may include receiving a first pulse from a first plane among one or more planes corresponding to the end of the first die operation, and receiving a second pulse from a second plane among one or more planes corresponding to the end of the second die operation. The first pulse and the second pulse partially overlap to make the pulses an extended pulse.

[0081] In operation 550, the status check is terminated. For example, the processing logic terminates the status check while the status indicator signal remains invalid. This default behavior of polling the status check can reduce congestion on the communication bus or other interfaces across controller 115 and memory device 130, thereby saving bandwidth. Method 500 can then loop back to operation 510 to monitor pulses on the status indicator signal.

[0082] Figure 6 This is a flowchart of an exemplary method 600 for state checking based on a pulse signal generated by a die, according to an exemplary embodiment. Method 600 can be performed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 600 is performed by, for example... Figure 1A The processing means of the memory subsystem controller 115 is used. In one embodiment, method 600 is performed by the state polling component 113 of the memory subsystem controller 115. Although shown in a specific order or sequence, the order of processes may be modified unless otherwise stated. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0083] In operation 610, a waiting process occurs. For example, the processing logic waits to perform any status checks until a pulse on the status indicator signal is validated by one or more of the multiple dies 230. This default behavior of polling status checks can reduce congestion on the communication bus or other interfaces across the controller 115 and memory device 130, thereby saving bandwidth.

[0084] In operation 620, a pulse is detected. For example, the processing logic detects that a pulse has been activated by one or more of a plurality of dies.

[0085] In operation 625, a status check is performed. For example, in response to the detection of a pulse, at least one status check is performed. For example, in operation 630, the processing logic performs an initial status check associated with die operations performed by multiple dies when the polling delay period expires.

[0086] In addition, in operation 635, further status checks are performed. For example, the processing logic performs zero or more additional status checks associated with die operation during the polling interval after the polling delay expires and before the pulse is invalidated. (Compared to operation 540) Figure 5Similarly, if the pulse width is long enough to exceed the polling delay period, the controller 115 performs at least one additional status check in response to the polling interval after the polling delay period has been reached.

[0087] In operation 640, a final state check is performed. For example, the processing logic performs a final state check of the die operation in response to detecting that a pulse has been invalidated.

[0088] In operation 650, the status check is terminated. For example, the processing logic terminates the status check while the status indicator signal remains invalid. This default behavior of polling the status check can reduce congestion on the communication bus or other interfaces across controller 115 and memory device 130, thereby saving bandwidth. Method 600 can then loop back to operation 610 to monitor pulses on the status indicator signal.

[0089] Figure 7 An exemplary machine for a computer system 700 is shown, in which a set of instructions can be executed to cause the machine to perform any one or more of the methods discussed herein. In some embodiments, the computer system 700 may correspond to a host system (e.g., Figure 1A The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1A The memory subsystem 110, or may be used for controller operations (e.g., executing an operating system to perform corresponding...). Figure 1A (Operation of the state polling component 113). In an alternative embodiment, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a client-server network environment as a server or client machine in a cloud computing infrastructure or environment.

[0090] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) specifying the action to be taken by the machine. Furthermore, although a single machine is shown, the term "machine" should also be considered as encompassing any collection of machines that individually or collectively execute one or more sets of instructions to perform any of the methods discussed herein.

[0091] The exemplary computer system 700 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or RDRAM), static memory 710 (e.g., flash memory, static random access memory (SRAM), etc.) and a data storage system 718, which communicate with each other via a bus 730.

[0092] Processing device 702 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 702 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 702 is configured to execute instructions 728 to perform the operations and steps discussed herein. Computer system 700 may further include a network interface device 712 for communication via network 720.

[0093] The data storage system 718 may include a machine-readable storage medium 724 (also referred to as a computer-readable medium) on which one or more sets of instructions 728 or software embodying any one or more methods or functions described herein are stored. The data storage system 718 may further include a local media controller 135, a cache, and a page buffer. The instructions 728 may also reside wholly or at least partially within the main memory 704 and / or the processing device 702 during execution by the computer system 700, the main memory 704, and the processing device 702, which also constitutes the machine-readable storage medium. The machine-readable storage medium 724, the data storage system 718, and / or the main memory 704 may correspond to... Figure 1A The memory subsystem 110.

[0094] In one embodiment, instruction 728 includes instructions for implementing the corresponding Figure 1A The state polling component 113 provides instructions for its function. Although the machine-readable storage medium 724 is shown as a single medium in one exemplary embodiment, the term "machine-readable storage medium" should be considered as a single medium or multiple media containing one or more sets of instructions. The term "machine-readable storage medium" should also be considered as any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered as including, but not limited to, solid-state memory, optical media, and magnetic media.

[0095] Some parts of the previously described algorithms and symbolic representations of operations on data bits within computer memory have been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. In this document and generally, algorithms are conceived as self-consistent sequences of operations that produce desired results. These operations are those that require physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has been found convenient, primarily for common reasons, to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc.

[0096] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient notations for application to those quantities. This disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates data represented as physical (electronic) quantities within the registers and memories of the computer system and converts them into other data represented similarly as physical quantities within the computer system's memory or registers or other such information storage systems.

[0097] This disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specifically constructed for its intended purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each of which is connected to a computer system bus.

[0098] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices for carrying out the methods described herein. The structures of various such systems will be presented as set forth in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It will be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0099] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being usable for programming a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) medium includes machine-readable storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0100] In the foregoing description, embodiments of the present disclosure have been described with reference to specific exemplary embodiments thereof. It will be apparent that various modifications can be made to the embodiments of the present disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A memory system comprising: Multiple dies with multiple planes; and A processing device coupled to the plurality of dies, the processing device being used for controller operation, the controller operation including: Receive a status indicator signal comprising one or more plane-activated pulses from the plurality of dies; In response to the detection of the pulse, at least one of the following two state checks is performed, including: The first state check of the die operation performed by the plurality of dies when the polling delay period expires; or A second state check in response to the detection that the pulse has been invalidated in the die operation; and The controller operation further includes terminating the state check when the state indicator signal remains invalid.

2. The memory system of claim 1, further comprising a ready busy pin coupled to the plurality of dies, the ready busy pin being configured to receive the status indicator signal from the plurality of dies.

3. The memory system of claim 1, wherein each of the plurality of dies includes corresponding control logic coupled to the one or more planes, wherein the control logic is used to validate the pulse to indicate the state of die operation of the one or more planes.

4. The memory system of claim 1, wherein the polling delay period is set to be greater than or equal to the pulse width of the pulse.

5. The memory system of claim 1, wherein receiving the status indicator signal comprises: Receive a first pulse from a first plane among the one or more planes corresponding to the end of the first die operation; and A second pulse is received from a second plane in one or more planes corresponding to the end of the second die operation, wherein the first pulse and the second pulse partially overlap to make the pulse an extended pulse.

6. The memory system of claim 1, wherein the controller operation further includes performing one or more additional status checks of the die operation during the polling interval after the polling delay period expires and before the pulse is detected to be invalidated.

7. The memory system of claim 1, wherein the die operation includes one of a read operation, a program operation, an erase operation, or an error state.

8. A method comprising: A status indicator signal comprising pulses effective by one or more planes of the plurality of dies is received by a processing device coupled to a plurality of dies comprising multiple planes; In response to the detection of the pulse, the processing device performs at least one of the following two state checks, which include: The first state check of the die operation performed by the plurality of dies when the polling delay period expires; or A second state check in response to the detection that the pulse has been invalidated in the die operation; and The method further includes having the processing device terminate the state check when the state indicator signal remains invalid.

9. The method of claim 8, further comprising validating the pulse by corresponding control logic coupled to the one or more planes to indicate the state of the die operation of the one or more planes.

10. The method of claim 8, wherein the polling delay period is set to be greater than or equal to the pulse width of the pulse.

11. The method of claim 8, wherein receiving the status indicator signal comprises: Receive a first pulse from a first plane among the one or more planes corresponding to the end of the first die operation; and A second pulse is received from a second plane in one or more planes corresponding to the end of the second die operation, wherein the first pulse and the second pulse partially overlap to make the pulse an extended pulse.

12. The method of claim 8, further comprising performing one or more additional status checks of the die operation during the polling interval after the polling delay period expires and before the pulse is detected to be invalidated.

13. The method of claim 8, wherein the die operation includes one of a read operation, a programming operation, an erase operation, or an error state.

14. A method comprising: The processing unit, coupled to multiple dies of one or more memory devices, waits to perform any status check until a pulse on the status indicator signal is valid; The processing device detects the pulse that is activated by one or more of the plurality of dies; and In response to the detection of the pulse: The processing device performs an initial state check associated with the die operations performed by the plurality of dies when the polling delay period expires; and The processing device performs one or more additional status checks associated with die operation during the polling interval after the polling delay period expires and before the pulse is detected to be invalidated.

15. The method of claim 14, further comprising validating the pulse by corresponding control logic coupled to the plurality of dies to indicate the state of the die operation, the state including an error state or completion of a read operation, a programming operation, or an erase operation.

16. The method of claim 14, wherein the polling delay period and each polling interval are set to be greater than or equal to the pulse width of the pulse.

17. The method of claim 14, further comprising: Receive a first pulse from the first die among the plurality of dies corresponding to the end of the first die operation; and A second pulse is received from the second die of the plurality of dies corresponding to the end of the second die operation, wherein the first pulse and the second pulse partially overlap to make the pulse an extended pulse.

18. The method of claim 14, further comprising: In response to the detection that the pulse has been invalidated, a final state check of the die operation is performed; and The processing device terminates the status check when the status indicator signal remains invalid.

19. The method of claim 14, further comprising: Receive a second status indicator signal including a second pulse that is hardware-activated by the sensor of the one or more memory devices; In response to the detection of the second pulse, at least one of the following two state checks is performed, including: A third state check of device operation performed by the one or more memory devices when the polling delay period expires; or A fourth state check in response to the detection that the second pulse has been invalidated; and The method further includes terminating the state check while the second state indicator signal remains invalid.

20. The method of claim 19, wherein the device operation includes one of a pause completion of memory operation associated with the one or more memory devices, a power event state, a security event state, or a temperature state.

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