Circuit arrangement, oscillator and processing system

Abstract

Provided are a circuit device, an oscillator, and a processing system that can effectively use a temperature sensor circuit of the circuit device to perform accurate temperature detection. The circuit device includes an oscillation circuit that generates an oscillation signal using a vibrator; a temperature sensor circuit that outputs temperature detection data; a temperature compensation circuit that temperature-compensates an oscillation frequency of the oscillation signal based on the temperature detection data; a memory that stores correction data for correcting the temperature detection data to find a temperature; and an interface circuit that outputs the temperature detection data and the correction data.

Description

Technical Field

[0001] This invention relates to circuit devices, oscillators, and processing systems. Background Technology

[0002] Previously, circuit devices with oscillation circuits that cause oscillators such as quartz oscillators to oscillate were known. In such circuit devices, there are circuit devices that include a temperature sensor circuit for temperature compensation of the oscillation frequency of the oscillation circuit. Furthermore, Patent Document 1 discloses an RTC (Real-Time Clock) with temperature compensation function that interrupts output when the detected temperature exceeds a threshold.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2001-222342

[0004] In a circuit device with an oscillation circuit and a temperature sensor circuit, if the temperature detection data from the temperature sensor circuit can be output to an external device, an external processing device can effectively utilize this data to measure the temperature of the surrounding environment. In this case, to output accurate temperature detection data to the external processing device, a calibration circuit is needed inside the circuit device to correct the temperature detection results of the temperature sensor circuit. However, installing such a calibration circuit can lead to problems such as wasted power consumption. Summary of the Invention

[0005] One aspect of this disclosure relates to a circuit apparatus comprising: an oscillation circuit that generates an oscillation signal using an oscillator; a temperature sensor circuit that outputs temperature detection data; a temperature compensation circuit that performs temperature compensation on the oscillation frequency of the oscillation signal based on the temperature detection data; a memory that stores correction data for correcting the temperature detection data to determine the temperature; and an interface circuit that outputs the temperature detection data and the correction data.

[0006] Another aspect of the present invention relates to an oscillator comprising: an oscillator; and a circuit arrangement comprising: an oscillation circuit that generates an oscillation signal using the oscillator; a temperature sensor circuit that outputs temperature detection data; a temperature compensation circuit that performs temperature compensation on the oscillation frequency of the oscillation signal based on the temperature detection data; a memory that stores correction data for correcting the temperature detection data to determine the temperature; and an interface circuit that outputs the temperature detection data and the correction data.

[0007] Furthermore, another aspect of this disclosure relates to a processing system comprising: the oscillator described above; and a processing device electrically connected to the oscillator, the processing device performing computational processing to correct the temperature detection data based on the correction data, and detecting the temperature. Attached Figure Description

[0008] Figure 1 This is a structural example of the circuit device in this embodiment.

[0009] Figure 2 This is a diagram illustrating the relationship between temperature measurement data and temperature.

[0010] Figure 3 This is a detailed structural example of the circuit device in this embodiment.

[0011] Figure 4 This is a detailed structural example of the circuit device in this embodiment.

[0012] Figure 5 This is a comparative example of the structure of this embodiment.

[0013] Figure 6 This is a comparative example of the structure of this embodiment.

[0014] Figure 7 This is an explanatory diagram illustrating the setting of the upper and lower limits in the comparative example.

[0015] Figure 8 This is an explanatory diagram of the interrupt signal generation in the comparative example.

[0016] Figure 9 This is an explanatory diagram illustrating the setting of the upper and lower limits in this embodiment.

[0017] Figure 10 This is an explanatory diagram of the interrupt signal generation in this embodiment.

[0018] Figure 11 This is an explanatory diagram of the operational circuit's computational processing.

[0019] Figure 12 This is an explanatory diagram of the operational circuit's computational processing.

[0020] Figure 13 This is a structural example of a processing system that includes an oscillator and a processing device.

[0021] Figure 14 This is an example of the structure of the I / O circuit of the interface circuit.

[0022] Figure 15 This is a signal waveform diagram illustrating a communication example of this embodiment.

[0023] Figure 16This is a signal waveform diagram illustrating a communication example of this embodiment.

[0024] Figure 17 This is an explanatory diagram of a communication protocol example in this embodiment.

[0025] Figure 18 This is an explanatory diagram of interrupt signals.

[0026] Figure 19 This is the first construction example of an oscillator.

[0027] Figure 20 This is the second construction example of an oscillator.

[0028] Label Explanation

[0029] 4: Oscillator; 6: First substrate; 7: Second substrate; 8: Third substrate; 10: Vibrator; 15: Package; 16: Base; 17: Cover; 18, 19: External terminals; 20: Circuit device; 30: Oscillating circuit; 32: Variable capacitor circuit; 40: Temperature sensor circuit; 42: Ring oscillator; 44: Counter; 46: Counter control unit; 48: Analog correction circuit; 49: Digital correction circuit; 50: Logic circuit; 60: Temperature compensation circuit; 61: Arithmetic circuit; 62: Interrupt signal generation circuit; 63: First register; 64: Second register; 65: Comparison circuit; 66, 67: Comparator; 68: OR circuit; 70: Memory; 72: Non-volatile memory; 80: Interface circuit; 82: I / O circuit; 90: Output circuit; 96: Power supply circuit; 100: Processing device; 110: Interface circuit; 200: Processing unit; System; BF: Input buffer; BMP: Bump; CDC1, CDC2: Connection; CK: Clock signal; DA: Data signal; DCT: Correction data; DFC: Frequency adjustment data; DTD: Temperature detection data; ECK: Clock input terminal; EDA: Data terminal; EDTD: Convert temperature detection data; EGND: Ground terminal; EVDD: Power terminal; INT: Interrupt signal; IV: Inverter; UL: Upper limit; LL: Lower limit; LUT: Lookup table; OFS: Offset; SL: Slope; OSC: Oscillation signal; PCK: Clock output connection disk; PDA: Connection disk 1; PGND: Ground connection disk; PVDD: Power connection disk; PX1, PX2: Connection disks; RP: Resistor; TCK: Clock output terminal; TDA: Terminal 1; TGND: Ground terminal; TVDD: Power terminal; TR: Transistor. Detailed Implementation

[0030] The embodiments will now be described. Furthermore, the embodiments described below do not unduly limit the scope of the claims. Also, not all structures described in these embodiments are necessarily essential structural elements.

[0031] 1. Circuit device

[0032] Figure 1 An example of the structure of the circuit device 20 of this embodiment is shown. The circuit device 20 of this embodiment includes: an oscillation circuit 30 that causes the oscillator 10 to oscillate; a temperature sensor circuit 40 that detects temperature; a temperature compensation circuit 60 that performs temperature compensation; a memory 70 that stores information; and an interface circuit 80 that performs communication interface processing.

[0033] The oscillator 10 is a component that generates mechanical vibration through an electrical signal. The oscillator 10 can be implemented, for example, using a quartz resonator or similar vibrating plate. For instance, the oscillator 10 can be implemented using a tuning fork type quartz resonator, a double tuning fork type quartz resonator, or a quartz resonator with an AT cut or SC cut for thickness shear vibration. For example, the oscillator 10 can be an oscillator built into a temperature-compensated quartz oscillator (TCXO) without a thermostatic bath, or an oscillator built into a thermostatic bath type quartz oscillator (OCXO) with a thermostatic bath. Furthermore, the oscillator 10 of this embodiment can be implemented using various vibrating plates, such as those other than tuning fork type, double tuning fork type, or thickness shear vibration type, or piezoelectric resonators made of materials other than quartz. For example, the oscillator 10 can also be a SAW (Surface Acoustic Wave) resonator or a MEMS (Micro Electro Mechanical Systems) oscillator formed using a silicon substrate as a silicon oscillator.

[0034] Circuit device 20 is an integrated circuit device called an IC (Integrated Circuit). For example, circuit device 20 is an IC manufactured using semiconductor processes, which is a semiconductor chip on a semiconductor substrate on which circuit elements are formed. Figure 1 In the circuit device 20, there are an oscillation circuit 30, a temperature sensor circuit 40, a temperature compensation circuit 60, a memory 70, and an interface circuit 80.

[0035] The oscillation circuit 30 is a circuit that causes the oscillator 10 to oscillate. For example, the oscillation circuit 30 generates an oscillation signal OSC by causing the oscillator 10 to oscillate. The oscillation signal OSC is an oscillation clock signal. As an example, the oscillation circuit 30 generates an oscillation signal OSC with a frequency of, for example, 32 kHz. However, the oscillation frequency is not limited to 32 kHz. For example, the oscillation circuit 30 can be implemented using an oscillation drive circuit and passive components such as capacitors or resistors electrically connected to one end and the other end of the oscillator 10. The drive circuit can be implemented, for example, using a CMOS inverter circuit or a bipolar transistor. The drive circuit is the core circuit of the oscillation circuit 30, and the drive circuit drives the oscillator 10 with voltage or current, thereby causing the oscillator 10 to oscillate. As the oscillation circuit 30, various types of oscillation circuits, such as inverter type, Pierce type, Colpitts type, or Hartley type, can be used. In addition, a variable capacitor circuit is provided in the oscillation circuit 30, and the oscillation frequency can be adjusted by adjusting the capacitance of the variable capacitor circuit. The variable capacitor circuit can be implemented, for example, using a capacitor array and a switch array connected to the capacitor array. Alternatively, a variable capacitor circuit can be implemented using variable capacitor elements such as varactor diodes. Furthermore, the connection in this embodiment is an electrical connection. An electrical connection is a connection capable of transmitting electrical signals and transmitting information via electrical signals. An electrical connection can also be a connection via passive components, etc.

[0036] Temperature sensor circuit 40 measures the ambient temperature and other temperatures of oscillator 10 and circuit device 20, and outputs the results as temperature detection data (DTD). Temperature detection data (DTD) is data that increases or decreases monotonically relative to temperature within the operating temperature range of circuit device 20, for example, as described later. Figure 4 As shown, the temperature sensor circuit 40 is a temperature sensor that utilizes the temperature dependence of the oscillation frequency of the ring oscillator 42. Specifically, as... Figure 4 As shown, the temperature sensor circuit 40 includes a ring oscillator 42 and a counter 44. The counter 44 counts the output pulse signal of the ring oscillator 42 as an oscillation signal during a counting period defined by a clock signal CK based on the oscillation signal OSC from the oscillation circuit 30, and outputs the count value as temperature detection data DTD. Alternatively, the temperature sensor circuit 40 may also include: an analog temperature sensor that utilizes the temperature dependence of the forward voltage of a PN junction to output a temperature detection voltage; and an A / D conversion circuit that performs A / D conversion on the temperature detection voltage to output temperature detection data DTD.

[0037] The temperature compensation circuit 60 performs temperature compensation processing based on the temperature detection data DTD from the temperature sensor circuit 40. This temperature compensation processing includes, for example, suppressing and compensating for fluctuations in the oscillation frequency caused by temperature variations. Specifically, the temperature compensation circuit 60 performs temperature compensation processing on the oscillation frequency of the oscillation circuit 30, ensuring that the frequency remains constant even in the presence of temperature variations. More specifically, the temperature compensation circuit 60 performs temperature compensation processing based on digital calculations, which are performed using the temperature detection data DTD from the temperature sensor circuit 40.

[0038] The memory 70 is a storage device for storing information. The memory 70 can be implemented, for example, using a semiconductor memory. For example, the memory 70 is preferably implemented using a non-volatile memory, but it is not limited to this. The memory 70 stores various information required for the operation of the circuit device 20. Furthermore, the memory 70 stores correction data DCT used to calibrate the temperature detection data DTD to determine the temperature.

[0039] Interface circuit 80 is a circuit that serves as an interface with an external device, such as one described later. Figure 13 The circuit shown communicates with the external processing device 100. In this embodiment, the interface circuit 80 outputs temperature detection data DTD from the temperature sensor circuit 40 and correction data DCT from the memory 70. That is, the interface circuit 80 outputs the temperature detection data DTD and the correction data DCT to the external processing device 100.

[0040] The interface circuit 80 can be implemented, for example, through a serial interface circuit that performs serial interface communication. For example, the interface circuit 80 can be implemented through a serial interface circuit described later. Figure 13 The serial interface circuit shown can be implemented using other serial interface circuits such as SPI (Serial Peripheral Interface) and I2C (Inter-Integrated Circuit). SPI or I2C uses a serial interface that employs a serial clock signal and serial data signals for communication. Furthermore, as interface circuit 80, variations of the parallel interface circuit for parallel communication can also be implemented.

[0041] As mentioned above, such as Figure 1As shown, the circuit device 20 of this embodiment includes an oscillation circuit 30, a temperature sensor circuit 40, a temperature compensation circuit 60, a memory 70, and an interface circuit 80. The oscillation circuit 30 generates an oscillation signal OSC using an oscillator 10, the temperature sensor circuit 40 detects the temperature, and outputs temperature detection data DTD. Furthermore, the temperature compensation circuit 60 performs temperature compensation on the oscillation frequency of the oscillation signal OSC based on the temperature detection data DTD, and the memory 70 stores correction data DCT used to correct the temperature detection data DTD to calculate the temperature. For example, during the manufacturing or inspection of the circuit device 20 or devices such as oscillators in which the circuit device 20 is assembled, the correction data DCT used to calculate the temperature is calculated based on the temperature detection data DTD output by the temperature sensor circuit 40. Then, the calculated correction data DCT is stored in the memory 70. Then, the interface circuit 80 outputs the temperature detection data DTD and the correction data DCT to the outside. The temperature detection data DTD is data used to determine the detected temperature and is data corresponding to the detected temperature. The calibration data DCT is data used by the external processing device 100 to determine the corresponding temperature based on the temperature detection data DTD. For example, the calibration data DCT is data used to correct the deviation between the temperature and the corresponding temperature detection data DTD.

[0042] Thus, in the circuit device 20 of this embodiment, in addition to the temperature detection data DTD, the interface circuit 80 also outputs correction data DCT to the outside for correcting the temperature detection data DTD to obtain the temperature. Therefore, Figure 13 The external processing device 100 is capable of performing calculations to correct the temperature detection data DTD received from the interface circuit 80 based on the correction data DCT received from the interface circuit 80, and measuring the accurate temperature corresponding to the temperature detection data DTD.

[0043] For example, Figure 2 An example of the characteristics of temperature detection data (DTD) relative to temperature is shown. Figure 2 The diagram illustrates an example of the characteristics of the temperature detection data (DTD) in devices DVA, DVB, DVC, and DVD. Devices DVA, DVB, DVC, and DVD are associated with circuitry 20 or, as described later, with circuitry 20 assembled thereon. Figure 3 The oscillator 4 corresponds to this. For example, due to variations in the device's manufacturing process, the characteristics of the temperature sensing data DTD may deviate. For instance, in the characteristics of the temperature sensing data DTD for devices DVA to DVD, the slope SL and offset OFS differ, resulting in individual variation deviations. Correction data DCT is used to correct such deviations in the characteristics of the temperature sensing data DTD relative to temperature. For example, in... Figure 2 In this case, the temperature can be expressed using the temperature detection data DTD as shown in equation (1).

[0044] Temperature (°C) = SL × DTD + OFS (1)

[0045] Therefore, in Figure 2 In the case of individual differences, even with the use of slope SL and offset OFS as correction data DCT, an accurate temperature can be calculated based on the temperature detection data DTD. Taking device DVA as an example, during the manufacturing and inspection of device DVA, an external device such as a tester can calculate the slope SL and offset OFS as correction data DCT by reading the temperature detection data DTD output by the temperature sensor circuit 40 at various temperatures. Then, the calculated correction data DCT is written into the memory 70 of the circuit device 20 and the product is shipped. Furthermore, during the actual operation of device DVA, the interface circuit 80 of device DVA outputs the temperature detection data DTD of the temperature sensor circuit 40 and the correction data DCT written into the memory 70. Furthermore, as a calculation process for correcting the temperature detection data DTD based on the correction data DCT, the external processing device 100 can measure the temperature by performing the calculation process of the above formula (1).

[0046] Here, the correction data DCT is, for example, the coefficient data of a polynomial representing the relationship between temperature and temperature detection data DTD. For example, in equation (1) above, the slope SL and offset OFS of the correction data DCT are the coefficient data of a first-order polynomial representing the relationship between temperature and temperature detection data DTD. More generally, the relationship between temperature and temperature detection data DTD can be represented by a polynomial such as equation (2) below.

[0047] Temperature (°C) = C n ×DTD n +C n-1 ×DTD n-1 ...+C1×DTD+C0 (2)

[0048] At this point, the correction data DCT becomes the coefficient data of the polynomial in equation (2) above, namely C. n C n-1 ...C1, C0. n is an integer greater than or equal to 1. Thus, when the characteristic representing the relationship between temperature and temperature detection data DTD can be expressed or approximated by a polynomial like the one in equation (2) above, C, which is the coefficient data of that polynomial, can be used as... n C n-1 ...C1 and C0 are used as calibration data DCT. Furthermore, the external processing device 100 can measure the temperature accurately by performing calculations to correct the temperature detection data DTD based on the calibration data DCT.

[0049] Furthermore, the calibration data DCT does not need to be the same across the entire temperature range, as will be discussed later. Figure 11 , Figure 12 In cases of balanced computational processing, different correction data DCTs can be set according to the temperature range. Furthermore, the correction method based on correction data DCTs in this embodiment is not limited to such a polynomial approximation method; for example, the memory 70 can implement various modifications such as storing the correspondence between temperature and temperature detection data DTDs in the form of a lookup table.

[0050] 2. Detailed structural example

[0051] Figure 3 A detailed structural example of the circuit device 20 and the oscillator 4 including the circuit device 20 of this embodiment is shown. Figure 3 In the circuit device 20, there are oscillation circuit 30, temperature sensor circuit 40, logic circuit 50, non-volatile memory 72, interface circuit 80, output circuit 90, and power supply circuit 96. Furthermore, the oscillator 4 includes a vibrator 10 and the circuit device 20. The vibrator 10 is electrically connected to the circuit device 20. For example, the vibrator 10 and the circuit device 20 are electrically connected using internal wiring, bonding wires, or metal bumps within a package that houses the vibrator 10 and the circuit device 20.

[0052] The oscillation circuit 30 is electrically connected to the oscillator 10 via connecting disks PX1 and PX2. Connecting disks PX1 and PX2 are for connecting the oscillator. An oscillation drive circuit for the oscillation circuit 30 is disposed between connecting disks PX1 and PX2. Furthermore, the oscillation circuit 30 includes a variable capacitor circuit 32. The variable capacitor circuit 32, for example, includes a capacitor array and a switch array connected to the capacitor array. The switches of the switch array in the variable capacitor circuit 32 are turned on and off according to frequency adjustment data from the temperature compensation circuit 60. For example, the variable capacitor circuit 32 includes a first capacitor array having multiple capacitors whose capacitance values ​​are binary-weighted. Furthermore, the variable capacitor circuit 32 includes a first switch array, each switch of which has multiple switches for turning on and off the connection between each capacitor of the first capacitor array and the connecting disk PX1. Furthermore, as the variable capacitor circuit 32, it may also be configured as follows: a first variable capacitor circuit having a first capacitor array and a first switch array, connected to the connection disk PX1; and a second variable capacitor circuit having a second capacitor array and a second switch array, connected to the connection disk PX2. The switches of the first and second switch arrays are turned on and off according to the frequency adjustment data.

[0053] Logic circuit 50 is a control circuit that performs various control processes. For example, logic circuit 50 performs overall control of circuit device 20, or controls the sequence of actions of circuit device 20. Furthermore, logic circuit 50 implements various processes for controlling oscillation circuit 30, or controls temperature sensor circuit 40 or power supply circuit 96, or controls the reading or writing of information in non-volatile memory 72. Logic circuit 50 can be implemented, for example, using an ASIC (Application Specific Integrated Circuit) circuit based on automatic configuration routing, such as a gate array.

[0054] Logic circuit 50 includes temperature compensation circuit 60 and interrupt signal generation circuit 62. Details of interrupt signal generation circuit 62 will be described later. Figure 4 The explanation is provided below.

[0055] The temperature compensation circuit 60 calculates frequency adjustment data based on the temperature detection data DTD. Furthermore, by adjusting the capacitance value of the variable capacitor circuit 32 of the oscillation circuit 30 according to the calculated frequency adjustment data, temperature compensation processing of the oscillation frequency of the oscillation circuit 30 is achieved. For example, the non-volatile memory 72 stores a lookup table (LUT) representing the correspondence between the temperature detection data DTD and the frequency adjustment data. Then, the temperature compensation circuit 60 uses the lookup table LUT to perform temperature compensation processing to calculate the frequency adjustment data based on the temperature detection data DTD.

[0056] Non-volatile memory 72 is a memory that retains information even when no power is supplied. For example, non-volatile memory 72 is a memory that can retain information even when no power is supplied and can rewrite the information. Non-volatile memory 72 stores various information required for the operation of circuit device 20, etc. Non-volatile memory 72 can be implemented by EEPROM (Electrically Erasable Programmable Read-Only Memory) or other types of memory, such as FAMOS (Floating Gate Avalanche Injection MOS memory) or MONOS (Metal-Oxide-Nitride-Oxide-Silicon memory).

[0057] Moreover, in Figure 3In this circuit, non-volatile memory 72 stores lookup table (LUT) and correction data (DCT). Temperature compensation circuit 60 uses lookup table (LUT) to perform the aforementioned temperature compensation process. Alternatively, temperature compensation circuit 60 can load information from lookup table (LUT) into storage circuits such as registers and perform temperature compensation processing based on the information loaded into the storage circuits. Furthermore, with... Figure 1 The non-volatile memory 72 corresponding to the memory 70 stores the calibration data DCT. Furthermore, in addition to outputting the temperature detection data DTD from the temperature sensor circuit 40 to the outside, the interface circuit 80 also outputs the calibration data DCT stored in the non-volatile memory 72 to the outside. Additionally, the readout control of the calibration data DCT from the non-volatile memory 72 is performed, for example, by the logic circuit 50.

[0058] Thus, in Figure 3 middle, Figure 1 The memory 70 is implemented by a non-volatile memory 72, and the calibration data DCT is stored in the non-volatile memory 72. In this way, the calibration data DCT used to calibrate the temperature detection data DTD to obtain the temperature is stored in the non-volatile memory 72. The calibration data DCT can be read from the non-volatile memory 72 and output to the outside along with the temperature detection data DTD through the interface circuit 80.

[0059] The interface circuit 80 outputs a data signal DA to the first connection panel PDA. Furthermore, this data signal DA is also output to the outside via the first terminal TDA of the oscillator 4. For example, the interface circuit 80 outputs temperature detection data DTD and calibration data DCT as data signal DA. Additionally, data signals DA from the outside are also input to the interface circuit 80.

[0060] Output circuit 90 outputs a clock signal CK based on the oscillation signal OSC. For example, output circuit 90 buffers the oscillation clock signal, i.e., the oscillation signal OSC, from oscillation circuit 30 and outputs it as clock signal CK to clock output connector PCK. Then, this clock signal CK is output to the outside via the clock output terminal TCK of oscillator 4. For example, output circuit 90 outputs clock signal CK in the form of a single-ended CMOS signal. Alternatively, output circuit 90 can also output clock signal CK in a signal form other than CMOS. Furthermore, a clock signal generation circuit, such as a PLL circuit, can be provided after oscillation circuit 30. This PLL circuit generates a clock signal CK with a frequency that is doubled by the frequency of the oscillation signal OSC. Output circuit 90 can also buffer and output the clock signal CK generated by this clock signal generation circuit.

[0061] The first connection pad PDA connected to the interface circuit 80 and the first terminal TDA of the oscillator 4 connected to the first connection pad PDA can also be used as an output enable connection pad and an output enable terminal. For example, when the first connection pad PDA is used as an output enable connection pad, when the first connection pad PDA and the first terminal TDA are set to an active level, such as a high level, the output circuit 90 outputs the clock signal CK to the outside. On the other hand, when the first connection pad PDA and the first terminal TDA are set to an inactive level, such as a low level, the output circuit 90 sets the clock signal CK to a fixed voltage level, such as a low level.

[0062] The power supply circuit 96 is supplied with power supply voltage VDD from the power connection pad PVDD and ground voltage GND from the ground connection pad PGND, supplying various power supply voltages used in the internal circuits of the circuit device 20. For example, the power supply circuit 96 supplies an regulated power supply voltage, after adjusting the power supply voltage VDD, to various circuits such as the oscillation circuit 30 of the circuit device 20.

[0063] The power connector PVDD is the connector to which the power supply voltage VDD is supplied. The connector is a terminal of the circuit device 20, which is a semiconductor chip. For example, in the connector area, a metal layer is exposed from a passivation film that serves as an insulating layer, and this exposed metal layer forms the connector as a terminal of the circuit device 20. For example, the power supply voltage VDD from an external power supply device is supplied to the power connector PVDD. The ground connector PGND is the terminal to which the ground voltage GND is supplied. GND can also be called VSS, and the ground voltage is, for example, the ground potential. In this embodiment, ground is appropriately referred to as GND. The power connector PVDD, ground connector PGND, clock output connector PCK, and first connector PDA are electrically connected to the external terminals of the oscillator 4, namely the power terminal TVDD, ground terminal TGND, clock output terminal TCK, and first terminal TDA. For example, these connectors and terminals are electrically connected using internal wiring of the package, bonding wires, or metal bumps.

[0064] Figure 4A more detailed structural example of the circuit arrangement 20 of this embodiment is shown. The temperature sensor circuit 40 includes a ring oscillator 42, a counter control unit 46, and a counter 44. The ring oscillator 42 is a circuit in which multiple delay elements are connected in a ring. Specifically, the ring oscillator 42 is, for example, a circuit in which an odd number of inverter circuits or other signal inversion circuits are connected in a ring, and outputs an output pulse signal as an oscillation signal. The counter 44 uses a clock signal based on the oscillation signal OSC to count the number of pulses of the output pulse signal of the ring oscillator 42, and outputs temperature detection data DTD based on the count value obtained by the counting process. The counter control unit 46 controls the counter 44. For example, the counter 44 calculates the temperature detection data DTD by calculating the count value of the number of pulses of the output pulse signal within the counting period specified by the clock signal.

[0065] The arithmetic circuit 61 performs calculations to adjust the temperature sensitivity of the temperature detection data DTD, and outputs the processed temperature detection data DTD to the lookup table LUT. The temperature sensitivity of the temperature detection data DTD is the degree of change of the temperature detection data DTD relative to temperature changes. The calculation processing of the arithmetic circuit 61 will be described later. Figure 11 , Figure 12 The details are explained below. Alternatively, the arithmetic circuit 61 can be omitted, and the temperature detection data DTD from the temperature sensor circuit 40 can be directly input into the lookup table LUT.

[0066] and Figure 1 The non-volatile memory 72 corresponding to memory 70 stores a lookup table (LUT) that maps temperature detection data DTD and frequency adjustment data DFC. For example, in the lookup table LUT, each value of the frequency adjustment data DFC corresponds to each value of the temperature detection data DTD. For example, the temperature detection data DTD is data that monotonically increases or monotonically decreases relative to the temperature. Then, as... Figure 4 The arithmetic circuit 61 is configured to perform calculations to adjust the temperature sensitivity of the temperature detection data DTD. That is, it performs calculations to adjust the degree of change of the temperature detection data DTD relative to temperature changes. Therefore, in the processed temperature detection data DTD, the slope of the change in the temperature detection data DTD relative to the temperature change varies depending on the temperature range.

[0067] The temperature compensation circuit 60 refers to a lookup table (LUT) and outputs frequency adjustment data (DFC) corresponding to the temperature detection data (DTD). For example, the temperature compensation circuit 60 reads the frequency adjustment data (DFC) corresponding to the temperature detection data (DTD) from the lookup table (LUT) and outputs it to the frequency adjustment circuit of the oscillation circuit 30, i.e., the variable capacitor circuit 32. In this way, the capacitance of the variable capacitor circuit 32 is adjusted using the frequency adjustment data (DFC) based on the temperature detection data (DTD), thereby adjusting the oscillation frequency of the oscillation circuit 30 and achieving temperature compensation processing of the oscillation frequency.

[0068] In addition, Figure 4 In this circuit, the circuit device 20 includes an arithmetic circuit 61. The arithmetic circuit 61 performs arithmetic processing to adjust the temperature sensitivity and outputs the processed temperature detection data DTD to a lookup table LUT. For example, the arithmetic circuit 61 performs a conversion process that makes the slope of the temperature detection data DTD relative to temperature in a first temperature range different from the slope of the temperature detection data DTD relative to temperature in a second temperature range, as an arithmetic processing to adjust the temperature sensitivity. If the arithmetic circuit 61 that performs such arithmetic processing to adjust the temperature sensitivity is provided, then even if the temperature sensitivity varies according to the temperature range, the arithmetic processing to adjust the temperature sensitivity appropriately can be performed, and the processed temperature detection data DTD can be output to the lookup table LUT.

[0069] In addition, Figure 4 In this embodiment, the temperature detection data DTD processed by the arithmetic circuit 61 is output to the outside via the interface circuit 80. By outputting the processed temperature detection data DTD in this way, compared with the case where the temperature detection data DTD before processing is output, the individual difference deviation can be reduced. However, this embodiment is not limited to this, and the temperature detection data DTD before processing by the arithmetic circuit 61 can also be output to the outside via the interface circuit 80.

[0070] In addition, such as Figure 4As shown, the circuit device 20 includes an interrupt signal generation circuit 62 that generates an interrupt signal INT. The interrupt signal generation circuit 62 generates the interrupt signal INT when the temperature detection data DTD exceeds the upper limit value UL or falls below the lower limit value LL. The upper limit value UL and the lower limit value LL can be written by an external processing device 100, for example, via the interface circuit 80, or stored in a memory 70 such as a non-volatile memory 72. Furthermore, the generated interrupt signal INT is output to the external processing device 100, for example, via the interface circuit 80. By providing such an interrupt signal generation circuit 62, the external processing device 100 can be notified that the temperature corresponding to the temperature detection data DTD exceeds the upper limit temperature or falls below the lower limit temperature. Therefore, the external processing device 100 can perform interrupt processing corresponding to the interrupt signal INT.

[0071] In addition, for example Figure 4 As shown, the interrupt signal generation circuit 62 includes a first register 63, a second register 64, and a comparison circuit 65. The first register 63 stores the upper limit value UL, and the second register 64 stores the lower limit value LL. Then, the comparison circuit 65 compares the temperature detection data DTD with either the upper limit value UL or the lower limit value LL, generating an interrupt signal INT. The first register 63 and the second register 64 can be implemented, for example, using a storage circuit such as a flip-flop circuit. An external processing device 100 can write the upper limit value UL and the lower limit value LL to the first register 63 and the second register 64, for example, via an interface circuit 80. Alternatively, a memory 70, such as a non-volatile memory 72, can also store the upper limit value UL and the lower limit value LL, and load the upper limit value UL and the lower limit value LL from the memory 70 into the first register 63 and the second register 64. Furthermore, the comparison circuit 65 includes comparators 66 and 67 and an OR circuit 68. The comparator 66 compares the value of the temperature detection data DTD with the upper limit value UL, and outputs a first comparison signal that becomes valid when the value of the temperature detection data DTD exceeds the upper limit value UL. Comparator 67 compares the temperature detection data DTD with the lower limit LL, and outputs a second comparison signal that becomes active when the temperature detection data DTD is lower than the lower limit LL. OR circuit 68 outputs an interrupt signal INT, which becomes active when either the first comparison signal from comparator 66 or the second comparison signal from comparator 67 becomes active. This interrupt signal INT is output to an external source, for example, via interface circuit 80.

[0072] The interrupt signal generation circuit 62, with this structure, pre-stores an upper limit value UL and a lower limit value LL in register 1 63 and register 2 64. By comparing the upper limit value UL and the lower limit value LL with the temperature detection data DTD, an interrupt signal INT can be generated. Furthermore, the interrupt signal INT can be used to notify an external processing device 100, etc., that the temperature corresponding to the temperature detection data DTD exceeds the upper limit temperature or falls below the lower limit temperature.

[0073] Furthermore, in this embodiment, the memory 70, such as the non-volatile memory 72, can also store the upper limit value UL and the lower limit value LL. For example, during the manufacturing and inspection of the circuit device 20 and the oscillator 4, an external device writes the upper limit value UL and the lower limit value LL calculated based on the correction data DCT into the memory 70 via the interface circuit 80. In this way, the upper limit value UL and the lower limit value LL, which have been corrected for individual differences according to the correction data DCT, can be written into and stored in the memory 70. Moreover, during the normal operation of the circuit device 20 and the oscillator 4, the upper limit value UL and the lower limit value LL are loaded from the memory 70 into the first register 63 and the second register 64. The interrupt signal generation circuit 62 compares the loaded upper limit value UL and the lower limit value LL with the temperature detection data DTD, thereby generating an interrupt signal INT. In this way, the interrupt signal generation circuit 62 can output an appropriate interrupt signal INT generated by comparing the upper limit value UL and the lower limit value LL, which have been corrected for individual differences, with the temperature detection data DTD to the outside.

[0074] In the above explanation Figure 3 , Figure 4 In the circuit device 20, the temperature sensor circuit 40 also outputs temperature detection data DTD, which is stored as correction data DCT in the non-volatile memory 72 of the memory 70. Then, the interface circuit 80 outputs the temperature detection data DTD and the correction data DCT to the outside. Thus, for example... Figure 13 The external processing device 100 performs calculations to correct the temperature detection data DTD based on the correction data DCT, and can detect the temperature accurately.

[0075] For example, Figure 5 , Figure 6 This is a structural example illustrating a comparative example of this embodiment. Figure 5 In the temperature sensor circuit 40, an analog correction circuit 48 is provided. This analog correction circuit 48 corrects, for example, the current flowing through the transistor constituting the delay element of the ring oscillator 42, thereby correcting the temperature detection data DTD. That is, the analog correction circuit 48 performs… Figure 2The characteristics of the temperature detection data DTD described herein are corrected for individual temperature variations. Then, the interface circuit 80 outputs the corrected temperature detection data DTD to the outside. Furthermore, in... Figure 6 In the temperature sensor circuit 40, a digital correction circuit 49 is provided. This digital correction circuit 49 performs digital correction of the temperature detection data DTD output from the counter 44, thereby correcting the individual differences in the characteristics of the temperature detection data DTD relative to the temperature.

[0076] In such Figure 5 , Figure 6 In the comparative example where correction is performed using analog correction circuit 48 or digital correction circuit 49, the power consumption of circuit device 20 increases due to the power consumption in analog correction circuit 48 or digital correction circuit 49. Furthermore, by including analog correction circuit 48 or digital correction circuit 49, the circuit layout area of ​​circuit device 20 increases, becoming a major reason for the increased cost. Additionally, in... Figure 5 In the calibration of the analog calibration circuit 48, the accuracy of the calibration for individual difference deviations is not high, so there is also the problem of deterioration in the accuracy of temperature measurement.

[0077] For example, in the circuit device 20 that uses a lookup table (LUT) for temperature compensation processing, it would not normally be necessary to use the analog correction circuit 48 or the digital correction circuit 49 to correct for temperature detection deviations. This is because, in such a circuit device 20, a lookup table (LUT) is used to correct for both the temperature detection deviation in the temperature sensor circuit 40 and the temperature characteristic deviation of the oscillator 10. However, in an oscillator 4 such as an RTC, the circuit device 20 cannot predict when the external processing device 100 will read the temperature detection data DTD. Furthermore, in the event that the temperature detected according to the temperature detection data DTD exceeds the upper limit temperature or falls below the lower limit temperature, the circuit device 20 cannot predict when this event will occur in the event of an interruption. Therefore, in Figure 5 , Figure 6 In the comparative example, although it is not necessary, the temperature detection deviation still needs to be corrected using the analog correction circuit 48 and the digital correction circuit 49, which results in the unnecessary consumption of power in these circuits.

[0078] Regarding this point, according to Figure 1 , Figure 3 , Figure 4In this embodiment, the circuit device 20, for example, does not perform temperature detection deviation correction, but outputs temperature detection data DTD from the temperature sensor circuit 40 from the interface circuit 80. Furthermore, correction data DCT, used to calibrate the temperature detection data DTD to obtain the temperature, is stored in a memory 70 such as a non-volatile memory 72. The temperature detection data DTD without temperature detection deviation correction and the correction data DCT from the memory 70 are output to the outside via the interface circuit 80. Thus, the external processing device 100, which reads the temperature detection data DTD and correction data DCT from the circuit device 20, can detect an accurate temperature by calibrating the temperature detection data DTD according to the correction data DCT. The temperature detection calibration process is performed only a minimum number of times in the overall system, thereby reducing the overall power consumption of the system. Furthermore, according to this embodiment, it is not necessary to install [a specific component] in the circuit device 20. Figure 5 , Figure 6 The analog correction circuit 48 and digital correction circuit 49 are shown. This eliminates the problems of wasted power consumption due to corrections in the analog correction circuit 48 or digital correction circuit 49, or the increased circuit size and cost caused by these circuits. Furthermore, the external processing device 100 that corrects the temperature detection data DTD based on the correction data DCT is implemented, for example, by an MCU (Micro Controller Unit). Since the MCU has an arithmetic logic unit (ALU), it also has the advantage of being able to correct the temperature detection data DTD based on the correction data DCT without adding additional hardware resources, thereby performing temperature detection.

[0079] Figure 7 , Figure 8 It is about Figure 5 , Figure 6 The diagram illustrates the setting of the upper limit value UL and the lower limit value LL, and the generation of the interrupt signal INT in the comparative example. (See diagram for reference.) Figure 7 As shown, in the comparative example, the upper limit value UL and the lower limit value LL are fixed values. Figure 7 For example, the upper limit value UL corresponding to 65°C is set to a fixed value of 1012, and the lower limit value LL corresponding to 0°C is set to a fixed value of 128. Furthermore, as... Figure 8 As shown, an interrupt signal INT is generated when the temperature exceeds the upper limit of 65°C and the value of the temperature detection data DTD exceeds the upper limit of UL = 1012. Furthermore, an interrupt signal INT is generated when the temperature falls below the lower limit of 0°C and the value of the temperature detection data DTD falls below the lower limit of LL = 128. Thus, in... Figure 5 , Figure 6In the comparative example, the upper limit UL and lower limit LL are fixed values. Therefore, whenever the temperature is measured, both the analog correction circuit 48 and the digital correction circuit 49 correct the temperature detection data DTD. Consequently, power is wasted every time the temperature is measured.

[0080] Figure 9 , Figure 10 This diagram illustrates the setting of the upper limit value UL and the lower limit value LL, and the generation of the interrupt signal INT in this embodiment. Figure 9 As shown, in this embodiment, the upper limit value UL and the lower limit value LL are not fixed values, but are calculated based on the correction data DCT. For example, during the actual operation of the circuit device 20, the external processing device 100 calculates the upper limit value UL and the lower limit value LL according to the correction data DCT and writes them into the first register 63 and the second register 64. Alternatively, during the manufacturing or inspection of the circuit device 20 or the oscillator 4, the external device calculates the upper limit value UL and the lower limit value LL and writes them into the memory 70, and during actual operation, they are loaded from the memory 70 into the first register 63 and the second register 64. Furthermore, as... Figure 10 As shown, an interrupt signal INT is generated when the temperature exceeds 65°C (the upper limit temperature) and the value of the temperature detection data DTD exceeds the upper limit value UL. Furthermore, an interrupt signal INT is generated when the temperature is below 0°C (the lower limit temperature) and the value of the temperature detection data DTD is below the lower limit value LL. In this case, in this embodiment, the analog correction circuit 48 and the digital correction circuit 49 may not be provided, thus preventing unnecessary power consumption in these circuits.

[0081] 3. Operational circuit

[0082] Next, regarding Figure 4 The detailed operation and processing of the arithmetic circuit 61 will be explained. Figure 11 This diagram illustrates the relationship between the temperature characteristics of the oscillation frequency and the address allocation when the temperature detection data (DTD) output by the temperature sensor circuit 40 is directly used as the address of the lookup table (LUT). Here, an example is shown where the temperature detection data (DTD) is linear with respect to temperature; however, a roughly linear relationship between the temperature detection data (DTD) and temperature is acceptable. Additionally, an example is shown where the temperature characteristics of the oscillation frequency are quadratic with respect to temperature; any temperature characteristic where the temperature sensitivity of the oscillation frequency changes with temperature is acceptable.

[0083] Figure 11The temperature characteristic shown is a quadratic characteristic with an upward convexity apex near room temperature. UT1 to UT3 represent temperature ranges with a unit temperature width. Temperature range UT1 is near room temperature, with a relatively small frequency change (FW1) per unit temperature. Temperature range UT2 is slightly further from room temperature, with a moderate frequency change (FW2) per unit temperature. Temperature range UT3 is further from room temperature than UT2, with a larger frequency change (FW3) per unit temperature. The frequency change per unit temperature corresponds to the temperature sensitivity of the oscillation frequency, meaning that the further away from room temperature, the greater the temperature sensitivity. The temperature sensitivity of the oscillation frequency is the degree of change of the oscillation frequency relative to temperature changes.

[0084] The temperature range UT1~UT3 with a unit temperature width corresponds to the address range AW1~ of the lookup table LUT.

[0085] AW3 assigns the frequency variation per unit temperature (FW1 to FW3) to the address range AW1 to AW3. Since the temperature detection data DTD is linear, each address range AW1 to AW3 contains the same number of addresses. Therefore, the frequency variation per address is smaller in temperature range UT1 and larger in temperature range UT3.

[0086] To achieve high-precision temperature compensation while efficiently utilizing the limited capacity of the memory 70, it is preferable to have a uniform frequency variation per address. However, as mentioned above, there is an over-allocation of addresses in temperature range UT1 and an under-allocation in temperature range UT3. For example, reducing the number of addresses per unit temperature can make the allocation in temperature range UT1 more appropriate, but the accuracy of temperature compensation decreases because the frequency variation per address increases in temperature range UT3. On the other hand, increasing the number of addresses per unit temperature can improve the accuracy of temperature compensation in temperature range UT3, but the utilization efficiency of memory 70 decreases because the address allocation increases even though the frequency variation is smaller in temperature range UT1. Thus, when the temperature detection data DTD output by the temperature sensor circuit 40 is directly used as the address of the lookup table LUT, it is difficult to achieve high-precision temperature compensation while efficiently utilizing the limited capacity of the memory 70, such as the non-volatile memory 72.

[0087] Figure 12 This diagram illustrates an example of converting temperature detection data DTD based on the computational processing of the arithmetic circuit 61. The arithmetic circuit 61 converts the temperature detection data DTD by adjusting the temperature sensitivity of the temperature detection data DTD through computational processing. Here, for ease of understanding, the temperature detection data before conversion by the arithmetic circuit 61 is recorded as DTD, and the temperature detection data after conversion by the arithmetic circuit 61, i.e., the converted temperature detection data, is recorded as EDTD. Figure 12The solid line represents the converted temperature detection data EDTD, and the dashed line represents the case where the temperature detection data DTD is directly used as the converted temperature detection data EDTD. Figure 12 In this code, temperature detection data DTD and converted temperature detection data EDTD are represented using decimal numbers. Furthermore, the high-order bits of the converted temperature detection data EDTD, i.e., EDTD[n:i+1], are represented as integers, with one integer value corresponding to one address.

[0088] exist Figure 12 In this context, a larger temperature detection data DTD value corresponds to a higher temperature. The range of temperature detection data DTD from 0 to 72 corresponds to the operating temperature range of circuit device 20. Here, the operating temperature range is divided into three temperature ranges: RTC (corresponding to 0 to 24), RTE (corresponding to 24 to 32), and RTA (corresponding to 32 to 72). The temperature range RTE is near room temperature. Figure 11 As explained in the text, in the temperature characteristics of the oscillation frequency, the temperature range with lower temperature sensitivity of the oscillation frequency is defined. In the temperature characteristics of the oscillation frequency, the temperature ranges RTC and RTA represent the temperature ranges with higher temperature sensitivity of the oscillation frequency compared to room temperature.

[0089] The arithmetic circuit 61 does not change the slope of the temperature detection data DTD corresponding to the temperature range RTE near room temperature, and performs offset addition processing on the temperature detection data DTD, thereby outputting the converted temperature detection data EDTD. Furthermore, the arithmetic circuit 61 sets the slope of the temperature detection data DTD corresponding to the temperature ranges RTC and RTA with high temperature sensitivity to the oscillation frequency to 1.5 times, and performs offset addition processing, thereby outputting the converted temperature detection data EDTD. The offset value added in the offset addition processing is set so that the lower limit of the converted temperature detection data EDTD within the operating temperature range is not negative. Figure 12 In this case, the offset value is set so that the lower limit of the conversion temperature detection data EDTD is zero, but it is acceptable to set the offset value so that the lower limit of the conversion temperature detection data EDTD is above zero.

[0090] Thus, the arithmetic circuit 61 performs calculations to adjust the temperature sensitivity of the temperature detection data DTD. For example, in Figure 12Within the temperature ranges RTC and RTA, the temperature sensitivity of the temperature detection data DTD is adjusted by increasing the slope of the DTD. Therefore, within the temperature ranges RTC and RTA where the temperature sensitivity of the oscillation frequency is high, the temperature sensitivity of the temperature detection data DTD can be adjusted to increase its sensitivity. In other words, according to this embodiment, the temperature detection data DTD conversion process is performed so that the slope of the DTD varies depending on the temperature range. Therefore, the slope of the temperature detection data DTD can be adjusted based on the temperature sensitivity within the temperature characteristics of the oscillation frequency. Specifically, the absolute value of the slope of the temperature detection data DTD can be increased within the temperature range with high temperature sensitivity, and the absolute value of the slope of the temperature detection data DTD can be decreased within the temperature range with low temperature sensitivity. Since the address of the lookup table LUT is specified by the temperature detection data DTD, the larger the absolute value of the slope of the temperature detection data DTD, the larger the number of addresses per unit temperature. Therefore, in a temperature range with high temperature sensitivity, the address allocation per unit temperature can be increased, while in a temperature range with low temperature sensitivity, the address allocation per unit temperature can be decreased. Thus, the limited capacity of the memory 70 can be utilized efficiently and high-precision temperature compensation can be achieved.

[0091] 4. Interface circuit and processing system

[0092] Next, detailed examples of the interface circuit 80 and processing system 200 in this embodiment will be described. For example... Figure 13 As shown, the processing system 200 of this embodiment includes an oscillator 4 and a processing device 100 electrically connected to the oscillator 4. For example, the oscillator 4 and the processing device 100 are electrically connected via wiring on a circuit board. This processing system 200 is, for example, assembled in an electronic device. The electronic device is, for example, a network-related device such as a base station or router, a high-precision measuring device for measuring physical quantities such as distance, time, flow rate, or flow rate, a biological information measuring device for measuring biological information, or an in-vehicle device. In addition, the electronic device may also be a sensor mesh network device, an IoT (Internet of Things) device, a wearable device such as a head-mounted display device or a watch-related device, a robot, a printing device, a projection device, a portable information terminal such as a smartphone, a content providing device for publishing content, or an imaging device such as a digital camera or video camera.

[0093] The processing device 100 can be implemented, for example, using a processor such as an MPU (Micro Processor Unit), an MCU (Micro Controller Unit), or a CPU (Central Processing Unit), or a circuit device such as an ASIC (Application Specific Integrated Circuit). For example, the processing device 100, as an external device, may also include such a circuit device and a circuit board on which the circuit device is mounted. Then, the processing device 100 performs calculations to correct the temperature detection data DTD based on the correction data DCT, and detects the temperature. That is, as... Figure 1 , Figure 3 As explained, the interface circuit 80 of the circuit device 20 transmits temperature detection data DTD and correction data DCT as data signals DA, and the external processing device 100 receives the temperature detection data DTD and correction data DCT. Specifically, the processing device 100 has an interface circuit 110 that receives the temperature detection data DTD and correction data DCT. Then, the processing device 100 performs calculations to correct the temperature detection data DTD based on the correction data DCT, and detects the temperature corresponding to the temperature detection data DTD. The calculations to correct the temperature detection data DTD can be executed, for example, by a program operating on the processor of the processing device 100.

[0094] Thus, according to Figure 13 The processing system 200 performs temperature detection by correcting temperature detection data DTD based on calibration data DCT in an external processing device 100, not within the circuit device 20. Therefore, when the processing device 100 needs to detect temperature, it performs temperature detection by correcting the temperature detection data DTD based on the calibration data DCT. For example, in... Figure 5 , Figure 6 In the comparative example, the analog correction circuit 48 or the digital correction circuit 49 always performs correction processing for temperature detection, even when temperature detection is not required, thus wasting power. In contrast, in Figure 13 In this process, the calibration process for temperature detection is performed only a minimum number of times throughout the entire processing system 200, thus reducing the power consumption of the entire processing system 200.

[0095] In addition, Figure 13In the circuit device 20, there are: a clock output connection disk PCK; an output circuit 90 that outputs a clock signal CK based on the oscillation signal OSC to an external processing device 100 via the clock output connection disk PCK; and a first connection disk PDA. The clock output connection disk PCK is electrically connected to the clock output terminal TCK of the oscillator 4, and the first connection disk PDA is electrically connected to the first terminal TDA of the oscillator 4. In addition, the output circuit 90 outputs a buffered signal of the oscillation signal OSC as the clock signal CK based on the oscillation signal OSC.

[0096] Alternatively, a PLL circuit can be configured to generate a clock signal CK that multiplies the frequency of the oscillation signal OSC from the oscillation circuit 30, and the output circuit 90 outputs the clock signal CK from this PLL circuit to the clock output connection disk PCK. In this case, the clock signal CK based on the oscillation signal OSC becomes a clock signal with the frequency multiplied by the oscillation signal OSC. For example, the PLL circuit may have a voltage-controlled oscillator circuit that performs a phase comparison between the oscillation signal OSC, which serves as a reference clock signal, and a feedback clock signal, and outputs a clock signal CK with the frequency multiplied by the oscillation signal OSC. In this case, a fractional-N type PLL circuit capable of fractional frequency multiplication can also be used as the PLL circuit.

[0097] Furthermore, the interface circuit 80 communicates with the processing device 100 via the data signal DA. Specifically, the processing device 100 has an interface circuit 110, and serial communication based on the data signal DA is performed between the interface circuit 110, which acts as a master device, and the interface circuit 80, which acts as a slave device. For example, the processing device 100 has a data terminal EDA for inputting and outputting the data signal DA, a clock input terminal ECK for inputting the clock signal CK, a power supply terminal EVDD for supplying VDD, and a ground terminal EGND for supplying GND. Then, the interface circuit 110 of the processing device 100 communicates with the interface circuit 80 via the clock signal CK input to the clock input terminal ECK and the data signal DA input and output via the data terminal EDA.

[0098] Furthermore, in this communication, the output circuit 90 outputs a clock signal CK to the processing device 100, which acts as the communication master device. That is, the master device typically outputs a clock signal for communication; in contrast, in… Figure 13In this configuration, the output circuit 90 on the slave device side outputs a clock signal CK. Furthermore, the interface circuit 80, acting as a communication slave device, receives a data signal DA transmitted from the processing unit 100, synchronized with the clock signal CK, via the first connection disk PDA. That is, the processing unit 100, acting as the master device, transmits the data signal DA synchronously with the clock signal CK from the slave device, and the interface circuit 80, acting as the slave device, receives the transmitted data signal DA. Alternatively, the interface circuit 80, acting as the communication slave device, transmits the data signal DA synchronously with the clock signal CK to the processing unit 100 via the first connection disk PDA. That is, the interface circuit 80, acting as the slave device, transmits the data signal DA synchronously with the clock signal CK, and the processing unit 100, acting as the master device, receives the transmitted data signal DA. In this way, synchronous communication of the data signal DA can be performed between the processing unit 100, acting as the communication master device, and the interface circuit 80, acting as the communication slave device, based on the clock signal CK output from the slave device side.

[0099] In addition, Figure 13 In this circuit, a pull-up resistor RP is provided between the data line of the data signal DA and the power line of VDD. This pulls up the data line connecting the processing device 100 and the interface circuit 80. That is, the data line is pulled up to the VDD power supply voltage level. Thus, even when neither the interface circuit 80 nor the processing device 100 drives the data line to a low level, the data line is pulled up to the VDD power supply voltage level, i.e., a high level. Specifically, the interface circuit 80 or the interface circuit 110 of the processing device 100 includes the following... Figure 14 In the case of the I / O circuit 82 shown, which has an open-drain N-type transistor TR, the data line is pulled up to a high level when the transistor TR is turned off. This enables serial data communication using the data line.

[0100] In addition, Figure 13 In this configuration, a pull-up resistor RP is provided between the data line of the data signal DA and the power line of VDD, but it can also be configured without such a pull-up resistor RP.

[0101] Figure 13 The oscillator 4 shown is a 4-terminal oscillator with a power supply terminal TVDD, a ground terminal TGND, a clock output terminal TCK, and a first terminal TDA. In such an oscillator 4 with a small number of terminals, how to achieve communication with an external processing device 100 becomes a challenge.

[0102] For example, as Figure 13A comparative method is considered as follows: During manufacturing and inspection, the operating mode is set to communication mode. For example, the clock output terminal TCK is switched to a clock input terminal for communication, and the first terminal TDA, which is an output enable terminal, is switched to a data terminal for communication. Furthermore, the communication clock signal from the processing device 100, which is the master device, is input to the clock output terminal TCK, which has been switched to a clock input terminal, and the communication of the data signal DA is implemented using the first terminal TDA, which has been switched to a data terminal for communication.

[0103] However, in this comparative example, the clock output terminal TCK is switched to a communication clock input terminal, therefore a clock signal CK based on the oscillation signal OSC of the oscillation circuit 30 cannot be output from the clock output terminal TCK. Therefore, when the processing device 100, as the master device, operates based on this clock signal CK, or when other external devices operate using this clock signal CK, in communication mode, the processing device 100 or other external devices cannot operate based on the clock signal CK. That is, it is impossible to simultaneously output the clock signal CK to the outside and communicate with the processing device 100.

[0104] Regarding this point, according to Figure 13 The structure uses the clock signal CK output by oscillator 4 for communication with processing device 100. That is, normally communication with processing device 100 uses the communication clock signal output by the master device, but... Figure 13 In this method, the clock signal CK, output from the oscillator 4 of the device, is used for communication with the processing unit 100. Therefore, it is not necessary to set the operating mode to communication mode and switch the clock output terminal TCK to a communication clock input terminal as in the comparative example described above. Furthermore, it is possible to output the clock signal CK from the clock output terminal TCK to the processing unit 100 or other external devices while simultaneously performing communication with the processing unit 100 using the clock signal CK and the data signal DA. Therefore, even when the number of terminals of the oscillator 4 is small, such as four terminals, it is possible to simultaneously output the clock signal CK from the clock output terminal TCK and perform communication with the processing unit 100 using the clock signal CK and the data signal DA.

[0105] Furthermore, when the oscillator 4 has five or more terminals, such as when a communication clock input terminal is provided in the oscillator 4, there is a problem that noise caused by the communication clock signal input to the communication clock input terminal adversely affects the signal characteristics of the clock signal CK. That is, in this case, the clock signal CK output from the oscillator 4 becomes asynchronous with the communication clock signal from the processing device 100. Therefore, the noise caused by the communication clock signal overlaps with the clock signal CK, generating jitter noise and other noise in the clock signal CK.

[0106] Regarding this point, according to Figure 13 The structure uses the clock signal CK output by oscillator 4 to replace the communication clock signal output by processing device 100 for communication with processing device 100. That is, the clock signal CK output by oscillator 4 is used as the clock signal for communication with processing device 100. Therefore, it can effectively prevent the following problem as described above: noise caused by the communication clock signal overlaps with the clock signal CK, thus degrading the clock signal characteristics.

[0107] In addition, Figure 13 In this circuit, the output circuit 90 outputs a clock signal CK even during periods other than communication periods. For example, the output circuit 90 outputs a clock signal CK during communication periods and also during periods other than communication periods. Thus, even during periods other than communication periods, the clock signal CK can be supplied to the processing device 100 or other external devices. As a result, the processing device 100 or other external devices can use the clock signal CK as an operating clock signal to operate, or can perform predetermined processing based on the clock signal CK.

[0108] For example, as Figure 13 Consider the following application example: A 32kHz clock signal CK from oscillator 4 is supplied to the RTC circuit of a processing device 100, such as a microcomputer, to perform calendar timing processing in the RTC. In this case, the calendar timing processing needs to be executed continuously; therefore, the clock signal CK from oscillator 4 needs to be continuously supplied to the RTC circuit of the processing device 100. On the other hand, the processing device 100 sometimes performs such calendar timing processing while detecting, for example, the ambient temperature, and performs warning notification processing if the temperature exceeds the upper limit or falls below the lower limit. In this case, the processing device 100 effectively utilizes the temperature detection data DTD from the temperature sensor circuit 40 of oscillator 4, detecting the temperature based on the temperature detection data DTD output from oscillator 4 via interface circuit 80, thereby enabling the execution of warning notification processing. In such a case, according to Figure 13The structure enables the temperature detection data DTD from the oscillator 4 to be sent to the processing unit 100 during communication, and the clock signal CK of the oscillator 4 is always provided to the RTC circuit during and outside of the communication period, thereby enabling calendar timing processing. Therefore, the processing unit 100 can simultaneously perform temperature detection based on the temperature detection data DTD and calendar timing processing based on the clock signal CK.

[0109] Figure 14 This is an example of the structure of the I / O circuit 82 included in the interface circuit 80 or interface circuit 110. The I / O circuit 82 includes an open-drain N-type transistor TR and an input buffer BF. Additionally, Figure 14 The IN / OUT terminals and Figure 13 Terminal 1 (TDA) corresponds to either the TDA terminal or the EDA terminal. Terminal 1 (TDA) corresponds to the data terminal of oscillator 4.

[0110] The output signal OUT from the internal circuitry is buffered, for example, by an inverter IV, and then input to the gate of transistor TR. For instance, when the output signal OUT is low and the gate of transistor TR is high, transistor TR is turned on, and the data line is driven low. Conversely, when the output signal OUT is high and the gate of transistor TR is low, transistor TR is turned off. In this case, the data line is in a state of... Figure 13 The resistor RP is pulled high. This allows the transmission of the data signal DA using the output signal OUT.

[0111] Furthermore, the IN / OUT terminals are connected to the input buffer BF, and the input signal IN from the IN / OUT terminals is buffered by the input buffer BF before being input to the internal circuit. This enables the reception of the data signal DA using the input signal IN.

[0112] Additionally, when using the unset... Figure 13 In the case of a pull-up resistor RP structure, in Figure 14 In the I / O circuit 82, instead of the open-drain N-type transistor TR, a push-pull output circuit consisting of a P-type transistor and an N-type transistor can be set up, for example, in series between VDD and GND.

[0113] Figure 15 , Figure 16 This is a signal waveform diagram illustrating a communication example of this embodiment. Figure 15 This is a signal waveform diagram showing the data writing process where the processing unit 100, acting as the master device, writes data to the oscillator 4. This data writing by the master device corresponds to the data reception by the interface circuit 80, which acts as the slave device, to the oscillator 4. Figure 16This is a signal waveform diagram showing the data readout process where the processing device 100 reads data from the oscillator 4. This data readout from the master device corresponds to the data transmission from the interface circuit 80, which acts as the slave device for the oscillator 4. Furthermore, in Figure 15 , Figure 16 In order to distinguish between the low level output of the master device and the low level output of the slave device, the low level of the slave device is schematically represented as a potential lower than the low level of the master device.

[0114] exist Figure 15 During data writing, the processing unit 100, acting as the master device, sends a communication start key, which is received by the interface circuit 80, acting as the slave device. In this case, the processing unit 100, acting as the master device, sends the communication start key synchronously with the clock signal CK from the slave device. Then, the interface circuit 80, acting as the slave device, receives the communication start key synchronized with the clock signal CK, determines whether the received communication start key is a key with appropriate code according to the protocol, and determines that communication has started if it is a key with appropriate code. Thus, in this embodiment, the interface circuit 80 starts communication based on the condition that the processing unit 100 receives the communication start key. In this way, communication between the master device and the slave device can begin based on the condition that the master device sends a communication start key with appropriate code to the slave device, enabling appropriate communication between the master device and the slave device starting from the communication start key. In addition, in this embodiment, the processing unit 100 is appropriately described only as the master device, and the interface circuit 80 is appropriately described only as the slave device.

[0115] After sending the communication start key, the master device outputs an R / XW indicating whether it is a write or read operation. In this R / XW, X represents negative logic; the master device outputs a high level when reading data and a low level when writing data. Figure 15 The data is written in the middle, therefore the master device outputs a low level as the XW of R / XW. That is, by making Figure 14 The open-drain N-type transistor of the I / O circuit 82 on the main device side is turned on and outputs a low level.

[0116] Thus, when the master device outputs a low level after the communication start key, the slave device outputs an SLA indicating its acknowledgment. Specifically, the slave device outputs a low level as the SLA. As mentioned above, the slave device's low level is designed to distinguish it from the master device's low level. Figure 15 The diagram illustrates a low level, which is a lower potential.

[0117] When the slave device outputs a low level as the SLA, the master device writes an address to the slave device. This address specifies the address of the slave device's register that will become the destination for the data write. During this address write, the master device sends the address information as the data signal DA, and the slave device receives this address information.

[0118] After writing the address, the master device outputs P / XC. P stands for Stop, and XC stands for Continue. Additionally, the X in XC indicates negative logic. Figure 15 In order to continue communication, the master device outputs a low level as XC of P / XC. Then, the master device sends the data written to the specified address as the data signal DA. Thus, data from the master device is written to the register at the specified address in the register of oscillator 4.

[0119] exist Figure 16 In the case of data reading, the master device first sends a communication start key, which the slave device then receives. Furthermore, because... Figure 16 This is a data read, so the master device outputs a high level as R for R / XW. Then, the slave device outputs a low level as an acknowledgment SLA.

[0120] After the device outputs the SLA in this manner, data is read. Furthermore, as described later, in the case of this data reading, the address for data reading is specified beforehand. Figure 16 Data reading is a slave device write operation where data is written from the slave device to the data line (DA). That is, data read from the slave device is written to the data line and sent to the master device. Then, the master device outputs a low level as XC of the P / XC signal to indicate that communication should continue and the next data read should proceed.

[0121] Figure 17 This is an explanatory diagram of a communication protocol example according to this embodiment. Figure 17 During data writing, after the master device outputs an 8-bit communication start key and XW, the slave device outputs a 1-bit SLA. Then, the master device writes an 8-bit address, specifying the write address. Next, after outputting a 1-bit XC indicating continued communication, the master device sends 8 bits of data to the slave device. Thus, data is written to the specified write address in the slave device. Then, after outputting an XC indicating continued communication, the master device sends the next data. In this case, the write address is automatically updated in the slave device, and data from the master device is written to the updated next write address. Afterward, after outputting an XC indicating continued communication, the master device sends the next data to the slave device. Furthermore, if the next written data disappears, the master device outputs a 1-bit P indicating the end of communication.

[0122] In addition, Figure 17 During data reading, after the master device outputs an 8-bit communication start key and XW, the slave device outputs a 1-bit SLA. Then, the master device writes an 8-bit address, specifying the address for data reading, and outputs a 1-bit P indicating the end of communication. Next, after the master device outputs an 8-bit communication start key and R, and the slave device outputs a 1-bit SLA, the master device reads and receives 8 bits of data from the slave device. In this case, the address for data reading is the address specified before data reading, as described above. Then, after the master device outputs XC indicating continued communication, it reads and receives the next data from the slave device. In this case, the address for data reading is automatically updated. Then, when there is no more data to read, the master device outputs a 1-bit P indicating the end of communication.

[0123] Thus, in this embodiment, in Figure 17 When data is written, after the interface circuit 80 receives the first data of a specified number of bits, if the processing device 100 outputs a low level, it determines that communication continues and receives the next second data of the specified number of bits. That is, in Figure 17 In the data writing process of the master device, the interface circuit 80, acting as the slave device, receives 8 bits of the first data as a predetermined number of bits. Specifically, the first data sent by the master device is received and written into a register. Furthermore, the predetermined number of bits is not limited to 8 bits; it can also be 16 bits, 32 bits, etc. Moreover, when the processing device 100 outputs a low level as an indication of continued communication (XC) after sending the first data, the interface circuit 80 determines that communication continues. Furthermore, when the processing device 100 sends the second data after outputting a low level as XC, the interface circuit 80 receives the sent second data and writes the received second data into a register. Thus, after receiving the first data, the interface circuit 80 detects whether the processing device 100 outputs a low level, thereby determining whether communication should continue and being able to receive the next second data. Therefore, the interface circuit 80 can continuously receive multiple data sets of a predetermined number of bits, such as the first data and the second data. Furthermore, if the processing device 100 does not output a low level after sending the first data, such as... Figure 13 As shown, the data line is pulled up by resistor RP and set to a high level. Therefore, interface circuit 80 can determine that communication will not continue and stop.

[0124] Furthermore, in this embodiment, in Figure 17 During data reading, after the interface circuit 80 sends the first data of a specified number of bits, when the processing device 100 outputs a low level, it determines that communication continues and sends the next second data of the specified number of bits. That is, in Figure 17In the data reading process of the master device, the interface circuit 80, acting as the slave device, sends the first data, consisting of 8 bits, as a predetermined number of bits. Then, when the processing device 100 outputs a low level as an indication to continue communication (XC), the interface circuit 80 determines that communication should continue and sends the next second data. Thus, after the first data is sent, the interface circuit 80 detects whether the processing device 100 outputs a low level, thereby determining whether communication should continue and enabling the transmission of the next second data. Therefore, the interface circuit 80 can continuously send multiple data sets of the predetermined number of bits, such as the first and second data. Furthermore, if the processing device 100 does not output a low level after the first data is sent by the interface circuit 80, the data line is pulled up by the resistor RP and set to a high level; therefore, the interface circuit 80 can determine that communication should not continue and stop.

[0125] In addition, Figures 15-17 In this embodiment, communication is performed with a low level when the logic level is "0" and a high level when the logic level is "1", but this embodiment is not limited to this. For example, the interface circuit 80 may also output a first-bit mode data signal DA when the logic level is "0" and a second-bit mode data signal DA when the logic level is "1". For example, in the first-bit mode data signal DA, TF1 outputs a low level in the first half period and TL1 outputs a high level in the second half period. On the other hand, in the second-bit mode data signal DA, TF2 outputs a low level in the first half period and TL2 outputs a high level in the second half period. Here, the relationship TF1 > TF2 and TL1 < TL2 holds. In addition, the relationship TF1 + TL1 = TF2 + TL2 holds. The periods TF1, TL1, TF2, and TL2 are periods of a specified number of clock cycles. As an example, the period TF1 is 4 clock cycles of the clock signal CK, and the period TL1 is 3 clock cycles. In addition, the period TF2 is 2 clock cycles, and the period TL2 is 5 clock cycles. Therefore, even when the frequency of the clock signal CK is high, errors can be prevented in the communication of the data signal DA based on the clock signal CK, thereby enabling proper communication processing.

[0126] That is, in Figure 13In general, at lower frequencies such as 32kHz, there are almost no problems with the clock signal CK. However, at higher frequencies, communication errors may occur when using the clock signal CK for communication. For example, when transmitting and receiving data signal DA between the master and slave devices synchronously with the clock signal CK, if the clock signal CK frequency is high, the sampling of data signal DA may not be timely, resulting in a communication error. To address this, if the interface circuit 80 outputs the first-bit mode data signal DA when the logic level is "0" and the second-bit mode data signal DA when the logic level is "1", as described above, such communication errors can be prevented. This enables highly reliable and stable communication between the master and slave devices.

[0127] In addition, such as Figure 10 As shown, if the temperature detection data DTD exceeds the upper limit UL or falls below the lower limit LL, the interface circuit 80 will output an interrupt signal INT at a specified voltage level via the first connection panel PDA to the processing device 100 for a given period. For example, in Figure 18 In this circuit, interface circuit 80 outputs an interrupt signal INT that changes from a high impedance state to a low level during a given period of time, where TA becomes a specified voltage level. For example, if the temperature detection data DTD exceeds the upper limit UL or falls below the lower limit LL, interface circuit 80 outputs an interrupt signal INT that changes from a high impedance state to a low level during this period.

[0128] For example, such as Figure 13 As shown, the data line of the data signal DA is pulled up by resistor RP. Therefore, if the interface circuit 80 or the processing device 100 does not drive the data line low, the data line becomes pulled up to a high level. Furthermore, if the temperature detection data DTD exceeds the upper limit UL or falls below the lower limit LL, the interface circuit 80 drives the data line low, as shown. Figure 18 As shown, the output is an interrupt signal INT that goes low during the period TA. Therefore, the processing device 100 can detect that the interface circuit 80 has output the interrupt signal INT by detecting the low level of the data line. Furthermore, the processing device 100, upon detecting the interrupt signal INT, can appropriately perform processing for situations where the temperature exceeds the upper limit or falls below the lower limit. For example, the processing device 100 can perform warning processing such as reporting that the temperature exceeds the upper limit or falls below the lower limit.

[0129] 5. Oscillator

[0130] Figure 19The first construction example of the oscillator 4 according to this embodiment is shown. The oscillator 4 includes an oscillator 10, a circuit device 20, and a package 15 for housing the oscillator 10 and the circuit device 20. The package 15 is formed, for example, of ceramic, and has a housing space inside, in which the oscillator 10 and the circuit device 20 are housed. The housing space is hermetically sealed, preferably in a near-vacuum state, i.e., a depressurized state. Through the package 15, the oscillator 10 and the circuit device 20 can be appropriately protected from the effects of impact, dust, heat, moisture, etc.

[0131] Package 15 includes a base 16 and a cover 17. Specifically, package 15 comprises a base 16 supporting the oscillator 10 and the circuit device 20, and a cover 17 engaged with the upper surface of the base 16 to form a receiving space between the cover and the base 16. The oscillator 10 is supported on a stepped portion provided inside the base 16 via terminal electrodes. The circuit device 20 is disposed on the inner bottom surface of the base 16. Specifically, the circuit device 20 is disposed with its active surface facing the inner bottom surface of the base 16. The active surface is the surface of the circuit device 20 where circuit elements are formed. Furthermore, bumps BMP are formed on the terminals of the circuit device 20. The circuit device 20 is supported on the inner bottom surface of the base 16 via conductive bumps BMP. The conductive bumps BMP are, for example, metal bumps, through which the oscillator 10 and the circuit device 20 are electrically connected. Furthermore, the circuit device 20 is electrically connected to the external terminals 18 and 19 of the oscillator 4 via the internal wiring of the bump BMP or package 15. The external terminals 18 and 19 are formed on the outer bottom surface of the package 15. The external terminals 18 and 19 are connected to external devices via external wiring. The external wiring is, for example, wiring formed on a circuit board on which external devices are mounted. Thus, clock signals can be output to external devices.

[0132] In addition, Figure 19 In this embodiment, the circuit device 20 is mounted upside down with its active surface facing downwards, but this embodiment is not limited to this mounting. For example, the circuit device 20 can also be mounted with its active surface facing upwards. That is, the circuit device 20 is mounted with its active surface facing the oscillator 10.

[0133] Figure 20A second construction example of the oscillator 4 is shown. The oscillator 4 includes an oscillator 10, a circuit device 20, and a package 15 for housing the oscillator 10 and the circuit device 20. The package 15 has a base 16 and a cover 17. The base 16 has a first substrate 6 serving as an intermediate substrate, a second substrate 7 stacked on the upper surface of the first substrate 6 in a generally rectangular frame shape, and a third substrate 8 stacked on the bottom surface of the first substrate 6 in a generally rectangular frame shape. The cover 17 is bonded to the upper surface of the second substrate 7, and the oscillator 10 is housed in a housing space S1 formed by the first substrate 6, the second substrate 7, and the cover 17. For example, the housing space S1 is hermetically sealed to house the oscillator 10, preferably in a near-vacuum state, i.e., a depressurized state. This allows the oscillator 10 to be appropriately protected from impacts, dust, heat, moisture, etc. In addition, the circuit device 20, which serves as a semiconductor chip, is housed in a housing space S2 formed by the first substrate and the third substrate 8. In addition, external terminals 18 and 19, which serve as external connections for the oscillator 4, are formed on the bottom surface of the third substrate 8.

[0134] Furthermore, in the storage space S1, the oscillator 10 is connected to a first electrode terminal (not shown) and a second electrode terminal (not shown) formed on the upper surface of the first substrate 6 via conductive connecting portions CDC1 and CDC2. The conductive connecting portions CDC1 and CDC2 can be implemented, for example, by conductive bumps such as metal bumps, or by conductive adhesives. Specifically, for example, a first electrode connecting plate (not shown) formed at one end of the tuning fork oscillator 10 is connected to the first electrode terminal formed on the upper surface of the first substrate 6 via the conductive connecting portion CDC1. The first electrode terminal is also electrically connected to the connecting plate PX1 of the circuit device 20. Additionally, a second electrode connecting plate (not shown) formed at the other end of the tuning fork oscillator 10 is connected to a second electrode terminal formed on the upper surface of the first substrate 6 via the conductive connecting portion CDC2. The second electrode terminal is also electrically connected to the connecting plate PX2 of the circuit device 20. Therefore, one end and the other end of the oscillator 10 can be electrically connected to the connection pads PX1 and PX2 of the circuit device 20 via conductive connection portions CDC1 and CDC2. Furthermore, conductive bumps BMP are formed on the multiple connection pads of the circuit device 20, which are semiconductor chips, and these conductive bumps BMP are connected to multiple electrode terminals formed on the bottom surface of the first substrate 6. Moreover, the electrode terminals connected to the connection pads of the circuit device 20 are electrically connected to the external terminals 18 and 19 of the oscillator 4 via internal wiring or the like.

[0135] Alternatively, the oscillator 4 can also be a wafer-level packaged (WLP) oscillator. In this case, the oscillator 4 includes: a base having a semiconductor substrate and a through electrode penetrating between a first surface and a second surface of the semiconductor substrate; an oscillator 10 fixed to the first surface of the semiconductor substrate via conductive bonding members such as metal bumps; and external terminals disposed on the second surface of the semiconductor substrate via an insulating layer such as a redistribution wiring layer. Furthermore, an integrated circuit forming a circuit device 20 is formed on either the first or second surface of the semiconductor substrate. In this case, by bonding a first semiconductor wafer with multiple bases on which the oscillator 10 and the integrated circuit are disposed to a second semiconductor wafer with multiple covers, the multiple bases and multiple covers are joined, and then the oscillator 4 is monolithically produced using a dicing machine or the like. In this way, a wafer-level packaged oscillator 4 can be realized, enabling the manufacture of the oscillator 4 with high productivity and low cost.

[0136] As described above, the circuit arrangement of this embodiment includes: an oscillation circuit that generates an oscillation signal using an oscillator; a temperature sensor circuit that outputs temperature detection data; a temperature compensation circuit that performs temperature compensation on the oscillation frequency of the oscillation signal based on the temperature detection data; a memory that stores correction data for calculating the temperature by correcting the temperature detection data; and an interface circuit that outputs the temperature detection data and the correction data.

[0137] According to this embodiment, the oscillation circuit generates an oscillation signal using an oscillator, the temperature sensor circuit detects the temperature, and outputs temperature detection data. Furthermore, the temperature compensation circuit performs temperature compensation on the oscillation frequency of the oscillation signal based on the temperature detection data, and the memory stores corrected data used to correct the temperature detection data to obtain the corrected temperature. The interface circuit then outputs the temperature detection data and the corrected data to an external device. Thus, it is possible to perform computational processing such as correcting the temperature detection data from the interface circuit based on the corrected data from the interface circuit, thereby detecting the temperature corresponding to the temperature detection data. Therefore, a circuit device can be provided that enables accurate temperature detection by effectively utilizing the temperature sensor circuit of the circuit device.

[0138] Alternatively, in this embodiment, the memory can store a lookup table that maps temperature detection data to frequency adjustment data, and the temperature compensation circuit can refer to the lookup table to output frequency adjustment data corresponding to the temperature detection data. Furthermore, the oscillation circuit can also generate an oscillation signal with an oscillation frequency corresponding to the frequency adjustment data.

[0139] In this way, the frequency adjustment data corresponding to the temperature detection data is output from the lookup table, and the oscillation frequency of the oscillation circuit is adjusted using the frequency adjustment data, thereby realizing the temperature compensation processing of the oscillation frequency.

[0140] Alternatively, in this embodiment, an arithmetic circuit may be included, which performs arithmetic processing to adjust the temperature sensitivity and outputs the processed temperature detection data to a lookup table.

[0141] In this way, for example, when the temperature sensitivity varies depending on the temperature range, the calculation process can be performed to appropriately adjust the temperature sensitivity, and the processed temperature detection data can be output to the lookup table.

[0142] Alternatively, in this embodiment, the memory may be a non-volatile memory.

[0143] Therefore, it is possible to store the correction data used to correct the temperature detection data in a non-volatile memory, read the correction data from the non-volatile memory, and output the correction data and the temperature detection data together to the outside through the interface circuit.

[0144] Alternatively, in this embodiment, the correction data may be the coefficient data of a polynomial representing the relationship between temperature and temperature detection data.

[0145] In this way, when the characteristic representing the relationship between temperature and temperature detection data can be represented or approximated by a polynomial, the coefficient data of the polynomial can be used as correction data.

[0146] Alternatively, in this embodiment, an interrupt signal generation circuit may be included, which generates an interrupt signal when the temperature detection data exceeds the upper limit or falls below the lower limit.

[0147] By setting up such an interrupt signal generation circuit, it is possible to notify external devices that the temperature corresponding to the temperature detection data exceeds the upper limit temperature or falls below the lower limit temperature.

[0148] Alternatively, in this embodiment, the interrupt signal generation circuit may include: a first register storing an upper limit value; a second register storing a lower limit value; and a comparison circuit that compares the temperature detection data with the upper or lower limit value to generate an interrupt signal.

[0149] In this way, the upper and lower limits are pre-stored in the first and second registers. The comparison circuit compares the upper or lower limit with the temperature detection data, thereby generating an interrupt signal.

[0150] Alternatively, in this embodiment, the memory may store an upper limit value and a lower limit value.

[0151] In this way, the upper and lower limits of the individual difference deviations corrected for based on the correction data can be written and stored in the memory.

[0152] Alternatively, this embodiment may also include: a clock output connection disk; an output circuit that outputs a clock signal based on an oscillation signal to an external processing device via the clock output connection disk; and a first connection disk, where an interface circuit communicates with the processing device via a data signal. Furthermore, in the communication, the output circuit may output a clock signal to the processing device, which acts as the master device for communication, and the interface circuit, acting as the slave device for communication, may receive a data signal synchronized with the clock signal sent from the processing device via the first connection disk, or transmit the data signal and clock signal synchronously to the processing device via the first connection disk.

[0153] In this way, synchronous communication of data signals can be performed between the processing device, which acts as the master device, and the interface circuit, which acts as the slave device, based on the clock signal output from the slave device.

[0154] Alternatively, in this embodiment, if the temperature detection data exceeds the upper limit or falls below the lower limit, the interface circuit may output an interrupt signal at a predetermined voltage level to the processing device via the first connection plate for a given period.

[0155] In this way, the external processing device can detect the interrupt signal output by the interface circuit by detecting the specified voltage level of the data line, and thus appropriately perform processing when the temperature exceeds the upper limit or falls below the lower limit.

[0156] Furthermore, the oscillator of this embodiment includes an oscillator and a circuit arrangement. The circuit arrangement includes: an oscillation circuit that generates an oscillation signal using the oscillator; a temperature sensor circuit that outputs temperature detection data; a temperature compensation circuit that performs temperature compensation on the oscillation frequency of the oscillation signal based on the temperature detection data; a memory that stores correction data for calculating the temperature by correcting the temperature detection data; and an interface circuit that outputs the temperature detection data and the correction data.

[0157] According to this embodiment, the oscillation circuit generates an oscillation signal using an oscillator, the temperature sensor circuit detects the temperature, and outputs temperature detection data. Furthermore, the temperature compensation circuit performs temperature compensation on the oscillation frequency of the oscillation signal based on the temperature detection data, and the memory stores corrected data used to correct the temperature detection data to obtain the corrected temperature. The interface circuit then outputs the temperature detection data and the corrected data to an external device. Thus, computational processing such as correcting the temperature detection data from the interface circuit based on the corrected data from the interface circuit can be performed, thereby detecting the temperature corresponding to the temperature detection data. Therefore, an oscillator or the like that can achieve accurate temperature detection by effectively utilizing the temperature sensor circuit of the circuit device can be provided.

[0158] Furthermore, the oscillator in this embodiment may also include a clock output terminal and a first terminal. Additionally, the circuit arrangement may include an output circuit that outputs a clock signal based on the oscillation signal to an external processing device via the clock output terminal, and an interface circuit that communicates with the processing device via a data signal. Furthermore, during communication, the output circuit may output a clock signal to the processing device, which acts as the master device, and the interface circuit, acting as the slave device, may receive a data signal synchronized with the clock signal sent from the processing device via the first terminal, or transmit a data signal synchronized with the clock signal to the processing device via the first terminal.

[0159] In this way, synchronous communication of data signals can be performed between the processing device, which acts as the master device, and the interface circuit, which acts as the slave device, based on the clock signal output from the slave device.

[0160] In addition, the processing system of this embodiment may also include: the above-mentioned oscillator; and a processing device electrically connected to the oscillator, wherein the processing device performs calculation processing to correct the temperature detection data based on the correction data, and detects the temperature.

[0161] In this way, the computational processing of correcting temperature detection data based on the correction data can be performed only when necessary in the entire processing system, thus reducing the power consumption of the entire processing system.

[0162] Furthermore, while this embodiment has been described in detail above, those skilled in the art should readily understand that various modifications can be made without substantially departing from the novel aspects and effects of this disclosure. Therefore, all such modifications are included within the scope of this disclosure. For example, in the specification or drawings, any term that is described at least once with a different term that is more general or synonymous can be replaced with that different term anywhere in the specification or drawings. Additionally, all combinations of this embodiment and its modifications are also included within the scope of this disclosure. Furthermore, the structure and operation of circuit devices, oscillators, processing systems, etc., are not limited to those described in this embodiment, and various modifications can be implemented.

Claims

1. A circuit device, characterized in that, The circuit device includes: An oscillating circuit that uses an oscillator to generate an oscillating signal; Temperature sensor circuit, which outputs temperature detection data; A temperature compensation circuit that performs temperature compensation on the oscillation frequency of the oscillation signal based on the temperature detection data; The memory stores correction data for calibrating the temperature detection data to obtain temperature, and a lookup table that maps the temperature detection data to the frequency adjustment data. The arithmetic circuit performs arithmetic processing to adjust the temperature sensitivity and outputs the temperature detection data after the arithmetic processing to the lookup table; as well as The interface circuit outputs the temperature detection data and the correction data.

2. The circuit device according to claim 1, characterized in that, The temperature compensation circuit refers to the lookup table and outputs the frequency adjustment data corresponding to the temperature detection data. The oscillation circuit generates an oscillation signal at the oscillation frequency corresponding to the frequency adjustment data.

3. The circuit device according to claim 1 or 2, characterized in that, The memory is a non-volatile memory.

4. The circuit device according to claim 1 or 2, characterized in that, The correction data is the coefficient data of a polynomial representing the relationship between the temperature and the temperature detection data.

5. The circuit device according to claim 1 or 2, characterized in that, The circuit device includes an interrupt signal generation circuit that generates an interrupt signal when the temperature detection data exceeds an upper limit or falls below a lower limit.

6. The circuit device according to claim 5, characterized in that, The interrupt signal generation circuit includes: Register 1 stores the upper limit value; The second register stores the lower limit value; and A comparison circuit compares the temperature detection data with the upper limit value or the lower limit value and generates the interrupt signal.

7. The circuit device according to claim 5, characterized in that, The memory stores the upper limit value and the lower limit value.

8. The circuit device according to claim 1 or 2, characterized in that, The circuit device includes: Clock output connection disk; The output circuit outputs a clock signal based on the oscillation signal to an external processing device via the clock output connector. as well as First connection disk, The interface circuit communicates with the processing device via data signals. In said communication, The output circuit outputs the clock signal to the processing device, which serves as the master device for the communication. The interface circuit, acting as a slave device in the communication, receives, via the first connection board, the data signal transmitted from the processing device and synchronized with the clock signal, or transmits the data signal to the processing device synchronously with the clock signal via the first connection board.

9. The circuit device according to claim 8, characterized in that, If the temperature detection data exceeds the upper limit or falls below the lower limit, the interface circuit will output an interrupt signal at a specified voltage level to the processing device via the first connection plate for a given period.

10. An oscillator, characterized in that, The oscillator contains: Oscillator; and Circuit device, The circuit device includes: An oscillating circuit that uses the oscillator to generate an oscillating signal; Temperature sensor circuit, which outputs temperature detection data; A temperature compensation circuit that performs temperature compensation on the oscillation frequency of the oscillation signal based on the temperature detection data; The memory stores correction data for calibrating the temperature detection data to obtain temperature, and a lookup table that maps the temperature detection data to the frequency adjustment data. The arithmetic circuit performs arithmetic processing to adjust the temperature sensitivity and outputs the temperature detection data after the arithmetic processing to the lookup table; as well as The interface circuit outputs the temperature detection data and the correction data.

11. The oscillator according to claim 10, characterized in that, The oscillator contains: Clock output terminal; and Terminal 1, The circuit device includes an output circuit that outputs a clock signal based on the oscillation signal to an external processing device via the clock output terminal. The interface circuit communicates with the processing device via data signals. In said communication, The output circuit outputs the clock signal to the processing device, which serves as the master device for the communication. The interface circuit, acting as a slave device in the communication, receives, via the first terminal, the data signal transmitted from the processing device and synchronized with the clock signal, or transmits the data signal synchronously with the clock signal to the processing device via the first terminal.

12. A processing system, characterized in that, The processing system includes: The oscillator as claimed in claim 10 or 11; and The processing device is electrically connected to the oscillator. The processing device performs calculations to correct the temperature detection data based on the correction data, and then detects the temperature.

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