Display substrate, preparation method thereof and display device

Abstract

A display substrate includes a display area and a non-display area. The non-display area is provided with a gate drive circuit including a plurality of cascaded shift register units connected with at least one power supply line. The shift register unit includes a first output circuit and a second output circuit. The first output circuit is connected with a first group of clock signal lines, and the second output circuit is connected with the first group of clock signal lines and a second group of clock signal lines. In a first direction, the first group of clock signal lines and the at least one power supply line are located between the first output circuit and the second output circuit, and the second group of clock signal lines is located on a side of the second output circuit away from the first group of clock signal lines.

Description

Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and in particular to a display substrate and its preparation method, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely fast response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become the mainstream products in the display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a display substrate, a method for preparing the same, and a display device.

[0005] In one aspect, this disclosure provides a display substrate, including a display area and a non-display area. The non-display area is provided with a gate driving circuit. The gate driving circuit includes a plurality of cascaded shift register units; each shift register unit is connected to at least one power supply line. Each shift register unit includes a first output circuit and a second output circuit. The first output circuit is connected to a first set of clock signal lines, and the second output circuit is connected to both the first and second sets of clock signal lines. In a first direction, the first set of clock signal lines and at least one power supply line are located between the first and second output circuits, and the second set of clock signal lines are located on the side of the second output circuit away from the first set of clock signal lines.

[0006] In some exemplary embodiments, the at least one power line includes a first power line and a second power line. The first power line is connected to a first output circuit, and the second power line is connected to a second output circuit. In the first direction, the first power line is located between the first output circuit and a first set of clock signal lines, and the second power line is located between the first set of clock signal lines and the second output circuit.

[0007] In some exemplary embodiments, the non-display area is further provided with a third power line and a fourth power line. The third power line is connected to the second output circuit, and the fourth power line is connected to the first output circuit. In the first direction, the fourth power line is located on the side of the first output circuit away from the first power line, and the third power line is located between the second power line and the second set of clock signal lines.

[0008] In some exemplary embodiments, the non-display area is further provided with an initial signal line. In the first direction, the initial signal line is located on the side of the fourth power line away from the first output circuit.

[0009] In some exemplary embodiments, the first output circuit includes: a first node control subcircuit, a second node control subcircuit, and a first output subcircuit. The first node control subcircuit is connected to an input terminal, a first output terminal, a first clock terminal, a second clock terminal, a third clock terminal, a first power supply terminal, a second power supply terminal, a first node, and a second node, and is configured to control the potentials of the first node and the second node under the control of the first clock terminal, the third clock terminal, and the input terminal. The second node control subcircuit is connected to the first node, the second node, the second power supply terminal, and the first output terminal, and is configured to maintain the potentials of the first node and the second node. The first output subcircuit is connected to the first node, the second node, the second clock terminal, the second power supply terminal, and the first output terminal, and is configured to control the first output terminal to output a first output signal under the control of the first node and the second node. The second node control subcircuit, the first output subcircuit, and the first node control subcircuit are arranged sequentially along a first direction.

[0010] In some exemplary embodiments, the first node control sub-circuit includes: a first control transistor, a second control transistor, a third control transistor, a fourth control transistor, a fifth control transistor, a sixth control transistor, a seventh control transistor, and an eighth control transistor. The control electrode of the first control transistor is connected to a first clock terminal, its first electrode is connected to an input terminal, and its second electrode is connected to the fourth node. The control electrode of the second control transistor is connected to the first clock terminal, its first electrode is connected to the fourth node, and its second electrode is connected to the first node. The control electrode of the third control transistor is connected to a third clock terminal, its first electrode is connected to a first power supply terminal, and its second electrode is connected to the second node. The control electrode of the fourth control transistor is connected to the second node, its first electrode is connected to a second power supply terminal, and its second electrode is connected to the third node. The control electrode of the fifth control transistor is connected to the second node, its first electrode is connected to the third node, and its second electrode is connected to the first node. The control electrode of the sixth control transistor is connected to the first node, its first electrode is connected to a first power supply terminal, and its second electrode is connected to the third node. The control electrode of the seventh control transistor is connected to an input terminal, its first electrode is connected to a second power supply terminal, and its second electrode is connected to the second node. The control electrode of the eighth control transistor is connected to the first output terminal, the first electrode is connected to the second clock terminal, and the second electrode is connected to the fourth node. The second node control sub-circuit includes a first capacitor and a second capacitor. The first electrode of the first capacitor is connected to the first node, and the second electrode is connected to the first output terminal. The first electrode of the second capacitor is connected to the second node, and the second electrode is connected to the second power supply terminal. The first output sub-circuit includes a first output transistor and a second output transistor. The control electrode of the first output transistor is connected to the first node, the first electrode is connected to the second clock terminal, and the second electrode is connected to the first output terminal. The control electrode of the second output transistor is connected to the second node, the first electrode is connected to the second power supply terminal, and the second electrode is connected to the first output terminal.

[0011] In some exemplary embodiments, the first capacitor and the first output transistor are adjacent to each other in the first direction, and the second capacitor and the second output transistor are adjacent to each other in the first direction. The first capacitor and the second capacitor are adjacent to each other in the second direction, and the first output transistor and the second output transistor are adjacent to each other in the second direction. The second direction intersects the first direction.

[0012] In some exemplary embodiments, the active layers of the first control transistor, the second control transistor, and the eighth control transistor are an integral structure, and the active layers of the fourth control transistor and the fifth control transistor are an integral structure; the active layers of the first output transistor and the second output transistor are an integral structure.

[0013] In some exemplary embodiments, in the first direction, the active layer of the sixth control transistor is located between the active layers of the fifth control transistor and the second control transistor, and the active layer of the seventh control transistor is located between the active layers of the fourth control transistor and the third control transistor.

[0014] In some exemplary embodiments, the second output circuit includes: a noise reduction control sub-circuit, a second output sub-circuit, and a third output sub-circuit. The noise reduction control sub-circuit is connected to a first output terminal, a first clock terminal, a third clock terminal, a first power supply terminal, a second power supply terminal, and a first noise reduction control node. It is configured to, under the control of the third clock signal terminal, rectify the charge of the first power supply terminal to the first noise reduction control node, maintaining the first noise reduction control node at a voltage that turns on the second output sub-circuit; and, under the control of the first output terminal, transmit the signal of the second power supply terminal to the first noise reduction control node, maintaining the first noise reduction control node at a voltage that turns off the second output sub-circuit. The second output sub-circuit is connected to the first noise reduction control node, the second output terminal, and the first power supply terminal. It is configured to, under the control of the first noise reduction control node, transmit the signal of the first power supply terminal to the second output terminal. The third output sub-circuit is connected to the first node, a fourth clock terminal, and the second output terminal. It is configured to, under the control of the first node, transmit the signal of the fourth clock terminal to the second output terminal. In the second direction, the second output sub-circuit and the third output sub-circuit are adjacent. In the first direction, the noise reduction control sub-circuit is located between the first set of clock signal lines and the second output sub-circuit. The second direction intersects the first direction.

[0015] In some exemplary embodiments, the noise reduction control sub-circuit includes: a first noise reduction control transistor, a second noise reduction control transistor, a third noise reduction control transistor, a fourth noise reduction control transistor, a third capacitor, and a fourth capacitor. The control electrode of the first noise reduction control transistor is connected to a first output terminal, its first electrode is connected to a second power supply terminal, and its second electrode is connected to a second noise reduction control node. The control electrode of the second noise reduction control transistor is connected to a third clock terminal, its first electrode is connected to a first power supply terminal, and its second electrode is connected to the second noise reduction control node. The control electrode and first electrode of the third noise reduction control transistor are connected to the second noise reduction control node, and its second electrode is connected to the first noise reduction control node. The control electrode of the fourth noise reduction control transistor is connected to a first output terminal, its first electrode is connected to a second power supply terminal, and its second electrode is connected to the first noise reduction control node. The first electrode of the third capacitor is connected to the second noise reduction control node, and its second electrode is connected to the first clock terminal. The first electrode of the fourth capacitor is connected to the first noise reduction control node, and its second electrode is connected to the first power supply terminal. The second output sub-circuit includes: a third output transistor. The control electrode of the third output transistor is connected to the first noise reduction control node, the first electrode is connected to the first power supply terminal, and the second electrode is connected to the second output terminal. The third output sub-circuit includes a fourth output transistor. The control electrode of the fourth output transistor is connected to the first node, the first electrode is connected to the fourth clock terminal, and the second electrode is connected to the second output terminal.

[0016] In some exemplary embodiments, the third output transistor and the fourth output transistor are adjacent in a second direction, and the first noise reduction control transistor and the second noise reduction control transistor are adjacent in a second direction. In the first direction, the third capacitor is located between the second noise reduction control transistor and the third noise reduction control transistor, and the fourth noise reduction control transistor is located between the first noise reduction control transistor and the fourth capacitor.

[0017] In some exemplary embodiments, the active layers of the first noise control transistor and the second noise control transistor are integral structures, and the active layers of the third output transistor and the fourth output transistor are integral structures.

[0018] In some exemplary embodiments, the first set of clock signal lines includes a first clock signal line, a second clock signal line, and a third clock signal line; the second set of clock signal lines includes a fourth clock signal line and a fifth clock signal line. The first clock signal provided by the first clock signal line, the second clock signal provided by the second clock signal line, and the third clock signal provided by the third clock signal line have the same duty cycle. The fourth clock signal provided by the fourth clock signal line and the fifth clock signal provided by the fifth clock signal line have the same duty cycle, and the duty cycle of the fourth clock signal is less than that of the first clock signal. The second clock signal is delayed by a set time compared to the first clock signal, and the third clock signal is delayed by a set time compared to the second clock signal, so that the first, second, and third clock signals do not simultaneously represent a first voltage; the fourth and fifth clock signals do not simultaneously represent a second voltage; and the first voltage is different from the second voltage.

[0019] In some exemplary embodiments, in the first direction, the first clock signal line, the second clock signal line, and the third clock signal line are arranged sequentially in a direction away from the first output circuit, and the fourth clock signal line and the fifth clock signal line are arranged sequentially in a direction away from the second output circuit.

[0020] In some exemplary embodiments, the first output circuit of any first-level shift register unit is connected to the first clock signal line, the second clock signal line, and the third clock signal line, and the second output circuit is connected to two clock signal lines in the first group of clock signal lines and one clock signal line in the second group of clock signal lines.

[0021] In some exemplary embodiments, the first clock input of the (6n+1)th stage shift register unit is connected to the first clock signal line, the second clock input is connected to the second clock signal line, the third clock input is connected to the third clock signal line, and the fourth clock input is connected to the fourth clock signal line. The first clock input of the (6n+2)th stage shift register unit is connected to the second clock signal line, the second clock input is connected to the third clock signal line, the third clock input is connected to the first clock signal line, and the fourth clock input is connected to the fifth clock signal line. The first clock input of the (6n+3)th stage shift register unit is connected to the third clock signal line, the second clock input is connected to the first clock signal line, the third clock input is connected to the second clock signal line, and the fourth clock input is connected to the fourth clock signal line. The first clock input of the (6n+4)th stage shift register unit is connected to the first clock signal line, the second clock input is connected to the second clock signal line, the third clock input is connected to the third clock signal line, and the fourth clock input is connected to the fifth clock signal line. The first clock input of the 6n+5th stage shift register unit is connected to the second clock signal line, the second clock input is connected to the third clock signal line, the third clock input is connected to the first clock signal line, and the fourth clock input is connected to the fourth clock signal line. Similarly, the first clock input of the 6n+6th stage shift register unit is connected to the third clock signal line, the second clock input is connected to the first clock signal line, the third clock input is connected to the second clock signal line, and the fourth clock input is connected to the fifth clock signal line. Here, n is a natural number.

[0022] In some exemplary embodiments, the first output of the (2k-1)th stage shift register unit is connected to the input of the (2k+1)th stage shift register unit, and the input of the first stage shift register unit is connected to the first initial signal line. The first output of the (2k)th stage shift register unit is connected to the input of the (2k+2)th stage shift register unit, and the input of the second stage shift register unit is connected to the second initial signal line, where k is a positive integer. The first group of clock signal lines includes a first group clock signal line and a second group clock signal line, and the second group of clock signal lines includes a third group clock signal line and a fourth group clock signal line. The (2k-1)th stage shift register unit is connected to the first group clock signal line and the third group clock signal line, and the (2k)th stage shift register unit is connected to the second group clock signal line and the fourth group clock signal line.

[0023] In some exemplary embodiments, in the first direction, the first group clock signal line and the second group clock signal line are arranged at intervals, and the third group clock signal line and the fourth group clock signal line are arranged at intervals.

[0024] In some exemplary embodiments, in a direction perpendicular to the display substrate, the non-display area of ​​the display substrate includes: a substrate and a first semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer disposed on the substrate. The first semiconductor layer includes at least: the active layer of a plurality of transistors of the shift register unit. The first conductive layer includes at least: the control electrode of the plurality of transistors of the shift register unit, and the first electrode of a plurality of capacitors. The second conductive layer includes at least: the second electrode of the plurality of capacitors of the shift register unit. The third conductive layer includes at least: the first and second electrodes of the plurality of transistors of the shift register unit, a first set of clock signal lines, a second set of clock signal lines, and a plurality of power supply lines. The fourth conductive layer includes at least: the connection electrode of a third output sub-circuit connecting the first node and the second output circuit.

[0025] On the other hand, embodiments of this disclosure provide a display device including a display substrate as described above.

[0026] On the other hand, this disclosure provides a method for fabricating a display substrate, for fabricating the display substrate as described above. The method includes: providing a substrate; forming a gate driving circuit in a non-display area. The gate driving circuit includes: a plurality of cascaded shift register units. Each shift register unit is connected to at least one power supply line. Each shift register unit includes: a first output circuit and a second output circuit; the first output circuit is connected to a first set of clock signal lines, and the second output circuit is connected to both the first and second set of clock signal lines. In a first direction, the first set of clock signal lines and at least one power supply line are located between the first and second output circuits, and the second set of clock signal lines are located on the side of the second output circuit away from the first set of clock signal lines.

[0027] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0028] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shape and size of one or more components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0029] Figure 1 This is a schematic diagram of the structure of a shift register unit according to at least one embodiment of the present disclosure;

[0030] Figure 2 This is an equivalent circuit diagram of a shift register unit according to at least one embodiment of the present disclosure;

[0031] Figure 3 for Figure 2 The timing diagram of the shift register unit shown is shown below;

[0032] Figure 4 This is a schematic diagram of the cascading of shift register units according to at least one embodiment of the present disclosure;

[0033] Figure 5 This is a top view of a shift register unit according to at least one embodiment of the present disclosure;

[0034] Figure 6 for Figure 5 A partial cross-sectional view along the QQ direction;

[0035] Figure 7A This is a top view of a shift register unit after the formation of the first semiconductor layer, according to at least one embodiment of the present disclosure;

[0036] Figure 7B This is a top view of a shift register unit after the formation of the first conductive layer, according to at least one embodiment of the present disclosure;

[0037] Figure 7C This is a top view of a shift register unit after the formation of the second conductive layer, according to at least one embodiment of this disclosure;

[0038] Figure 7D This is a top view of a shift register unit after the formation of the fourth insulating layer, according to at least one embodiment of this disclosure;

[0039] Figure 7E This is a top view of a shift register unit after the formation of the third conductive layer, according to at least one embodiment of this disclosure;

[0040] Figure 7F This is a top view of a shift register unit after the formation of the fourth conductive layer, according to at least one embodiment of this disclosure;

[0041] Figure 8 This is another cascaded diagram of a shift register unit according to at least one embodiment of the present disclosure;

[0042] Figure 9 This is a timing diagram of a clock signal according to at least one embodiment of the present disclosure;

[0043] Figure 10 This is another top view of a shift register unit according to at least one embodiment of the present disclosure;

[0044] Figure 11A This is another top view of a shift register unit after the formation of the first semiconductor layer, according to at least one embodiment of the present disclosure;

[0045] Figure 11BThis is another top view of a shift register unit after the formation of the first conductive layer, according to at least one embodiment of the present disclosure;

[0046] Figure 11C This is another top view of a shift register unit after the formation of the second conductive layer, according to at least one embodiment of the present disclosure;

[0047] Figure 11D This is another top view of a shift register unit after the formation of the third conductive layer, according to at least one embodiment of the present disclosure;

[0048] Figure 11E This is another top view of the shift register unit after the formation of the fourth conductive layer, according to at least one embodiment of the present disclosure;

[0049] Figure 12 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Detailed Implementation

[0050] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be changed to one or more forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the contents described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0051] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0052] The ordinal numbers “first,” “second,” “third,” etc., used in this disclosure are provided to avoid confusion among the constituent elements, not to limit the quantity. The term “multiple” in this disclosure refers to two or more quantities.

[0053] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately changed depending on the direction in which the constituent elements are described. Therefore, the description is not limited to the terms used in the specification and may be appropriately replaced as appropriate.

[0054] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate. "Electrical connection" includes situations where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the term "component having some electrical function," as long as it enables the transmission of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with one or more functions.

[0055] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain) and the source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0056] In this disclosure, to distinguish the two electrodes of a transistor other than the gate electrode, one electrode is referred to as the first electrode and the other as the second electrode. The first electrode can be either the source electrode or the drain electrode, and the second electrode can be either the drain electrode or the source electrode. Furthermore, the gate electrode of the transistor is referred to as the control electrode. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0057] In this disclosure, "parallel" refers to a state in which the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore can include a state in which the angle is greater than or equal to -5° and less than 5°. Furthermore, "perpendicular" refers to a state in which the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore can include a state in which the angle is greater than or equal to 85° and less than 95°.

[0058] In this disclosure, the terms "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be replaced with "conductive film". Similarly, sometimes "insulating film" can be replaced with "insulating layer".

[0059] In this disclosure, "about" or "approximately" means without strictly defining the limits, allowing for the possibility of errors in the process and measurement.

[0060] This disclosure provides a display substrate, including a display area and a non-display area. A gate driving circuit is disposed in the non-display area. The gate driving circuit includes a plurality of cascaded shift register units; each shift register unit is connected to at least one power supply line. Each shift register unit includes a first output circuit and a second output circuit; the first output circuit is connected to a first set of clock signal lines, and the second output circuit is connected to both the first and second set of clock signal lines. In a first direction, the first set of clock signal lines and at least one power supply line are located between the first and second output circuits, and the second set of clock signal lines is located on the side of the second output circuit away from the first set of clock signal lines.

[0061] The display substrate provided in this embodiment saves wiring space and facilitates the realization of a narrow bezel design by setting the first output circuit and the second output circuit to share the first set of clock signal lines, and placing the power line and the shared first set of clock signal lines between the first output circuit and the second output circuit.

[0062] In some exemplary embodiments, the output signals of the first output circuit and the second output circuit are out of phase.

[0063] In some exemplary embodiments, at least one power line includes: a first power line and a second power line, wherein the first power line is connected to a first output circuit, and the second power line is connected to a second output circuit. In a first direction, the first power line is located between the first output circuit and a first set of clock signal lines, and the second power line is located between the first set of clock signal lines and the second output circuit. In some examples, the first power line continuously provides a low-level signal, and the second power line continuously provides a high-level signal. However, this embodiment is not limited thereto.

[0064] In some exemplary embodiments, the non-display area is further provided with a third power line and a fourth power line. The third power line is connected to the second output circuit, and the fourth power line is connected to the first output circuit. In a first direction, the fourth power line is located on the side of the first output circuit away from the first power line, and the third power line is located between the second power line and the second set of clock signal lines. In some examples, the third power line continuously provides a low-level signal, and the fourth power line continuously provides a high-level signal. However, this embodiment is not limited to this.

[0065] In some exemplary embodiments, an initial signal line is also provided in the non-display area. In a first direction, the initial signal line is located on the side of the fourth power line away from the first output circuit. In some examples, the input terminal of the first-stage shift register unit is connected to the initial signal line. In some examples, the initial signal line includes a first initial signal line and a second initial signal line, with the first initial signal line connected to the input terminal of the first-stage shift register unit and the second initial signal line connected to the input terminal of the second-stage shift register unit. However, this embodiment is not limited in this respect.

[0066] In some exemplary embodiments, the first output circuit includes: a first node control sub-circuit, a second node control sub-circuit, and a first output sub-circuit. The first node control sub-circuit is connected to an input terminal, a first output terminal, a first clock terminal, a second clock terminal, a third clock terminal, a first power supply terminal, a second power supply terminal, a first node, and a second node, and is configured to control the potentials of the first node and the second node under the control of the first clock terminal, the third clock terminal, and the input terminal. The second node control sub-circuit is connected to the first node, the second node, the second power supply terminal, and the first output terminal, and is configured to maintain the potentials of the first node and the second node. The first output sub-circuit is connected to the first node, the second node, the second clock terminal, the second power supply terminal, and the first output terminal, and is configured to control the first output terminal to output a first output signal under the control of the first node and the second node. The second node control sub-circuit, the first output sub-circuit, and the first node control sub-circuit are arranged sequentially along a first direction. In some examples, the first power supply terminal continuously provides a low-level signal, and the second power supply terminal continuously provides a high-level signal. The circuit layout of this embodiment can save wiring space.

[0067] In some exemplary embodiments, the first node control sub-circuit includes: a first control transistor, a second control transistor, a third control transistor, a fourth control transistor, a fifth control transistor, a sixth control transistor, a seventh control transistor, and an eighth control transistor. The control electrode of the first control transistor is connected to a first clock terminal, its first terminal is connected to an input terminal, and its second terminal is connected to the fourth node. The control electrode of the second control transistor is connected to the first clock terminal, its first terminal is connected to the fourth node, and its second terminal is connected to the first node. The control electrode of the third control transistor is connected to a third clock terminal, its first terminal is connected to a first power supply terminal, and its second terminal is connected to the second node. The control electrode of the fourth control transistor is connected to the second node, its first terminal is connected to a second power supply terminal, and its second terminal is connected to the third node. The control electrode of the fifth control transistor is connected to the second node, its first terminal is connected to the third node, and its second terminal is connected to the first node. The control electrode of the sixth control transistor is connected to the first node, its first terminal is connected to a first power supply terminal, and its second terminal is connected to the third node. The control electrode of the seventh control transistor is connected to an input terminal, its first terminal is connected to a second power supply terminal, and its second terminal is connected to the second node. The control electrode of the eighth control transistor is connected to the first output terminal, the first electrode is connected to the second clock terminal, and the second electrode is connected to the fourth node. The second node control sub-circuit includes a first capacitor and a second capacitor. The first electrode of the first capacitor is connected to the first node, and the second electrode is connected to the first output terminal. The first electrode of the second capacitor is connected to the second node, and the second electrode is connected to the second power supply terminal. The first output sub-circuit includes a first output transistor and a second output transistor. The control electrode of the first output transistor is connected to the first node, the first electrode is connected to the second clock terminal, and the second electrode is connected to the first output terminal. The control electrode of the second output transistor is connected to the second node, the first electrode is connected to the second power supply terminal, and the second electrode is connected to the first output terminal.

[0068] In some exemplary embodiments, the first capacitor and the first output transistor are adjacent in a first direction, and the second capacitor and the second output transistor are adjacent in the first direction; the first capacitor and the second capacitor are adjacent in a second direction, and the first output transistor and the second output transistor are adjacent in the second direction. The second direction intersects the first direction. For example, the first direction and the second direction are in the same plane and perpendicular to each other.

[0069] In some exemplary embodiments, the active layers of the first control transistor, the second control transistor, and the eighth control transistor are integrally formed, the active layers of the fourth control transistor and the fifth control transistor are integrally formed, and the active layers of the first output transistor and the second output transistor are integrally formed. However, this embodiment is not limited to this.

[0070] In some exemplary embodiments, in the first direction, the active layer of the sixth control transistor is located between the active layers of the fifth and second control transistors, and the active layer of the seventh control transistor is located between the active layers of the fourth and third control transistors. However, this embodiment is not limited thereto.

[0071] In some exemplary embodiments, the second output circuit includes: a noise reduction control sub-circuit, a second output sub-circuit, and a third output sub-circuit. The noise reduction control sub-circuit is connected to a first output terminal, a first clock terminal, a third clock terminal, a first power supply terminal, a second power supply terminal, and a first noise reduction control node. It is configured to, under the control of the third clock signal terminal, rectify the charge at the first power supply terminal to the first noise reduction control node, maintaining the first noise reduction control node at a voltage that turns on the second output sub-circuit; and, under the control of the first output terminal, transmit the signal from the second power supply terminal to the first noise reduction control node, maintaining the first noise reduction control node at a voltage that turns off the second output sub-circuit. The second output sub-circuit is connected to the first noise reduction control node, the second output terminal, and the first power supply terminal. It is configured to, under the control of the first noise reduction control node, transmit the signal from the first power supply terminal to the second output terminal. The third output sub-circuit is connected to the first node, a fourth clock terminal, and the second output terminal. It is configured to, under the control of the first node, transmit the signal from the fourth clock terminal to the second output terminal. In the second direction, the second and third output sub-circuits are adjacent; in the first direction, the noise reduction control sub-circuit is located between the first set of clock signal lines and the second output sub-circuit. The second direction intersects the first direction.

[0072] In some exemplary embodiments, the noise reduction control sub-circuit includes: a first noise reduction control transistor, a second noise reduction control transistor, a third noise reduction control transistor, a fourth noise reduction control transistor, a third capacitor, and a fourth capacitor. The control electrode of the first noise reduction control transistor is connected to a first output terminal, its first electrode is connected to a second power supply terminal, and its second electrode is connected to a second noise reduction control node. The control electrode of the second noise reduction control transistor is connected to a third clock terminal, its first electrode is connected to a first power supply terminal, and its second electrode is connected to the second noise reduction control node. The control electrode and first electrode of the third noise reduction control transistor are connected to the second noise reduction control node, and its second electrode is connected to the first noise reduction control node. The control electrode of the fourth noise reduction control transistor is connected to a first output terminal, its first electrode is connected to a second power supply terminal, and its second electrode is connected to the first noise reduction control node.

[0073] The first electrode of the third capacitor is connected to the second noise reduction control node, and the second electrode is connected to the first clock terminal.

[0074] The first electrode of the fourth capacitor is connected to the first noise reduction control node, and the second electrode is connected to the first power supply terminal. The second output sub-circuit includes a third output transistor. The control electrode of the third output transistor is connected to the first noise reduction control node, the first electrode is connected to the first power supply terminal, and the second electrode is connected to the second output terminal. The third output sub-circuit also includes a fourth output transistor. The control electrode of the fourth output transistor is connected to the first node, the first electrode is connected to the fourth clock terminal, and the second electrode is connected to the second output terminal.

[0075] In some exemplary embodiments, the third output transistor and the fourth output transistor are adjacent in a second direction, and the first noise reduction control transistor and the second noise reduction control transistor are adjacent in a second direction. In a first direction, the third capacitor is located between the second noise reduction control transistor and the third noise reduction control transistor, and the fourth noise reduction control transistor is located between the first noise reduction control transistor and the fourth capacitor. However, this embodiment is not limited thereto.

[0076] In some exemplary embodiments, the active layers of the first and second noise reduction control transistors are integral structures, as are the active layers of the third and fourth output transistors. However, this embodiment is not limited to this.

[0077] In some exemplary embodiments, the first set of clock signal lines includes a first clock signal line, a second clock signal line, and a third clock signal line. The second set of clock signal lines includes a fourth clock signal line and a fifth clock signal line. The first clock signal provided by the first clock signal line, the second clock signal provided by the second clock signal line, and the third clock signal provided by the third clock signal line have the same duty cycle. The fourth clock signal provided by the fourth clock signal line and the fifth clock signal provided by the fifth clock signal line have the same duty cycle, and the duty cycle of the fourth clock signal is less than that of the first clock signal. The second clock signal is delayed by a set time compared to the first clock signal, and the third clock signal is delayed by a set time compared to the second clock signal, so that the first, second, and third clock signals are not simultaneously a first voltage. The fourth and fifth clock signals are not simultaneously a second voltage. The first voltage is different from the second voltage. For example, the first voltage is less than the second voltage. For example, the first voltage can be a low level, and the second voltage can be a high level. However, this embodiment is not limited in this respect.

[0078] In some exemplary embodiments, in the first direction, the first clock signal line, the second clock signal line, and the third clock signal line are arranged sequentially in a direction away from the first output circuit, and the fourth clock signal line and the fifth clock signal line are arranged sequentially in a direction away from the second output circuit. However, this embodiment does not limit the arrangement order of the multiple clock signal lines of the first group of clock signal lines, nor does it limit the arrangement order of the multiple clock signal lines of the second group of clock signal lines.

[0079] In some exemplary embodiments, the first output circuit of any level shift register unit is connected to the first clock signal line, the second clock signal line, and the third clock signal line, and the second output circuit is connected to two clock signal lines in the first group of clock signal lines and one clock signal line in the second group of clock signal lines.

[0080] In some exemplary embodiments, the first clock input of the (6n+1)th stage shift register unit is connected to the first clock signal line, the second clock input is connected to the second clock signal line, the third clock input is connected to the third clock signal line, and the fourth clock input is connected to the fourth clock signal line. The first clock input of the (6n+2)th stage shift register unit is connected to the second clock signal line, the second clock input is connected to the third clock signal line, the third clock input is connected to the first clock signal line, and the fourth clock input is connected to the fifth clock signal line. The first clock input of the (6n+3)th stage shift register unit is connected to the third clock signal line, the second clock input is connected to the first clock signal line, the third clock input is connected to the second clock signal line, and the fourth clock input is connected to the fourth clock signal line. The first clock input of the (6n+4)th stage shift register unit is connected to the first clock signal line, the second clock input is connected to the second clock signal line, the third clock input is connected to the third clock signal line, and the fourth clock input is connected to the fifth clock signal line. The first clock input of the 6n+5th stage shift register unit is connected to the second clock signal line, the second clock input is connected to the third clock signal line, the third clock input is connected to the first clock signal line, and the fourth clock input is connected to the fourth clock signal line. The first clock input of the 6n+6th stage shift register unit is connected to the third clock signal line, the second clock input is connected to the first clock signal line, the third clock input is connected to the second clock signal line, and the fourth clock input is connected to the fifth clock signal line. Here, n is a natural number. In this example, the six cascaded shift register units, as a single minimum periodic repetition unit, can drive six rows of sub-pixels in the display area.

[0081] In some exemplary embodiments, the first output of the (2k-1)th stage shift register unit is connected to the input of the (2k+1)th stage shift register unit, and the input of the first stage shift register unit is connected to the first initial signal line. The first output of the (2k)th stage shift register unit is connected to the input of the (2k+2)th stage shift register unit, and the input of the second stage shift register unit is connected to the second initial signal line, where k is a positive integer. The first group of clock signal lines includes a first group clock signal line and a second group clock signal line, and the second group of clock signal lines includes a third group clock signal line and a fourth group clock signal line. The (2k-1)th stage shift register unit is connected to the first group clock signal line and the third group clock signal line, and the (2k)th stage shift register unit is connected to the second group clock signal line and the fourth group clock signal line. In some examples, the twelve shift register units can serve as a minimum periodic repetition unit, driving twelve rows of sub-pixels in the display area.

[0082] In some exemplary embodiments, in a first direction, the first group clock signal line and the second group clock signal line are arranged at intervals, and the third group clock signal line and the fourth group clock signal line are arranged at intervals. However, this embodiment is not limited to this. For example, the first group clock signal line and the second group clock signal line are arranged sequentially along the first direction, and the third group clock signal line and the fourth group clock signal line are arranged sequentially along the first direction.

[0083] In some exemplary embodiments, the first group of clock signal lines includes: a first clock signal line, a second clock signal line, and a third clock signal line; the second group of clock signal lines includes: a sixth clock signal line, a seventh clock signal line, and an eighth clock signal line. The third group of clock signal lines includes: a fourth clock signal line and a fifth clock signal line; the fourth group of clock signal lines includes: a ninth clock signal line and a tenth clock signal line. The first clock signal provided by the first clock signal line, the second clock signal provided by the second clock signal line, the third clock signal provided by the third clock signal line, the sixth clock signal provided by the sixth clock signal line, the seventh clock signal provided by the seventh clock signal line, and the eighth clock signal provided by the eighth clock signal line all have the same duty cycle. The second clock signal is delayed by a first set time compared to the first clock signal, and the third clock signal is delayed by a first set time compared to the second clock signal, so that the first, second, and third clock signals do not simultaneously constitute the first voltage. The seventh clock signal is delayed by a first set time compared to the sixth clock signal, and the eighth clock signal is delayed by a first set time compared to the seventh clock signal, so that the sixth, seventh, and eighth clock signals do not simultaneously constitute the first voltage. The sixth clock signal is delayed by a second set time compared to the first clock signal, the seventh clock signal is delayed by a second set time compared to the second clock signal, and the eighth clock signal is delayed by a second set time compared to the third clock signal. The fourth clock signal provided by the fourth clock signal line, the fifth clock signal provided by the fifth clock signal line, the ninth clock signal provided by the ninth clock signal line, and the tenth clock signal provided by the tenth clock signal line all have the same duty cycle. The duty cycle of the fourth clock signal is less than that of the first clock signal. The fourth and fifth clock signals do not simultaneously constitute the second voltage, and the ninth and tenth clock signals do not simultaneously constitute the second voltage; the second voltage is different from the first voltage. The ninth clock signal is delayed by a second set time compared to the fourth clock signal, and the tenth clock signal is delayed by a second set time compared to the fifth clock signal.

[0084] In some exemplary embodiments, in a direction perpendicular to the display substrate, the non-display area of ​​the display substrate includes: a substrate and a first semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer disposed on the substrate. The first semiconductor layer includes at least: an active layer of a plurality of transistors in the shift register unit. The first conductive layer includes at least: control electrodes of the plurality of transistors in the shift register unit, and first electrodes of a plurality of capacitors. The second conductive layer includes at least: second electrodes of the plurality of capacitors in the shift register unit. The third conductive layer includes at least: first and second electrodes of the plurality of transistors in the shift register unit, a first set of clock signal lines, a second set of clock signal lines, and a plurality of power supply lines. The fourth conductive layer includes at least: connection electrodes of a third output sub-circuit connecting the first node and the second output circuit.

[0085] The following examples illustrate the solution of this embodiment.

[0086] In some exemplary embodiments, the display substrate may include a display area and a non-display area. For example, the non-display area may be located around the periphery of the display area. However, this embodiment is not limited to this. The display area includes at least a plurality of regularly arranged pixel circuits, a plurality of gate lines extending along a first direction (e.g., scan lines, reset signal lines, and light emission control lines), and a plurality of data lines and power lines extending along a second direction. The first and second directions are located in the same plane, and the first and second directions intersect; for example, the first direction is perpendicular to the second direction.

[0087] In some exemplary embodiments, a pixel unit within a display area may include three sub-pixels, which may be a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively. However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, which may be a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, respectively.

[0088] In some exemplary embodiments, the shape of the sub-pixels can be rectangular, rhomboid, pentagonal, or hexagonal. When a pixel unit includes three sub-pixels, the three sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement; when a pixel unit includes four sub-pixels, the four sub-pixels can be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement. However, this embodiment is not limited in this respect.

[0089] In some example implementations, the non-display area may be provided with a timing controller, a data driving circuit, and a gate driving circuit. The gate driving circuit may be located on opposite sides of the display area, for example, on the left and right sides of the display area; the timing controller and the data driving circuit may be located on one side of the display area, for example, on the lower side of the display area. However, this embodiment is not limited to this.

[0090] In some exemplary embodiments, the data driving circuit can provide data signals to the sub-pixels via data lines. The gate driving circuit can provide scan signals to the sub-pixels via scan lines, reset signals via reset signal lines, or light emission control signals via light emission control lines. The timing controller can provide driving signals to the data driving circuit and the gate driving circuit. The operation of the gate driving circuit and the data driving circuit can be controlled by the timing controller. The timing controller can provide grayscale data specifying the grayscale level to be displayed in the sub-pixels to the data driving circuit. The data driving circuit can provide a data signal corresponding to the potential of the grayscale data of the sub-pixels to the sub-pixels of the row selected by the gate driving circuit via data lines.

[0091] In some exemplary embodiments, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C structure. However, this embodiment is not limited to this. For example, the pixel driving circuit can include N-type transistors and P-type transistors. The N-type transistor can be, for example, an oxide thin-film transistor, and the P-type transistor can be, for example, a low-temperature polycrystalline silicon thin-film transistor. The active layer of the low-temperature polycrystalline silicon thin-film transistor is made of low-temperature polycrystalline silicon (LTPS), and the active layer of the oxide thin-film transistor is made of oxide semiconductor. Low-temperature polycrystalline silicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polycrystalline silicon thin-film transistors and oxide thin-film transistors on a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can utilize the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0092] In some exemplary embodiments, the gate drive circuit includes multiple cascaded shift register units. For example, the input of a first-stage shift register unit can be connected to an initial signal line; the first output of the i-th-stage shift register unit can be connected to the input of the (i+1)-th-stage shift register unit, providing an input signal to the (i+1)-th-stage shift register unit, where i is a positive integer. The second output of the shift register unit can provide a scan signal to the sub-pixel via a scan line and a reset signal to the sub-pixel via a reset signal line. For example, the first output signal provided by the first output of the shift register unit can be configured to control the turn-on of a P-type transistor (e.g., a low-temperature polycrystalline silicon thin-film transistor) in the pixel circuit, and the second output signal provided by the second output of the shift register unit can be configured to control the turn-on of an N-type transistor (e.g., an oxide thin-film transistor) in the pixel circuit. However, this embodiment is not limited in this respect.

[0093] Figure 1 This is a schematic diagram of the structure of a shift register unit according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as... Figure 1 As shown, the shift register unit provided in this exemplary embodiment includes a first output circuit 10 and a second output circuit 20. The first output circuit 10 outputs a first output signal through a first output terminal OUT1, and the second output circuit 20 outputs a second output signal through a second output terminal OUT2. The first output signal and the second output signal are out of phase.

[0094] In some exemplary implementations, such as Figure 1As shown, the first output circuit 10 includes: a first node control sub-circuit 11, a second node control sub-circuit 12, and a first output sub-circuit 13. The first node control sub-circuit 11 is connected to the input terminal INPUT, the first output terminal OUT1, the first power supply terminal V1, the second power supply terminal V2, the first clock terminal CK1, the second clock terminal CK2, the third clock terminal CK3, the first node N1, and the second node N2, and is configured to control the potentials of the first node N1 and the second node N2 under the control of the first clock terminal CK1, the input terminal INPUT, and the third clock terminal CK3. The second node control sub-circuit 12 is connected to the first node N1, the second node N2, the second power supply terminal V2, and the first output terminal OUT1, and is configured to maintain the potentials of the first node N1 and the second node N2. The first output sub-circuit 13 is connected to the second clock terminal CK2, the second power supply terminal V2, the first node N1, the second node N2, and the first output terminal OUT1, and is configured to control the first output terminal OUT1 to output a first output signal under the control of the first node N1 and the second node N2.

[0095] In some exemplary implementations, such as Figure 1 As shown, the second output circuit 20 includes a noise reduction control sub-circuit 21, a second output sub-circuit 22, and a third output sub-circuit 23. The noise reduction control sub-circuit 21 is connected to a first clock terminal CK1, a third clock terminal CK3, a first noise reduction control node PD1, a first output terminal OUT1, a first power supply terminal V1, and a second power supply terminal V2. The noise reduction control sub-circuit 21 is configured to, under the control of the third clock terminal CK3, rectify the charge of the first power supply terminal V1 to the first noise reduction control node PD1, maintaining the first noise reduction control node PD1 at a voltage that turns on the second output sub-circuit 22; and, under the control of the first output terminal OUT1, transmit the signal from the second power supply terminal V2 to the first noise reduction control node PD1, maintaining the first noise reduction control node PD1 at a voltage that turns off the second output sub-circuit 22. The second output sub-circuit 22 is connected to the first noise reduction control node PD1, the second output terminal OUT2, and the first power supply terminal V1, and is configured to, under the control of the first noise reduction control node PD1, transmit the signal from the first power supply terminal V1 to the second output terminal OUT2. The third output sub-circuit 23 is connected to the first node N1, the fourth clock terminal CB, and the second output terminal OUT2, and is configured to transmit the signal of the fourth clock terminal CB to the second output terminal OUT2 under the control of the first node N1.

[0096] In some examples, the first power supply terminal V1 can continuously provide a low-level signal, and the second power supply terminal V2 can continuously provide a high-level signal. However, this embodiment is not limited to this.

[0097] In this exemplary embodiment, the first output signal output from the first output terminal OUT1 and the second output signal output from the second output terminal OUT2 are out of phase. By setting a noise reduction control sub-circuit in the second output circuit, continuous noise reduction can be achieved for the second output terminal OUT2 of the shift register unit, thereby improving display stability.

[0098] Figure 2 This is an equivalent circuit diagram of a shift register unit according to at least one embodiment of the present disclosure. Figure 2 As shown, the first node control sub-circuit 11 includes: a first control transistor M1, a second control transistor M2, a third control transistor M5, a fourth control transistor M6, a fifth control transistor M7, a sixth control transistor M8, a seventh control transistor M9, and an eighth control transistor M10.

[0099] The first control transistor M1 has its control electrode connected to the first clock terminal CK1, its first terminal connected to the input terminal INPUT, and its second terminal connected to the fourth node N4. The second control transistor M2 has its control electrode connected to the first clock terminal CK1, its first terminal connected to the fourth node N4, and its second terminal connected to the first node N1. The third control transistor M5 has its control electrode connected to the third clock terminal CK3, its first terminal connected to the first power supply terminal V1, and its second terminal connected to the second node N2. The fourth control transistor M6 has its control electrode connected to the second node N2, its first terminal connected to the second power supply terminal V2, and its second terminal connected to the third node N3. The fifth control transistor M7 has its control electrode connected to the second node N2, its first terminal connected to the third node N3, and its second terminal connected to the first node N1. The sixth control transistor M8 has its control electrode connected to the first node N1, its first terminal connected to the first power supply terminal V1, and its second terminal connected to the third node N3. The seventh control transistor M9 has its control electrode connected to the input terminal INPUT, its first terminal connected to the second power supply terminal V2, and its second terminal connected to the second node N2. The control electrode of the eighth control transistor M10 is connected to the first output terminal OUT1, the first electrode is connected to the second clock terminal CK2, and the second electrode is connected to the fourth node N4.

[0100] In this exemplary embodiment, the first control transistor M1 and the second control transistor M2 constitute a dual-gate transistor. Dual-gate transistors have low leakage current. An eighth control transistor M10 is used to control the potential of the fourth node N4, thereby reducing the drain-source voltage of the first and second control transistors M1 and M2 within a set time period, thus lowering their leakage current. The fourth control transistor M6 and the fifth control transistor M7 constitute a dual-gate transistor, and a sixth control transistor M8 is used to control the potential of the third node N3, thereby reducing the drain-source voltage of the fourth control transistor M6 and the fifth control transistor M7 within a set time period, thus lowering their leakage current.

[0101] The second node control sub-circuit 12 includes: a first capacitor C1 and a second capacitor C2. The first electrode of the first capacitor C1 is connected to the first node N1, and the second electrode is connected to the first output terminal OUT1. The first electrode of the second capacitor C2 is connected to the second node N2, and the second electrode is connected to the second power supply terminal V2.

[0102] The first output sub-circuit 13 includes a first output transistor M3 and a second output transistor M4. The control electrode of the first output transistor M3 is connected to the first node N1, the first electrode is connected to the second clock terminal CK2, and the second electrode is connected to the first output terminal OUT1. The control electrode of the second output transistor M4 is connected to the second node N2, the first electrode is connected to the second power supply terminal V2, and the second electrode is connected to the first output terminal OUT1.

[0103] In some exemplary implementations, such as Figure 2 As shown, the noise reduction control sub-circuit 21 includes: a first noise reduction control transistor M11, a second noise reduction control transistor M12, a third noise reduction control transistor M13, a fourth noise reduction control transistor M14, a third capacitor C3, and a fourth capacitor C4.

[0104] The control electrode of the first noise reduction control transistor M11 is connected to the first output terminal OUT1, the first electrode is connected to the second power supply terminal V2, and the second electrode is connected to the second noise reduction control node PD2. The control electrode of the second noise reduction control transistor M12 is connected to the third clock terminal CK3, the first electrode is connected to the first power supply terminal V1, and the second electrode is connected to the second noise reduction control node PD2. The control electrode and the first electrode of the third noise reduction control transistor M13 are connected to the second noise reduction control node PD2, and the second electrode is connected to the first noise reduction control node PD1. The control electrode of the fourth noise reduction control transistor M14 is connected to the first output terminal OUT1, the first electrode is connected to the second power supply terminal V2, and the second electrode is connected to the first noise reduction control node PD1. The first electrode of the third capacitor C3 is connected to the second noise reduction control node PD2, and the second electrode is connected to the first clock terminal CK1. The first electrode of the fourth capacitor C4 is connected to the first noise reduction control node PD1, and the second electrode is connected to the first power supply terminal V1.

[0105] In this exemplary embodiment, the second noise reduction control transistor M12, the third noise reduction control transistor M13, the third capacitor C3, and the fourth capacitor C4 form a charge pump structure. By utilizing the voltage regulation effect of the charge pump structure, the potential of the first noise reduction control node PD1 is stabilized at a potential that enables the second output sub-circuit to turn on, thereby ensuring that the second output sub-circuit remains on during the holding phase of driving a row of gate lines, thus continuously reducing noise for the second output terminal.

[0106] In some exemplary embodiments, the second output sub-circuit includes a third output transistor M15. The control electrode of the third output transistor M15 is connected to the first noise reduction control node PD1, the first electrode is connected to the first power supply terminal V1, and the second electrode is connected to the second output terminal OUT2. The third output sub-circuit also includes a fourth output transistor M16. The control electrode of the fourth output transistor M16 is connected to the first node N1, the first electrode is connected to the fourth clock terminal CB, and the second electrode is connected to the second output terminal OUT2.

[0107] In this exemplary embodiment, the first noise reduction control node PD1, the second noise reduction control node PD2, the first node N1, the second node N2, the third node N3, and the fourth node N4 do not represent actual existing components, but rather represent the junction points of related electrical connections in the circuit diagram. In other words, these nodes are equivalent to the junction points of related electrical connections in the circuit diagram.

[0108] In this exemplary embodiment, Figure 2The diagram illustrates an exemplary structure of a first node control subcircuit, a second node control subcircuit, a first output subcircuit, a noise reduction control subcircuit, a second output subcircuit, and a third output subcircuit. Those skilled in the art will readily understand that the implementation of the first node control subcircuit, second node control subcircuit, first output subcircuit, noise reduction control subcircuit, second output subcircuit, and third output subcircuit is not limited to this, as long as its functionality is achieved.

[0109] The technical solution of this disclosure embodiment is further illustrated below through the working process of the shift register unit. The following description takes the working process of the first-stage shift register unit as an example. The input terminal INPUT of the first-stage shift register unit is connected to the initial signal line STV. Figure 3 for Figure 2 The timing diagram of the shift register unit shown is shown.

[0110] In this exemplary embodiment, during the driving process of a row of gate lines within a frame period, after the shift register unit outputs a scan signal through the second output terminal, the shift register unit outputs a non-working voltage to the gate line it is connected to during the holding phase, so as to ensure that the sub-pixel connected to the gate line is turned off.

[0111] The following description uses an example where all transistors in the shift register unit are P-type transistors, the first power supply terminal V1 provides a low-level voltage, and the second power supply terminal V2 provides a high-level voltage. In this exemplary embodiment, the first clock terminal CK1 of the shift register unit is connected to the first clock signal line GCK1, the second clock terminal CK2 is connected to the second clock signal line GCK2, the third clock terminal CK3 is connected to the third clock signal line GCK3, and the fourth clock terminal CB is connected to the fourth clock signal line GCB1.

[0112] like Figure 3 As shown, the shift register unit provided in this exemplary embodiment includes at least the following stages in the driving process of a row of gate lines: precharge stage S1, bootstrap output stage S2, node pull-up stage S3, and hold stage S4.

[0113] During the pre-charge phase S1, the initial signal line STV provides a low-level signal, the first clock signal line GCK1 provides a low-level signal, the fourth clock signal line GCB1 provides a low-level signal, and the second clock signal line GCK2 and the third clock signal line GCK3 provide high-level signals. The first control transistor M1 and the second control transistor M2 are turned on under the control of the low-level signal provided by the first clock signal line GCK1. The initial signal line STV provides a low-level signal to the first node N1, pulling the potential of the first node N1 to a low potential VGL+Vth. The first output transistor M3 is turned on under the control of the low potential of the first node N1. The second clock signal line GCK2 provides a high-level signal to the first output terminal OUT1. The voltage stored across the first capacitor C1 is VGL+Vth-VGH, where Vth is the threshold voltage of the first control transistor M1, and VGL is the low voltage.

[0114] During the precharge phase S1, the seventh control transistor M9 is turned on under the control of a low-level signal provided by the input terminal INPUT, and the second power supply terminal V2 provides a high-level signal to the second node N2. The second output transistor M4, the fourth control transistor M6, and the fifth control transistor M7 are turned off under the control of a high potential at the second node N2. The third control transistor M5 is turned off under the control of a high-level signal provided by the third clock signal line GCK3. The sixth control transistor M8 is turned on under the control of a low potential at the first node N1, and the first power supply terminal V1 provides a low-level signal to the third node N3. The eighth control transistor M10 is turned off under the control of a high-level signal at the first output terminal OUT1.

[0115] During the pre-charge phase S1, both the first noise reduction control transistor M11 and the fourth noise reduction control transistor M14 are turned off under the control of a high-level signal at the first output terminal OUT1. The second noise reduction control transistor M12 is turned off under the control of a high-level signal provided by the third clock signal line GCK3. The fourth output transistor M16 is turned on under the control of a low potential at the first node N1, and the fourth clock signal line GCB1 provides a low-level signal to the second output terminal OUT2.

[0116] During the bootstrap output phase S2, the initial signal line STV provides a high-level signal, the first clock signal line GCK1, the third clock signal line GCK3, and the fourth clock signal line GCB1 provide high-level signals, and the second clock signal line GCK2 provides a low-level signal. The first control transistor M1 and the second control transistor M2 are turned off under the control of the high-level signal provided by the first clock signal line GCK1. The first node N1 remains at a low potential, and the first output transistor M3 is turned on. The second clock signal line GCK2 provides a low-level signal to the first output terminal OUT1. Since the voltage across the first capacitor C1 cannot change abruptly, under the action of the first capacitor C1, the potential of the first node N1 is pulled low to 2VGL + Vth - 2VGH to ensure that the first output transistor M3 is turned on. Here, VGH is a high voltage.

[0117] During the bootstrap output phase S2, the seventh control transistor M9 is turned off under the control of the high-level signal provided by the initial signal line STV. Under the action of the second capacitor C2, the second node N2 maintains a high potential, and the second output transistor M4, the fourth control transistor M6, and the fifth control transistor M7 are turned off. The sixth control transistor M8 is turned on under the control of the low potential of the first node N1, and the first power supply terminal V1 provides a low-level signal to the third node N3.

[0118] During the bootstrap output phase S2, both the first denoising control transistor M11 and the fourth denoising control transistor M14 are turned on under the control of a low-level signal at the first output terminal OUT1. The second power supply terminal V2 provides a high-level signal to the first denoising control node PD1 and the second denoising control node PD2. The second denoising control node M12 is turned off under the control of a high-level signal provided by the third clock signal line GCK3. The third denoising control transistor M13 is turned off under the control of a high potential at the second denoising control node PD2, and the third output transistor M15 is turned off under the control of a high potential at the first denoising control node PD1. The fourth output transistor M16 is turned on under the control of a low potential at the first node N1, and the fourth clock signal line GCB1 provides a high-level signal to the second output terminal OUT2.

[0119] During the later time period included in the bootstrap output phase S2, the second clock signal provided by the second clock signal line GCK2 changes from a low level signal to a high level signal. Since the potential of the first node N1 is still lower than the potential of the second clock signal, the first output transistor M3 is turned on, and the first output terminal OUT1 outputs the second clock signal, realizing the low pulse output of the first output terminal OUT1.

[0120] During the bootstrap output phase S2, the low potential of the first node N1 controls the fourth output transistor M16 to turn on, and the second output terminal OUT2 outputs the fourth clock signal provided by the fourth clock signal line GCB1. Since the high pulse width of the fourth clock signal is smaller than the low pulse width of the second clock signal provided by the second clock signal line GCK2, all pulses of the fourth clock signal can be transmitted to the second output terminal OUT2, including both rising and falling parts. The low potential of the first output terminal OUT1 controls the first denoising control transistor M11 and the fourth denoising control transistor M14 to turn on, stabilizing the potentials of the first denoising control node PD1 and the second denoising control node PD2 at a high potential, causing the third output transistor M15 to turn off, thus avoiding logical conflicts in the output of the second output terminal OUT2.

[0121] During the node pull-up phase S3, the initial signal line STV provides a high-level signal, the first clock signal line GCK1 and the second clock signal line GCK2 provide high-level signals, and the third clock signal line GCK3 and the fourth clock signal line GCB1 provide low-level signals. The third control transistor M5 is turned on under the control of the low-level signal provided by the third clock signal line GCK3, and the first power supply terminal V1 provides a low-level signal to the second node N2. The second output transistor M4, the fourth control transistor M6, and the fifth control transistor M5 are turned on under the control of the low potential of the second node N2, and the second power supply terminal V2 provides a high-level signal to the first output terminal OUT1 and the first node N1. The first output transistor M3 and the sixth control transistor M8 are turned off under the control of the high potential of the first node N1.

[0122] During the node pull-up phase S3, both the first denoising control transistor M11 and the fourth denoising control transistor M14 are turned off under the control of the high-level signal at the first output terminal OUT1. The second denoising control transistor M12 is turned on under the control of the low-level signal provided by the third clock signal line GCK3, and the first power supply terminal V1 provides a low-level signal to the second denoising control node PD2. Since the first clock signal line GCK1 provides a high-level signal, the storage potential of the third capacitor C3 is VGL + Vth12 - VGH; where Vth12 is the threshold voltage of the second denoising control transistor M12. The third denoising control transistor M13 is turned on under the control of the low potential of the second denoising control node PD2, and the first denoising control node PD1 is pulled low. The third output transistor M15 is turned on under the control of the low potential of the first denoising control node PD1, and the first power supply terminal V1 provides a low-level signal to the second output terminal OUT2. The fourth output transistor M16 is turned off under the control of the high potential of the first node N1.

[0123] During the hold phase S4, the third clock signal provided by the third clock signal line GCK3 periodically pulls the potential of the second node N2 to a low level, ensuring that the second output transistor M4 is turned on, so that the first output terminal OUT1 stably outputs a high level. The third clock signal periodically pulls the potentials of the second noise reduction control node PD2 and the first noise reduction control node PD1 low, storing VGL+Vth12-VGH in the third capacitor C3. At the same time, the first clock signal provided by the first clock signal line GCK1 periodically jumps to a low voltage, which, through the third capacitor C3, can pull the potentials of the second noise reduction control node PD2 and the first noise reduction control node PD1 to an even lower level, ensuring that the third output transistor M15 is fully turned on, outputting the low-level signal provided by the first power supply terminal V1 to the second output terminal OUT2.

[0124] This exemplary embodiment can maintain the stability of the displayed image and improve the display effect by continuously denoising the second output terminal OUT2 during the holding phase S4.

[0125] In some exemplary implementations, such as Figure 3 As shown, the first clock signal provided by the first clock signal line GCK1, the second clock signal provided by the second clock signal line GCK2, the third clock signal provided by the third clock signal line GCK3, the fourth clock signal provided by the fourth clock signal line GCB1, and the fifth clock signal provided by the fifth clock signal line GCB2 are all pulse signals. The duty cycles of the first, second, and third clock signals can be the same. The second clock signal is delayed by a set duration compared to the first clock signal, and the third clock signal is delayed by a set duration compared to the second clock signal, so that the first, second, and third clock signals are not simultaneously at a low voltage. For example, the second clock signal is delayed by 1H compared to the first clock signal, and the third clock signal is delayed by 1H compared to the second clock signal, where H is the duration required to refresh one row of pixels. The duty cycles of the fourth and fifth clock signals can be the same. The duty cycle of the fourth clock signal can be less than the duty cycle of the first clock signal. The duty cycle refers to the proportion of the high-level duration within a pulse cycle (including the high-level duration and the low-level duration). The fourth and fifth clock signals are not simultaneously at a high voltage. However, this embodiment is not limited in this respect.

[0126] In some exemplary embodiments, the duty cycles of the first clock signal, the second clock signal, and the third clock signal may be slightly less than 1 / 3, or the duty cycles of the first clock signal, the second clock signal, and the third clock signal may be approximately equal to 1 / 3. However, this embodiment is not limited to this.

[0127] Figure 4 This is a schematic diagram of a gate drive circuit according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as Figure 4 As shown, the gate drive circuit includes multiple cascaded shift register units.

[0128] Specifically, the first clock terminal of the 6n+1th stage shift register unit is connected to the first clock signal line GCK1, the second clock terminal is connected to the second clock signal line GCK2, the third clock terminal is connected to the third clock signal line GCK3, and the fourth clock terminal is connected to the fourth clock signal line GCB1.

[0129] The first clock input of the 6n+2 level shift register unit is connected to the second clock signal line GCK2, the second clock input is connected to the third clock signal line GCK3, the third clock input is connected to the first clock signal line GCK1, and the fourth clock input is connected to the fifth clock signal line GCB2.

[0130] The first clock input of the 6n+3 level shift register unit is connected to the third clock signal line GCK3, the second clock input is connected to the first clock signal line GCK1, the third clock input is connected to the second clock signal line GCK2, and the fourth clock input is connected to the fourth clock signal line GCB1.

[0131] The first clock input of the 6n+4th stage shift register unit is connected to the first clock signal line GCK1, the second clock input is connected to the second clock signal line GCK2, the third clock input is connected to the third clock signal line GCK3, and the fourth clock input is connected to the fifth clock signal line GCB2.

[0132] The first clock input of the 6n+5th stage shift register unit is connected to the second clock signal line GCK2, the second clock input is connected to the third clock signal line GCK3, the third clock input is connected to the first clock signal line GCK1, and the fourth clock input is connected to the fourth clock signal line GCB1.

[0133] The first clock input of the 6n+6th stage shift register unit is connected to the third clock signal line GCK3, the second clock input is connected to the first clock signal line GCK1, the third clock input is connected to the second clock signal line GCK2, and the fourth clock input is connected to the fifth clock signal line GCB2. Here, n is a natural number.

[0134] In this exemplary embodiment, the first group of clock signal lines includes a first clock signal line GCK1, a second clock signal line GCK2, and a third clock signal line GCK3; the second group of clock signal lines includes a fourth clock signal line GCB1 and a fifth clock signal line GCB2. Each shift register unit is connected to three clock signal lines from the first group and one clock signal line from the second group. The six cascaded shift register units of the gate drive circuit in this embodiment can serve as a minimum periodic repetition unit to drive six rows of sub-pixels in the display area.

[0135] The explanation of the clock signals provided by the first clock signal line GCK1 to the fifth clock signal line GCB2 is as described above, so it will not be repeated here.

[0136] Figure 5 This is a top view of a shift register unit according to at least one embodiment of the present disclosure. Figure 5 The diagram uses the cascaded shift register units at levels 6n+1 and 6n+2 (e.g., n=1) as an example. The following explanation primarily focuses on the structure of the shift register unit at level 6n+1. Figure 6 for Figure 5 A partial cross-sectional view along the QQ direction is shown. The equivalent circuit diagram of the shift register unit in this exemplary embodiment is shown below. Figure 2 As shown. In this exemplary embodiment, the transistor in the shift register unit is a P-type transistor, and specifically a low-temperature polycrystalline silicon thin-film transistor, as an example for explanation. However, this embodiment is not limited to this.

[0137] In some exemplary implementations, such as Figure 5 As shown, in a plane parallel to the display substrate, the first output circuit, the first set of clock signal lines, the second output circuit, and the second set of clock signal lines are arranged sequentially along the first direction X. In this example, the first output circuit and the second output circuit share the first set of clock signal lines, and the first set of clock signal lines is arranged between the first output circuit and the second output circuit, which can save wiring space.

[0138] In some exemplary implementations, such as Figure 5 As shown, the first group of clock signal lines includes: a first clock signal line GCK1, a second clock signal line GCK2, and a third clock signal line GCK3. The second group of clock signal lines includes: a fourth clock signal line GCB1 and a fifth clock signal line GCB2. The first clock signal line GCK1, the second clock signal line GCK2, and the third clock signal line GCK3 are arranged sequentially in the first direction X, away from the first output circuit. The fourth clock signal line GCB1 and the fifth clock signal line GCB2 are arranged sequentially in the first direction X, away from the second output circuit.

[0139] In some exemplary implementations, such as Figure 5As shown, in the first direction X, the first set of clock signal lines is located between the first node control subcircuit of the first output circuit and the noise reduction control subcircuit of the second output circuit. The second set of clock signal lines is located on the side of the second and third output subcircuits away from the noise reduction control subcircuit. The first node control subcircuit is located between the first output subcircuit and the first set of clock signal lines. The first output subcircuit is located between the second node control subcircuit and the first node control subcircuit. The noise reduction control subcircuit is located between the first set of clock signal lines and the second output subcircuit. The second and third output subcircuits are arranged sequentially along the second direction Y. The first direction X and the second direction Y intersect, for example, the first direction X and the second direction Y are perpendicular to each other.

[0140] In some exemplary implementations, such as Figure 5 As shown, a low-level signal is continuously provided through the first power line PL1a and the third power line PL1b. The first power line PL1a is connected to the first output circuit of the shift register unit and is configured to provide a low-level signal to the first output circuit; the third power line PL1b is connected to the second output circuit of the shift register unit and is configured to provide a low-level signal to the second output circuit. In the first direction X, the first power line PL1a is located between the first node control sub-circuit and the first group of clock signal lines, and the third power line PL1b is located on the side of the second output sub-circuit and the third output sub-circuit closer to the first group of clock signal lines. However, this embodiment is not limited in this respect.

[0141] In some exemplary implementations, such as Figure 5 As shown, a high-level signal is continuously provided through the second power line PL2b and the fourth power line PL2a. The second power line PL2b is connected to the second output circuit and configured to provide a high-level signal to the second output circuit. The fourth power line PL2a is connected to the first output circuit and configured to provide a high-level signal to the first output circuit. In the first direction X, the fourth power line PL2a is located on the side of the first output sub-circuit away from the first node control sub-circuit, and the second power line PL2b is located on the side of the noise reduction control sub-circuit closer to the first set of clock signal lines. However, this embodiment is not limited in this respect.

[0142] In some exemplary implementations, such as Figure 5 As shown, in the first direction X, the initial signal line STV is located on the side of the fourth power line PL2a away from the first output sub-circuit. However, this embodiment is not limited to this.

[0143] In some exemplary implementations, such as Figure 5As shown, the first clock signal line GCK1, the second clock signal line GCK2, the third clock signal line GCK3, the fourth clock signal line GCB1, the fifth clock signal line GCB2, the first power supply line PL1a, the fourth power supply line PL2a, the third power supply line PL1b, the second power supply line PL2b, and the initial signal line STV all extend along the second direction Y. The first output terminal OUT1 and the second output terminal OUT2 both extend along the first direction X.

[0144] In some exemplary implementations, such as Figure 5 As shown, in a plane parallel to the display substrate, the first output transistor M3 and the second output transistor M4 of the first output sub-circuit are adjacent in the second direction Y. The first capacitor C1 and the second capacitor C2 of the second node control sub-circuit are adjacent in the second direction Y. The first capacitor C1 and the first output transistor M3 are adjacent in the first direction X, and the first capacitor C1 is located on the side of the first output transistor M3 away from the first node control sub-circuit. The second capacitor C2 and the second output transistor M4 are adjacent in the first direction X, and the second capacitor C2 is located on the side of the second output transistor M4 away from the first node control sub-circuit.

[0145] In some exemplary implementations, such as Figure 5 As shown, in a plane parallel to the display substrate, the fourth control transistor M6 and the fifth control transistor M7 are adjacent in the second direction Y. The seventh control transistor M9 and the fourth control transistor M6 are adjacent in the first direction X, and the seventh control transistor M9 is located on the side of the fourth control transistor M6 away from the second output transistor M4. The sixth control transistor M8 and the fifth control transistor M7 are adjacent in the first direction X, and the sixth control transistor M8 is located on the side of the fifth control transistor M7 away from the first output transistor M3. The second control transistor M2 and the sixth control transistor M8 are adjacent in the first direction X, and the second control transistor M2 is located on the side of the sixth control transistor M8 away from the fifth control transistor M7. The eighth control transistor M10 and the second control transistor M2 are adjacent in the first direction X, and the eighth control transistor M10 is located on the side of the second control transistor M2 away from the sixth control transistor M8. In the first direction X, the first control transistor M1 is located between the second control transistor M2 and the eighth control transistor M10. The third control transistor M5 and the first control transistor M1 are adjacent in the first direction X, and the third control transistor M5 is located on the side of the first control transistor M1 away from the second control transistor M2.

[0146] In some exemplary implementations, such as Figure 5As shown, in a plane parallel to the display substrate, the first noise reduction control transistor M11 and the second noise reduction control transistor M12 are adjacent in the second direction Y. The first noise reduction control transistor M11 and the second noise reduction control transistor M12 are adjacent to the second power line PL2b in the first direction X. The first noise reduction control transistor M11 and the fourth noise reduction control transistor M14 are adjacent in the first direction X, and the fourth noise reduction control transistor M14 is located on the side of the first noise reduction control transistor M11 away from the second power line PL2b. The third capacitor C3 and the second noise reduction control transistor M12 are adjacent in the first direction X, and the third capacitor C3 is located on the side of the second noise reduction control transistor M12 away from the second power line PL2b. The third noise reduction control transistor M13 and the third capacitor C3 are adjacent in the first direction X, and the third noise reduction control transistor M13 is located on the side of the third capacitor C3 away from the second noise reduction control transistor M12. The fourth capacitor C4 and the fourth noise reduction control transistor M14 are adjacent in the first direction X, and the fourth capacitor C4 is located on the side of the fourth noise reduction control transistor M14 away from the first noise reduction control transistor M11. The third noise reduction control transistor M13 and the fourth capacitor C4 are adjacent in the second direction Y.

[0147] In some exemplary implementations, such as Figure 5 As shown, in a plane parallel to the display substrate, the third output transistor M15 and the fourth output transistor M16 are adjacent in the second direction Y. The third output transistor M15 and the fourth capacitor C4 are adjacent in the first direction X, and the third output transistor M15 is located on the side of the fourth capacitor C4 away from the fourth noise reduction control transistor M14. The fourth output transistor M16 and the third noise reduction control transistor M13 are adjacent in the first direction X, and the fourth output transistor M16 is located on the side of the third noise reduction control transistor M13 away from the third capacitor C3.

[0148] In some exemplary implementations, such as Figure 5As shown, in a plane parallel to the display substrate, in the first direction X, the first output transistor M3 and the second output transistor M4 of the first output sub-circuit, and the first control transistors M1 to M10 of the first node control sub-circuit are located between the first power line PL1a and the fourth power line PL2a. In the first direction X, the first noise reduction control transistor M11, the second noise reduction control transistor M12, and the fourth noise reduction control transistor M14 of the noise reduction control sub-circuit are located between the third power line PL1b and the second power line PL2b. The third noise reduction control transistor M13 of the noise reduction control sub-circuit, and the third output transistor M15 and the fourth output transistor M16 of the second output sub-circuit are located in the first direction X between the third power line PL1b and the second set of clock signal lines. The first clock signal line GCK1, the second clock signal line GCK2, and the third clock signal line GCK3 are located in the first direction X between the first power line PL1a and the second power line PL2b.

[0149] In some exemplary implementations, such as Figure 6 As shown, in a plane perpendicular to the display substrate, the non-display area of ​​the display substrate may include: a substrate 60, and a first semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed on the substrate 60. A first insulating layer 61 is disposed between the substrate 60 and the first semiconductor layer; a second insulating layer 62 is disposed between the first conductive layer and the first semiconductor layer; a third insulating layer 63 is disposed between the first and second conductive layers; and a fourth insulating layer 64 is disposed between the second and third conductive layers. A fifth insulating layer 65 and a sixth insulating layer 66 are disposed between the third and fourth conductive layers. The fifth insulating layer 65 is located on the side of the sixth insulating layer 66 closest to the substrate 60. In some examples, the first insulating layers 61 to 65 are inorganic insulating layers, and the sixth insulating layer 66 is an organic insulating layer. However, this embodiment is not limited to this.

[0150] Figure 7A This is a top view of a shift register unit after the formation of the first semiconductor layer, according to at least one embodiment of this disclosure. Figures 5 to 7AAs shown, the first semiconductor layer in the non-display area includes at least the active layers of multiple transistors in the shift register unit. For example, the first semiconductor layer includes at least: an active layer 110 of the first control transistor M1, an active layer 120 of the second control transistor M2, an active layer 150 of the third control transistor M5, an active layer 160 of the fourth control transistor M6, an active layer 170 of the fifth control transistor M7, an active layer 180 of the sixth control transistor M8, an active layer 190 of the seventh control transistor M9, an active layer 200 of the eighth control transistor M10, and an active layer 130 of the first output transistor M3. -1 and 130-2, the active layers 140-1 and 140-2 of the second output transistor M4, the active layer 210 of the first noise reduction control transistor M11, the active layer 220 of the second noise reduction control transistor M12, the active layer 230 of the third noise reduction control transistor M13, the active layer 240 of the fourth noise reduction control transistor M14, the active layers 250-1 and 250-2 of the third output transistor M15, and the active layers 260-1 and 260-2 of the fourth output transistor M16.

[0151] In some exemplary embodiments, in the first direction X, the active layer 160 of the fourth control transistor M6 is located between the active layer 140-2 of the second output transistor M4 and the active layer 190 of the seventh control transistor M9; the active layer 170 of the fifth control transistor M7 is located between the active layer 130-2 of the first output transistor M3 and the active layer 180 of the sixth control transistor M8; the active layer 110 of the first control transistor M1 and the active layer 120 of the second control transistor M2 are located between the active layer 200 of the eighth control transistor M10 and the active layer 180 of the sixth control transistor M8; the active layer 230 of the third noise reduction control transistor M13 is located between the active layer 220 of the second noise reduction control transistor M12 and the active layer 260-1 of the fourth output transistor M16; and the active layer 240 of the fourth noise reduction control transistor M14 is located between the active layer 210 of the first noise reduction control transistor M11 and the active layer 250-1 of the third output transistor M15.

[0152] In some exemplary embodiments, the active layer 130-1 of the first output transistor M3 and the active layer 140-1 of the second output transistor M4 are integral structures, for example, rectangles with notches; the active layers 130-2 of the first output transistor M3 and 140-2 of the second output transistor M4 are integral structures, for example, rectangles with notches. The active layer 160 of the fourth control transistor M6 and the active layer 170 of the fifth control transistor M7 are integral structures, for example, rectangles. The active layer 110 of the first control transistor M1, the active layer 120 of the second control transistor M2, and the active layer 200 of the eighth control transistor M10 are integral structures. The active layer 210 of the first noise reduction control transistor M11 and the active layer 220 of the second noise reduction control transistor M12 are integral structures. The active layer 250-1 of the third output transistor M15 and the active layer 260-1 of the fourth output transistor M16 are an integral structure, for example, rectangular; the active layer 250-2 of the third output transistor M15 and the active layer 260-2 of the fourth output transistor M16 are also an integral structure, for example, rectangular. However, this embodiment is not limited in this respect.

[0153] In some exemplary embodiments, the material of the first semiconductor layer may include, for example, polycrystalline silicon. The active layer may include at least one channel region and multiple doped regions. The channel region may be undoped and possess semiconductor properties. The multiple doped regions may be located on either side of the channel region and are doped with impurities, thus possessing conductivity. The impurities may vary depending on the type of transistor.

[0154] In some exemplary embodiments, the doped regions of the active layer can be interpreted as the source or drain electrodes of a transistor. For example, the source electrode of the first control transistor M1 may correspond to the first doped region 110b, which is doped with impurities, surrounding the channel region 110a of the active layer 110, and the drain electrode of the first control transistor M1 may correspond to the second doped region 110c, which is doped with impurities, surrounding the channel region 110a of the active layer 110. Additionally, portions of the active layer between transistors can be interpreted as doped wiring, which can be used to electrically connect transistors.

[0155] Figure 7B This is a top view of a shift register unit after the formation of the first conductive layer, according to at least one embodiment of this disclosure. Figures 5 to 7BAs shown, the first conductive layer in the non-display area includes at least: control electrodes of multiple transistors in the shift register unit and first electrodes of multiple capacitors. For example, the first conductive layer may include: control electrode 113 of the first control transistor M1, control electrode 123 of the second control transistor M2, control electrodes 153a and 153b of the third control transistor M5, control electrode 163 of the fourth control transistor M6, control electrode 173 of the fifth control transistor M7, control electrode 183 of the sixth control transistor M8, control electrode 193 of the seventh control transistor M9, control electrodes 203a and 203b of the eighth control transistor M10, control electrodes 133a, 133b and 133c of the first output transistor M3, control electrode 143 of the second output transistor M4, and a first noise reduction control electrode. The control electrodes 213a and 213b of transistor M11, the control electrode 223 of second noise reduction control transistor M12, the control electrode 233 of third noise reduction control transistor M13, the control electrodes 243a and 243b of fourth noise reduction control transistor M14, the control electrode 253 of third output transistor M15, the control electrodes 263a, 263b and 263c of fourth output transistor M16, the first electrode 301 of first capacitor C1, the first electrode 302 of second capacitor C2, the first electrode 303 of third capacitor C3, the first electrode 304 of fourth capacitor C4, the first connection electrode 501 and the second connection electrode 502.

[0156] In some exemplary embodiments, the first electrode 301 of the first capacitor C1, the control electrodes 133a, 133b, and 133c of the first output transistor M3, and the control electrode 183 of the sixth control transistor M8 can be an integral structure. The first electrode 302 of the second capacitor C2, the control electrode 143 of the second output transistor M4, the control electrode 163 of the fourth control transistor M6, and the control electrode 173 of the fifth control transistor M7 can be an integral structure. The control electrode 113 of the first control transistor M1 and the control electrode 123 of the second control transistor M2 can be an integral structure. The control electrodes 153a and 153b of the third control transistor M5 and the control electrode 223 of the second noise reduction control transistor M12 can be an integral structure. The control electrodes 213a and 213b of the first noise reduction control transistor M11 and the control electrodes 243a and 243b of the fourth noise reduction control transistor M14 can be an integral structure. The first electrode 303 of the third capacitor C3 and the control electrode 233 of the third noise reduction control transistor M13 can be an integral structure. The first electrode 304 of the fourth capacitor C4 and the control electrode 253 of the third output transistor M15 can be a single integrated structure. The control electrodes 263a, 263b, and 263c of the fourth output transistor M16 can also be a single integrated structure. The control electrode 193 of the seventh control transistor M9 of any first-level shift register unit, the control electrodes 203a and 203b of the eighth control transistor M10 of the previous-level shift register unit, and the first connection electrode 501 of the previous-level shift register unit can all be a single integrated structure. However, this embodiment is not limited in this respect.

[0157] In this exemplary embodiment, the third control transistor M5, the eighth control transistor M10, the first noise reduction control transistor M11, and the fourth noise reduction control transistor M14 can be dual-gate transistors, and the first output transistor M3 and the fourth output transistor M16 can be tri-gate transistors to prevent and reduce leakage current. However, this embodiment is not limited in this respect.

[0158] Figure 7C This is a top view of a shift register unit after the formation of the second conductive layer, according to at least one embodiment of this disclosure. Figures 5 to 7C As shown, the second conductive layer in the non-display area includes at least: the second electrodes of multiple capacitors in the shift register unit, a first output terminal, and a second output terminal. For example, the second conductive layer may include: the second electrode 401 of the first capacitor C1, the second electrode 402 of the second capacitor C2, the second electrode 403 of the third capacitor C3, the second electrode 404 of the fourth capacitor C4, the first output terminal OUT1, the second output terminal OUT2, the third connection electrode 503, and the first connection line 701.

[0159] In some exemplary embodiments, the orthographic projection of the second electrode 401 of the first capacitor C1 onto the substrate 60 overlaps with the orthographic projection of the first electrode 301 of the first capacitor C1 onto the substrate 60. Similarly, the orthographic projection of the second electrode 402 of the second capacitor C2 onto the substrate 60 overlaps with the orthographic projection of the first electrode 302 of the second capacitor C2 onto the substrate 60. Likewise, the orthographic projection of the second electrode 403 of the third capacitor C3 onto the substrate 60 overlaps with the orthographic projection of the first electrode 303 of the third capacitor C3 onto the substrate 60. Finally, the orthographic projection of the second electrode 404 of the fourth capacitor C4 onto the substrate 60 overlaps with the orthographic projection of the first electrode 304 of the fourth capacitor C4 onto the substrate 60.

[0160] In some exemplary embodiments, the first output terminal OUT1 and the second output terminal OUT2 extend along a first direction X. The first output terminal OUT1 is located on the side of the third output transistor M15 away from the fourth output transistor M16 in the second direction Y, and the second output terminal OUT2 is located on the side of the third output transistor M15 away from the fourth capacitor C4 in the first direction X. The first connection line 701 extends along the first direction X, and the first connection line 701 is located between two adjacent shift register units in the second direction Y.

[0161] Figure 7D This is a top view of a shift register unit after the formation of the fourth insulating layer, according to at least one embodiment of this disclosure. Figures 5 to 7D As shown, a plurality of vias are formed on the fourth insulating layer 64 in the non-display area. For example, the plurality of vias may include: a plurality of first vias K1 to K30, a plurality of second vias H1 to H17, and a plurality of third vias D1 to D10. The fourth insulating layer 64, the third insulating layer 63, and the second insulating layer 62 within the plurality of first vias K1 to K30 are etched away, exposing the surface of the first semiconductor layer. The fourth insulating layer 64 and the third insulating layer 63 within the plurality of second vias H1 to H17 are etched away, exposing the surface of the first conductive layer. The fourth insulating layer 64 within the plurality of third vias D1 to D10 is etched away, exposing the surface of the second conductive layer.

[0162] Figure 7E This is a top view of a shift register unit after the formation of the third conductive layer, according to at least one embodiment of this disclosure. Figures 5 to 7EAs shown, the third conductive layer in the non-display area includes at least: the first and second terminals of multiple transistors in the shift register unit, a first set of clock signal lines, a second set of clock signal lines, and multiple power supply lines. For example, the third conductive layer may include: the first terminal 111 and second terminal 112 of the first control transistor M1, the first terminal 121 and second terminal 122 of the second control transistor M2, the first terminal 151 and second terminal 152 of the third control transistor M5, the first terminal 161 and second terminal 162 of the fourth control transistor M6, the first terminal 171 and second terminal 172 of the fifth control transistor M7, the first terminal 181 and second terminal 182 of the sixth control transistor M8, the first terminal 191 and second terminal 192 of the seventh control transistor M9, the first terminal 201 and second terminal 202 of the eighth control transistor M10, the first terminal 131 and second terminal 132 of the first output transistor M3, the first terminal 141 and second terminal 142 of the second output transistor M4, and the first terminal 211 and second terminal 212 of the first noise reduction control transistor M11. The first electrode 221 and the second electrode 222 of the second noise reduction control transistor M12, the first electrode 231 and the second electrode 232 of the third noise reduction control transistor M13, the first electrode 241 and the second electrode 242 of the fourth noise reduction control transistor M14, the first electrode 251 and the second electrode 252 of the third output transistor M15, the first electrode 261 and the second electrode 262 of the fourth output transistor M16, the initial signal line STV, the first power supply line PL1a, the third power supply line PL1b, the fourth power supply line PL2a, the second power supply line PL2b, the first clock signal line GCK1, the second clock signal line GCK2, the third clock signal line GCK3, the fourth clock signal line GCB1, the fifth clock signal line GCB2, the fourth connection electrode 504, the fifth connection electrode 505, the sixth connection electrode 506, and the second connection line 702.

[0163] In some exemplary embodiments, the fourth power line PL2a, the first terminal 141 of the second output transistor M4, the first terminal 161 of the fourth control transistor M6, and the first terminal 191 of the seventh control transistor M9 can be an integral structure. The second terminal 132 of the first output transistor M3 and the second terminal 142 of the second output transistor M4 can be an integral structure. The second terminal 162 of the fourth control transistor M6, the first terminal 171 of the fifth control transistor M7, and the second terminal 182 of the sixth control transistor M8 can be an integral structure. The second terminal 112 of the first control transistor M1, the first terminal 121 of the second control transistor M2, and the second terminal 202 of the eighth control transistor M10 can be an integral structure. The second terminal 192 of the seventh control transistor M9 and the second terminal 152 of the third control transistor M5 can be an integral structure. The first power line PL1a, the first terminal 151 of the third control transistor M5, and the first terminal 181 of the sixth control transistor M8 can be an integral structure. The second power line PL2b, the first terminal 211 of the first noise reduction control transistor M11, and the first terminal 241 of the fourth noise reduction control transistor M14 can be an integral structure. The third power supply line PL1b, the first terminal 221 of the second noise reduction control transistor M12, and the first terminal 251 of the third output transistor M15 can be a single integrated structure. The second terminal 212 of the first noise reduction control transistor M11 and the second terminal 222 of the second noise reduction control transistor M12 can be a single integrated structure. The second terminal 252 of the third output transistor M15 and the second terminal 262 of the fourth output transistor M16 can be a single integrated structure.

[0164] Figure 7F This is a top view of a shift register unit after the formation of the fourth conductive layer, according to at least one embodiment of this disclosure. Figures 5 to 7F As shown, a plurality of vias are formed on the sixth insulating layer 66 in the non-display area. For example, the plurality of vias may include a plurality of fourth vias F1 to F3. The fifth insulating layer 65 and the sixth insulating layer 66 within the plurality of fourth vias F1 to F3 are etched away, exposing the surface of the third conductive layer.

[0165] In some exemplary embodiments, the fourth conductive layer in the non-display area includes at least a connection electrode. For example, the fourth conductive layer may include a seventh connection electrode 507 and a third connection line 703. Both the seventh connection electrode 507 and the third connection line 703 extend along a first direction X. The seventh connection electrode 507 can be connected to the second electrode 172 of the fifth control transistor M7 through a fourth via F1, and also to the fifth connection electrode 505 through a fourth via F2. The fifth connection electrode 505 is connected to the control electrode 263c of the fourth output transistor M16 through two vertically arranged second vias H17. The third connection line 703 can be connected to the second connection line 702 through a fourth via F3, and the second connection line 702 can be connected to the first connection line 701 through a third via D3.

[0166] In some examples, the gate driving circuit of this embodiment can be configured to provide scan signals and reset signals to the sub-pixels of the display area. In this example, a light-emitting driving circuit can be provided on the side of the gate driving circuit away from the display area, configured to provide light-emitting control signals to the sub-pixels of the display area. The light-emitting driving circuit may include multiple cascaded shift register units. The output of any stage shift register unit of the light-emitting driving circuit can be connected to the first connection line 701, and then sequentially connected through the second connection line 702 and the third connection line 703 to transmit the light-emitting control signal to the display area. However, this embodiment is not limited in this respect.

[0167] In some exemplary embodiments, the first control transistor M1 includes an active layer 110, a control electrode 113, a first electrode 111, and a second electrode 112. The active layer 110 includes a channel region 110a, a first doped region 110b, and a second doped region 110c. The control electrode 113 of the first control transistor M1 and the control electrode 123 of the second control transistor M2 are integrally formed. The control electrode 113 of the first control transistor M1 is connected to the first clock signal line GCK1 through two vertically arranged second vias H6. The first electrode 111 of the first control transistor M1 is connected to the first doped region 110b of the active layer 110 through three parallel first vias K14, and is also connected to the control electrode 193 of the seventh control transistor M9 through second vias H4. The second electrode 112 of the first control transistor M1 is connected to the second doped region 110c of the active layer 110 through six first vias K15 arranged in a 2*3 array. The second electrode 113 of the first control transistor M1, the first electrode 121 of the second control transistor M2, and the second electrode 202 of the eighth control transistor M10 are integrated into one structure.

[0168] In the embodiments of this disclosure, "side-by-side arrangement" can mean arranged sequentially along the first direction X, and "vertical arrangement" can mean arranged sequentially along the second direction Y.

[0169] In some exemplary embodiments, the second control transistor M2 includes an active layer 120, a control electrode 123, a first electrode 121, and a second electrode 122. The active layer 120 includes a channel region 120a, a first doped region 120b, and a second doped region 120c. The active layer 120 of the second control transistor M2 is integral with the active layer 110 of the first control transistor M1, and the first doped region 120b of the active layer 120 is connected to the second doped region 110c of the active layer 110. The second electrode 122 of the second control transistor M2 is connected to the second doped region 120c of the active layer 120 through two vertically arranged first vias K13, and is also connected to the control electrode 183 of the sixth control transistor M8 through two vertically arranged second vias H3.

[0170] In some exemplary embodiments, the third control transistor M5 includes: an active layer 150, control electrodes 153a and 153b, a first electrode 151, and a second electrode 152. The active layer 150 includes: channel regions 150a1, 150a2, and 150a3, a first doped region 150b, and a second doped region 150c. The control electrodes 153a and 153b of the third control transistor M5 are integrally formed with the control electrode 223 of the second noise reduction control transistor M12. The control electrodes 153a and 153b of the third control transistor M5 are connected to the third clock signal line GCK3 through two vertically arranged second vias H5. The first electrode 151 of the third control transistor M5 is connected to the first doped region 150b of the active layer 150 through a first via K17. The first electrode 151 of the third control transistor M5 is integrally formed with the first power line PL1a. The second electrode 152 of the third control transistor M5 is connected to the second doped region 150c of the active layer 150 through a first via K16. The second electrode 152 of the third control transistor M5 and the second electrode 192 of the seventh control transistor M9 are integrated into one structure.

[0171] In some exemplary embodiments, the fourth control transistor M6 includes an active layer 160, a control electrode 163, a first electrode 161, and a second electrode 162. The active layer 160 includes a channel region 160a, a first doped region 160b, and a second doped region 160c. The active layer 160 of the fourth control transistor M6 and the active layer 170 of the fifth control transistor M7 are integrally formed, and the second doped region 160c of the active layer 160 is connected to the first doped region 170b of the active layer 170. The control electrode 163 of the fourth control transistor M6 is connected to the second electrode 192 of the seventh control transistor M9 through a second via H1. The control electrode 163 of the fourth control transistor M6, the control electrode 173 of the fifth control transistor M7, the control electrode 143 of the second output transistor M4, and the first electrode 302 of the second capacitor C2 can be integrally formed. The first electrode 161 of the fourth control transistor M6 is connected to the first doped region 160b of the active layer 160 through a first via K6. The first electrode 161 of the fourth control transistor M6, the first electrode 191 of the seventh control transistor M9, the first electrode 141 of the second output transistor M4, and the fourth power line PL2a are integrated into a single structure. The second electrode 162 of the fourth control transistor M6 is connected to the second doped region 160c of the active layer 160 through the first via K7. The second electrode 162 of the fourth control transistor M6, the first electrode 172 of the fifth control transistor M7, and the second electrode 182 of the sixth control transistor M8 are integrated into a single structure.

[0172] In some exemplary embodiments, the fifth control transistor M7 includes an active layer 170, a control electrode 173, a first electrode 171, and a second electrode 172. The active layer 170 includes a channel region 170a, a first doped region 170b, and a second doped region 170c. The second electrode 172 of the fifth control transistor M7 is connected to the second doped region 170c of the active layer 170 through a first via K8, and is also connected to the control electrode 183 of the sixth control transistor M6 through a second via H2.

[0173] In some exemplary embodiments, the sixth control transistor M8 includes an active layer 180, a control electrode 183, a first electrode 181, and a second electrode 182. The active layer 180 includes a channel region 180a, a first doped region 180b, and a second doped region 180c. The control electrode 183 of the sixth control transistor M8, the control electrodes 133a, 133b, and 133c of the first output transistor M3, and the first electrode 301 of the first capacitor C1 can be an integral structure. The first electrode 181 of the sixth control transistor M8 is connected to the first doped region 180b of the active layer 180 through a first via K12. The first electrode 181 of the sixth control transistor M8 is an integral structure with the first power line PL1a. The second electrode 182 of the sixth control transistor M8 is connected to the second doped region 180c of the active layer 180 through a first via K11.

[0174] In some exemplary embodiments, the seventh control transistor M9 includes an active layer 190, a control electrode 193, a first electrode 191, and a second electrode 192. The active layer 190 includes a channel region 190a, a first doped region 190b, and a second doped region 190c. The first electrode 191 of the seventh control transistor M9 is connected to the first doped region 190b of the active layer 190 through a first via K9, and the second electrode 192 is connected to the second doped region 190c of the active layer 190 through a first via K10. The control electrode 193 of the seventh control transistor M9 in any level shift register unit is integrated with the control electrodes 203a and 203b of the eighth control transistor M10 in the previous level shift register unit and the first connection electrode 501 of the previous level shift register unit. In this way, the first output signal output by the current level shift register unit is transmitted to the input terminal of the next level shift register unit. The first connection electrode 501 is connected to the second electrode 132 of the first output transistor M3 through two second vias H10 arranged side by side.

[0175] In some exemplary embodiments, the eighth control transistor M10 includes: an active layer 200, control electrodes 203a and 203b, a first electrode 201, and a second electrode 202. The active layer 200 includes: channel regions 200a1, 200a2, and 200a3, a first doped region 200b, and a second doped region 200c. The active layer 200 of the eighth control transistor M10 is integral with the active layer 110 of the first control transistor M1, and the second doped region 200c of the active layer 200 is connected to the second doped region 110c of the active layer 110. The control electrodes 203a and 203b of the eighth control transistor M10 are integral and can be connected to the sixth connection electrode 506 through a second via H11. The sixth connection electrode 506 can be connected to the first output terminal OUT1 through a third via D4. The first electrode 201 of the eighth control transistor M10 is connected to the first doped region 200b of the active layer 200 through the first via K18, and is also connected to the second connection electrode 502 through the second via H7. The second connection electrode 502 is connected to the first electrode 131 of the first output transistor M3 through the second via H8, and is also connected to the second clock signal line GCK2 through two vertically arranged second vias H9.

[0176] In some exemplary embodiments, the first output transistor M3 includes: active layers 130-1 and 130-2, control electrodes 133a, 133b and 133c, a first electrode 131 and a second electrode 132. Active layer 130-1 includes: channel regions 130-1a1, 130-1a2 and 130-1a3, a first doped region 130-1b, a second doped region 130-1c, a third doped region 130-1d and a fourth doped region 130-1e. Active layer 130-2 includes: channel regions 130-2a1, 130-2a2 and 130-2a3, a first doped region 130-2b, a second doped region 130-2c, a third doped region 130-2d and a fourth doped region 130-2e. The active layer 130-1 of the first output transistor M3 and the active layer 140-1 of the second output transistor M4 are integrally formed, and the fourth doped region 130-1e of the active layer 130-1 is connected to the second doped region 140-1c of the active layer 140-1. The active layer 130-2 of the first output transistor M3 and the active layer 140-2 of the second output transistor M4 are integrally formed, and the fourth doped region 130-2e of the active layer 130-2 is connected to the second doped region 140-2c of the active layer 140-1.

[0177] The first electrode 131 of the first output transistor M3 is connected to the first doped region 130-1b of the active layer 130-1 through a plurality of first vias K5 arranged side by side (e.g., seven first vias K5), to the first doped region 130-2b of the active layer 130-2 through a plurality of first vias K5 arranged side by side (e.g., seven first vias K5), to the third doped region 130-1d of the active layer 130-1 through a plurality of first vias K3 arranged side by side (e.g., seven first vias K3), to the third doped region 130-2d of the active layer 130-2 through a plurality of first vias K3 arranged side by side (e.g., seven first vias K3), and to the second connecting electrode 502 through a second via H8.

[0178] The second electrode 132 of the first output transistor M3 is connected to the second doped region 130-1c of the active layer 130-1 through a plurality of first vias K4 arranged side by side (e.g., seven first vias K4), to the second doped region 130-2c of the active layer 130-2 through a plurality of first vias K4 arranged side by side (e.g., seven first vias K4), and also to the fourth doped region 130-1e of the active layer 130-1 through a plurality of first vias K2 arranged side by side (e.g., seven first vias K2), and to the fourth doped region 130-2e of the active layer 130-2 through a plurality of first vias K2 arranged side by side (e.g., seven first vias K2). The second electrode 132 of the first output transistor M3 is also connected to the second electrode 302 of the second capacitor C2 through three third vias D2 arranged vertically, and to the first connection electrode 501 through two second vias H10 arranged side by side. The second electrode 132 of the first output transistor M3 and the second electrode 142 of the second output transistor M4 are integrated into one structure.

[0179] In some exemplary embodiments, the second output transistor M4 includes: active layers 140-1 and 140-2, a control electrode 143, a first electrode 141, and a second electrode 142. Active layer 140-1 includes: a channel region 140-1a, a first doped region 140-1b, and a second doped region 140-1c. Active layer 140-2 includes: a channel region 140-2a, a first doped region 140-2b, and a second doped region 140-2c. The first electrode 141 of the second output transistor M4 is connected to the first doped region 140-1b of active layer 140-1 through a plurality of first vias K1 arranged side-by-side (e.g., six first vias K1), and is also connected to the first doped region 140-2b of active layer 140-2 through a plurality of first vias K1 arranged side-by-side (e.g., six first vias K1).

[0180] In some exemplary embodiments, the first capacitor C1 includes a first electrode 301 and a second electrode 401. The first electrode 301 is integrally formed with the control electrodes 133a1, 133a2, and 133a3 of the first output transistor M3. The second electrode 401 is connected to the second electrode 132 of the first output transistor M3 through three vertically arranged third vias D2. The second capacitor C2 includes a first electrode 302 and a second electrode 402. The first electrode 302 is integrally formed with the control electrode 143 of the second output transistor M4. The second electrode 402 is connected to the fourth power line PL2a through a third via D1.

[0181] In some exemplary embodiments, the first noise reduction control transistor M11 includes: an active layer 210, control electrodes 213a and 213b, a first electrode 211, and a second electrode 212. The active layer 210 includes: channel regions 210a1, 210a2, and 210a3, a first doped region 210b, and a second doped region 210c. The active layer 210 of the first noise reduction control transistor M11 and the active layer 220 of the second noise reduction control transistor M12 are integrally formed, and the second doped region 210c of the active layer 210 is connected to the second doped region 220c of the active layer 220. The control electrodes 213a and 213b of the first noise reduction control transistor M11 and the control electrodes 243a and 243b of the fourth noise reduction control transistor M14 are integrally formed and connected to the fourth connection electrode 504 through a second via H16. The fourth connection electrode 504 can be connected to the first output terminal OUT1 through a third via D5. The first electrode 211 of the first noise reduction control transistor M11 is connected to the first doped region 210b of the active layer 210 through the first via K21. The second electrode 212 of the second noise reduction control transistor M11 is connected to the second doped region 210c of the active layer 210 through four first vias K20 arranged in a 2*2 array, and is also connected to the first electrode 303 of the third capacitor C3 through the second via H12. The first electrode 211 of the first noise reduction control transistor M11 and the first electrode 241 of the fourth noise reduction control transistor M14 are integrally formed. The second electrode 212 of the first noise reduction control transistor M11 and the second electrode 222 of the second noise reduction control transistor M12 are integrally formed.

[0182] In some exemplary embodiments, the second noise reduction control transistor M12 includes an active layer 220, a control electrode 223, a first electrode 221, and a second electrode 222. The active layer 220 includes a channel region 220a, a first doped region 220b, and a second doped region 220c. The first electrode 221 of the second noise reduction control transistor M12 is connected to the first doped region 220b of the active layer 220 through two side-by-side first vias K19.

[0183] In some exemplary embodiments, the third noise reduction control transistor M13 includes: an active layer 230, a control electrode 233, a first electrode 231, and a second electrode 232. The active layer 230 includes: a channel region 230a, a first doped region 230b, and a second doped region 230c. The control electrode of the third noise reduction control transistor M13 and the first electrode 303 of the third capacitor C3 are integrally formed. The first electrode 231 of the third noise reduction control transistor M13 is connected to the first doped region 230b of the active layer 230 through two side-by-side first vias K24, and is also connected to the first electrode 303 of the third capacitor C3 through two side-by-side second vias H13. The second electrode 232 of the third noise reduction control transistor M13 is connected to the second doped region 230c of the active layer 230 through two side-by-side first vias K25, and is also connected to the first electrode 304 of the fourth capacitor C4 through two side-by-side second vias H14.

[0184] In some exemplary embodiments, the fourth noise reduction control transistor M14 includes: an active layer 240, control electrodes 243a and 243b, a first electrode 241, and a second electrode 242. The active layer 240 includes: channel regions 240a1, 240a2, and 240a3, a first doped region 240b, and a second doped region 240c. The first electrode 241 of the fourth noise reduction control transistor M14 is connected to the first doped region 240b of the active layer 240 through a first via K22. The second electrode 242 of the fourth noise reduction control transistor M14 is connected to the second doped region 240c of the active layer 240 through a first via K23, and is also connected to the first electrode 304 of the fourth capacitor C4 through a second via H15.

[0185] In some exemplary embodiments, the third output transistor M15 includes: active layers 250-1 and 250-2, a control electrode 253, a first electrode 251, and a second electrode 252. Active layer 250-1 includes: a channel region 250-1a, a first doped region 250-1b, and a second doped region 250-1c. Active layer 250-2 includes: a channel region 250-2a, a first doped region 250-2b, and a second doped region 250-2c. The active layer 250-1 of the third output transistor M15 and the active layer 260-1 of the fourth output transistor M16 are integral structures, and the second doped region 250-1c of active layer 250-1 and the fourth doped region 260-1e of active layer 260-1 are connected. The active layer 250-2 of the third output transistor M15 and the active layer 260-2 of the fourth output transistor M16 are integrated into one structure, and the second doped region 250-2c and the fourth doped region 260-2e of the active layer 250-2 are connected. The control electrode 253 of the third output transistor M15 and the first electrode 303 of the fourth capacitor C4 are integrated into one structure.

[0186] The first electrode 251 of the third output transistor M15 is connected to the first doped region 250-1b of the active layer 250-1 through a plurality of first vias K30 arranged side by side (e.g., four first vias K30), and is also connected to the first doped region 250-2b of the active layer 250-2 through a plurality of first vias K30 arranged side by side (e.g., four first vias K30). The first electrode 251 of the third output transistor M15 and the third power line PL1b are integrally structured.

[0187] The second electrode 252 of the third output transistor M15 is connected to the second doped region 250-1c of the active layer 250-1 through a plurality of first vias K29 arranged side by side (e.g., four first vias K29), and is also connected to the second doped region 250-2c of the active layer 250-2 through a plurality of first vias K29 arranged side by side (e.g., four first vias K29). The second electrode 252 of the third output transistor M15 and the second electrode 262 of the fourth output transistor M16 are of a single integrated structure.

[0188] In some exemplary embodiments, the fourth output transistor M16 includes: active layers 260-1 and 260-2, control electrodes 263a, 263b and 263c, a first electrode 261 and a second electrode 262. Active layer 260-1 includes: channel regions 260-1a1, 260-1a2 and 260-1a3, a first doped region 260-1b, a second doped region 260-1c, a third doped region 260-1d, and a fourth doped region 260-1e. Active layer 260-2 includes: channel regions 260-2a1, 260-2a2 and 260-2a3, a first doped region 260-2b, a second doped region 260-2c, a third doped region 260-2d, and a fourth doped region 260-2e.

[0189] The control electrodes 263a, 263b, and 263c of the fourth output transistor M16 are integrated into a single structure and are connected to the fifth connection electrode 505 through two vertically arranged second vias H17. The fifth connection electrode 505 is connected to the sixth connection electrode 506 through the fourth via F2. The sixth connection electrode 506 is connected to the second electrode 172 of the fifth control transistor M7 through the fourth via F1.

[0190] The first electrode 261 of the fourth output transistor M16 is connected to the first doped region 260-1b of the active layer 260-1 through a plurality of first vias K26 arranged side-by-side (e.g., four first vias K26), to the first doped region 260-2b of the active layer 260-2 through a plurality of first vias K26 arranged side-by-side (e.g., four first vias K26), and to the third doped region 260-1d of the active layer 260-1 through a plurality of first vias K28 arranged side-by-side (e.g., four first vias K28), and to the third doped region 260-2d of the active layer 260-2 through a plurality of first vias K28 arranged side-by-side (e.g., four first vias K28). The first electrode 261 of the fourth output transistor M16 is also connected to the third connection electrode 503 through two third vias D8 arranged side-by-side. The third connection electrode 503 is connected to the fourth clock signal line GCB1 through two third vias D9 arranged vertically.

[0191] The second terminal 262 of the fourth output transistor M16 is connected to the second doped region 260-1c of the active layer 260-1 through a plurality of first vias K27 arranged side by side (e.g., four first vias K27), and to the second doped region 260-2c of the active layer 260-2 through a plurality of first vias K27 arranged side by side (e.g., four first vias K27). The second terminal 262 of the fourth output transistor M16 is connected to the second output terminal OUT2 through two third vias D10 arranged vertically.

[0192] In some exemplary embodiments, the third capacitor C3 includes a first electrode 303 and a second electrode 403. The first electrode 303 is connected to the first terminal 231 of the third noise reduction control transistor M13 and the second terminal 222 of the second noise reduction control transistor M12. The second electrode 403 is connected to the first clock signal line GCK1 through two vertically arranged third vias D6. The fourth capacitor C4 includes a first electrode 304 and a second electrode 404. The first electrode 304 is connected to the second terminal 232 of the third noise reduction control transistor M13 and the second terminal 242 of the fourth noise reduction control transistor M14. The second electrode 404 is connected to the third power line PL1b through two vertically arranged third vias D7.

[0193] In some exemplary implementations, such as Figures 5 to 7FAs shown, the control electrode 113 of the first control transistor M1 in the 6n+1th stage shift register unit can be connected to the first clock signal line GCK1 through the second via, and the second electrode 403 of the third capacitor C3 can be connected to the first clock signal line GCK1 through the third via; the control electrode of the third control transistor M5 and the control electrode of the second noise reduction control transistor M12 are integrated into one structure and can be connected to the third clock signal line GCK3 through the second via; the second connection electrode 502 is connected to the second clock signal line GCK2, and the second connection electrode 502 is connected to the first electrode 201 of the eighth control transistor M10 and the first electrode 131 of the first output transistor M3. The first electrode 261 of the fourth output transistor M16 is connected to the fourth clock signal line GCB1 through the third connection electrode 503.

[0194] In some exemplary implementations, such as Figures 5 to 7F As shown, the control electrode 113 of the first control transistor M1 in the 6n+2th stage shift register unit can be connected to the second clock signal line GCK2 through the second via, and the second electrode 403 of the third capacitor C3 can be connected to the second clock signal line GCK2 through the second via; the control electrode of the third control transistor M5 and the control electrode of the second noise reduction control transistor M12 are integrated into one structure and can be connected to the first clock signal line GCK1 through the second via; the second connection electrode 502 can be connected to the third clock signal line GCK3, and the second connection electrode 502 is connected to the first electrode 201 of the eighth control transistor M10 and the first electrode 131 of the first output transistor M3; the first electrode 261 of the fourth output transistor M16 is connected to the fifth clock signal line GCB2 through the third connection electrode 503.

[0195] In this exemplary embodiment, combined with Figure 4 The cascading relationship of the shift register units shown and Figures 5 to 7F The structure of the shift register shown determines the connection method between each shift register unit and the first and second sets of clock signal lines, so it will not be described in detail here.

[0196] The structure of a display substrate is illustrated below using an example of its fabrication process. The "patterning process" described in this disclosure includes depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping. Deposition can be performed using one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using one or more of spraying and spin coating; and etching can be performed using one or more of dry and wet etching. A "thin film" refers to a thin film of a material fabricated on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern."

[0197] The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the projection of A includes the projection of B" means that the boundary of the projection of B falls within the boundary range of the projection of A, or the boundary of the projection of A overlaps with the boundary of the projection of B.

[0198] The fabrication process of the display substrate in this exemplary embodiment includes the following steps.

[0199] (1) Provide a substrate.

[0200] In some exemplary embodiments, the substrate 60 may be a rigid substrate or a flexible substrate. A rigid substrate may include one or more of glass and metal foil. A flexible substrate may include one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.

[0201] (2) Forming the pattern of the first semiconductor layer.

[0202] In some exemplary embodiments, a first insulating film and a first semiconductor film are sequentially deposited on a substrate 60. The first semiconductor film is patterned using a patterning process to form a first insulating layer 61 covering the entire substrate 60, and a first semiconductor layer pattern disposed on the first insulating layer 61, such as... Figure 7AAs shown. The first semiconductor layer pattern includes at least an active layer for a plurality of transistors (e.g., transistors M1 to M16) in a shift register unit. The active layer may include at least one channel region and a plurality of doped regions. The channel region may be undoped and has semiconductor properties. The doped regions are doped with impurities and therefore have conductivity. The impurities may vary depending on the type of transistor (e.g., N-type or P-type). In some examples, the material of the first semiconductor thin film may be polycrystalline silicon.

[0203] (3) Form the pattern of the first conductive layer.

[0204] In some exemplary embodiments, a second insulating film and a first conductive film are sequentially deposited on the substrate 60 on which the aforementioned pattern is formed. The first conductive film is patterned using a patterning process to form a second insulating layer 62 covering the pattern of the first semiconductor layer, and a first conductive layer pattern disposed on the second insulating layer 62, such as... Figure 7B As shown. In some examples, the first conductive layer pattern may include: control electrodes of a plurality of transistors (e.g., transistors M1 to M16) of the shift register unit, first electrodes of a plurality of capacitors (e.g., first capacitor C1 to fourth capacitor C4) of the shift register unit, and a plurality of connection electrodes (e.g., first connection electrode 501 and second connection electrode 502).

[0205] (4) Forming the pattern of the second conductive layer.

[0206] In some exemplary embodiments, a third insulating film and a second conductive film are sequentially deposited on the substrate 60 on which the aforementioned pattern is formed. The second conductive film is patterned using a patterning process to form a third insulating layer 63 covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer 63, such as... Figure 7C As shown. In some examples, the second conductive layer pattern may include: second electrodes of multiple capacitors of the shift register unit (e.g., first capacitor C1 to fourth capacitor C4), a first output terminal OUT1, a second output terminal OUT2, and a connection electrode (e.g., a third connection electrode 503).

[0207] (5) Form the fourth insulating layer pattern.

[0208] In some exemplary embodiments, a fourth insulating film is deposited on the substrate 60 on which the aforementioned pattern is formed, and the fourth insulating film is patterned by a patterning process to form a pattern of a fourth insulating layer 64 covering the second conductive layer, such as... Figure 7DAs shown. In some examples, a plurality of vias are formed on the fourth insulating layer 64. The plurality of vias includes at least: a plurality of first vias K1 to K30, a plurality of second vias H1 to H17, and a plurality of third vias D1 to D10. The fourth insulating layer 64, the third insulating layer 63, and the second insulating layer 62 within the plurality of first vias K1 to K30 are etched away, exposing the surface of the first semiconductor layer. The fourth insulating layer 64 and the third insulating layer 63 within the plurality of second vias H1 to H17 are etched away, exposing the surface of the first conductive layer. The fourth insulating layer 64 within the plurality of third vias D1 to D10 is etched away, exposing the surface of the second conductive layer.

[0209] (6) Forming the pattern of the third conductive layer.

[0210] In some exemplary embodiments, a third conductive film is deposited on the substrate 60 on which the aforementioned pattern is formed, and the third conductive film is patterned by a patterning process to form a third conductive layer pattern on the fourth insulating layer 64, such as... Figure 7E As shown. In some examples, the third conductive layer pattern may include: first and second terminals of a plurality of transistors (e.g., transistors M1 to M16) of the shift register unit, a first set of clock signal lines (e.g., including first clock signal line GCK1, second clock signal line GCK2, and third clock signal line GCK3), a second set of clock signal lines (e.g., including fourth clock signal line GCB1 and fifth clock signal line GCB2), a plurality of power supply lines (e.g., first power supply line PL1a, fourth power supply line PL2a, third power supply line PL1b, and second power supply line PL2b), and connection electrodes (e.g., fourth connection electrode 504, fifth connection electrode 505, and sixth connection electrode 506).

[0211] (7) Form the patterns of the fifth and sixth insulating layers.

[0212] In some exemplary embodiments, a fifth insulating film 65 is deposited on the substrate 60 on which the aforementioned pattern is formed. Then, a sixth insulating film is coated, and a sixth insulating layer 66 pattern is formed by masking, exposing, and developing the sixth insulating film. Subsequently, a patterning process is performed on the fifth insulating film to form the fifth insulating layer 65 pattern. In some examples, a plurality of vias are formed on the sixth insulating layer 66. For example, the plurality of vias may include a plurality of fourth vias F1 to F3. The fifth insulating layer 65 and the sixth insulating layer 66 within the plurality of fourth vias F1 to F3 are etched away, exposing the surface of the third conductive layer.

[0213] (8) Form the pattern of the fourth conductive layer.

[0214] In some exemplary embodiments, a fourth conductive film is deposited on the substrate 60 on which the aforementioned pattern is formed, and the fourth conductive film is patterned by a patterning process to form a fourth conductive layer pattern on the sixth insulating layer 66, such as... Figure 7F As shown. In some examples, the fourth conductive layer pattern includes at least: connecting electrodes, for example, it may include: a seventh connecting electrode 507 and a third connecting line 703.

[0215] In some exemplary embodiments, pixel circuits can be formed in the display area while shift register units are formed in the non-display area. For example, the first semiconductor layer of the display area may include the active layer of the transistors of the pixel driving circuit, the first conductive layer of the display area may include the control electrode of the transistors of the pixel driving circuit and the first electrode of the storage capacitor, the second conductive layer of the display area may include at least the second electrode of the storage capacitor of the pixel driving circuit, the third conductive layer of the display area may include at least the first and second electrodes of the transistors of the pixel driving circuit, and the fourth conductive layer of the display area may include at least the connection electrode between the pixel driving circuit and the anode of the light-emitting element. After forming the first conductive layer, a second semiconductor layer can be formed in the display area, and an insulating layer is disposed between the second semiconductor layer and the first conductive layer. The material of the second semiconductor thin film can be a metal oxide, such as IGZO. However, this embodiment does not limit the location of the second semiconductor layer.

[0216] In some exemplary embodiments, after forming the fourth conductive layer, a pattern of a seventh insulating layer, an anode layer, a pixel definition layer, an organic light-emitting layer, a cathode layer, and an encapsulation layer can be sequentially formed in the display area. In some examples, a seventh insulating film is coated on a substrate with the aforementioned pattern, and a seventh insulating layer pattern is formed by masking, exposing, and developing the seventh insulating film. Subsequently, an anode film is deposited on the substrate of the display area with the aforementioned pattern, and the anode film is patterned using a patterning process to form an anode pattern on the seventh insulating layer. Then, a pixel definition film is coated on the substrate with the aforementioned pattern, and a pixel definition layer (PDL) pattern is formed using a masking, exposing, and developing process. The pixel definition layer is formed in each sub-pixel of the display area, and each sub-pixel has a pixel opening that exposes the anode. Subsequently, an organic light-emitting layer is formed within the aforementioned pixel opening, and the organic light-emitting layer is connected to the anode. Subsequently, a cathode film is deposited, and the cathode film is patterned using a patterning process to form a cathode pattern. The cathode is connected to the organic light-emitting layer and a second power line, respectively. Subsequently, an encapsulation layer is formed on the cathode, which may include a stacked structure of inorganic / organic / inorganic materials. In some possible implementations, the cathode can be connected to the second power line in various ways, such as laser drilling.

[0217] In some exemplary embodiments, the first, second, third, and fourth conductive layers can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo. The first insulating layer 61, second insulating layer 62, third insulating layer 63, fourth insulating layer 64, and fifth insulating layer 65 can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). They can be single-layer, multi-layer, or composite layers. The sixth insulating layer 66 and the seventh insulating layer can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The first insulating layer 61 can be referred to as a buffer layer, configured to improve the water and oxygen resistance of the substrate 60; the second insulating layer 62 and the third insulating layer 63 are referred to as gate insulating (GI) layers, the fourth insulating layer 64 is referred to as an interlayer insulating (ILD) layer, the fifth insulating layer 65 is referred to as a passivation (PVX) layer; the sixth insulating layer 66 and the seventh insulating layer are referred to as planarization layers. The pixel definition layer can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The anode can be made of transparent conductive materials such as indium tin oxide (ITO) or indium zinc oxide (IZO). The cathode can be made of any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or an alloy made of any one or more of the above metals. However, this embodiment is not limited in this respect. For example, the anode can be made of a reflective material such as a metal, and the cathode can be made of a transparent conductive material.

[0218] The structure and fabrication process shown in this exemplary embodiment are merely illustrative. In some exemplary embodiments, the corresponding structure and the patterning process can be modified and increased or decreased as needed. For example, the fourth conductive layer may be omitted. Furthermore, the order of multiple clock signal lines in the first group of clock signal lines may be changed, and the order of multiple clock signal lines in the second group of clock signal lines may be changed. However, this embodiment is not limited in this respect.

[0219] The preparation process of this exemplary embodiment can be realized using currently mature preparation equipment, is well compatible with existing preparation processes, is simple to implement, has high production efficiency, low production cost, and high yield.

[0220] The display substrate provided in this exemplary embodiment provides a clock signal line shared by the first output circuit and the second output circuit, and a first set of clock signal lines, a first power line and a second power line are provided between the first output circuit and the second output circuit. This can increase the layout density of the shift register unit, which is beneficial for achieving a narrow bezel. Moreover, it can reduce the load on the clock signal line, which is beneficial for improving the performance of the shift register unit.

[0221] In some exemplary embodiments, the gate drive circuit includes multiple cascaded shift register units. The first output of the (2k-1)th stage shift register unit is connected to the input of the (2k+1)th stage shift register unit, and the input of the first stage shift register unit is connected to the first initial signal line STVO. The first output of the 2kth stage shift register unit is connected to the input of the (2k+2)th stage shift register unit, and the input of the second stage shift register unit is connected to the second initial signal line STVE. Here, k is a positive integer.

[0222] In some exemplary embodiments, the first group of clock signal lines includes a first group of clock signal lines and a second group of clock signal lines, and the second group of clock signal lines includes a third group of clock signal lines and a fourth group of clock signal lines. The 2k-1 stage shift register unit is connected to the first group of clock signal lines and the third group of clock signal lines, and the 2k-stage shift register unit is connected to the second group of clock signal lines and the fourth group of clock signal lines.

[0223] In some exemplary embodiments, the first group of clock signal lines includes: a first clock signal line GCKO1, a second clock signal line GCKO2, and a third clock signal line GCKO3. The second group of clock signal lines includes: a sixth clock signal line GCKE1, a seventh clock signal line GCKE2, and an eighth clock signal line GCKE3. The third group of clock signal lines includes: a fourth clock signal line GCBO1 and a fifth clock signal line GCBO2. The fourth group of clock signal lines includes: a ninth clock signal line GCBE1 and a tenth clock signal line GCBE2.

[0224] In this exemplary embodiment, odd-numbered shift register units are cascaded sequentially and connected to the first and third group clock signal lines, while even-numbered shift register units are cascaded sequentially and connected to the second and fourth group clock signal lines. By increasing the number of clock signals and employing odd / even row driving, the gate drive circuit of this exemplary embodiment can increase the charging time, ensuring effective pixel charging and can be applied to high-frequency driving modes.

[0225] Figure 8 This is another schematic diagram of a gate drive circuit according to at least one embodiment of the present disclosure. In some exemplary embodiments, such as Figure 8As shown, the first clock terminal of the 12n+1th stage shift register unit is connected to the first clock signal line GCKO1, the second clock terminal is connected to the second clock signal line GCKO2, the third clock terminal is connected to the third clock signal line GCKO3, and the fourth clock terminal is connected to the fourth clock signal line GCBO1.

[0226] The first clock input of the 12n+3 level shift register unit is connected to the second clock signal line GCKO2, the second clock input is connected to the third clock signal line GCKO3, the third clock input is connected to the first clock signal line GCKO1, and the fourth clock input is connected to the fifth clock signal line GCBO2.

[0227] The first clock input of the 12n+5th stage shift register unit is connected to the third clock signal line GCKO3, the second clock input is connected to the first clock signal line GCKO1, the third clock input is connected to the second clock signal line GCKO2, and the fourth clock input is connected to the fourth clock signal line GCBO1.

[0228] The first clock input of the 12n+7th stage shift register unit is connected to the first clock signal line GCKO1, the second clock input is connected to the second clock signal line GCKO2, the third clock input is connected to the third clock signal line GCKO3, and the fourth clock input is connected to the fifth clock signal line GCBO2.

[0229] The first clock input of the 12n+9th stage shift register unit is connected to the second clock signal line GCKO2, the second clock input is connected to the third clock signal line GCKO3, the third clock input is connected to the first clock signal line GCKO1, and the fourth clock input is connected to the fourth clock signal line GCBO1.

[0230] The first clock input of the 12n+11th stage shift register unit is connected to the third clock signal line GCKO3, the second clock input is connected to the first clock signal line GCKO1, the third clock input is connected to the second clock signal line GCKO2, and the fourth clock input is connected to the fifth clock signal line GCBO2.

[0231] The first clock input of the 12n+2 level shift register unit is connected to the sixth clock signal line GCKE1, the second clock input is connected to the seventh clock signal line GCKE2, the third clock input is connected to the eighth clock signal line GCKE3, and the fourth clock input is connected to the ninth clock signal line GCBE1.

[0232] The first clock input of the 12n+4th stage shift register unit is connected to the seventh clock signal line GCKE2, the second clock input is connected to the eighth clock signal line GCKE3, the third clock input is connected to the sixth clock signal line GCKE1, and the fourth clock input is connected to the tenth clock signal line GCBE2.

[0233] The first clock input of the 12n+6th stage shift register unit is connected to the eighth clock signal line GCKE3, the second clock input is connected to the sixth clock signal line GCKE1, the third clock input is connected to the seventh clock signal line GCKE2, and the fourth clock input is connected to the ninth clock signal line GCBE1.

[0234] The first clock input of the 12n+8th stage shift register unit is connected to the sixth clock signal line GCKE1, the second clock input is connected to the seventh clock signal line GCKE2, the third clock input is connected to the eighth clock signal line GCKE3, and the fourth clock input is connected to the tenth clock signal line GCBE2.

[0235] The first clock input of the 12n+10th stage shift register unit is connected to the seventh clock signal line GCKE2, the second clock input is connected to the eighth clock signal line GCKE3, the third clock input is connected to the sixth clock signal line GCKE1, and the fourth clock input is connected to the ninth clock signal line GCBE1.

[0236] The first clock input of the 12n+12th stage shift register unit is connected to the eighth clock signal line GCKE3, the second clock input is connected to the sixth clock signal line GCKE1, the third clock input is connected to the seventh clock signal line GCKE2, and the fourth clock input is connected to the tenth clock signal line GCBE2. Here, n is a natural number.

[0237] In this embodiment, the 12 shift register units of the gate drive circuit can be used as a minimum periodic repetition unit to drive 12 rows of sub-pixels.

[0238] Figure 9 This is a timing diagram of a clock signal according to at least one embodiment of the present disclosure. Figure 9 As shown, the first clock signal provided by the first clock signal line GCKO1, the second clock signal provided by the second clock signal line GCKO2, the third clock signal provided by the third clock signal line GCKO3, the fourth clock signal provided by the fourth clock signal line GCBO1, the fifth clock signal provided by the fifth clock signal line GCBO2, the sixth clock signal provided by the sixth clock signal line GCKE1, the seventh clock signal provided by the seventh clock signal line GCKE2, the eighth clock signal provided by the eighth clock signal line GCKE3, the ninth clock signal provided by the ninth clock signal line GCBE1, and the tenth clock signal provided by the tenth clock signal line GCBE2 ​​are all pulse signals.

[0239] In some exemplary implementations, such as Figure 9As shown, the duty cycles of the first, second, third, sixth, seventh, and eighth clock signals can be the same. The second clock signal is delayed by a first predetermined duration (e.g., 2H) compared to the first clock signal, and the third clock signal is delayed by a first predetermined duration (e.g., 2H) compared to the second clock signal line, so that the first, second, and third clock signals are not simultaneously at a low voltage. The seventh clock signal is delayed by a first predetermined duration (e.g., 2H) compared to the sixth clock signal, and the eighth clock signal is delayed by a first predetermined duration (e.g., 2H) compared to the seventh clock signal line, so that the sixth, seventh, and eighth clock signals are not simultaneously at a low voltage. The sixth clock signal is delayed by a second predetermined duration (e.g., 1H) compared to the first clock signal, the seventh clock signal is delayed by a second predetermined duration (e.g., 1H) compared to the second clock signal, and the eighth clock signal is delayed by a second predetermined duration (e.g., 1H) compared to the third clock signal.

[0240] In some exemplary implementations, such as Figure 9 As shown, the second initial signal provided by the second initial signal line STVE is delayed by 1H compared to the first initial signal provided by the first initial signal line STVO.

[0241] In some exemplary implementations, such as Figure 9 As shown, the duty cycles of the fourth, fifth, ninth, and tenth clock signals can be the same. The duty cycle of the fourth clock signal can be less than the duty cycle of the first clock signal. The fourth and fifth clock signals are not simultaneously high voltage, and the ninth and tenth clock signals are not simultaneously high voltage. The ninth clock signal is delayed by a second set duration (e.g., 1 hour) compared to the fourth clock signal, and the tenth clock signal is delayed by a second set duration (e.g., 1 hour) compared to the fifth clock signal.

[0242] In some exemplary embodiments, Figure 8 The timing sequence of the first-stage shift register unit can include a first stage OS1, a second stage OS2, a third stage OS3, and a fourth stage OS4. The operation of the second-stage shift register unit can include a first stage ES1, a second stage ES2, a third stage ES3, and a fourth stage ES4. The operation of these four stages can be found in the description of the shift register unit's operation in the aforementioned embodiment, and will not be repeated here.

[0243] Figure 10 This is another top view of a shift register unit according to at least one embodiment of the present disclosure. Figure 10 The diagram uses the 12n+1 and 12n+2 level shift register units (e.g., n=1) as examples. The following explanation mainly focuses on the structure of the 12n+1 level shift register unit.

[0244] Figure 11A This is a top view of a shift register unit after the formation of the first semiconductor layer, according to at least one embodiment of the present disclosure. Figure 11B This is another top view of a shift register unit after the formation of the first conductive layer, according to at least one embodiment of this disclosure. Figure 11C This is another top view of a shift register unit after the formation of the second conductive layer, according to at least one embodiment of this disclosure. Figure 11D This is another top view of a shift register unit after the formation of the third conductive layer, which is at least one embodiment of this disclosure. Figure 11E This is another top view of the shift register unit after the formation of the fourth conductive layer, which is at least one embodiment of this disclosure.

[0245] In some exemplary implementations, such as Figure 10 As shown, in a plane parallel to the display substrate, in the first direction X, the second initial signal line STVE is located between the first initial signal line STVO and the fourth power line PL2a. The first group of clock signal lines is located between the first power line PL1a and the second power line PL2b, and the third power line PL1b is located between the second power line PL2b and the second group of clock signal lines. The first group of clock signal lines includes a first group of clock signal lines and a second group of clock signal lines. The first group of clock signal lines and the second group of clock signal lines are arranged at intervals in the first direction X. In this example, the first group of clock signal lines includes: a first clock signal line GCKO1, a second clock signal line GCKO2, and a third clock signal line GCKO3. The second group of clock signal lines includes: a sixth clock signal line GCKE1, a seventh clock signal line GCKE2, and an eighth clock signal line GCKE3. In the first direction D1 from the first power line PL1a to the second power line PL2b, the first clock signal line GCKO1, the sixth clock signal line GCKE1, the second clock signal line GCKO2, the seventh clock signal line GCKE2, the third clock signal line GCKO3, and the eighth clock signal line GCKE3 are arranged sequentially. The second group of clock signal lines includes the third group of clock signal lines and the fourth group of clock signal lines. The third group of clock signal lines includes the fourth clock signal line GCBO1 and the fifth clock signal line GCBO2, and the fourth group of clock signal lines includes the ninth clock signal line GCBE1 and the tenth clock signal line GCBE2. In the first direction D1 away from the second output circuit, the fourth clock signal line GCBO1, the ninth clock signal line GCBE1, the fifth clock signal line GCBO2, and the tenth clock signal line GCBE2 ​​are arranged sequentially. However, this embodiment is not limited to this. In some examples, the first group of clock signal lines and the second group of clock signal lines can be arranged sequentially along the first direction, and the third group of clock signal lines and the fourth group of clock signal lines can be arranged sequentially along the first direction.

[0246] In some exemplary implementations, such as Figure 11B As shown, the first conductive layer in the non-display area includes at least: control electrodes of multiple transistors (e.g., transistors M1 to M16) of the shift register unit, and first electrodes of multiple capacitors (e.g., first capacitor C1 to fourth capacitor C4). The control electrodes 203a and 203b of the eighth control transistor M10 of any level shift register unit can be an integral structure with the first connection electrode 501, and are not connected to the control electrode 193 of the seventh control transistor M9 of the next level shift register unit.

[0247] In some exemplary implementations, such as Figure 11D As shown, the third conductive layer in the non-display area may include: the first and second electrodes of multiple transistors (e.g., transistors M1 to M16) of the shift register unit, a first set of clock signal lines, a second set of clock signal lines, multiple power supply lines, and connection electrodes (e.g., the eighth connection electrode 508 and the ninth connection electrode 509). For example, the control electrode 193 of the seventh control transistor M9 of the 12n+1 stage shift register unit can be connected to the eighth connection electrode 508 through two vertically arranged second vias H18, so as to be connected to the first output terminal OUT1 of the 12n-1 stage shift register unit through the eighth connection electrode 508. The first output terminal OUT1 of the 12n+1 stage shift register unit can be connected to another eighth connection electrode 508 through a third via D11, so as to be connected to the control electrode 193 of the seventh control transistor M9 of the 12n+3 stage shift register unit through the eighth connection electrode 508, providing an input signal to the 12n+3 stage shift register unit. The control electrode 193 of the seventh control transistor M9 of the 12n+2th stage shift register unit can be connected to the ninth connection electrode 509 through two vertically arranged second vias H19, so as to be connected to the first output terminal OUT1 of the 12nth stage shift register unit through the ninth connection electrode 509.

[0248] In some exemplary implementations, such as Figures 10 to 11E As shown, the control electrodes of the third control transistor M5 and the second noise reduction control transistor M12 in the 12n+1th stage shift register unit can be a single structure, connected to the third clock signal line GCKO3 via a second via. The second electrode of the third capacitor C3 is connected to the first clock signal line GCKO1 via a third via. The control electrode of the first control transistor M1 is connected to the first clock signal line GCKO1 via a second via. The second connection electrode connected to the first electrode of the eighth control transistor M10 can be connected to the second clock signal line GCKO2 via a second via. The second connection electrode is also connected to the first electrode of the first output transistor M3 via a second via. The first electrode of the fourth output transistor M16 is connected to the fourth clock signal line GCBO1 via a third connection electrode.

[0249] In some exemplary implementations, such as Figures 10 to 11E As shown, the control electrodes of the third control transistor M5 and the second noise reduction control transistor M12 in the 12n+2 stage shift register unit can be integrated into one structure and connected to the eighth clock signal line GCKE3 through the second via. The second electrode of the third capacitor C3 is connected to the sixth clock signal line GCKE1 through the third via. The control electrode of the first control transistor M1 is connected to the sixth clock signal line GCKE1 through the second via. The second connection electrode connected to the first electrode of the eighth control transistor M10 can be connected to the seventh clock signal line GCKE2 through the second via. The second connection electrode is also connected to the first electrode of the first output transistor M3 through the second via. The first electrode of the fourth output transistor M16 is connected to the ninth clock signal line GCBE1 through the third connection electrode.

[0250] The cascading relationship of the shift register units in this embodiment can be referred to... Figure 8 As shown, the remaining structure of the display substrate in this embodiment can be referred to the description of the foregoing embodiment, and therefore will not be repeated here.

[0251] This disclosure also provides a method for fabricating a display substrate, used to fabricate the display substrate as described above. The fabrication method of this embodiment includes: providing a substrate; forming a gate driving circuit in a non-display area. The gate driving circuit includes: a plurality of cascaded shift register units; each shift register unit is connected to at least one power supply line. Each shift register unit includes: a first output circuit and a second output circuit; the first output circuit is connected to a first set of clock signal lines, and the second output circuit is connected to both the first and second set of clock signal lines. In a first direction, the first set of clock signal lines and at least one power supply line are located between the first and second output circuits, and the second set of clock signal lines are located on the side of the second output circuit away from the first set of clock signal lines.

[0252] The method for preparing the display substrate in this embodiment can be referred to the description of the foregoing embodiment, and therefore will not be repeated here.

[0253] Figure 12 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Figure 12As shown, this embodiment provides a display device 91, including a display substrate 910. The display substrate 910 is the display substrate provided in the aforementioned embodiment. The display substrate 910 can be an OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device 91 can be any product or component with display function, such as an OLED display device, a watch, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator. However, this embodiment is not limited to this.

[0254] The accompanying drawings in this disclosure only illustrate the structures involved in this disclosure; other structures can be referred to with common design. Unless otherwise specified, the embodiments and features described in these embodiments can be combined to obtain new embodiments. Those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of this disclosure without departing from the spirit and scope of this disclosure, and all such modifications and substitutions should be covered within the scope of the claims of this disclosure.

Claims

1. A display substrate, comprising: The display area and the non-display area are provided with a gate driving circuit, which includes a plurality of cascaded shift register units; the shift register units are connected to at least one power supply line. The shift register unit includes: a first output circuit and a second output circuit; the first output circuit is connected to a first group of clock signal lines, and the second output circuit is connected to the first group of clock signal lines and the second group of clock signal lines. In a first direction, the first set of clock signal lines and at least one power line are located between the first output circuit and the second output circuit, and the second set of clock signal lines are located on the side of the second output circuit away from the first set of clock signal lines. The first output circuit includes: a first node control sub-circuit, a second node control sub-circuit, and a first output sub-circuit; The first node control sub-circuit is connected to the input terminal, the first output terminal, the first clock terminal, the second clock terminal, the third clock terminal, the first power supply terminal, the second power supply terminal, the first node, and the second node, and is configured to control the potential of the first node and the second node under the control of the first clock terminal, the third clock terminal, and the input terminal; The second node control sub-circuit is connected to the first node, the second node, the second power supply terminal and the first output terminal, and is configured to maintain the potential of the first node and the second node; The first output sub-circuit is connected to the first node, the second node, the second clock terminal, the second power supply terminal and the first output terminal, and is configured to control the first output terminal to output a first output signal under the control of the first node and the second node; The second node control sub-circuit, the first output sub-circuit, and the first node control sub-circuit are arranged sequentially along the first direction.

2. The display substrate according to claim 1, wherein, The at least one power line includes: a first power line and a second power line, wherein the first power line is connected to the first output circuit and the second power line is connected to the second output circuit; In the first direction, the first power line is located between the first output circuit and the first set of clock signal lines, and the second power line is located between the first set of clock signal lines and the second output circuit.

3. The display substrate according to claim 2, wherein, The non-display area is also provided with a third power line and a fourth power line; The third power line is connected to the second output circuit, and the fourth power line is connected to the first output circuit; In the first direction, the fourth power line is located on the side of the first output circuit away from the first power line, and the third power line is located between the second power line and the second set of clock signal lines.

4. The display substrate according to claim 3, wherein, The non-display area is also provided with an initial signal line, which is located on the side of the fourth power line away from the first output circuit in the first direction.

5. The display substrate according to claim 1, wherein, The first node control sub-circuit includes: a first control transistor, a second control transistor, a third control transistor, a fourth control transistor, a fifth control transistor, a sixth control transistor, a seventh control transistor, and an eighth control transistor; The control electrode of the first control transistor is connected to the first clock terminal, the first electrode is connected to the input terminal, and the second electrode is connected to the fourth node. The control electrode of the second control transistor is connected to the first clock terminal, the first electrode is connected to the fourth node, and the second electrode is connected to the first node; The control electrode of the third control transistor is connected to the third clock terminal, the first electrode is connected to the first power supply terminal, and the second electrode is connected to the second node; The control electrode of the fourth control transistor is connected to the second node, the first electrode is connected to the second power supply terminal, and the second electrode is connected to the third node. The control electrode of the fifth control transistor is connected to the second node, the first electrode is connected to the third node, and the second electrode is connected to the first node; The control electrode of the sixth control transistor is connected to the first node, the first electrode is connected to the first power supply terminal, and the second electrode is connected to the third node; The control electrode of the seventh control transistor is connected to the input terminal, the first electrode is connected to the second power supply terminal, and the second electrode is connected to the second node; The control electrode of the eighth control transistor is connected to the first output terminal, the first electrode is connected to the second clock terminal, and the second electrode is connected to the fourth node. The second node control sub-circuit includes: a first capacitor and a second capacitor; the first electrode of the first capacitor is connected to the first node, and the second electrode is connected to the first output terminal; the first electrode of the second capacitor is connected to the second node, and the second electrode is connected to the second power supply terminal. The first output sub-circuit includes: a first output transistor and a second output transistor; the control electrode of the first output transistor is connected to a first node, the first electrode is connected to a second clock terminal, and the second electrode is connected to a first output terminal; the control electrode of the second output transistor is connected to a second node, the first electrode is connected to a second power supply terminal, and the second electrode is connected to a first output terminal.

6. The display substrate according to claim 5, wherein, The first capacitor and the first output transistor are adjacent in the first direction, and the second capacitor and the second output transistor are adjacent in the first direction; the first capacitor and the second capacitor are adjacent in the second direction, and the first output transistor and the second output transistor are adjacent in the second direction. The second direction intersects with the first direction.

7. The display substrate according to claim 5, wherein, The active layers of the first control transistor, the second control transistor, and the eighth control transistor are integral structures; the active layers of the fourth control transistor and the fifth control transistor are integral structures; and the active layers of the first output transistor and the second output transistor are integral structures.

8. The display substrate according to claim 7, wherein, In the first direction, the active layer of the sixth control transistor is located between the active layers of the fifth control transistor and the second control transistor, and the active layer of the seventh control transistor is located between the active layers of the fourth control transistor and the third control transistor.

9. The display substrate according to any one of claims 1 to 8, wherein, The second output circuit includes: a noise reduction control sub-circuit, a second output sub-circuit, and a third output sub-circuit; The noise reduction control sub-circuit is connected to a first output terminal, a first clock terminal, a third clock terminal, a first power supply terminal, a second power supply terminal, and a first noise reduction control node. It is configured to rectify the charge of the first power supply terminal to the first noise reduction control node under the control of the third clock signal terminal, so that the first noise reduction control node is maintained at a voltage that turns on the second output sub-circuit, and to transmit the signal of the second power supply terminal to the first noise reduction control node under the control of the first output terminal, so that the first noise reduction control node is maintained at a voltage that turns off the second output sub-circuit. The second output sub-circuit is connected to the first noise reduction control node, the second output terminal and the first power supply terminal, and is configured to transmit the signal from the first power supply terminal to the second output terminal under the control of the first noise reduction control node. The third output sub-circuit is connected to the first node, the fourth clock terminal, and the second output terminal, and is configured to transmit the signal of the fourth clock terminal to the second output terminal under the control of the first node. In the second direction, the second output sub-circuit and the third output sub-circuit are adjacent to each other; In the first direction, the noise reduction control sub-circuit is located between the first set of clock signal lines and the second output sub-circuit, and the second direction intersects the first direction.

10. The display substrate according to claim 9, wherein, The noise reduction control sub-circuit includes: a first noise reduction control transistor, a second noise reduction control transistor, a third noise reduction control transistor, a fourth noise reduction control transistor, a third capacitor, and a fourth capacitor; The control electrode of the first noise reduction control transistor is connected to the first output terminal, the first electrode is connected to the second power supply terminal, and the second electrode is connected to the second noise reduction control node; The control electrode of the second noise reduction control transistor is connected to the third clock terminal, the first electrode is connected to the first power supply terminal, and the second electrode is connected to the second noise reduction control node. The control electrode and the first electrode of the third noise reduction control transistor are connected to the second noise reduction control node, and the second electrode is connected to the first noise reduction node. The control electrode of the fourth noise reduction control transistor is connected to the first output terminal, the first electrode is connected to the second power supply terminal, and the second electrode is connected to the first noise reduction control node. The first electrode of the third capacitor is connected to the second noise reduction control node, and the second electrode is connected to the first clock terminal. The first electrode of the fourth capacitor is connected to the first noise reduction control node, and the second electrode is connected to the first power supply terminal. The second output sub-circuit includes: a third output transistor; The control electrode of the third output transistor is connected to the first noise reduction control node, the first electrode is connected to the first power supply terminal, and the second electrode is connected to the second output terminal. The third output sub-circuit includes: a fourth output transistor; The control electrode of the fourth output transistor is connected to the first node, the first electrode is connected to the fourth clock terminal, and the second electrode is connected to the second output terminal.

11. The display substrate according to claim 10, wherein, The third output transistor and the fourth output transistor are adjacent in the second direction, and the first noise reduction control transistor and the second noise reduction control transistor are adjacent in the second direction. In the first direction, the third capacitor is located between the second noise control transistor and the third noise control transistor, and the fourth noise control transistor is located between the first noise control transistor and the fourth capacitor.

12. The display substrate according to claim 10, wherein, The active layers of the first and second noise reduction control transistors are integral structures, and the active layers of the third and fourth output transistors are integral structures.

13. The display substrate according to any one of claims 1 to 8, wherein, The first group of clock signal lines includes: a first clock signal line, a second clock signal line, and a third clock signal line; The second group of clock signal lines includes: a fourth clock signal line and a fifth clock signal line; The first clock signal provided by the first clock signal line, the second clock signal provided by the second clock signal line, and the third clock signal provided by the third clock signal line have the same duty cycle. The fourth clock signal provided by the fourth clock signal line and the fifth clock signal provided by the fifth clock signal line have the same duty cycle, and the duty cycle of the fourth clock signal is less than that of the first clock signal. The second clock signal is delayed by a set time compared to the first clock signal, and the third clock signal is delayed by a set time compared to the second clock signal, so that the first clock signal, the second clock signal, and the third clock signal are not simultaneously the first voltage; the fourth clock signal and the fifth clock signal are not simultaneously the second voltage; and the first voltage is different from the second voltage.

14. The display substrate according to claim 13, wherein, In the first direction, the first clock signal line, the second clock signal line, and the third clock signal line are arranged sequentially in a direction away from the first output circuit, and the fourth clock signal line and the fifth clock signal line are arranged sequentially in a direction away from the second output circuit.

15. The display substrate according to claim 13, wherein, The first output circuit of any level shift register unit is connected to the first clock signal line, the second clock signal line, and the third clock signal line, and the second output circuit is connected to two clock signal lines in the first group of clock signal lines and one clock signal line in the second group of clock signal lines.

16. The display substrate according to claim 15, wherein, The first clock terminal of the 6n+1th stage shift register unit is connected to the first clock signal line, the second clock terminal is connected to the second clock signal line, the third clock terminal is connected to the third clock signal line, and the fourth clock terminal is connected to the fourth clock signal line. The first clock input of the 6n+2 level shift register unit is connected to the second clock signal line, the second clock input is connected to the third clock signal line, the third clock input is connected to the first clock signal line, and the fourth clock input is connected to the fifth clock signal line. The first clock input of the 6n+3 level shift register unit is connected to the third clock signal line, the second clock input is connected to the first clock signal line, the third clock input is connected to the second clock signal line, and the fourth clock input is connected to the fourth clock signal line. The first clock input of the 6n+4th stage shift register unit is connected to the first clock signal line, the second clock input is connected to the second clock signal line, the third clock input is connected to the third clock signal line, and the fourth clock input is connected to the fifth clock signal line. The first clock input of the 6n+5th stage shift register unit is connected to the second clock signal line, the second clock input is connected to the third clock signal line, the third clock input is connected to the first clock signal line, and the fourth clock input is connected to the fourth clock signal line. The first clock input of the 6n+6th stage shift register unit is connected to the third clock signal line, the second clock input is connected to the first clock signal line, the third clock input is connected to the second clock signal line, and the fourth clock input is connected to the fifth clock signal line. Where n is a natural number.

17. The display substrate according to any one of claims 1 to 8, wherein, The first output of the 2k-1 stage shift register unit is connected to the input of the 2k+1 stage shift register unit, and the input of the first stage shift register unit is connected to the first initial signal line. The first output of the 2k-th stage shift register unit is connected to the input of the 2k+2-th stage shift register unit, and the input of the second stage shift register unit is connected to the second initial signal line, where k is a positive integer; The first group of clock signal lines includes: a first group of clock signal lines and a second group of clock signal lines; the second group of clock signal lines includes: a third group of clock signal lines and a fourth group of clock signal lines. The 2k-1 level shift register unit is connected to the first group clock signal line and the third group clock signal line, and the 2k level shift register unit is connected to the second group clock signal line and the fourth group clock signal line.

18. The display substrate according to claim 17, wherein, In the first direction, the first group clock signal line and the second group clock signal line are arranged at intervals, and the third group clock signal line and the fourth group clock signal line are arranged at intervals.

19. The display substrate according to claim 17, wherein, The first group clock signal line includes: a first clock signal line, a second clock signal line, and a third clock signal line; The second group clock signal line includes: a sixth clock signal line, a seventh clock signal line, and an eighth clock signal line; The third group clock signal line includes: a fourth clock signal line and a fifth clock signal line; The fourth group clock signal line includes: the ninth clock signal line and the tenth clock signal line; The first clock signal provided by the first clock signal line, the second clock signal provided by the second clock signal line, the third clock signal provided by the third clock signal line, the sixth clock signal provided by the sixth clock signal line, the seventh clock signal provided by the seventh clock signal line, and the eighth clock signal provided by the eighth clock signal line all have the same duty cycle; the second clock signal is delayed by a first set time compared to the first clock signal, and the third clock signal is delayed by a first set time compared to the second clock signal, so that the first, second, and third clock signals are not simultaneously used as the first voltage; the seventh clock signal is delayed by a first set time compared to the sixth clock signal, and the eighth clock signal is delayed by a first set time compared to the seventh clock signal, so that the sixth, seventh, and eighth clock signals are not simultaneously used as the first voltage; the sixth clock signal is delayed by a second set time compared to the first clock signal, the seventh clock signal is delayed by a second set time compared to the second clock signal, and the eighth clock signal is delayed by a second set time compared to the third clock signal; The fourth clock signal provided by the fourth clock signal line, the fifth clock signal provided by the fifth clock signal line, the ninth clock signal provided by the ninth clock signal line, and the tenth clock signal provided by the tenth clock signal line have the same duty cycle; the duty cycle of the fourth clock signal is less than that of the first clock signal; the fourth clock signal and the fifth clock signal are not simultaneously the second voltage, the ninth clock signal and the tenth clock signal are not simultaneously the second voltage, and the second voltage is different from the first voltage; the ninth clock signal is delayed by a second set time compared to the fourth clock signal, and the tenth clock signal is delayed by a second set time compared to the fifth clock signal.

20. The display substrate according to any one of claims 1 to 8, wherein, In a direction perpendicular to the display substrate, the non-display area of ​​the display substrate includes: a substrate and a first semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer disposed on the substrate. The first semiconductor layer includes at least: an active layer of a plurality of transistors in the shift register unit; The first conductive layer includes at least: the control electrodes of a plurality of transistors in the shift register unit, and the first electrodes of a plurality of capacitors; The second conductive layer includes at least the second electrodes of the plurality of capacitors in the shift register unit; The third conductive layer includes at least: the first and second terminals of multiple transistors in the shift register unit, a first set of clock signal lines, a second set of clock signal lines, and multiple power supply lines; The fourth conductive layer includes at least: a connection electrode for a third output sub-circuit that connects the first node and the second output circuit.

21. A display device comprising a display substrate as claimed in any one of claims 1 to 20.

22. A method for preparing a display substrate, used to prepare a display substrate as described in any one of claims 1 to 20, the method comprising: Provide a substrate; A gate drive circuit is formed in the non-display area; The gate driving circuit includes: a plurality of cascaded shift register units; each shift register unit is connected to at least one power supply line; each shift register unit includes: a first output circuit and a second output circuit; the first output circuit is connected to a first set of clock signal lines, and the second output circuit is connected to both the first set of clock signal lines and the second set of clock signal lines; in a first direction, the first set of clock signal lines and at least one power supply line are located between the first output circuit and the second output circuit, and the second set of clock signal lines are located on the side of the second output circuit away from the first set of clock signal lines.

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