Stacked memory and storage systems

Abstract

This application discloses a stacked memory and storage system, relating to the field of memory, for preventing degradation of power integrity and signal integrity of the stacked memory without increasing the number of dies. The stacked memory includes stacked volatile memory dies and non-volatile memory dies; wherein, the non-volatile memory die includes a non-volatile memory array and peripheral circuitry, the peripheral circuitry including power integrity circuitry and signal integrity circuitry; the power integrity circuitry is used to optimize the power supply obtained from the lower diery layer before transmitting it to the upper diery layer; the signal integrity circuitry is used to optimize the signal obtained from the lower diery layer before transmitting it to the upper diery layer.

Description

Technical Field

[0001] This application relates to the field of memory, and more particularly to a stacked memory and a storage system. Background Technology

[0002] To increase the storage space of a single memory module, multiple memory dies can be stacked to form a stacked memory. The number of memory dies stacked in a stacked memory is increasing, but due to space constraints within the installed electronic device, the thickness of each memory die layer is becoming increasingly thinner, leading to a decrease in overall memory reliability. At high stack counts, parasitic capacitance and resistance can cause a decrease in power integrity and signal integrity in the upper memory dies. In existing technologies, circuitry for improving power integrity and signal integrity occupies the space of a separate die layer. This increases the overall height of the stacked memory while keeping the thickness of each die layer constant, and conversely, reduces the thickness of each die layer while keeping the overall height constant, further contributing to the decrease in reliability. Summary of the Invention

[0003] This application provides a stacked memory and storage system to prevent degradation of the power integrity and signal integrity of the stacked memory without increasing the number of dies.

[0004] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0005] In a first aspect, a stacked memory is provided, comprising stacked volatile memory dies, non-volatile memory dies, and control dies; wherein the non-volatile memory die includes a non-volatile memory array and peripheral circuitry, the peripheral circuitry including a power integrity circuit and a signal integrity circuit; the power integrity circuitry is used to perform power integrity optimization on power received from the lower die before transmitting it to the upper die; the power integrity optimization includes at least one of filtering voltage noise and reducing IR drop; the signal integrity circuitry is used to perform signal integrity optimization on signals received from the lower die before transmitting them to the upper die; the signal integrity optimization includes at least one of reducing common-mode noise and impedance matching.

[0006] The stacked memory provided in this application includes stacked volatile memory dies and non-volatile memory dies. Each non-volatile memory die includes a non-volatile memory array and peripheral circuitry. The peripheral circuitry includes power integrity circuitry and signal integrity circuitry. The power integrity circuitry optimizes the power received from the lower-layer die before transmitting it to the upper-layer die; the signal integrity circuitry optimizes the signal received from the lower-layer die before transmitting it to the upper-layer die. The non-volatile memory array can be used to store data, and the peripheral circuitry can improve the power integrity and signal integrity between the bottom and top dies of the stacked memory. Since the peripheral circuitry does not occupy a separate layer of dies, it prevents a decrease in the power integrity and signal integrity of the stacked memory without increasing the number of dies.

[0007] In one possible implementation, the stacked memory further includes a control die, which is used to: control peripheral circuitry to store data from the volatile memory die to a non-volatile memory die; or, control peripheral circuitry to store data from the non-volatile memory die to the volatile memory die. The control die storing data from the volatile memory die to the non-volatile memory die enables data backup; the control die storing data from the non-volatile memory die to the volatile memory die enables data recovery. This not only improves the reliability of data storage but also reduces energy consumption during data backup and recovery by implementing data backup and recovery internally, eliminating the need for inter-chip data transfer.

[0008] In one possible implementation, the control die is specifically used to: when a power outage is detected, control the peripheral circuitry to store data from the volatile memory die to the non-volatile memory die; and when a power outage is detected, control the peripheral circuitry to store data from the non-volatile memory die to the volatile memory die. This stacked memory can be used for power-down data backup.

[0009] In one possible implementation, the data is checkpoint data, and the control die is specifically used to: upon receiving a checkpoint data backup command or when the backup cycle is reached, control the peripheral circuitry to store the data from the volatile memory die to the non-volatile memory die; and upon receiving a checkpoint data recovery command, control the peripheral circuitry to store the data from the non-volatile memory die to the volatile memory die. That is, this stacked memory can be used for checkpoint data backup.

[0010] In one possible implementation, upon receiving a checkpoint data backup command or when the backup cycle is reached, the control of the die specifically involves: if the free storage resources in the non-volatile memory die are above a threshold, storing the current checkpoint state data in the free storage resources of the non-volatile memory die; otherwise, overwriting the oldest checkpoint state data with the current checkpoint state data. This implementation can prevent insufficient storage space for backing up checkpoint state data.

[0011] In one possible implementation, the non-volatile memory array and peripheral circuitry are implemented on the same substrate as the non-volatile memory die. That is, the non-volatile memory array and peripheral circuitry are implemented on the same substrate as the non-volatile memory die in a two-dimensional planar structure.

[0012] In one possible implementation, the non-volatile memory array includes a first non-volatile memory array and a second non-volatile memory array, which are implemented on opposite sides of the peripheral circuitry on the same layer. The non-volatile memory die has a symmetrical structure, and the latency difference between the peripheral circuitry reading and writing data stored in the two non-volatile memory arrays is very small.

[0013] In one possible implementation, the non-volatile memory array and peripheral circuitry are implemented on different layers of the non-volatile memory die. That is, the non-volatile memory array and peripheral circuitry are implemented on different layers of the non-volatile memory die in a three-dimensional stacked structure.

[0014] In one possible implementation, the non-volatile memory die further includes a substrate, a first metal layer group, and a second metal layer group. Peripheral circuitry is implemented on the substrate, and the first metal layer group, the non-volatile memory array, the second metal layer group, and the substrate are sequentially stacked on different layers of the non-volatile memory die. In other words, the non-volatile memory array and peripheral circuitry are implemented in a three-dimensional stacked structure on different layers of the non-volatile memory die.

[0015] In one possible implementation, the storage cell types of the non-volatile memory array include flash memory, ferroelectric random access memory, magnetic memory, phase-change random access memory, or resistive random access memory.

[0016] In one possible implementation, the volatile memory die includes a first volatile memory die and a second volatile memory die, wherein the first volatile memory die, the non-volatile memory die, the second volatile memory die, and the control die are stacked in sequence.

[0017] In one possible implementation, the volatile memory die includes a first volatile memory die and a second volatile memory die, and the non-volatile memory die includes a first non-volatile memory die and a second non-volatile memory die, wherein the first volatile memory die, the first non-volatile memory die, the second volatile memory die, the second non-volatile memory die, and the control die are stacked sequentially.

[0018] In one possible implementation, volatile memory dies, non-volatile memory dies, and control dies are stacked sequentially.

[0019] In a second aspect, a storage system is provided, comprising: a stacked memory as described in the first aspect and any embodiment thereof, a working power supply and a backup power supply; wherein the working power supply powers the operation of the stacked memory when the storage system is operating normally; wherein when the working power supply fails, the system switches to the backup power supply to power the operation of the stacked memory; and wherein when the working power supply is restored, the system switches back to the working power supply to power the operation of the stacked memory.

[0020] The technical effects of the second aspect can be referred to the technical effects of the first aspect and any of its embodiments. Attached Figure Description

[0021] Figure 1 This application provides a schematic diagram of the structure of a storage system according to an embodiment of the present application.

[0022] Figure 2 This is a schematic diagram of another storage system provided in an embodiment of this application;

[0023] Figure 3 A schematic diagram of a stacked memory provided in an embodiment of this application. Figure 1 ;

[0024] Figure 4 This is a schematic diagram of the structure of another storage system provided in an embodiment of this application;

[0025] Figure 5 A schematic diagram of a stacked memory provided in an embodiment of this application. Figure 2 ;

[0026] Figure 6 A schematic diagram of a stacked memory provided in an embodiment of this application. Figure 3 ;

[0027] Figure 7 A schematic diagram of a stacked memory provided in an embodiment of this application. Figure 4 ;

[0028] Figure 8 This is a schematic diagram of the structure of a non-volatile memory die provided in an embodiment of this application;

[0029] Figure 9 This is a schematic diagram of another non-volatile memory die provided in an embodiment of this application;

[0030] Figure 10 A schematic diagram of the structure of another non-volatile memory die provided in the embodiments of this application;

[0031] Figure 11 This application provides a schematic diagram of the structure of a power integrity circuit and a signal integrity circuit according to embodiments of the present application.

[0032] Figure 12 This is a schematic diagram of a stacked memory and processor package provided in an embodiment of this application. Detailed Implementation

[0033] In the embodiments of this application, the term "exemplary" is used to indicate that it is an example, illustration, or description. Any embodiment or design that is described as "exemplary" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Rather, the use of the term "exemplary" is intended to present the concept in a specific manner.

[0034] First, some concepts involved in the embodiments of this application will be described:

[0035] Signal integrity (SI): In stacked memory, memory dies are stacked together using through-silicon vias (TSVs) and / or bonding techniques. This results in parasitic capacitance and resistance. Signal integrity refers to the ability of a signal to continue operating normally after it has been transmitted from the bottom die to the top die via TSVs and / or bonding. Signal integrity issues include, but are not limited to, impedance matching problems (ringing, crosstalk) and common-mode noise (ground bounce, IR drop) during signal transmission.

[0036] Power integrity (PI): In stacked memory, power integrity refers to the ability of the supply voltage to meet normal operating requirements after being transferred from the bottom die to the top die via TSV and / or bonding. Power integrity issues include, but are not limited to, IR drop during supply voltage transfer and voltage noise (e.g., significant noise introduced by current variations during DRAM read / write operations).

[0037] A checkpoint is a specific point in time at which the processor synchronizes pages in memory and pages in the shared memory buffer.

[0038] A processor can be a chip. For example, it can be a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a system-on-a-chip (SoC), a central processing unit (CPU), a network processor (NP), a digital signal processor (DSP), a microcontroller unit (MCU), a programmable logic device (PLD), or other integrated chips.

[0039] Stacked memory is a type of memory that is made up of multiple layers of memory dies stacked together. Each layer of memory die includes a memory array composed of multiple memory cells.

[0040] Volatile memory refers to memory whose stored data disappears when the power supply is turned off. The volatile memory involved in the embodiments of this application includes: dynamic random access memory (DRAM), high-bandwidth memory (HBM), hybrid memory cube (HMC), etc.

[0041] Non-volatile memory refers to memory whose stored data is retained even when the power supply is turned off. Non-volatile memory is further categorized into non-rewritable and rewritable memory based on whether it can be rewritten. In this application, the non-volatile memory referred to is rewritable memory, including flash memory, ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), phase-change random access memory (PRAM), and resistance-switching random access memory (ReRAM). FeRAM uses ferroelectric thin-film capacitors instead of conventional charge storage capacitors, utilizing the high dielectric constant and ferroelectric polarization characteristics of ferroelectric materials to store data through polarization reversal. MRAM uses magnetic field polarization rather than charge to store data. PRAM uses the difference in conductivity exhibited by special materials during transitions between crystalline and amorphous states to store data. ReRAM stores data based on differences in resistance values.

[0042] This application provides a storage system based on non-volatile dual inline memory modules (NVDIMMs) to improve the data reliability of stacked memory. For example... Figure 1 As shown, the storage system includes: volatile memory 11, NVDIMM 12, operating power supply 13, and backup power supply 14. The memory in NVDIMM 12 can be a stacked memory. The volatile memory 11 can include HBM, HMC, etc.

[0043] Volatile memory 11 and NVDIMM 12 are connected via a bus. During normal operation of the entire storage system, the operating power supply 13 powers both volatile memory 11 and NVDIMM 12. If the operating power supply 13 fails due to a malfunction, the system switches to backup power supply 14 to power both volatile memory 11 and NVDIMM 12, and backs up the data stored in volatile memory 11 to NVDIMM 12. When the operating power supply 13 is restored, the system switches back to backup power supply 14 to power both volatile memory 11 and NVDIMM 12, and restores the data stored in NVDIMM 12 to volatile memory 11.

[0044] The aforementioned storage system consumes a significant amount of energy during data backup and recovery due to the data transfer between chips, placing higher demands on backup power supplies, increasing costs, and reducing the battery life of electronic devices.

[0045] This application provides another storage system for backing up and restoring checkpoint data. For example... Figure 2 As shown, the storage system includes a processor 21 and dual inline memory modules (DIMMs) 22.

[0046] When running a program, processor 21 periodically backs up checkpoint data to the stacked memory of DIMM 22 via a double data rate (DDR) bus. When a program encounters an error, the checkpoint data stored in the stacked memory of DIMM 22 is restored to processor 21, thus preventing processor 21 from crashing after running the program for an extended period. However, this storage system also consumes a significant amount of energy during the backup and restore of checkpoint data due to the data transfer between chips.

[0047] Furthermore, as electronic devices demand increasingly larger storage spaces, the number of memory dies stacked in stacked memories is also increasing. However, due to space constraints within the installed electronic devices, the thickness of each memory die layer is becoming increasingly thinner, leading to a decrease in overall memory reliability. For example, excessively thin memory chips are prone to breakage, data retention time is reduced, and power integrity and signal integrity decrease at high stack counts. This application provides a stacked memory to prevent degradation of power integrity and signal integrity.

[0048] This application provides a stacked memory for improving the power integrity and signal integrity of the stacked memory. For example... Figure 3 As shown, the stacked memory includes at least one volatile memory die 31, at least one buffer die 32, and a control die 33. The volatile memory die 31, the buffer die 32, and the control die 33 are stacked together via through-silicon via (TSV) and / or bonding techniques.

[0049] The control die 33 is used to control read and write operations on each volatile memory die 31. The buffer die 32 is not used to store data, but integrates decoupling capacitors and amplifiers to improve the power integrity and signal integrity of data transmission between the control die 33 and the volatile memory die 31.

[0050] However, in the aforementioned stacked memory, the buffer die 32 occupies the space of a single die layer. This increases the overall height of the stacked memory while keeping the thickness of each die layer constant, and decreases the thickness of each die layer while keeping the overall height of the stacked memory constant, further leading to a decrease in reliability.

[0051] This application provides another storage system with stacked memory, including stacked non-volatile memory dies and volatile memory dies. Circuitry for improving signal integrity and power integrity is implemented in the peripheral circuitry of the non-volatile memory dies without occupying additional memory dies. Furthermore, data transfer can occur between the non-volatile and volatile memory dies, enabling data backup and recovery through internal chip data transfer. This reduces energy consumption and the need for backup power, thereby lowering costs and increasing the battery life of electronic devices.

[0052] like Figure 4 As shown, the storage system includes a stacked memory 41, a working power supply 42, a backup power supply 43, and optionally, a processor 44.

[0053] When the entire storage system is operating normally, the operating power supply 42 powers the stacked memory 41 and the processor 44. If the operating power supply 42 fails due to a malfunction or other reason, the power supply switches to the backup power supply 43 to power the stacked memory 41 and the processor 44. When the operating power supply 42 is restored, the power supply switches back to powering the stacked memory 41 and the processor 44.

[0054] like Figures 5-7 As shown, the stacked memory includes: a volatile memory die 51, a non-volatile memory die 52, and a control die 53. The volatile memory die 51, the non-volatile memory die 52, and the control die 53 are stacked together via through-silicon via (TSV) and / or bonding techniques.

[0055] This application does not limit the stacking order of the volatile memory die 51, the non-volatile memory die 52, and the control die 53:

[0056] For example, such as Figure 5 As shown, the volatile memory die 51, the non-volatile memory die 52, and the control die 53 can be stacked in sequence.

[0057] Or, such as Figure 6As shown, the volatile memory die 51 includes a first volatile memory die 51A and a second volatile memory die 51B, and the non-volatile memory die 52 includes a first non-volatile memory die 52A and a second non-volatile memory die 52B. The first volatile memory die 51A, the first non-volatile memory die 52A, the second volatile memory die 51B, and the second non-volatile memory die 52B are stacked sequentially, and then stacked sequentially with the control die 53. That is, the volatile memory die 51 and the non-volatile memory die 52 are stacked alternately before being stacked with the control die 53.

[0058] Or, such as Figure 7 As shown, the volatile memory die 51 includes a first volatile memory die 51A and a second volatile memory die 51B. The first volatile memory die 51A, the non-volatile memory die 52, and the second volatile memory die 51B are stacked in sequence, and then stacked in sequence with the control die 53, that is, the non-volatile memory die 52 is stacked between the two volatile memory dies.

[0059] like Figures 8-10 As shown, the non-volatile memory die includes a non-volatile memory array 521 and peripheral circuitry 522.

[0060] The non-volatile memory array 521 includes a plurality of non-volatile memory cells arranged in sequence.

[0061] The peripheral circuit 522 includes read, write, and erase drive circuits, data judgment circuits, and instruction sending circuits. These circuits are used to control the reading and writing of data stored in the non-volatile memory array 521.

[0062] like Figure 11 As shown, the peripheral circuit 522 also includes a power integrity (PI) circuit 5221 and a signal integrity (SI) circuit 5222. The PI circuit 5221 is used to optimize the power supply voltage obtained from the lower die (e.g., the control die) (e.g., via TSV) and then transmit it (e.g., via TSV) to the upper die (e.g., the volatile memory die) to improve the power integrity between the lower and upper dies of the stacked memory; the SI circuit is used to optimize the signal obtained from the lower die (e.g., via TSV) and then transmit it (e.g., via TSV) to the upper die to improve the signal integrity between the lower and upper dies of the stacked memory.

[0063] Power integrity optimization includes, but is not limited to, filtering voltage noise (e.g., Figure 11 The boost circuits shown in A and B reduce the IR voltage drop (exemplary examples are shown in Figure 1). Figure 11At least one of the linear regulated sources shown in C in the diagram. Signal integrity optimization includes, but is not limited to, reducing common-mode noise (exemplary examples such as...). Figure 11 The differential amplifier (D) and filter (E) in the diagram achieve impedance matching (for example, as shown in the diagram). Figure 11 At least one of the impedance matching circuits shown in F in the diagram.

[0064] The manufacturing process of non-volatile memory dies includes front-end and back-end processes. Front-end processes include photolithography, etching, cleaning, ion implantation, and chemical mechanical planarization. Back-end processes include wire bonding, bonding, flux-cooper backing (FCB), ball grid array (BGA) ball placement, inspection, and testing. Peripheral circuitry can be implemented through the front-end processes.

[0065] and Figure 3 Compared to stacked memory, Figure 5 The peripheral circuitry of the stacked memory can improve the power integrity and signal integrity of the stacked memory by integrating the circuitry that improves power integrity and signal integrity into the non-volatile memory die, without occupying the space of a separate die layer, and therefore without increasing the height of the stacked memory.

[0066] This application does not limit the stacking method of the non-volatile memory array and peripheral circuitry. In one possible implementation, such as Figure 8 or Figure 9 As shown, the non-volatile memory array 521 and peripheral circuitry 522 can be implemented on the same substrate of a single non-volatile memory die. For example... Figure 9 As shown, the non-volatile memory array 521 may include a first non-volatile memory array 5211 and a second non-volatile memory array 5212, which can be implemented on both sides of the peripheral circuit 522 on the same layer. It should be noted that the embodiments of this application do not limit the number of non-volatile memory arrays on the same layer.

[0067] In another possible implementation, such as Figure 10As shown, the non-volatile memory array 521 and peripheral circuitry 522 can be implemented on different layers of a non-volatile memory die. For example, the non-volatile memory die also includes a substrate 523, a first metal layer group 524, and a second metal layer group 525. The peripheral circuitry 522 is implemented on the substrate 523, and the first metal layer group 524, the non-volatile memory array 521, the second metal layer group 525, and the substrate 523 are sequentially stacked on different layers of the non-volatile memory die. The first metal layer group 524 and the second metal layer group 525 are used to arrange traces within the non-volatile memory die.

[0068] This application does not limit the number of layers of the volatile memory die 51, for example, it can be 8 layers, 16 layers, etc.

[0069] This application does not limit the type of storage cell in the non-volatile memory array. The types of storage cells in the non-volatile memory array include, but are not limited to, flash memory, FeRAM, MRAM, PRAM, ReRAM, etc.

[0070] The control die 53 is used to: back up and store data from the volatile memory die 51 to the non-volatile memory die 52; or, store data from the non-volatile memory die 52 to the volatile memory die 51.

[0071] In one possible implementation, when a power outage is detected, the control die 53 controls the peripheral circuit 522 to store data from the volatile memory die 51 to the non-volatile memory die 52. When a power outage is detected, the control die 53 controls the peripheral circuit 522 to store data from the non-volatile memory die 52 to the volatile memory die 51.

[0072] For example, if the operating power supply suddenly fails, the power detection module in control die 53 or other power detection modules detect the power failure event, and control die 53 starts the backup power supply to enter the power failure data backup mode. Control die 53 then stores some or all of the data stored in volatile memory die 51 into the first storage area in non-volatile memory die 52. After completion, the backup power supply can be turned off. If the operating power supply is restored, the power detection module in control die 53 or other power detection modules detect the power failure recovery event, and control die 53 restores the data stored in the first storage area of ​​non-volatile memory die 52 to volatile memory die 51.

[0073] In the event of a power outage, the storage system does not need to back up the data stored in volatile memory to external non-volatile memory; similarly, in the event of a power outage recovery, the storage system does not need to transfer the data backed up from external non-volatile memory to volatile memory. Data backup and recovery can be achieved within the stacked memory, reducing energy consumption, lowering the requirement for backup power, and thus reducing costs.

[0074] In another possible implementation, the data is checkpoint data during program execution. Upon receiving a checkpoint data backup command or when the timer reaches the backup cycle, the control die 53 controls the peripheral circuit 522 to store the data from the volatile memory die 51 to the non-volatile memory die 52. Upon receiving a checkpoint data recovery command, the control peripheral circuit 522 stores the data from the non-volatile memory die 52 to the volatile memory die 51.

[0075] For example, such as Figure 12 As shown, the stacked memory 41 and the processor 44 can be packaged on a package substrate. The stacked memory 41 and the processor 44 are electrically connected through a bus in a wiring layer, and the stacked memory 41 and the processor 44 are electrically connected to the package substrate through wiring layers, respectively.

[0076] The processor periodically sends checkpoint data backup commands to the control die 53 of the stacked memory according to the backup cycle. After receiving the checkpoint data backup command, the control die 53 backs up the checkpoint data stored in the volatile memory die 51 to the second storage area of ​​the non-volatile memory die 52 according to the parameters in the checkpoint data backup command. That is, the control die 53 backs up the checkpoint data according to the processor's instructions. Alternatively, when the timer of the control die 53 reaches the backup cycle, it backs up the checkpoint data stored in the volatile memory die 51 to the second storage area of ​​the non-volatile memory die 52. That is, the control die 53 can back up the checkpoint data autonomously.

[0077] When a program crash occurs, the processor sends a checkpoint data recovery command to the control die 53 of the stacked memory. After receiving the checkpoint data recovery command, the control die 53 recovers and stores the latest checkpoint data stored in the second storage area of ​​the non-volatile memory die 52 to the volatile memory die 51 according to the parameters in the checkpoint data recovery command.

[0078] When periodically backing up checkpoint data, the storage system does not need to back up the checkpoint data stored in volatile memory to external non-volatile memory; similarly, when restoring checkpoint data, the storage system does not need to store the checkpoint data backed up from external non-volatile memory to volatile memory. Checkpoint data backup and recovery can be achieved within the stacked memory, reducing energy consumption.

[0079] The first storage area and the second storage area mentioned above can be the same area or different areas. When they are different areas, the storage system can simultaneously perform power failure data storage and recovery as well as checkpoint data storage and recovery.

[0080] Upon receiving a checkpoint data backup command or when the backup cycle is reached, if the free storage resources in the non-volatile memory die 52 are higher than a threshold, the current checkpoint data is stored in the free storage resources of the non-volatile memory die 52 without overwriting the oldest checkpoint data. Otherwise, the current checkpoint status data overwrites the oldest checkpoint data in a first-in, first-out (FIFO) order.

[0081] By retaining the original technical characteristics of hybrid high-bandwidth memory, such as high integration, low implementation cost and difficulty, this method can still ensure the signal integrity and power integrity transmitted between the bottom control die and the top DRAM die without increasing the die cost, thus ensuring the reliability of three-dimensional memory chips with high stacking numbers.

[0082] Furthermore, controlling the die to store data from volatile memory to non-volatile memory enables data backup; controlling the die to store data from non-volatile memory to volatile memory enables data recovery. This not only improves the reliability of data storage but also reduces energy consumption during backup and recovery by implementing data backup and recovery internally, eliminating the need for inter-chip data transfer.

[0083] In summary, the stacked memory and storage system provided in this application include stacked volatile memory dies and non-volatile memory dies. Each non-volatile memory die includes a non-volatile memory array and peripheral circuitry. The peripheral circuitry includes power integrity circuitry and signal integrity circuitry. The power integrity circuitry optimizes the power received from the lower-layer die before transmitting it to the upper-layer die; the signal integrity circuitry optimizes the signal received from the lower-layer die before transmitting it to the upper-layer die. The non-volatile memory array can be used to store data, and the peripheral circuitry can improve the power integrity and signal integrity between the bottom and top dies of the stacked memory. Since the peripheral circuitry does not occupy a separate layer of dies, it prevents a decrease in the power integrity and signal integrity of the stacked memory without increasing the number of dies.

[0084] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0085] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0086] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0087] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0088] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0089] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented using software programs, implementation can be, in whole or in part, in the form of a computer program product. This computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device containing one or more servers, data centers, etc., that can be integrated with the medium. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state drives (SSDs)).

[0090] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A stacked memory, characterized in that, It includes stacked volatile memory dies and non-volatile memory dies; wherein, the non-volatile memory die includes a non-volatile memory array and peripheral circuitry, the peripheral circuitry including power integrity circuitry and signal integrity circuitry; The power integrity circuit is used to optimize the power obtained from the lower-layer die and then transmit it to the upper-layer die; the power integrity optimization includes at least one of filtering voltage noise and reducing IR voltage drop; The signal integrity circuit is used to optimize the signal obtained from the lower-layer die before transmitting it to the upper-layer die; the signal integrity optimization includes at least one of common-mode noise reduction and impedance matching.

2. The stacked memory according to claim 1, characterized in that, The stacked memory also stacks control dies, which are used for: The peripheral circuitry is controlled to store data from the volatile memory die to the non-volatile memory die; or, the peripheral circuitry is controlled to store data from the non-volatile memory die to the volatile memory die.

3. The stacked memory according to claim 2, characterized in that, The control die is specifically used for: When a power failure is detected, the peripheral circuit is controlled to store the data in the volatile memory die to the non-volatile memory die. When the power supply is detected to be restored, the peripheral circuit is controlled to store the data in the non-volatile memory die to the volatile memory die.

4. The stacked memory according to claim 2, characterized in that, The data is checkpoint data, and the control die is specifically used for: When a checkpoint data backup command is received or the backup cycle is reached, the peripheral circuit is controlled to store the data in the volatile memory die to the non-volatile memory die. Upon receiving a checkpoint data recovery command, the peripheral circuitry is controlled to store the data from the non-volatile memory die to the volatile memory die.

5. The stacked memory according to claim 4, characterized in that, Upon receiving a checkpoint data backup command or when the backup cycle is reached, the control die is specifically used for: If the free storage resources in the non-volatile memory die are higher than a threshold, the current checkpoint state data is stored in the free storage resources of the non-volatile memory die. Otherwise, the current checkpoint state data will overwrite the earliest checkpoint state data.

6. The stacked memory according to any one of claims 1-5, characterized in that, The non-volatile memory array and the peripheral circuitry are implemented on the same substrate as the non-volatile memory die.

7. The stacked memory according to claim 6, characterized in that, The non-volatile memory array includes a first non-volatile memory array and a second non-volatile memory array, which are implemented on both sides of the peripheral circuit on the same layer.

8. The stacked memory according to any one of claims 1-5, characterized in that, The non-volatile memory array and the peripheral circuitry are implemented on different layers of the non-volatile memory die.

9. The stacked memory according to claim 8, characterized in that, The non-volatile memory die also includes a substrate, a first metal layer group and a second metal layer group, and the peripheral circuit is implemented on the substrate. The first metal layer group, the non-volatile memory array, the second metal layer group and the substrate are stacked sequentially on different layers of the non-volatile memory die.

10. The stacked memory according to any one of claims 1-5, 7, and 9, characterized in that, The storage cell types of the non-volatile memory array include flash memory, ferroelectric random access memory, magnetic memory, phase-change random access memory, or resistive random access memory.

11. The stacked memory according to any one of claims 1-5, 7, and 9, characterized in that, The volatile memory die includes a first volatile memory die and a second volatile memory die, which are stacked sequentially.

12. The stacked memory according to any one of claims 1-5, 7, and 9, characterized in that, The volatile memory die includes a first volatile memory die and a second volatile memory die, and the non-volatile memory die includes a first non-volatile memory die and a second non-volatile memory die, wherein the first volatile memory die, the first non-volatile memory die, the second volatile memory die, and the second non-volatile memory die are stacked in sequence.

13. The stacked memory according to any one of claims 1-5, 7, and 9, characterized in that, The volatile memory die and the non-volatile memory die are stacked in sequence.

14. A storage system, characterized in that, include: The stacked memory, operating power supply, and backup power supply as described in any one of claims 1-13; When the storage system is working normally, the stacked memory is powered by the operating power supply. When the operating power supply fails, the operation of the stacked memory is switched to be powered by the backup power supply. When the operating power supply is restored, the system switches back to using the operating power supply to power the stacked memory.

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