A graphics processor-based BIOS updating method

Abstract

The application is suitable for the technical field of graphic processor, and provides a BIOS updating method based on a graphic processor, which comprises the following steps: a parameter configuration step, a file segmentation sending step, a data translation step, an instruction separation step, a data writing step, a data reading step and a check and comparison step.In the application, the graphic processor directly stores the received BIOS file into a FLASH chip according to an address space through an SPI module, and compares the data check values of the written data and the read data, so as to ensure the data correctness; the BIOS file to be updated is transmitted and stored in the form of a binary file, so as to ensure the confidentiality and stability of the data protocol, and further improve the overall stability of the system; and the design cost of the logic device is reduced, and the hardware design cost of the whole system is also reduced.

Description

Technical Field

[0001] This invention belongs to the field of graphics processor technology, and particularly relates to a BIOS update method based on a graphics processor. Background Technology

[0002] After years of exploration and development, domestically produced platforms have achieved a certain degree of self-control, and the industry and ecosystem have gradually become more complete. Based on the widespread acceptance and use of domestically produced platforms, and considering the platform's unique characteristics and data security, the BIOS (Basic Input Output System) of the computer system and graphics card is a crucial component connecting software and hardware, and a vital link in device security verification. With the upgrading of computer hardware and software systems, some imperfections in graphics cards will inevitably be exposed, requiring continuous modification and improvement of the graphics card BIOS. The adaptation of new drivers for domestically produced graphics processors also requires corresponding BIOS updates. Therefore, updating the BIOS of domestically produced graphics processors is of great significance.

[0003] Traditional methods for updating graphics card BIOS under Windows systems require installing Windows graphics card drivers and GPU-Z, a tool for reading graphics card information, in order to save the BIOS file. It also requires running the command `nvflash.exefilename` with administrator privileges to flash the BIOS. The system environment and system tools are completely incompatible with domestic hardware, and the relevant operation commands are not supported on domestic platforms.

[0004] The current online BIOS update method for domestically produced processor servers updates the BIOS stored in multiple SPI FLASH chips via the BMC (Baseboard Management Controller). This occurs when the server is running normally or fails to boot, and the BMC updates the BIOS firmware. Analog switches automatically switch between multiple SPI FLASH chips used for storing the BIOS firmware, enabling automatic BIOS flashing. The BMC controller is controlled by software, which in turn controls the switching of the analog switches, and then the BMC controller operates the SPI FLASH chips for file storage. This method requires additional hardware costs and control of multiple hardware modules, increasing the overall system design cost and the probability of data storage errors. Summary of the Invention

[0005] In view of the above problems, the purpose of this invention is to provide a BIOS update method based on a graphics processor, which aims to solve the technical problems existing in the prior art, such as conditional constraints, platform incompatibility, and the need for additional hardware.

[0006] The graphics processor-based BIOS update method includes the following steps:

[0007] Step S1: Configure the software communication module with parameter information, including protocol parameters, mode parameters, base address parameter values, and offset address parameter values;

[0008] Step S2: The software communication module loads the BIOS file, calculates the write data verification value through the data verification algorithm and saves it to the cache of the software communication module, divides the BIOS file into segment files, combines the segment files with parameter information to form a data stream, and periodically writes the data stream to the receiving protocol module. The receiving protocol module sends the data stream to the encoding module.

[0009] Step S3: The encoding module parses the received data stream and translates it into valid operation instructions;

[0010] Step S4: The read / write module separates the write instruction and the data to be written from the operation instructions;

[0011] Step S5: After receiving the write command, the SPI module writes the base address parameter value and the offset address parameter value into the data buffer register, erases the area block corresponding to the base address parameter value and the offset address parameter value, verifies the enable read / write command status value, write write command enable status value, write write phase status value, and verifies the write phase status value. After completion, the written data is written to the specified address location corresponding to the FLASH chip according to the spatial layer.

[0012] Step S6: The software communication module sends operation message information to the encoding module through the receiving protocol module. The encoding module parses the received operation message information and translates it into a valid operation command. The read / write module separates the read command from the operation command. After receiving the read command, the SPI module first writes the base address parameter value and the offset address parameter value into the data buffer register, then writes the enable read / write command, writes the read phase status value and the check read enable status value, writes the current read phase status value, and writes the read status register. Finally, it reads data from the specified address position corresponding to the FLASH chip according to the base address parameter value and the offset address parameter value and sends it to the software communication module in strips.

[0013] Step S7: After the software communication module finishes receiving data, it calculates the read data verification value using a data verification algorithm and saves it to the software communication module's cache. It then determines whether the written data verification value is the same as the read data verification value. If they are the same, it prompts that the BIOS file update is complete; otherwise, it prompts an error message.

[0014] The beneficial effects of this invention are: the BIOS update method based on the graphics processor provided by this invention does not require additional hardware or logic device protocol conversion. The structure and format of the input file data ensure the stability of the overall data during transmission, thereby improving the data performance stability of the FLASH chip, rationally allocating the FLASH chip storage space, and reducing the power consumption of the FLASH chip storage. Attached Figure Description

[0015] Figure 1 This is a structural block diagram of the BIOS update method provided in the embodiments of the present invention;

[0016] Figure 2 This is a flowchart illustrating the BIOS update method provided in this embodiment of the invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0018] To illustrate the technical solution described in this invention, specific embodiments are described below.

[0019] Figure 1 The diagram illustrates the structural block diagram of the BIOS update method of this invention, including a domestically produced processor and graphics processor, a FLASH chip, and a software communication module. The domestically produced processor and graphics processor are connected via a PCI-Express bus. The domestically produced graphics processor includes a receiving protocol module, a transmitting protocol module, an encoding module, a read / write module, and an SPI module. The SPI module communicates with the SPI NOR FLASH chip. The software communication module flexibly adapts to different computer platforms according to a defined communication protocol, providing human-computer interaction, convenience, speed, and high versatility. The domestically produced graphics processor receives the BIOS file to be stored from the software communication module via the receiving protocol module, translates it through the encoding module, and then transmits it to the SPI module via the read / write module. The SPI module saves the BIOS file to the FLASH chip, completing data storage. The specific implementation process is as follows: Figure 2 As shown, only the parts related to the embodiments of the present invention are shown for ease of explanation.

[0020] like Figure 2 As shown, the BIOS update method based on a graphics processor provided in this embodiment includes the following steps:

[0021] Step S1, Parameter Configuration Step: Configure parameter information for the software communication module. The parameter information includes protocol parameters, mode parameters, base address parameter value, and offset address parameter value.

[0022] The software communication module sends messages according to the set protocol parameters. A complete message instruction consists of 11 bytes, including: 1 byte for the operation mode, 1 byte for the operation width, 5 bytes for the operation address, and 4 bytes for the operation data. The message instruction functions include: baud rate setting, read operation, write operation, and soft reset operation. The operation mode byte definition is also included.

[0023] First, the entire platform is powered on. The configuration file for the software communication module contains parameters including protocol parameters, mode parameters, base address parameters, and offset address parameters. The protocol parameters include the operation mode and operation bit width. The mode parameters include exit XIP mode, base address configuration mode, enable read / write command mode, read / write phase state mode, read current phase state mode, block erase mode, set write operation mode, and set write status register mode. The base address parameter is a custom initial address value for the FLASH chip's storage space. The offset address parameters include VBIOS space offset address, MCU space offset address, STARTUP space offset address, and configuration information space offset address, dividing the FLASH chip's storage space into four data spaces: VBIOS space, MCU space, STARTUP space, and configuration information space. The data in the BIOS file is stored in binary format. In subsequent steps, the BIOS file can be stored hierarchically into the corresponding specified FLASH chip storage spaces based on the base address parameter and offset address parameter values.

[0024] Step S2, File Segmentation and Transmission Step: The software communication module loads the BIOS file, calculates the write data verification value through the data verification algorithm and saves it to the cache of the software communication module, divides the BIOS file into segment files, combines the segment files with parameter information to form a data stream, and periodically writes the data stream to the receiving protocol module. The receiving protocol module then sends the data stream to the encoding module.

[0025] The data verification algorithm is not specifically limited in this embodiment; existing algorithms such as MD5 or DES can be used. The main function of this step is to load the BIOS file and send it to the domestic graphics processor, generating a data stream from the BIOS file and sending it. As a specific implementation scheme, the specific process of this step is as follows:

[0026] S21. The software communication module loads the BIOS file from the disk. Specifically, it reads the complete BIOS file from the disk using a zero-copy method and stores it in the page cache.

[0027] The BIOS file is stored on the disk. The software communication module then reads the BIOS file from the disk and uses zero-copy technology to read the complete data of the BIOS file and store it in the system's page cache.

[0028] S22. Calculate the written data verification value using the data verification algorithm and save it to the cache of the software communication module.

[0029] S23. Divide the BIOS file into segment files and cache the segment files into the skip list in sequential mode.

[0030] To improve write performance, segments are cached in a skip list in a sequential manner.

[0031] S24. Search for the segment file in the skip list cache. If the file is found, append a record to the segment file. The record includes an index file, a header file, and a timestamp file. The index file is written to the file channel, and the header file and timestamp file are written to the memory-mapped file.

[0032] S25. The segment file containing the records and the parameter information are combined into a data stream, and the data stream is periodically written into the receiving protocol module. The receiving protocol module then sends the data stream to the encoding module.

[0033] Step S3, Data Translation Step: The encoding module parses the received data stream and translates it into valid operation instructions.

[0034] Step S4, Instruction Separation Step: The read / write module separates the write instruction and the written data from the operation instructions.

[0035] The read / write module receives the operation instruction data transmitted by the encoding module. The read / write module separates the write command and write data from the operation instruction and transmits the write data on the write data channel.

[0036] Step S5, Data Writing Step: After receiving the write command, the SPI module writes the base address parameter value and offset address parameter value into the data buffer register, erases the area block corresponding to the base address parameter value and offset address parameter value, verifies the enable read / write command status value, write write command enable status value, write write phase status value, and verifies the write phase status value. After completion, the written data is written to the specified address location corresponding to the FLASH chip according to the spatial layer.

[0037] In this step, after the status value is written, the data is written to the data block and written to the VBIOS space, MCU space, STARTUP space, and configuration information space of the FLASH chip according to the space layer.

[0038] Step S6, Data Reading Step: The software communication module sends operation message information to the encoding module through the receiving protocol module. The encoding module parses the received operation message information and translates it into a valid operation command. The read / write module separates the read command from the operation command. After receiving the read command, the SPI module first writes the base address parameter value and offset address parameter value into the data buffer register, then writes the enable read / write command, writes the read phase status value and checks the read enable status value, writes the current read phase status value, and writes it into the read status register. Finally, it reads data from the specified address position corresponding to the FLASH chip according to the base address parameter value and offset address parameter value and sends it to the software communication module in strips.

[0039] Step S7, Verification and Checking Step: After the software communication module finishes receiving data, it calculates the read data verification value using a data verification algorithm and saves it to the software communication module's cache. It then determines whether the written data verification value is the same as the read data verification value. If they are the same, it prompts that the BIOS file update is complete; otherwise, it prompts an error message.

[0040] The specific process for this step is as follows:

[0041] S71. For each piece of data received by the software communication module, it is stored in the file virtual linked list according to the file index. The index file is searched using the binary search algorithm. The file channel is traversed according to the offset recorded in the index file. The segment file is obtained according to the offset and the size to be pulled. All data is received and a complete BIOS file is formed.

[0042] S72. Calculate the read data verification value using the data verification algorithm and save it to the cache of the software communication module. Determine whether the written data verification value is the same as the read data verification value. If they are the same, prompt that the BIOS file update is complete; otherwise, prompt an error message.

[0043] Restart the device after completing the BIOS file update.

[0044] This invention employs a communication protocol that eliminates the need for a clock or any other timing signals. It includes a parity check bit for convenient error checking. Stable communication is achieved simply by configuring the data packet structure at both the receiving and transmitting ends. The domestically produced graphics processor directly stores the received BIOS file into the FLASH chip according to its address space via the SPI module, comparing the data checksums of the written and read data to ensure data correctness. The BIOS file to be updated is transmitted and stored in binary format, ensuring the confidentiality and stability of the data protocol and further improving the overall system stability. This not only reduces the design cost of logic devices but also lowers the overall hardware design cost of the system.

[0045] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A BIOS update method based on a graphics processor, characterized in that, The method includes the following steps: Step S1: Configure the software communication module with parameter information, including protocol parameters, mode parameters, base address parameter values, and offset address parameter values; Step S2: The software communication module loads the BIOS file, calculates the write data verification value through the data verification algorithm and saves it to the cache of the software communication module, divides the BIOS file into segment files, combines the segment files with parameter information to form a data stream, and periodically writes the data stream to the receiving protocol module. The receiving protocol module sends the data stream to the encoding module. Step S3: The encoding module parses the received data stream and translates it into valid operation instructions; Step S4: The read / write module separates the write instruction and the data to be written from the operation instructions; Step S5: After receiving the write command, the SPI module writes the base address parameter value and the offset address parameter value into the data buffer register, erases the area block corresponding to the base address parameter value and the offset address parameter value, verifies the enable read / write command status value, write write command enable status value, write write phase status value, and verifies the write phase status value. After completion, the written data is written to the specified address location corresponding to the FLASH chip according to the spatial layer. Step S6: The software communication module sends operation message information to the encoding module through the receiving protocol module. The encoding module parses the received operation message information and translates it into a valid operation command. The read / write module separates the read command from the operation command. After receiving the read command, the SPI module first writes the base address parameter value and the offset address parameter value into the data buffer register, then writes the enable read / write command, writes the read phase status value and the check read enable status value, writes the current read phase status value, and writes the read status register. Finally, it reads data from the specified address position corresponding to the FLASH chip according to the base address parameter value and the offset address parameter value and sends it to the software communication module in strips. Step S7: After the software communication module finishes receiving data, it calculates the read data verification value using a data verification algorithm and saves it to the software communication module's cache. It then determines whether the written data verification value is the same as the read data verification value. If they are the same, it prompts that the BIOS file update is complete; otherwise, it prompts an error message. The protocol parameters include operation mode and operation bit width. The mode parameters include exit XIP mode, base address configuration mode, enable read / write command mode, read / write phase state mode, read current phase state mode, block erase mode, set write operation mode, and set write status register mode. The base address parameter value is a custom initial address value of the FLASH chip's storage space. The offset address parameter value includes VBIOS space offset address value, MCU space offset address value, STARTUP space offset address value, and configuration information space offset address value, dividing the FLASH chip's storage space into four data spaces: VBIOS space, MCU space, STARTUP space, and configuration information space.

2. The BIOS update method based on a graphics processor as described in claim 1, characterized in that, The specific process of step S2 is as follows: S21. The software communication module loads the BIOS file from the disk, specifically by reading the complete BIOS file from the disk using a zero-copy method and storing it in the page cache; S22. Calculate the write data verification value using the data verification algorithm and save it to the cache of the software communication module; S23. Divide the BIOS file into segment files and cache the segment files into the skip list in sequential mode; S24. Search for the segment file in the skip list cache. If the file is found, append a record to the segment file. The record contains an index file, a header file, and a timestamp file. The index file is written to the file channel, and the header file and timestamp file are written to the memory-mapped file. S25. The segment file containing the records and the parameter information are combined into a data stream, and the data stream is periodically written into the receiving protocol module. The receiving protocol module then sends the data stream to the encoding module.

3. The BIOS update method based on a graphics processor as described in claim 2, characterized in that, The specific process of step S7 is as follows: S71. For each piece of data received by the software communication module, it is stored in the file virtual linked list according to the file index. The index file is searched using the binary search algorithm. The file channel is traversed according to the offset recorded in the index file. The segment file is obtained according to the offset and the size to be pulled. All data is received and a complete BIOS file is formed. S72. Calculate the read data verification value using the data verification algorithm and save it to the cache of the software communication module. Determine whether the written data verification value is the same as the read data verification value. If they are the same, prompt that the BIOS file update is complete; otherwise, prompt an error message.

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