Semiconductor device

Abstract

A semiconductor device includes a first transmission path which outputs a first preliminary signal, a second transmission path which outputs a second preliminary signal, a third transmission path which outputs a third preliminary signal, a first calibration circuit which generates a first calibration code corresponding to a difference in delay value between the first transmission path and a selected transmission path having a maximum delay value among the first transmission path to the third transmission path, a second calibration circuit which generates a second calibration code corresponding to a difference in delay value between the second transmission path and the selected transmission path, a third calibration circuit which generates a third calibration code corresponding to a difference in delay value between the third transmission path and the selected transmission path, a first delay control circuit which generates a first signal, a second delay control circuit which generates a second signal, and a third delay control circuit which generates a third signal.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0120934, filed on September 10, 2021, the entirety of which is incorporated herein by reference. Technical Field

[0003] Various embodiments of the present invention relate to semiconductor design technology, and more specifically, to methods for correcting delay time differences between multiple chips. Background Technology

[0004] With the rapid development of semiconductor memory technology, semiconductor device packaging technology is also required to have high integration and high performance. Therefore, in addition to two-dimensional structures that use wires or bumps to planarize integrated circuit chips on printed circuit boards (PCBs), three-dimensional structures for vertically stacking multiple integrated circuit chips are being widely developed.

[0005] This three-dimensional structure can be implemented as a stacked memory device in which multiple memory chips are stacked vertically. The vertically stacked memory chips are electrically connected to each other through through-silicon vias (TSVs) and mounted on a substrate for semiconductor packaging.

[0006] Recently, memory devices comprising multiple stacked memory chips have been widely used. Stacked memory chips exhibit operational characteristics such as varying latency values ​​between them due to process variations. Techniques to reduce process variations between stacked memory chips are crucial because problems such as insufficient memory margins and speed degradation can occur due to differences in operating characteristics between the chips. Summary of the Invention

[0007] Embodiments of the present invention relate to techniques for reducing process variations between multiple chips.

[0008] The technical effects that are intended to be achieved in the embodiments of the present invention are not limited to the above-described technical effects, and those skilled in the art to which the present invention pertains can clearly understand other unmentioned technical effects from the following description.

[0009] According to an embodiment of the present invention, a semiconductor device includes: a first transmission path that outputs a first preparation signal; a second transmission path that outputs a second preparation signal; a third transmission path that outputs a third preparation signal; a first calibration circuit that generates a first calibration code corresponding to the difference in delay values ​​between the first transmission path and a selected transmission path having the maximum delay value among the first transmission path to the third transmission path; a second calibration circuit that generates a second calibration code corresponding to the difference in delay values ​​between the second transmission path and the selected transmission path; a third calibration circuit that generates a third calibration code corresponding to the difference in delay values ​​between the third transmission path and the selected transmission path; a first delay control circuit that generates a first signal; a second delay control circuit that generates a second signal; and a third delay control circuit that generates a third signal.

[0010] According to another embodiment of the present invention, a semiconductor device includes: a plurality of stacked chips having different chip IDs, each chip including: a transmission path adapted to transmit a source signal transmitted via a first normal pass electrode and an output preparation signal; a delay control circuit adapted to delay the preparation signal by using a delay value determined based on a calibration code to generate an internal strobe signal; a replication circuit adapted to simulate the delay value of the transmission path and generate a test signal by delaying a test source signal transmitted via the first test pass electrode; a driving circuit adapted to transmit the generated test signal to a second test pass electrode corresponding to the chip ID in a second test pass electrode; and a calibration circuit adapted to generate a calibration code based on the generated test signal and test signals transmitted from other chips via the second test pass electrode.

[0011] According to another embodiment of the present invention, a semiconductor device includes: a stack of chips, each chip including: an operation circuit configured to receive a source signal via a normal pass-through electrode to generate an internal gating signal by delaying the source signal according to a calibration amount based on a calibration code; a replication circuit configured to generate a test signal by delaying a test source signal provided via a first test pass-through electrode by an amount representing a delay within the operation circuit other than the calibration amount; a driving circuit configured to provide the test signal to a remaining chip via a corresponding one of a second test pass-through electrode; and a calibration circuit configured to generate a calibration code by detecting a corresponding delay amount of an external test signal with reference to the test signal, the external test signals being provided from the remaining chip via a remaining second test pass-through electrode. Attached Figure Description

[0012] Figure 1 This is a block diagram illustrating a semiconductor device 100 according to an embodiment of the present invention.

[0013] Figure 2 This illustrates the relationship between the present invention and... Figure 1 The diagram shows a detailed block diagram of the structure related to the generation of the calibration code.

[0014] Figure 3 This illustrates an embodiment of the present invention. Figure 1 A detailed schematic diagram of the driving circuit of the chip is shown.

[0015] Figure 4 This illustrates an embodiment of the present invention. Figure 2 A block diagram of the calibration circuit.

[0016] Figure 5 This illustrates an embodiment of the present invention. Figure 4 A schematic diagram of the selection circuit.

[0017] Figure 6 This is a table illustrating the operation of the selection circuit according to an embodiment of the present invention.

[0018] Figure 7 This illustrates an embodiment of the present invention. Figure 4 The block diagram shown is of the code generation circuit.

[0019] Figure 8 This illustrates an embodiment of the present invention. Figure 7 A schematic diagram of the first-time digital conversion circuit.

[0020] Figure 9 and Figure 10 This is a timing diagram illustrating the operation of a first time-to-digital conversion circuit according to an embodiment of the present invention.

[0021] Figure 11 This illustrates an embodiment of the present invention. Figure 7 A block diagram of the decoder.

[0022] Figure 12 This illustrates an embodiment of the present invention. Figure 11 A schematic diagram showing the detailed structure of the delay calculation circuit.

[0023] Figure 13 It is used to describe embodiments of the present invention. Figure 11 The table shows the operation of the encoding circuit.

[0024] Figure 14 This is a timing diagram illustrating the calibration operation of a semiconductor device according to an embodiment of the present invention.

[0025] Figure 15 This is a block diagram illustrating a storage system according to an embodiment of the present invention. Detailed Implementation

[0026] Various embodiments of the invention will now be described in more detail with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure thorough and complete, and to fully convey the scope of the invention to those skilled in the art. Throughout this disclosure, the same reference numerals denote the same parts in the various figures and embodiments of the invention.

[0027] Figure 1 This is a block diagram illustrating a semiconductor device 100 according to an embodiment of the present invention.

[0028] Reference Figure 1 The semiconductor device 100 may include a plurality of stacked chips 114, 112_0, 112_1 and 112_2, and through electrodes TSV_ID, TSV_DQS, TSV_DQ, TSV_TDQS, TSV_TDQ0, TSV_TDQ1 and TSV_TDQ2 for transmitting signals between the stacked chips 114, 112_0, 112_1 and 112_2.

[0029] The lower chip 114 can be a chip that acts as an interface. Such a chip can also be referred to as a base die. Chips 112_0 to 112_2 can be memory chips used to store data. Chips 112_0 to 112_2 can communicate with other chips outside the semiconductor device 100 (e.g., processors including memory controllers, such as CPUs, GPUs, or APs) via chip 114. Chips 112_0 to 112_2 can also be referred to as core dies.

[0030] Chip 114 may include transmitters TX1 and TX3, receiver RX1, ID setting circuit 142, source signal generation circuit 144, and test source signal generation circuit 146.

[0031] The source signal generation circuit 144 of chip 114 can generate a source signal PDQS, which will be used as a gating signal in each of chips 112_0, 112_1, and 112_2, based on a clock signal transmitted from outside semiconductor device 100 or generated internally in chip 114. Transmitter TX1 can transmit the source signal PDQS to chips 112_0, 112_1, and 112_2 via the first normal pass-through electrode TSV_DQS.

[0032] The receiver RX1 of chip 114 can receive signals transmitted through the second normal pass-through electrode TSV_DQ (i.e., read data RDATA_C_0, RDATA_C_1, and RDATA_C_2 transmitted from chips 112_0 to 112_2) and generate read data RDATA_B. Read data RDATA_B can be output to the outside of semiconductor device 100 via input / output pad DQ_PD. Although in Figure 1 The diagram shows one second normal pass-through electrode TSV_DQ and one receiver RX1, but multiple second normal pass-through electrodes TSV_DQ and multiple receivers RX1 can exist. For example, multi-bit read data RDATA_C_0 can be transmitted from chip 112_0 through multiple second normal pass-through electrodes TSV_DQ, and multiple receivers RX1 can receive multi-bit parallel data RDATA_C_0. A parallel-to-serial conversion circuit (not shown) can perform parallel-to-serial conversion to generate serial data RDATA_B. The serial data RDATA_B can be output to the outside of semiconductor device 100 through input / output pad DQ_PD.

[0033] The test source signal generation circuit 146 of chip 114 can generate a test source signal TPDQS for calibration operations to compensate for process deviations between chips 160_0, 160_1, and 160_2, and the transmitter TX3 can transmit the test source signal TPDQS to chips 112_0, 112_1, and 112_2 through the first test pass-through electrode TSV_TDQS. The calibration operation can be performed when the semiconductor device 100 is initialized.

[0034] The ID setting circuit 142 of chip 114 can generate an initial ID SID in response to the initialization signal BOOTUP of semiconductor device 100 and transmit it to the third normal pass electrode TSV_ID.

[0035] Chips 112_0, 112_1, and 112_2 may include storage cores 120_0, 120_1, and 120_2, data output circuits 130_0, 130_1, and 130_2, receivers RX2_0, RX2_1, and RX2_2, paths PATH_0, PATH_1, and PATH_2, delay control circuits 150_0, 150_1, and 150_2, test signal providing circuits 160_0, 160_1, and 160_2, and calibration circuits 170_0, 170_1, and 170_2.

[0036] Since chips 112_0, 112_1 and 112_2 have the same structure, the structure of chips 112_0, 112_1 and 112_2 can be described by describing chip 112_2.

[0037] A storage core 120_2 may be provided for storing data. The storage core 120_2 may include multiple row lines (word lines), multiple column lines (bit lines), multiple storage cells formed at the intersections between the row lines and column lines, and circuitry for reading / writing data to the storage cells.

[0038] Receiver RX2_2 can receive the source signal PDQS transmitted by transmitter TX1 to the first normal pass electrode TSV_DQS. Path PATH_2 can represent the path used within chip 112_2 to transmit the source signal received by receiver RX2_2. Path PATH_2 may include multiple buffers for transmitting the source signal in chip 112_2 and conductive lines between the buffers. The source signal can be transmitted through path PATH_2 and undergoes a delay. As the source signal is delayed through path PATH_2, a preparatory signal A_2 can be obtained.

[0039] Different chips 112_0, 112_1, and 112_2 may have different process variations. Therefore, the paths PATH_0, PATH_1, and PATH_2 for chips 112_0, 112_1, and 112_2 can all have different delay values. The delay differences between the source signal PDQS and the preparatory signal A_0, between the source signal PDQS and the preparatory signal A_1, and between the source signal PDQS and the preparatory signal A_2 can all be different. Since preparatory signals A_0, A_1, and A_2 are used to generate strobe signals for the output chip, when the delay values ​​of preparatory signals A_0, A_1, and A_2 are different from each other, the data output timing can vary depending on which chip among chips 112_0, 112_1, and 112_2 is outputting data. For example, when data RDATA_C_0 is output from chip 112_0, this data RDATA_C_0 may be transmitted to chip 114 at an earlier timing, while when data RDATA_C_1 is output from chip 112_1, this data RDATA_C_1 may be output to chip 114 at an intermediate timing. When data RDATA_C_2 is output from chip 112_2, this data RDATA_C_2 may be transmitted to chip 114 at a later timing. When the operation timing depends on which of the stacked chips 112_0, 112_1, and 112_2 performs the same operation at different times, the operation may be inconsistent, thus leading to problems such as insufficient margin in semiconductor device 100 and reduced speed.

[0040] The delay control circuit 150_2 can delay the preparatory signal A_2 to generate the internal strobe signal IDQS_2 by using a delay value determined based on the calibration code CAL_CODE_2<0:k>. The delay control circuit 150_2 can be a circuit used to compensate for the delay value difference between paths PATH_0, PATH_1 and PATH_2 of chips 112_0, 112_1 and 112_2.

[0041] The calibration codes CAL_CODE_0<0:k>, CAL_CODE_1<0:k>, and CAL_CODE_2<0:k> for each of chips 112_0, 112_1, and 112_2 can be generated as different values. Therefore, since the delay values ​​of delay control circuits 150_0, 150_1, and 150_2 are also set differently, the difference in delay values ​​of paths PATH_0, PATH_1, and PATH_2 can be compensated. As a result of calibrating the delay values ​​of delay control circuits 150_0 to 150_2 using calibration codes CAL_CODE_0<0:k>, CAL_CODE_1<0:k>, and CAL_CODE_2<0:k>, the following relationship can be obtained: the sum of the delay value of path PATH_0 of chip 112_0 and the delay value of delay control circuit 150_0 = the sum of the delay value of path PATH_1 of chip 112_1 and the delay value of delay control circuit 150_1 = the sum of the delay value of path PATH_2 of chip 112_2 and the delay value of delay control circuit 150_2. Consequently, the delay values ​​experienced intentionally or unintentionally by each chip 112_0, 112_1, and 112_2 during the generation of internal strobe signals IDQS_0, IDQS_1, and IDQS_2 from the source signal PDQS can be the same.

[0042] The calibration circuit 170_2 can generate a calibration code CAL_CODE_2<0:k> based on the signals SDQ0_2, SDQ1_2, and SDQ2_2 provided by the test signal providing circuit 160_2. The calibration circuit 170_2 can generate a calibration code CAL_CODE_2<0:k> corresponding to the difference in delay value between the transmission path with the largest delay value among the transmission paths PATH_0, PATH_1, and PATH_2 and the transmission path PATH_2.

[0043] When the delay value of transmission path PATH_0 is X, the delay value of transmission path PATH_1 is Y, the delay value of transmission path PATH_2 is Z, and Y is the largest among X, Y, and Z, the calibration code CAL_CODE_0<0:k> can be generated as the difference between the delay values ​​Y and X. Similarly, the calibration code CAL_CODE_1<0:k> can be generated as the difference between the delay values ​​Y and Y, and the calibration code CAL_CODE_2<0:k> can be generated as the difference between the delay values ​​Z and Y.

[0044] The test signal providing circuit 160_2 provides the signals SDQ0_2, SDQ1_2, and SDQ2_2 required to generate the calibration code CAL_CODE_2<0:k> for the calibration circuit 170_2. (Refer to...) Figure 2 Describe in detail the structure and operation of the test signal providing circuit 160_2.

[0045] ID allocation circuit 140_2 can generate chip ID CID_2<0:1> based on the initial ID SID transmitted through the third normal pass-through electrode TSV_ID. Chip ID CID_2<0:1> can be an ID used to distinguish chips 112_0, 112_1 and 112_2 from each other.

[0046] The ID allocation circuits 140_0, 140_1, and 140_2 of chips 112_0, 112_1, and 112_2 can generate different chip IDs CID_0<0:1>, CID_1<0:1>, and CID_2<0:1>. The ID allocation circuits 140_0, 140_1, and 140_2 can generate sequentially increasing chip IDs CID_0<0:1>, CID_1<0:1>, and CID_2<0:1> based on the initial ID SID transmitted through the third normal through electrode. For example, chip 112_0 can generate a chip ID CID_0<0:1> of '00' based on the initial ID SID, and chip 112_1 can generate a chip ID CID_1<0:1> of '01' by incrementing the initial ID SID by +1. Chip 112_2 can generate a chip ID of '10', CID_2<0:1>, by incrementing the initial ID SID by +2.

[0047] Despite Figure 1The diagram shows three chips 112_0, 112_1, and 112_2 stacked on chip 114, which serves as an interface. However, it will be apparent to those skilled in the art that the number of chips may differ. For example, four or eight chips may be stacked on chip 114. Furthermore, the present invention is proposed to compensate for different process variations between chips, and it can be applied not only to semiconductor devices comprising stacked chips but also to semiconductor devices comprising multiple laterally formed chips (e.g., chiplet structures).

[0048] Figure 2 This is a detailed illustration of the embodiments of the present invention. Figure 1 The diagram shows the block diagram of the structure related to the generation of calibration codes CAL_CODE_0<0:k>, CAL_CODE_1<0:k>, and CAL_CODE_2<0:k>.

[0049] Reference Figure 2 The test signal providing circuits 160_0, 160_1, and 160_2 of chips 112_0, 112_1, and 112_2 may respectively include receivers RX3_0, RX3_1, and RX3_2, replication circuits 250_0, 250_1, and 250_2, and driving circuits 260_0, 260_1, and 260_2.

[0050] Receivers RX3_0, RX3_1 and RX3_2 can receive the test source signal TPDQS transmitted through the first test through electrode TSV_TDQS.

[0051] The replication circuits 250_0, 250_1, and 250_2 can generate test signals REP_OUT_0, REP_OUT_1, and REP_OUT_2 by delaying the test source signals received by receivers RX3_0, RX3_1, and RX3_2. The replication circuits 250_0, 250_1, and 250_2 can be designed by replicating the delay values ​​of paths PATH_0, PATH_1, and PATH_2. Replication circuit 250_0 can be designed to have the same delay value as path PATH_0, and replication circuit 250_1 can be designed to have the same delay value as path PATH_1. Replication circuit 250_2 can be designed to have the same delay value as path PATH_2. Furthermore, the delay between the test source signal TPDQS and the test signal REP_OUT_0 can be the same as the delay between the source signal PDQS and the preparatory signal A_0. Similarly, the delay between the test source signal TPDQS and the test signal REP_OUT_1 can be the same as the delay between the source signal PDQS and the preparatory signal A_1, and the delay between the test source signal TPDQS and the test signal REP_OUT_2 can be the same as the delay between the source signal PDQS and the preparatory signal A_2.

[0052] Driver circuits 260_0, 260_1, and 260_2 can transmit test signals REP_OUT_0, REP_OUT_1, and REP_OUT_2 to different chips, and receive test signals REP_OUT_0, REP_OUT_1, and REP_OUT_2 from different chips. Driver circuit 260_0 can transmit test signal REP_OUT_0 to other chips 120_1 and 120_2 through the second test pass-through electrode TSV_TDQ0, driver circuit 260_1 can transmit test signal REP_OUT_1 to other chips 120_0 and 120_2 through the second test pass-through electrode TSV_TDQ1, and driver circuit 260_2 can transmit test signal REP_OUT_2 to other chips 120_0 and 120_1 through the second test pass-through electrode TSV_TDQ2. Additionally, drive circuits 260_0, 260_1, and 260_2 can receive test signals REP_OUT_0, REP_OUT_1, and REP_OUT_2 loaded on the second test through electrodes TSV_TDQ0, TSV_TDQ1, and TSV_TDQ2, and provide them to calibration circuits 170_0, 170_1, and 170_2.

[0053] The activated transmitters and receivers in the drive circuits 260_0, 260_1, and 260_2 are marked with black triangles. As a result, the test signal REP_OUT_0 can be transmitted as signals SDQ0_0, SDQ0_1, and SDQ0_2; the test signal REP_OUT_1 can be transmitted as signals SDQ1_0, SDQ1_1, and SDQ1_2; and the test signal REP_OUT_2 can be transmitted as signals SDQ2_0, SDQ2_1, and SDQ2_2. That is, through the operation of the drive circuits 260_0, 260_1, and 260_2, the calibration circuits 170_0, 170_1, and 170_2 can receive output signals not only from replication circuits of the same chip but also from replication circuits of different chips.

[0054] Since the test signals REP_OUT_0, REP_OUT_1, and REP_OUT_2 of chips 112_0, 112_1, and 112_2 are simultaneously transmitted to the calibration circuits 170_0, 170_1, and 170_2 of chips 112_0, 112_1, and 112_2 through the operation of the driving circuits 260_0, 260_1, and 260_2, the calibration circuits 170_0, 170_1, and 170_2 of chips 112_0, 112_1, and 112_2 can simultaneously generate calibration codes CAL_CODE_0<0:k>, CAL_CODE_1<0:k>, and CAL_CODE_2<0:k>. Because the operations for generating calibration codes CAL_CODE_0<0:k>, CAL_CODE_1<0:k>, and CAL_CODE_2<0:k> are performed in parallel, calibration codes CAL_CODE_0<0:k>, CAL_CODE_1<0:k>, and CAL_CODE_2<0:k> can be generated quickly.

[0055] Figure 3 This is a detailed illustration of embodiments according to the present invention. Figure 1 The schematic diagram shows the driving circuit 260_2 of the chip 112_2.

[0056] Reference Figure 3 The driving circuit 260_2 may include an activation control circuit 310, transmitters DRV0, DRV1 and DRV2, and receivers RCV0, RCV1 and RCV2.

[0057] The activation control circuit 310 can decode chip ID CID_2<0:1> to activate one of the drive enable signals EN0, EN1, and EN2. The activation control circuit 310 may include inverters INV1 and INV2, AND gates AD1 and AD2, and NOR gate NR1. The activation control circuit 310 can activate the drive enable signal EN0 when chip ID CID_2<0:1> is '00', activate the drive enable signal EN1 when chip ID CID_2<0:1> is '01', and activate the drive enable signal EN2 when chip ID CID_2<0:1> is '10'. Since the chip ID CID_2<0:1> of chip 112_2 is '10', the drive enable signal EN2 can be activated.

[0058] Since the drive enable signal EN2 is activated in the drive circuit 260_2 of chip 112_2, transmitter DRV2 can be activated to transmit the test signal REP_OUT_2 to the second test pass-through electrode TSV_TDQ2. Receivers RCV0, RCV1, and RCV2 can all be activated to receive signals from the second test pass-through electrodes RSV_TDQ0, TSV_TDQ1, and TSV_TDQ2 and transmit them to the calibration circuit 170_2.

[0059] In the driving circuit 260_0 of chip 112_0, the drive enable signal EN0 can be activated to activate transmitter DRV0, and transmitter DRV0 can transmit the test signal REP_OUT_0 to the second test pass-through electrode TSV_TDQ0. Additionally, in the driving circuit 260_1 of chip 112_1, the drive enable signal EN1 can be activated to activate transmitter DRV1, and transmitter DRV1 can transmit the test signal REP_OUT_1 to the second test pass-through electrode TSV_TDQ1.

[0060] Figure 4 This illustrates an embodiment of the present invention. Figure 2 A block diagram of calibration circuit 170_x is provided. In the following text, x can be one of 0, 1, and 2. That is, calibration circuit 170_x can be one of calibration circuits 170_0, 170_1, and 170_2.

[0061] Reference Figure 4 The calibration circuit 170_x may include a selection circuit 410 and a code generation circuit 420.

[0062] In each of chips 120_0, 120_1, and 120_2, selection circuit 410 can select one of test signals SDQ0_x, SDQ1_x, and SDQ2_x as a reference signal STR according to chip ID CID_x<0:1>, and select other test signals as detection signals DS0 and DS1. Selection circuit 410 can select the test signal of the chip including itself as the reference signal STR, and can select the test signal of other chips as the detection signals DS0 and DS1. For example, selection circuit 410 of chip 112_0 can select test signal SDQ0_0 as the reference signal STR, and selection circuit 410 of chip 112_1 can select test signal SDQ1_1 as the reference signal STR. Selection circuit 410 of chip 112_2 can select test signal SDQ2_2 as the reference signal STR.

[0063] The code generation circuit 420 can generate a calibration code CAL_CODE_x<0:k> based on the difference between the delay values ​​between the reference signal STR and the detection signals DS0 and DS1.

[0064] Figure 5 This illustrates an embodiment of the present invention. Figure 4 A schematic diagram of the selection circuit 410. Figure 6 This is a table illustrating the operation of the selection circuit 410 according to an embodiment of the present invention.

[0065] Reference Figure 5 The selection circuit 410 may include multiplexers S00 to S12. Multiplexers S00 to S02 may be defined as upper multiplexers. Upper multiplexers S00 to S02 may be based on the first bit of the chip ID CID_x<0:1>. <0> This is used to select and output one of the test signals SDQ0_x, SDQ1_x, and SDQ2_x. Multiplexers S10 to S12 can be defined as lower multiplexers. Lower multiplexers S10 to S12 can be based on the second bit of the chip ID CID_x<0:1>. <1> Select one of the outputs of the upper multiplexer S00 to S02, and output the reference signal STR, the first detection signal DS0, and the second detection signal DS1 respectively.

[0066] Specifically, the multiplexer S00 can be based on the first bit CID_x <0> Select one of the test signals SDQ0_x and SDQ1_x. For example, multiplexer S00 can select CID_x in the first bit. <0> When the logic level is low, the test signal SDQ0_x is selected, and the first bit CID_x is selected. <0> When the logic level is high, the test signal SDQ1_x is selected.

[0067] Multiplexer S01 can be based on the first bit CID_x <0> Select one of the test signals SDQ1_x and SDQ2_x. For example, multiplexer S01 can select one of the first bits, CID_x. <0> When the logic level is low, the test signal SDQ1_x is selected, and the first bit CID_x is selected. <0> When the logic level is high, the test signal SDQ2_x is selected.

[0068] Multiplexer S02 can be based on the first bit CID_x <0> Select one of the test signals SDQ2_x and SDQ0_x. For example, multiplexer S02 can select one of the first bits, CID_x. <0> When the logic level is low, the test signal SDQ2_x is selected, and the first bit CID_x is selected. <0> When the logic level is high, the test signal SDQ0_x is selected.

[0069] Multiplexer S10 can be based on the second bit CID_x <1> Select one of the outputs of multiplexer S00 and multiplexer S02 and output it as the reference signal STR. For example, multiplexer S10 can select the second bit CID_x. <1> When the logic level is low, the output of the multiplexer S00 is selected, and the second bit CID_x is selected. <1> When the logic level is high, the output of multiplexer S02 is selected.

[0070] Multiplexer S11 can be based on the second bit CID_x <1> Select one of the outputs of multiplexer S01 and multiplexer S00 and output it as the detection signal DS0. For example, multiplexer S11 can select the second bit CID_x. <1> When the logic level is low, the output of multiplexer S01 is selected, and the second bit CID_x is selected. <1> When the logic level is high, the output of the multiplexer S00 is selected.

[0071] Multiplexer S12 can be based on the second bit CID_x <1> Select one of the outputs of multiplexer S02 and multiplexer S01 and output it as the detection signal DS1. For example, multiplexer S12 can select the second bit CID_x. <1> When the logic level is low, the output of multiplexer S02 is selected, and the second bit CID_x is selected. <1> When the logic level is high, the output of the multiplexer S01 is selected.

[0072] Reference Figure 6 When the chip ID signal CID_x<0:1> is “00”, the selection circuit 410 of chip 112_0 can select the test signal SDQ0_0 as the reference signal STR, and output the test signal SDQ1_0 and the test signal SDQ2_0 as the detection signal DS0 and the detection signal DS1 respectively.

[0073] When the chip ID signal CID_x<0:1> is “01”, the selection circuit 410 of chip 112_1 can select the test signal SDQ1_1 as the reference signal STR, and output the test signal SDQ2_1 and the test signal SDQ0_1 as the detection signal DS0 and the detection signal DS1 respectively.

[0074] When the chip ID signal CID_x<0:1> is “10”, the selection circuit 410 of chip 112_2 can select the test signal SDQ2_2 as the reference signal STR, and output the test signal SDQ0_2 and the test signal SDQ1_2 as the detection signal DS0 and the detection signal DS1 respectively.

[0075] Figure 7 This illustrates an embodiment of the present invention. Figure 4 The block diagram of the code generation circuit 420 is shown.

[0076] Reference Figure 7 The code generation circuit 420 may include time-to-digital conversion circuits 710 and 730 and a decoder 750.

[0077] The first time-to-digital converter circuit 710 can generate multiple first delayed reference signals SRD0<0:n> by sequentially delaying the reference signal STR, and generate a first digital code OUT0<0:n> by performing a time-to-digital conversion (TDC) operation to trigger the detection signal DS0 based on the first delayed reference signals SRD0<0:n>. The second time-to-digital converter circuit 730 can generate multiple second delayed reference signals SRD1<0:n> by sequentially delaying the reference signal STR, and generate a second digital code OUT1<0:n> by performing a time-to-digital conversion (TDC) operation to trigger the detection signal DS1 based on the second delayed reference signals SRD1<0:n>. The first digital code OUT0<0:n> can be a code corresponding to the delay amount between the reference signal STR and the detection signal DS0, and it can represent a skew caused by process variations between the chip providing the reference signal STR and the chip providing the detection signal DS0. Similarly, the second digital code OUT1<0:n> can be a code corresponding to the amount of delay between the reference signal STR and the detection signal DS1, and it can represent the skew caused by the process variation between the chip providing the reference signal STR and the chip providing the detection signal DS1.

[0078] For reference, the code generation circuit 420 may include a time-to-digital conversion circuit corresponding to the number of detection signals, and the number of detection signals may vary depending on the number of chips stacked in the semiconductor device 100.

[0079] The first time-to-digital converter circuit 710 may include a first delay circuit 712 and a first trigger circuit 714, and the second time-to-digital converter circuit 730 may include a second delay circuit 732 and a second trigger circuit 734. The second time-to-digital converter circuit 730 may have substantially the same structure as the first time-to-digital converter circuit 710. (Refer to...) Figures 8 to 10 Describe the detailed structure and operation of the first-time digital conversion circuit 710.

[0080] Decoder 750 can generate calibration code CAL_CODE_x<0:k> based on the first digital code OUT0<0:n> and the second digital code OUT1<0:n>. For example, decoder 750 can generate delay code (which is...) based on the first digital code OUT0<0:n> and the second digital code OUT1<0:n>. Figure 11 The generated delay code TOUT<0:n> can be converted and output as a calibration code CAL_CODE_x<0:k> (which is a binary code). Refer to... Figures 11 to 13 This describes the detailed structure and operation of decoder 750. The calibration end signal CAL_ENB can be used to fix the value of the calibration code CAL_CODE_x<0:k>. When the calibration operation used to generate the calibration code CAL_CODE_x<0:k> ends, the calibration end signal CAL_ENB can go high. Here, decoder 750 can fix the value of the calibration code CAL_CODE_x<0:k>.

[0081] Figure 8 This illustrates an embodiment of the present invention. Figure 7 A schematic diagram of the first-time digital conversion circuit 710, and Figure 9 and Figure 10 This is a timing diagram illustrating the operation of the first time-to-digital converter circuit 710 according to an embodiment of the present invention.

[0082] Reference Figure 8 The first-time digital conversion circuit 710 may include a first delay circuit 812 (corresponding to...) Figure 7 The first delay circuit 712) and the first trigger circuit 814 (corresponding to) Figure 7The first trigger circuit 714). The first delay circuit 812 may include a plurality of unit delayers 812_0 to 812_n. The unit delayers 812_0 to 812_n can generate a plurality of first delayed reference signals STRD0<0:n> by sequentially delaying the reference signal STR. The unit delayers 812_0 to 812_n may have the same structure. For example, the first unit delayer 812_0 may include a cascaded first NAND gate ND1 and a second NAND gate ND2 and a buffer B1. The first NAND gate ND1 may receive the reference signal STR and the power supply voltage VDD, and the second NAND gate ND2 may receive the output of the first NAND gate ND1 and the power supply voltage VDD. Therefore, the first unit delayer 812_0 can generate the first delayed reference signal STRD0 by delaying the reference signal STR by up to the delay time D1 of the first NAND gate ND1 and the second NAND gate ND2. <0> Similarly, the second unit delay unit 812_1 can generate the first delayed reference signal STRD0 by delaying the reference signal STR by up to a delay time D1*2. <1> In this way, the first delay circuit 812 can generate the first delayed reference signal STRD0<0:n> by sequentially delaying the reference signal STR by up to delay time D1, delay time D1*2, ..., delay time D1*(n+1).

[0083] The first trigger circuit 814 can generate the first digital code OUT0<0:n> by triggering the logic level of the detection signal DS0 synchronously with the rising edge of the first delayed reference signal STRD0<0:n>. The first trigger circuit 814 may include a plurality of flip-flops 814_0 to 814_n that latch the first detection signal DS0 based on the first delayed reference signal STRD0<0:n> and output it as the first digital code OUT0<0:n>.

[0084] According to an embodiment of the present invention, the first time-to-digital conversion circuit 710 may further include a buffer circuit 816 for buffering the detection signal DS0. The buffer circuit 816 may be provided to compensate for the loading caused by the plurality of flip-flops 814_0 to 814_n of the first trigger circuit 814, and may be implemented as an even number of inverters coupled in series with each other.

[0085] With the above structure, the first time-to-digital converter 710 can generate a plurality of first delayed reference signals STRD0<0:n> that are activated sequentially at intervals of a predetermined time D1 after the pulse formation of the reference signal STR, and can generate the first digital code OUT0<0:n> by triggering the logic level of the detection signal DS0 synchronously with the rising edge of the first delayed reference signal STRD0<0:n>.

[0086] Reference Figure 9The diagram illustrates a case where the pulse formation of the reference signal STR is faster than that of the detection signal DS0. The first-time digital conversion circuit 710 can output the corresponding bits of the first digital code OUT0<0:n> as low bits during the low segment of the detection signal DS0, and output the corresponding bits of the first digital code OUT0<0:n> as high bits during the high segment of the detection signal DS0. In this case, the most significant bit (MSB) of the first digital code OUT0<0:n> can be set as a low bit, and the number of low bits preceding the first high bit of the first digital code OUT0<0:n> (i.e., before the high segment of the detection signal DS0) can correspond to the delay value of the detection signal relative to the reference signal STR.

[0087] Reference Figure 10 The diagram illustrates a case where the pulse formation of the detection signal DS0 is faster than that of the reference signal STR. The first-time digital conversion circuit 710 can output the corresponding first digital code OUT0<0:n> as a high bit during the high segment of the detection signal DS0, and output the corresponding first digital code OUT0<0:n> as a low bit during the low segment of the detection signal DS0. In this case, the MSB of the first digital code OUT0<0:n> can be set to a high bit, and the delay value of the detection signal DS0 relative to the reference signal STR can be zero (“0”).

[0088] Figure 11 This illustrates an embodiment of the present invention. Figure 7 Block diagram of decoder 750. Figure 12 This illustrates an embodiment of the present invention. Figure 11 A schematic diagram showing the detailed structure of the delay calculation circuit 1110. Figure 13 This is an explanation of the embodiments of the present invention. Figure 11 The table shows the operation of the encoding circuit 1120.

[0089] Reference Figure 11 The decoder 750 may include a delay calculation circuit 1110 and an encoding circuit 1120.

[0090] The delay calculation circuit 1110 can calculate the delay code TOUT<0:n> based on the first digital code OUT0<0:n> and the second digital code OUT1<0:n>. The delay calculation circuit 1110 can select the detection signal DS0 or DS1 that has a larger delay relative to the reference signal STR based on the first digital code OUT0<0:n> and the second digital code OUT1<0:n>, and output the digital code corresponding to the selected detection signal as the delay code TOUT<0:n>. The delay code TOUT<0:n> can correspond to the larger delay value between the delay value of the detection signal DS0 relative to the reference signal STR and the delay value of the detection signal DS1 relative to the reference signal STR.

[0091] Reference Figure 12 The delay calculation circuit 1110 may include multiple AND gates AD00 to AD0n and multiple OR gates OR00 to OR0n.

[0092] AND gates AD00 to AD0n and OR gates OR00 to OR0n correspond to the corresponding bits of the first digital code OUT0<0:n> and the second digital code OUT1<0:n>. AND gates AD00 to AD0n perform a logical AND operation on the corresponding bits of the first digital code OUT0<0:n> and the second digital code OUT1<0:n>. OR gates OR00 to OR0n perform a logical OR operation on the output of the corresponding AND gate and the output of the previous stage OR gate, and output a delay code TOUT<0:n>. The first-stage OR gate OR00 receives the output of the corresponding AND gate AD00 and the ground voltage GND signal.

[0093] With the above structure, the delay calculation circuit 1110 can output the corresponding delay code TOUT<0:n> as a high bit only when both the bits of the first digital code OUT0<0:n> and the bits of the second digital code OUT1<0:n> are high bits. When at least one of the bits of the first digital code OUT0<0:n> and the bits of the second digital code OUT1<0:n> is a low bit, the delay calculation circuit 1110 can determine the corresponding delay code TOUT<0:n> based on the lower bits of the delay code TOUT<0:n>. Furthermore, when the lower bits of the delay code TOUT<0:n> are high bits, the upper bits of the delay code TOUT<0:n> can also all be high bits. As a result, the delay calculation circuit 1110 can generate a thermometer code type (i.e., unary code) delay code TOUT<0:n>.

[0094] For example, when the first digital code OUT0<0:n> of “00011111” and the second digital code OUT1<0:n> of “00000111” are input, the delay calculation circuit 1110 can generate a delay code TOUT<0:n> of “00000111” corresponding to the second digital code OUT1<0:n> with a large delay value. For example, when the first digital code OUT0<0:n> of “11100000” and the second digital code OUT1<0:n> of “00001111” are input, the delay calculation circuit 1110 can generate a delay code TOUT<0:n> of “00001111” corresponding to the second digital code OUT1<0:n> with a large delay value. For example, when the first digital code OUT0<0:n> of “11100000” and the second digital code OUT1<0:n> of “1100000” are input, the delay calculation circuit 1110 can generate the delay code TOUT<0:n> of “111111111” with a delay value corresponding to zero.

[0095] Return to reference Figure 11 The encoding circuit 1120 can convert the delay code TOUT<0:n> into the calibration code CAL_CODE_x<0:k> as a binary code, and output the calibration code CAL_CODE_x<0:k>. When the calibration end signal CAL_ENB is at a logic high level, the encoding circuit can fix the value of the calibration code CAL_CODE_x<0:k>.

[0096] Reference Figure 13 The diagram illustrates a 4-bit calibration code CAL_CODE_x<0:3> based on an 8-bit delay code TOUT<0:7>. Since the delay code TOUT<0:7> is a thermometer code type, the 8-bit delay code TOUT<0:7> can have nine possible cases. For example, when a delay code TOUT<0:n> with all high bits (“11111111”) is input, the encoding circuit 1120 can generate a preliminary calibration code PRE_CAL_CODE<0:k> with all zero bits (“0000”), and the calibration code CAL_CODE_x<0:3> can increase as the number of low bits in the delay code TOUT<0:n> increases. Finally, when a delay code TOUT<0:n> with all low bits (“00000000”) is input, the encoding circuit 1120 can generate a 4-bit calibration code CAL_CODE_x<0:k> with a maximum value of “1000”.

[0097] With the above structure, as the number of low bits of the delay code TOUT<0:n> increases, the encoding circuit 1120 can generate the calibration code CAL_CODE_x<0:k> with a larger value.

[0098] Figure 14 This is a timing diagram illustrating the calibration operation of a semiconductor device 100 according to an embodiment of the present invention.

[0099] Reference Figure 14 During the calibration operation, the test source signal TPDQS can be generated in chip 114 and transmitted to the first test through electrode TSV_TDQS.

[0100] The replication circuits 250_0, 250_1, and 250_2 of chips 112_0, 112_1, and 112_2 can delay and output the test source signal TPDQS with delay values ​​of paths PATH_0, PATH_1, and PATH_2. The test signals REP_OUT_0, REP_OUT_1, and REP_OUT_2 generated by the replication circuits 250_0, 250_1, and 250_2 can be provided to chips 112_0, 112_1, and 112_2 via drive circuits 260_0, 260_1, and 260_2. The test signals provided to chip 112_0 are labeled SDQ0_0, SDQ1_0, and SDQ2_0, and the test signals provided to chip 112_1 are labeled SDQ0_1, SDQ1_1, and SDQ2_1. The test signals provided to chip 112_2 are labeled as SDQ0_2, SDQ1_2, and SDQ2_2.

[0101] Here, the operating characteristic of chip 112_0 is FAST, the operating characteristic of chip 112_1 is TYPICAL, and the operating characteristic of chip 112_2 is SLOW. The delay of the pulse formation of the test signal SDQ0_0 generated in chip 112_0 relative to the pulse formation of the test source signal TPDQS is +10, the delay of the pulse formation of the test signal SDQ1_1 generated in chip 112_1 relative to the pulse formation of the test source signal TPDQS is +13, and the delay of the pulse formation of the test signal SDQ2_2 generated in chip 112_2 relative to the pulse formation of the test source signal TPDQS is +15.

[0102] The calibration circuit 170_0 of chip 112_0 can select the test signal SDQ0_0 as the reference signal STR. The calibration circuit 170_0 can trigger the detection signal DS0 to generate a first digital code OUT0<0:n> by using a first delayed reference signal STRD0<0:n> generated by sequentially delaying the selected reference signal STR, and trigger the detection signal DS1 to generate a second digital code OUT1<0:n> by using a second delayed reference signal STRD1<0:n> generated by sequentially delaying the selected reference signal STR. The calibration circuit 170_0 can output a calibration code CAL_CODE_0<0:k> based on the first digital code OUT0<0:n> and the second digital code OUT1<0:n>.

[0103] Since the selected reference signal STR is +3 faster than the detection signal DS0 and +5 faster than the detection signal DS1, the calibration circuit 170_0 can generate a calibration code CAL_CODE_0<0:k> corresponding to the +5 delay value. Therefore, during the read operation, the delay control circuit 150_0 of chip 112_0 can delay the signal provided by path PATH_0 by the +5 delay value corresponding to the calibration code CAL_CODE_0<0:k> to generate the internal strobe signal IDQS_0.

[0104] On the other hand, the calibration circuit 170_1 of chip 112_1 can select the test signal SDQ1_1 as the reference signal STR. Since the selected reference signal STR is +2 faster than the detection signal DS0 but slower than the detection signal DS1, the calibration circuit 170_1 can generate a calibration code CAL_CODE_1<0:k> corresponding to the +2 delay value. Therefore, during the read operation, the delay control circuit 150_1 of chip 112_1 can delay the signal provided by path PATH_1 by the +2 delay value corresponding to the calibration code CAL_CODE_1<0:k> to generate the internal strobe signal IDQS_1.

[0105] The calibration circuit 170_2 of chip 112_2 can select the test signal SDQ2_2 as the reference signal STR. Since the selected reference signal STR is slower than the detection signals DS0 and DS1, the calibration circuit 170_2 can generate a calibration code CAL_CODE_2<0:k> corresponding to a delay value of 0. Therefore, during a read operation, the delay control circuit 150_2 of chip 112_2 can generate the signal provided through path PATH_2 as the internal strobe signal IDQS_2 without any delay.

[0106] Figure 15 This is a block diagram illustrating a storage system 1500 according to an embodiment of the present invention.

[0107] Reference Figure 15 The storage system 1500 may include a memory 1510, a processor 1520, an intermediate 1530, and a packaging substrate 1540 formed by stacking multiple chips 1514 and 1512_0 to 1512_3.

[0108] Intermediate 1530 may be formed on package substrate 1540, and memory 1510 and processor 1520 may be formed on intermediate 1530.

[0109] Processor 1520 may include memory controller (MC) 1521 and PHY interface 1522 for interfacing with memory controller 1521. PHY interface 1522 may be used by memory controller 1521 to communicate with memory 1510. Processor 1520 may be one of various processors, such as graphics processing unit (GPU), central processing unit (CPU), and application processor (AP).

[0110] The memory 1510 may include a base die 1514 and core dies 1512_0 to 1512_3 stacked on the base die 1514. The chip 114 of the semiconductor device 100 described above may correspond to the base die 1514, and the chips 112_0, 112_1, and 112_2 may correspond to the core dies 1512_0 to 1512_3. Figure 1 The structure may be included in the base die 1514 and the core dies 1512_0 to 1512_3. An example of the memory 1510 formed by stacking multiple chips as described above may be a high-bandwidth memory (HBM).

[0111] Each of the core dies 1512_0 to 1512_3 may include: a cell array for storing data, and circuitry for writing data to and reading data from the cell array. The base die 1514 may include circuitry for interfacing between the core dies 1512_0 to 1512_3 and the base die 1514, and circuitry for interfacing between the base die 1514 and the memory controller 1521. The base die 1514 may also be referred to as the base die. Multiple through-silicon vias (TSVs) may be formed between the stacked core dies 1512_0 to 1512_3, and commands, addresses, and data can be transferred between the core dies 1512_0 to 1512_3 and the base die 1514 through the TSVs.

[0112] The PHY interface 1516 of the base die 1514 can serve as an interface for communication between the base die 1514 and the memory controller 1521, and the Direct Access (DA) interface 1517 can serve as an interface for testing the memory 1510. The PHY interface 1516 can be coupled to an intermediary 1530 via microbumps, and the intermediary 1530 can electrically connect the PHY interface 1516 of the base die 1514 to the PHY interface 1522 of the memory controller 1521 via internal interconnects (not shown). Additionally, the PHY interfaces 1516 and 1522 can be electrically connected to each other via the intermediary 1530 for communication. The PHY interface 1516 can be coupled to the intermediary 1530 via more than 1000 microbumps. Due to the very large physical number of microbumps, testing the memory 1510 using the PHY interface 1516 is practically very difficult. Therefore, the DA interface 1517, which is directly accessed and mated to the pads, can be used to test the memory 1510. The number of directly accessed pads is relatively smaller than the number of microbumps and their physical size is relatively larger than the physical size of the microbumps.

[0113] The package substrate 1540 may include solder balls for supplying power to the memory 1510 and the processor 1520, as well as solder balls enabling the processor 1520 to communicate with external devices (e.g., other chips on a graphics card). The package substrate 1540 may be coupled to, for example, a graphics card.

[0114] According to embodiments of the present invention, process variations between multiple chips can be reduced.

[0115] The effects expected in the embodiments of the present invention are not limited to those mentioned above, and those skilled in the art to which the present invention pertains can clearly understand from the description other effects not mentioned above.

[0116] Although the invention has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.

[0117] For example, the location and type of the logic gates and transistors exemplarily described in the above embodiments of this disclosure should be implemented differently depending on the polarity of the input signal. Furthermore, embodiments can be combined to form additional embodiments.

Claims

1. A semiconductor device, comprising: The first transmission path is suitable for: receiving the source signal and outputting the first preparatory signal; The second transmission path is adapted to: receive the source signal and output a second preparatory signal; The third transmission path is suitable for: receiving the source signal and outputting a third preparatory signal; A first calibration circuit is adapted to generate a first calibration code, the first calibration code corresponding to the difference in delay value between the first transmission path and the selected transmission path with the maximum delay value among the first transmission path to the third transmission path. A second calibration circuit is adapted to generate a second calibration code, the second calibration code corresponding to the difference in delay value between the second transmission path and the selected transmission path; A third calibration circuit is adapted to generate a third calibration code, the third calibration code corresponding to the difference in delay values ​​between the third transmission path and the selected transmission path; A first delay control circuit is adapted to generate a first signal by delaying the first preparatory signal with a delay value determined based on the first calibration code; The second delay control circuit is adapted to generate the second signal by delaying the second preparatory signal with a delay value determined based on the second calibration code; as well as A third delay control circuit is adapted to generate a third signal by delaying the third preparatory signal with a delay value determined based on the third calibration code.

2. The semiconductor device according to claim 1, further comprising: The first chip is adapted to use the first signal as a strobe signal for outputting data of the first chip, and includes the first transmission path, the first calibration circuit and the first delay control circuit. The second chip is adapted to use the second signal as a strobe signal for outputting data of the second chip, and includes the second transmission path, the second calibration circuit and the second delay control circuit; as well as The third chip is adapted to use the third signal as a strobe signal for outputting data of the third chip, and includes the third transmission path, the third calibration circuit and the third delay control circuit.

3. The semiconductor device of claim 2, wherein, The first chip, the second chip, and the third chip are stacked.

4. The semiconductor device according to claim 2, wherein The first chip also includes: A first replication circuit is adapted to: simulate the delay value of the first transmission path, and generate a first test signal using a delay test source signal; and A first transmitter is adapted to transmit the first test signal to the second chip and the third chip, and The second chip also includes: The second replication circuit is adapted to: simulate the delay value of the second transmission path, and generate a second test signal by delaying the test source signal; and A second transmitter is adapted to transmit the second test signal to the first chip and the third chip, and The third chip also includes: A third replication circuit is adapted to: simulate the delay value of the third transmission path, and generate a third test signal by delaying the test source signal; and A third transmitter is adapted to transmit the third test signal to the first chip and the second chip.

5. The semiconductor device according to claim 4, wherein The first calibration circuit includes: A first-time digital conversion circuit is adapted to generate a first digital code corresponding to the amount of delay between the first test signal and the second test signal; A second time-to-digital converter circuit is adapted to generate a second digital code corresponding to the amount of delay between the first test signal and the third test signal; and A first decoder is adapted to generate a first calibration code corresponding to the larger of the first and second digital codes. The second calibration circuit includes: A third time-to-digital converter circuit is adapted to generate a third digital code corresponding to the amount of delay between the second test signal and the first test signal; A fourth time-to-digital converter circuit is adapted to generate a fourth digital code corresponding to the amount of delay between the second test signal and the third test signal; and The second decoder is adapted to generate the second calibration code corresponding to the larger of the third and fourth digital codes, and The third calibration circuit includes: The fifth time-to-digital converter circuit is adapted to generate a fifth digital code corresponding to the amount of delay between the third test signal and the first test signal; A sixth time-to-digital converter circuit is adapted to generate a sixth digital code corresponding to the amount of delay between the third test signal and the second test signal; and The third decoder is adapted to generate the third calibration code corresponding to the larger of the fifth and sixth digital codes.

6. A semiconductor device comprising a plurality of stacked chips having different chip IDs, each chip comprising: The transmission path is suitable for: transmitting the source signal transmitted via the first normal through electrode, and outputting a preparatory signal; A delay control circuit is adapted to generate an internal strobe signal by delaying the preparatory signal with a delay value determined based on a calibration code; The replication circuit is adapted to: simulate the delay value of the transmission path, and generate a test signal by delaying the test source signal transmitted via the first test through electrode; A driving circuit is adapted to transmit the generated test signal to the second test through electrode corresponding to the chip ID in the second test through electrode. as well as The calibration circuit is adapted to generate the calibration code based on the generated test signal and the test signal transmitted from other chips via the second test pass electrode.

7. The semiconductor device of claim 6, wherein, Each of the chips also includes a data output circuit adapted to output data of the chip to a second normal pass-through electrode based on the internal strobe signal.

8. The semiconductor device according to claim 6, It also includes a lower chip located at the lower end of the chip. in, Each of the chips also includes an ID allocation circuit adapted to generate a corresponding chip ID from the chip IDs based on an initial ID transmitted from the lower chip.

9. The semiconductor device according to claim 6, wherein, The driving circuit includes: Multiple transmitters, adapted to drive the test signal to the second test pass-through electrode in response to multiple drive enable signals; and Multiple receivers are adapted to: receive the test signal transmitted from the other chip via the second test through electrode, and to transmit the received test signal to the calibration circuit.

10. The semiconductor device according to claim 9, wherein, The driving circuit further includes an activation control circuit, which is adapted to: generate the driving enable signal by decoding the chip ID, and activate the driving enable signal corresponding to the chip ID among the driving enable signals.

11. The semiconductor device according to claim 6, wherein, The calibration circuit includes: The selection circuit is adapted to: select one of the test signals of the chip as a reference signal based on the chip ID, and select other test signals as detection signals; and The code generation circuit is adapted to generate the calibration code based on the difference between corresponding delay values ​​between the reference signal and the corresponding detection signal.

12. The semiconductor device according to claim 11, wherein, The selection circuit includes: Multiple upper-level multiplexers, each adapted to: select and output one of the test signals based on a first bit of the chip ID; and A plurality of lower multiplexers, each adapted to: select one of the outputs of the upper multiplexer based on a second bit of the chip ID, and output the selected output as one of the reference signal and the detection signal.

13. The semiconductor device according to claim 11, wherein, The code generation circuit includes: Multiple time-to-digital conversion circuits are suitable for: generating multiple delayed reference signals by sequentially delaying the reference signals, and generating multiple digital codes by performing a time-to-digital conversion operation based on the delayed reference signals to trigger the detection signal; and A decoder suitable for generating calibration codes based on the digital codes.

14. The semiconductor device according to claim 13, wherein, Each of the time-to-digital conversion circuits includes: Multiple unit delayers, adapted to sequentially delay the reference signal to generate the delayed reference signal; and Multiple triggers, which: latch the corresponding detection signal according to the delay reference signal, and output the digital code.

15. The semiconductor device according to claim 13, wherein, The decoder includes: A delay calculation circuit is suitable for: selecting a detection signal among the detection signals that has a large delay relative to the reference signal based on the digital code; and outputting a digital code corresponding to the selected detection signal as a delay code; and An encoding circuit is adapted to: convert the delay code into the calibration code, and output the calibration code.

16. The semiconductor device according to claim 15, wherein, The delay code is of thermometer code type, and the calibration code is of binary code type.

17. A semiconductor device comprising stacked chips, each of the chips comprising: The operating circuit receives a source signal via a normal through electrode to generate an internal gating signal by delaying the source signal by a calibration amount that depends on the calibration code. The replication circuit generates a test signal by delaying a test source signal provided via a first test through electrode by an amount representing a delay within the operating circuit other than a calibration amount. A driving circuit that provides the test signal to the remaining chip via a corresponding one of the second test through electrodes; as well as The calibration circuit generates the calibration code by detecting a corresponding delay in an external test signal with reference to the test signal, the external test signal being provided from the remaining chip via the remaining second test pass-through electrode.

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