Display panel and display device

Abstract

This invention relates to a display panel and a display device. The first end of a first touch electrode is electrically connected to the first end of a first touch lead, the second end of the first touch lead is electrically connected to the first end of a first touch trace, and the second end of the first touch trace is electrically connected to a second touch lead. This invention extends the first touch trace, which is disposed on the same layer as the blocking unit, from the first bezel area to the second bezel area. Compared to the prior art where the first touch trace occupies the first, third, and fourth bezel areas and wraps around to the second bezel area, this invention can reduce the width of the first, third, and fourth bezel areas, thereby meeting the user's demand for a narrow bezel design. The second touch trace of this invention is disposed in the second bezel area and electrically connected to the second end of the first touch electrode. Compared to a single set of touch traces in the prior art, the combination of the first and second touch traces of this invention can reduce RC (radius resistance) and improve touch performance.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel and display device. Background Technology

[0002] Organic Light Emitting Diode (OLED) is a photoelectric technology that uses organic semiconductor materials to generate reversible color changes under the drive of an electric current to achieve multi-color displays. OLED has advantages such as being thin and light, having high brightness, being self-emissive, having low power consumption, a wide viewing angle, fast response, flexibility, a wide operating temperature range, low voltage requirements, high energy efficiency, fast response, simple structure, low cost, and almost infinite contrast ratio. It is considered to be the most promising next-generation display technology.

[0003] As OLED display panels are increasingly used in medium to large-sized products such as foldable phones, tablets, and laptops, touch technology also needs to be adapted. In external touch technologies, the distance between the touch layer and the cathode is approximately 140 micrometers, and the capacitive load is approximately 200 pF. DOT (Direct On Cell Touch) technology is a touch technology that directly integrates the touch layer onto the encapsulation layer. In DOT technology, the distance between the touch layer and the cathode is approximately 15 micrometers, and the capacitive load is approximately 900 pF. Compared to external touch technologies, DOT technology suffers from longer capacitor charging time (RC) and inferior touch performance, making its use in medium to large-sized products a bottleneck.

[0004] To utilize DOT technology in medium to large-sized products, a 2T2R (two sets of Tx traces and two sets of Rx traces) approach is typically used to reduce RC. Using two sets of Rx traces, compared to one set, can reduce RC to 1 / 4 of its original value.

[0005] However, the current 2T2R routing requires pulling out one set of RX traces from the bottom edge of the product and another set of RX traces from the top edge of the product. The set of RX traces on the top edge will occupy the space of the top edge, left edge and right edge, resulting in the width of the top edge, left edge and right edge of the product becoming larger, which is not conducive to the narrow edge design of the product. Summary of the Invention

[0006] The purpose of this invention is to provide a display panel and display device that can reduce the problems of large bezel size and inability to meet narrow bezel design requirements when using 2T2R technology in the prior art.

[0007] To address the aforementioned problems, the present invention provides a display panel comprising a display area and a border area surrounding the display area; the border area includes a first border area and a second border area disposed opposite to each other; the display panel includes: a substrate; a shielding layer disposed on the substrate; and the shielding layer includes: a plurality of first touch traces, the first touch traces extending along a first direction, a first end of the first touch traces disposed in the first border area, and a second end of the first touch traces disposed in the second border area; a touch layer disposed on the side of the shielding layer away from the substrate; the touch layer includes: a plurality of first touch electrodes, all extending along the first direction and disposed in the display area; and a plurality of first touch leads, each corresponding to one of the first touch electrodes and disposed in the first border area; a first end of each first touch lead is electrically connected to a first end of the first touch electrode, and a second end of each first touch lead is electrically connected to a first end of the first touch trace through a first via.

[0008] Furthermore, the display panel further includes: a thin-film transistor layer disposed between the shielding layer and the touch layer; and a first conductive layer disposed between the thin-film transistor layer and the touch layer; the first conductive layer includes: a plurality of second touch leads disposed in the second frame area; and the second end of each first touch lead is electrically connected to the second touch lead.

[0009] Furthermore, the thin-film transistor layer includes a plurality of thin-film transistor devices arranged in an array; each thin-film transistor device includes an active layer disposed on the side of the shielding layer away from the substrate; the shielding layer also includes shielding units disposed between the active layer and the substrate; the shielding units include: a plurality of first shielding units extending along the first direction; and a plurality of second shielding units extending along a second direction intersecting the first direction.

[0010] Furthermore, the projection of the first touch trace on the substrate does not overlap with the projection of the blocking unit on the substrate.

[0011] Furthermore, each of the thin-film transistor devices further includes: a source-drain layer disposed on the active layer; the source-drain layer includes a source electrode, a drain electrode, and a conductive unit spaced apart from each other; the first touch trace is electrically connected to the conductive unit through a second via, and the conductive unit is electrically connected to the second touch lead through a third via.

[0012] Furthermore, the second via extends from the surface of the conductive unit near the substrate to the surface of the first touch trace away from the substrate.

[0013] Furthermore, the first via extends from the surface of the touch layer near the substrate to the surface of the first touch trace away from the substrate.

[0014] Furthermore, the touch layer also includes: a plurality of second touch traces, which are arranged one-to-one with the first touch electrode and are disposed in the second frame area; each of the second touch traces is electrically connected to the second end of the first touch electrode.

[0015] Furthermore, the border area further includes a third border area and a fourth border area disposed opposite to each other, the third border area and the fourth border area being disposed between the first border area and the second border area; the touch layer further includes: a plurality of second touch electrodes extending along a second direction intersecting the first direction and insulated from the first touch electrodes; a plurality of third touch traces electrically connected to the first end of the second touch electrodes and disposed in the third border area and extending to the second border area; and a plurality of fourth touch traces electrically connected to the second end of the second touch electrodes and disposed in the fourth border area and extending to the second border area.

[0016] To address the aforementioned problems, the present invention provides a display device comprising the display panel described herein.

[0017] The advantages of this invention are: the first end of the first touch electrode is electrically connected to the first end of the first touch lead, the second end of the first touch lead is electrically connected to the first end of the first touch trace, and the second end of the first touch trace is electrically connected to the second touch lead. This invention extends the first touch trace, which is disposed on the same layer as the blocking unit, from the first frame area to the second frame area. Compared with the prior art where the first touch trace occupies the first frame area, the third frame area, and the fourth frame area and wraps around to the second frame area, this invention can reduce the width of the first frame area, the third frame area, and the fourth frame area, thereby meeting the user's demand for a narrow frame design.

[0018] The second touch trace of the present invention is disposed in the second frame area and electrically connected to the second end of the first touch electrode. Compared with a set of touch traces in the prior art, the combination of the first touch trace and the second touch trace of the present invention can reduce RC and improve touch performance. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a plan view of the display panel of the present invention;

[0021] Figure 2 yes Figure 1 Schematic diagram of section AA in the diagram;

[0022] Figure 3 This is a plan view of the shielding layer of the present invention;

[0023] Figure 4 yes Figure 1 Schematic diagram of the BB section in the diagram;

[0024] Figure 5 yes Figure 1 A schematic diagram of the CC section.

[0025] Explanation of reference numerals in the attached figures:

[0026] 100. Display panel; 101. Display area;

[0027] 102. Border area; 1021. First border area;

[0028] 1022, Second border area; 1023, Third border area;

[0029] 1024, Fourth Border Area;

[0030] 1. Substrate; 2. Masking layer;

[0031] 3. Barrier layer; 4. Buffer layer;

[0032] 5. Thin-film transistor layer; 6. First planarization layer;

[0033] 7. First conductive layer; 8. Second planarization layer;

[0034] 9. Light-emitting layer; 10. Encapsulation layer;

[0035] 11. Touch layer; 12. First via;

[0036] 13. Second via;

[0037] 21. First touch trace; 22. Obstruction unit;

[0038] 221. First occlusion unit; 222. Second occlusion unit;

[0039] 51. Thin-film transistor devices; 511. Active layer;

[0040] 512, First gate insulating layer; 513, First gate;

[0041] 514. Second gate insulating layer; 515. Second gate;

[0042] 516. Interlayer insulation layer; 517. Source / drain layer;

[0043] 5171, Source; 5172, Drain;

[0044] 5173, Conductive unit; 71, Second touch lead;

[0045] 111. First touch electrode; 112. First touch lead;

[0046] 113. Second touch trace; 114. Second touch electrode;

[0047] 115. Third touch trace; 116. Fourth touch trace. Detailed Implementation

[0048] The preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings to fully introduce the technical content of the present invention to those skilled in the art, and to demonstrate that the present invention can be implemented, making the disclosed technical content of the present invention clearer and enabling those skilled in the art to more easily understand how to implement the present invention. However, the present invention can be embodied in many different forms of embodiments, and the scope of protection of the present invention is not limited to the embodiments mentioned herein. The following description of the embodiments is not intended to limit the scope of the present invention.

[0049] The directional terms used in this invention, such as "up", "down", "front", "back", "left", "right", "inner", "outer", and "side", are only for the directions shown in the accompanying drawings. The directional terms used herein are for the purpose of explaining and illustrating this invention, and not for limiting the scope of protection of this invention.

[0050] In the accompanying drawings, components with the same structure are indicated by the same numerical designation, and components with similar structures or functions are indicated by similar numerical designations. Furthermore, for ease of understanding and description, the dimensions and thicknesses of each component shown in the drawings are arbitrary, and the present invention does not limit the dimensions and thicknesses of each component.

[0051] Example 1

[0052] like Figure 1 As shown, the present invention provides a display device. The display device includes a display panel 100.

[0053] like Figure 1As shown, the display panel 100 includes a display area 101 and a border area 102 surrounding the display area 101. The border area 102 includes a first border area 1021, a second border area 1022, a third border area 1023, and a fourth border area 1024. The first border area 1021 and the second border area 1022 are arranged opposite to each other, and the third border area 1023 and the fourth border area 1024 are arranged opposite to each other. The third border area 1023 and the fourth border area 1024 are both connected between the first border area 1021 and the second border area 1022.

[0054] like Figure 2 As shown, the display panel 100 includes: a substrate 1, a shielding layer 2, a blocking layer 3, a buffer layer 4, a thin film transistor layer 5, a first planarization layer 6, a first conductive layer 7, a second planarization layer 8, a light-emitting layer 9, an encapsulation layer 10, and a touch layer 11.

[0055] The substrate 1 is made of materials including glass, polyimide, polycarbonate, polyethylene terephthalate, and polyethylene naphthalate. In this embodiment, the substrate 1 is made of polyimide, which gives it good impact resistance and effectively protects the display panel 100.

[0056] like Figure 3 As shown, the shielding layer 2 is disposed on the substrate 1. The shielding layer 2 includes: a plurality of first touch traces 21 and shielding units 22.

[0057] The first touch trace 21 extends along the first direction M, the first end of the first touch trace 21 is disposed in the first border area 1021, and the second end of the first touch trace 21 is disposed in the second border area 1022.

[0058] The shielding unit 22 is disposed corresponding to the active layer of the thin-film transistor device within the thin-film transistor layer. The shielding unit 22 shields the electric field formed by the non-coincident charge centers of positive and negative ions within the substrate 1 and the electric field formed at the interface of different film layers, preventing these electric fields from affecting the operating characteristics of the active layer and avoiding image retention and ESD damage. The shielding unit 22 includes multiple first shielding units 221 and multiple second shielding units 222. The first shielding units 221 extend along the first direction M; the multiple second shielding units 222 extend along a second direction N intersecting the first direction M. In this embodiment, the first direction M and the second direction N are perpendicular to each other.

[0059] The projection of the first touch trace 21 onto the substrate 1 does not overlap with the projection of the blocking unit 22 onto the substrate 1. In other words, the first touch trace 21 and the blocking unit 22 are spaced apart from each other and insulated from each other.

[0060] The blocking layer 3 is disposed on the shielding layer 2.

[0061] The buffer layer 4 is disposed on the side of the barrier layer away from the substrate 1. The buffer layer 4 mainly serves a buffering function, and its material can be SiOx, SiNx, SiNOx, or a combination of SiNx and SiOx, etc.

[0062] The thin-film transistor layer 5 is disposed on the side of the buffer layer 4 away from the substrate 1. The thin-film transistor layer 5 includes a plurality of thin-film transistor devices 51 arranged in an array.

[0063] like Figure 2 As shown, each of the thin-film transistor devices 51 includes: an active layer 511, a first gate insulating layer 512, a first gate 513, a second gate insulating layer 514, a second gate 515, an interlayer insulating layer 516, and a source / drain layer 517.

[0064] The first gate insulating layer 512 is disposed on the side of the active layer 511 away from the substrate 1 and extends to cover the buffer layer 4. The first gate insulating layer 512 is mainly used to prevent short circuits between the active layer 511 and the first gate 513. The material of the first gate insulating layer 512 can be SiOx, SiNx, Al2O3, a combination of SiNx and SiOx, or a combination of SiOx, SiNx, and SiOx, etc.

[0065] The first gate 513 is disposed on the side of the first gate insulating layer 512 away from the substrate 1. The material of the first gate 513 may be Mo or a combination of Mo and Al, a combination of Mo and Cu, a combination of Mo, Cu and IZO, a combination of IZO, Cu and IZO, a combination of Mo, Cu and ITO, a combination of Ni, Cu and Ni, a combination of MoTiNi, Cu and MoTiNi, a combination of NiCr, Cu and NiCr, or CuNb, etc.

[0066] The second gate insulating layer 514 is disposed on the side of the first gate 513 away from the substrate 1 and extends to cover the first gate insulating layer 512. The second gate insulating layer 514 is mainly used to prevent short circuits between the first gate 513 and the second gate 515. The material of the second gate insulating layer 514 can be SiOx, SiNx, Al2O3, a combination of SiNx and SiOx, or a combination of SiOx, SiNx, and SiOx, etc.

[0067] The second gate 515 is disposed on the side of the second gate insulating layer 514 away from the substrate 1. The second gate 515 is used to couple with the first gate 513 to form a storage capacitor Cst. The material of the second gate 515 can be Mo or a combination of Mo and Al, a combination of Mo and Cu, a combination of Mo, Cu and IZO, a combination of IZO, Cu and IZO, a combination of Mo, Cu and ITO, a combination of Ni, Cu and Ni, a combination of MoTiNi, Cu and MoTiNi, a combination of NiCr, Cu and NiCr, or CuNb, etc.

[0068] The interlayer insulating layer 516 is disposed on the side of the second gate 515 away from the substrate 1 and extends to cover the second gate insulating layer 514. The material of the interlayer insulating layer 516 may be SiOx, SiNx, or SiNOx, etc.

[0069] The source-drain layer 517 is disposed on the side of the interlayer insulating layer 516 away from the substrate 1. The source-drain layer 517 includes a source electrode 5171, a drain electrode 5172, and a conductive unit 5173 spaced apart from each other. The source electrode 5171 and the drain electrode 5172 are electrically connected to the two ends of the active layer 511, respectively.

[0070] The first planarization layer 6 covers the source / drain layer 517. The material of the first planarization layer 6 can be SiOx, SiNx, SiNOx, or a combination of SiNx and SiOx, etc.

[0071] The first conductive layer 7 is disposed on the side of the first planarization layer 6 away from the substrate 1. The first conductive layer 7 includes a plurality of second touch leads 71. The second touch leads 71 ​​are disposed in the second border area 1022.

[0072] The second planarization layer 8 covers the first conductive layer 7. The material of the second planarization layer 8 can be SiOx, SiNx, SiNOx, or a combination of SiNx and SiOx, etc.

[0073] The light-emitting layer 9 is disposed on the side of the second planarization layer 8 away from the substrate 1. The light-emitting layer 9 includes film structures such as an anode (not shown), a light-emitting unit (not shown), and a cathode (not shown).

[0074] The encapsulation layer 10 is disposed on the side of the light-emitting layer 9 away from the substrate 1. The encapsulation layer 10 includes film structures such as a first inorganic encapsulation layer (not shown), an organic encapsulation layer (not shown), and a second inorganic encapsulation layer (not shown).

[0075] like Figure 2 , Figure 4 as well as Figure 5 As shown, the touch layer 11 is disposed on the side of the encapsulation layer 10 away from the substrate 1. The touch layer 11 includes: a plurality of first touch electrodes 111, a plurality of first touch leads 112, a plurality of second touch traces 113, a plurality of second touch electrodes 114, a plurality of third touch traces 115, and a plurality of fourth touch traces 116. In this embodiment, the first touch electrodes 111 are receiving electrodes, and the second touch electrodes 114 are transmitting electrodes. In other embodiments, the first touch electrodes 111 can be transmitting electrodes, and the second touch electrodes 114 can be receiving electrodes.

[0076] Among them, a plurality of first touch electrodes 111 extend along the first direction M and are disposed in the display area 101.

[0077] Among them, a plurality of first touch leads 112 are arranged one-to-one with the first touch electrodes 111 and are arranged in the first frame area 1021.

[0078] In this configuration, multiple second touch traces 113 are arranged in a one-to-one correspondence with the first touch electrode 111 and are disposed in the second frame area 1022. Each second touch trace 113 is electrically connected to the second end of the first touch electrode 111.

[0079] The plurality of second touch electrodes 114 extend along a second direction N intersecting the first direction M and are insulated from the first touch electrode 111.

[0080] Among them, a plurality of third touch lines 115 are electrically connected to the first end of the second touch electrode 114, and are disposed in the third frame area 1023 and extend to the second frame area 1022.

[0081] Among them, a plurality of fourth touch lines 116 are electrically connected to the second end of the second touch electrode 114, and are disposed in the fourth frame area 1024 and extend to the second frame area 1022.

[0082] The first end of each of the first touch leads 112 is electrically connected to the first end of the first touch electrode 111, and the second end of each of the first touch leads 112 is electrically connected to the first end of the first touch trace 21 through the first via 12.

[0083] The first via 12 extends from the surface of the touch layer 11 near the substrate 1 to the surface of the first touch trace 21 away from the substrate 1.

[0084] The second end of each of the first touch traces 21 is electrically connected to the second touch lead 71. Specifically, the second end of the first touch trace 21 is electrically connected to the conductive unit 5173 through the second via 13, and the conductive unit 5173 is electrically connected to the second touch lead 71 through the third via.

[0085] The second via 13 extends from the surface of the conductive unit 5173 near the substrate 1 to the surface of the first touch trace 21 away from the substrate 1.

[0086] The first end of the first touch electrode 111 of the present invention is electrically connected to the first end of the first touch lead 112, the second end of the first touch lead 112 is electrically connected to the first end of the first touch trace 21, and the second end of the first touch trace 21 is electrically connected to the second touch lead 71. The present invention extends the first touch trace 21, which is disposed on the same layer as the blocking unit 22, from the first border area 1021 to the second border area 1022. Compared with the prior art, in which the first touch trace 21 occupies the first border area 1021, the third border area 1023, and the fourth border area 1024 and wraps around to the second border area 1022, the width of the first border area 1021, the third border area 1023, and the fourth border area 1024 can be reduced, thereby meeting the user's demand for narrow border design.

[0087] The second touch trace 113 of the present invention is disposed in the second frame area 1022 and electrically connected to the second end of the first touch electrode 111. Compared with a set of touch traces in the prior art, the combination of the first touch trace 21 and the second touch trace 113 of the present invention can reduce RC and improve touch performance.

[0088] Furthermore, the above provides a detailed description of the display panel and display device provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A display panel, characterized in that, It includes a display area and a border area surrounding the display area; the border area includes a first border area and a second border area that are disposed opposite to each other. The display panel includes: substrate; A shielding layer is disposed on the substrate; The shielding layer includes: a plurality of first touch lines, the first touch lines extending along a first direction, a first end of the first touch lines being disposed in the first border area, and a second end of the first touch lines being disposed in the second border area; A touch layer is disposed on the side of the shielding layer away from the substrate; The touch layer includes multiple first touch electrodes and multiple first touch leads. A plurality of the first touch electrodes extend along the first direction and are disposed in the display area; A plurality of first touch leads are provided in a one-to-one correspondence with the first touch electrodes and are provided in the first frame area; the first end of each first touch lead is electrically connected to the first end of the first touch electrode, and the second end of each first touch lead is electrically connected to the first end of the first touch trace through a first via. A thin-film transistor layer is disposed between the shielding layer and the touch layer; and A first conductive layer is disposed between the thin-film transistor layer and the touch layer; The first conductive layer includes: a plurality of second touch leads disposed in the second border area; The second end of each of the first touch traces is electrically connected to the second touch lead.

2. The display panel according to claim 1, characterized in that, The thin-film transistor layer includes a plurality of thin-film transistor devices arranged in an array; each of the thin-film transistor devices includes an active layer disposed on the side of the shielding layer away from the substrate; The shielding layer also includes a shielding unit correspondingly disposed between the active layer and the substrate; The blocking unit includes: Multiple first blocking units extend along the first direction; as well as Multiple second blocking units extend along a second direction intersecting the first direction.

3. The display panel according to claim 2, characterized in that, The projection of the first touch trace on the substrate does not overlap with the projection of the shielding unit on the substrate.

4. The display panel according to claim 2, characterized in that, Each of the aforementioned thin-film transistor devices further includes: A source-drain layer is disposed on the active layer; the source-drain layer includes mutually spaced source electrodes, drain electrodes, and conductive units; The first touch trace is electrically connected to the conductive unit through a second via, and the conductive unit is electrically connected to the second touch trace through a third via.

5. The display panel according to claim 4, characterized in that, The second via extends from the surface of the conductive unit near the substrate to the surface of the first touch trace away from the substrate.

6. The display panel according to claim 1, characterized in that, The first via extends from the surface of the touch layer near the substrate to the surface of the first touch trace away from the substrate.

7. The display panel according to claim 1, characterized in that, The touch layer also includes: Multiple second touch traces are configured to correspond one-to-one with the first touch electrode and are located in the second frame area; each second touch trace is electrically connected to the second end of the first touch electrode.

8. The display panel according to claim 7, characterized in that, The border area also includes a third border area and a fourth border area that are disposed opposite to each other, and the third border area and the fourth border area are disposed between the first border area and the second border area; The touch layer also includes: Multiple second touch electrodes extend along a second direction intersecting the first direction and are insulated from the first touch electrodes; Multiple third touch traces are electrically connected to the first end of the second touch electrode, and are disposed in the third frame area and extend to the second frame area; and Multiple fourth touch traces are electrically connected to the second end of the second touch electrode and are disposed in the fourth frame area, extending to the second frame area.

9. A display device, characterized in that, The display panel includes any one of claims 1-8.

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