Semiconductor memory device

Abstract

Generally, according to one embodiment, a storage device includes a first storage unit and a control circuit. The first storage unit includes a first resistance change element and a first switching element. The control circuit is configured to perform a first detection of a first value of a first physical quantity related to the first storage unit, perform a first write for storing first data in the first storage unit, perform a second detection of a second value of the first physical quantity related to the first storage unit after the first write, and read second data related to the first storage unit based on the first value and the second value. At least one of the first value and the second value is a value during a change of the first physical quantity related to the first storage unit.

Description

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Japanese Patent Application No. 2021-152414, filed September 17, 2021, and U.S. Patent Application No. 17 / 691198, filed March 10, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] In summary, the implementation methods described herein relate to storage devices. Background Technology

[0004] A storage device with magnetic elements is known. Summary of the Invention

[0005] Generally, according to one embodiment, a storage device includes a first storage unit and a control circuit.

[0006] The first storage cell includes a first resistance changing element and a first switching element. The control circuit is configured to perform a first detection that detects a first value of a first physical quantity associated with the first storage cell, perform a first write operation for storing first data in the first storage cell, perform a second detection that detects a second value of the first physical quantity associated with the first storage cell after the first write operation, and read second data associated with the first storage cell based on the first value and the second value. At least one of the first value and the second value is a value during a change in the first physical quantity associated with the first storage cell. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating an example of the structure of a storage device according to the first embodiment;

[0008] Figure 2 This is a block diagram illustrating an example of the structure of the core circuitry of a storage device according to the first embodiment;

[0009] Figure 3 This is a diagram illustrating an example of the circuit structure of a memory cell array of a memory device according to the first embodiment;

[0010] Figure 4 This is a diagram illustrating a portion of the structure of a memory cell array of a memory device according to a first embodiment;

[0011] Figure 5 This is a cross-sectional view showing an example of the structure of a storage cell of a storage device according to the first embodiment;

[0012] Figure 6This is an example diagram showing the current-voltage (IV) characteristics of the switching elements used to represent a memory cell;

[0013] Figure 7 This is a diagram showing an example of a graph used to represent the IV characteristics of a memory cell;

[0014] Figure 8 This is a diagram illustrating an example of the circuit structure of a write driver, a precharge circuit, a read amplifier, other write drivers, other precharge circuits, and a read receiver in a storage device according to the first embodiment.

[0015] Figure 9 This is a timing diagram illustrating an example of the time variation of the voltage applied to the bit line and word line corresponding to the selected memory cell when the memory device according to the first embodiment performs a certain read operation.

[0016] Figure 10 This is a diagram illustrating the timing of voltage sampling during the first and second readout operations of the readout amplifier of the storage device according to the first embodiment;

[0017] Figure 11 This is a diagram illustrating the further advantageous effects that can be obtained from the storage device according to the first embodiment;

[0018] Figure 12 This is a timing diagram illustrating an example of the time variation of the voltage applied to the bit line and word line corresponding to the selected memory cell when the memory device performs a certain read operation according to a modified example of the first embodiment.

[0019] Figure 13 This is a diagram illustrating the timing of voltage sampling during the first and second readout operations of the readout amplifier of the storage device according to a modified example of the first embodiment.

[0020] Figure 14 This is a block diagram illustrating an example of the structure of a storage device according to the second embodiment;

[0021] Figure 15 This is a diagram showing an example of the layout of various wirings that can serve as voltage transmission paths for each memory cell of the memory device according to the second embodiment.

[0022] Figure 16 This is a diagram illustrating the grouping of memory cells for explaining the timing control performed by the memory device according to the second embodiment during a read operation; and

[0023] Figure 17 This is a diagram illustrating the timing of voltage sampling in the first and second readout operations of the readout amplifier of the storage device according to the second embodiment. Detailed Implementation

[0024] In the following description, various embodiments will be described with reference to the accompanying drawings. Components having the same function and configuration are denoted using the same reference numerals. When distinguishing multiple components with common reference numerals, a suffix is ​​added to the common reference numerals for differentiation. Where multiple components do not require special distinction, only common reference numerals are added to the multiple components, and no suffix is ​​added.

[0025] Each functional block can be implemented using either hardware or software, or a combination of both. Furthermore, as described below, distinguishing functional blocks is not required. For example, some functions may be performed by functional blocks different from the exemplary functional block. Additionally, the exemplary functional block can be divided into more granular sub-functional blocks. Moreover, the names of functional blocks and components in the following description are for convenience only and do not limit the configuration and operation of functional blocks and components.

[0026] <First Implementation Method>

[0027] The storage device 1 according to the first embodiment will be described below.

[0028] [Structure Example]

[0029] (1) Storage device

[0030] Figure 1 This is a block diagram illustrating an example of the structure of the storage device 1 according to the first embodiment.

[0031] The storage device 1 according to the first embodiment can store data in a non-volatile manner. Specifically, the storage device 1 is, for example, a perpendicular magnetization type magnetic storage device (MRAM: magnetic random access memory), which uses a resistance-changing element that utilizes the tunnel magnetoresistance (TMR) effect based on a magnetic tunnel junction (MTJ) as a storage element. The TMR effect is, for example, a phenomenon in which the resistance of an element changes when a tunneling current flows, by changing the magnetization direction of a ferromagnetic material by applying a magnetic field or current.

[0032] exist Figure 1 In addition to storage device 1, memory controller 2 and host device 4 are also shown. Storage device 1 and memory controller 2 constitute storage system 3.

[0033] The memory controller 2 receives host commands from a host device (external device) 4, such as a personal computer, and controls the storage device 1 based on the host commands. Under this control, various actions are performed, such as actions to store data in the storage device 1 (hereinafter referred to as write actions) and actions to read data from the storage device 1 (hereinafter referred to as read actions).

[0034] The following describes the signals transmitted between the memory controller 2 and the storage device 1 related to control.

[0035] Memory controller 2 is connected to storage device 1 via a memory bus. The memory bus transmits, for example, data signals DQ and external control signals CNT. Data signals DQ include write data or read data. External control signals CNT include, for example, command and address information.

[0036] Next, the details of the structure of storage device 1 will be described.

[0037] The storage device 1 includes a core circuit 11, a column decoder 12, a row decoder 13, a command / address input circuit 14, a sequencer 15, and an input / output circuit 16.

[0038] Core circuit 11 includes multiple non-volatile memory cells associated with word lines and bit lines. Word lines include global word lines and local word lines. Bit lines include global bit lines and local bit lines. Hereinafter, local word lines will be simply referred to as word lines. Similarly, local bit lines will be simply referred to as bit lines. In a write operation, data is written to memory cells in core circuit 11. In a read operation, data is read from memory cells in core circuit 11.

[0039] Command / address input circuit 14 receives external control signal CNT sent from memory controller 2 and transmits the command and address information in external control signal CNT to sequencer 15.

[0040] The sequencer 15 controls the storage device 1 based on the transmitted commands and address information. For example, the sequencer 15 controls the core circuit 11, column decoder 12, row decoder 13, input / output circuit 16, etc., to perform various operations such as write operations and read operations.

[0041] The sequencer 15 includes a voltage generation circuit 151. The voltage generation circuit 151 generates various voltages for write operations, read operations, etc. The sequencer 15 provides the voltage generated by the voltage generation circuit 151 to the core circuit 11.

[0042] Input / output circuit 16 receives write data from the data signal DQ sent from memory controller 2 and transmits the write data to core circuit 11. Input / output circuit 16 also receives read data from core circuit 11 and temporarily holds the read data. Input / output circuit 16 then transmits the read data to memory controller 2.

[0043] The column decoder 12 receives address information from the sequencer 15. Based on the address information, the column decoder 12 generates a signal related to the selection of bit lines and transmits the signal to the core circuit 11.

[0044] The line decoder 13 receives address information from the sequencer 15. Based on the address information, the line decoder 13 generates a signal related to the selection of word lines and transmits the signal to the core circuit 11.

[0045] (2) Core Circuit

[0046] Figure 2 This is a block diagram illustrating an example of the structure of the core circuit 11 of the storage device 1 according to the first embodiment.

[0047] The core circuit 11 includes a memory cell array MCA, a column transfer switch group CTS, a write driver CWD, a precharge circuit CPC, a sense amplifier SA, a row transfer switch group RTS, a write driver RWD, a precharge circuit RPC, and a read sink RS.

[0048] The storage cell array (MCA) comprises the multiple storage cells described above.

[0049] The write driver (CWD), precharge circuit (CPC), sense amplifier (SA), and column transfer switch group (CTS) are connected to the global bit line (GBL). The column transfer switch group (CTS) is connected to multiple memory cells in the memory cell array (MCA) via multiple bit lines. One memory cell is connected to one bit line.

[0050] For example, the column transfer switch group CTS receives a signal related to the selection of the bit line from the column decoder 12, and based on the signal, electrically connects the bit line and global bit line GBL of the memory cell that are the objects of the action performed by the memory device 1.

[0051] During a write operation, the write driver (CWD) controls the current flowing through the global bit line (GBL). This current flows through the memory cell targeted for the write operation. Therefore, the write data received by the input / output circuit 16 and transmitted to the core circuit 11 can be written to the target memory cell.

[0052] For example, during a read operation, the precharge circuit CPC applies a specific voltage from the sequencer 15 to the global bit line GBL. For example, this voltage is transmitted to the bit line BL connected to the memory cell that is the object of the read operation.

[0053] During a read operation, the sense amplifier SA applies a voltage based on a specific voltage provided from the sequencer 15 to the global bit line GBL. For example, this voltage is sent to the bit line BL connected to the memory cell to be read. Furthermore, during a read operation, the sense amplifier SA detects the voltage associated with the memory cell to be read via the global bit line GBL. Therefore, the sense amplifier SA reads the data stored in the memory cell and transmits the read data to the input / output circuit 16.

[0054] The write driver (RWD), precharge circuit (RPC), read receiver (RS), and row transfer switch group (RTS) are connected to the global word line (GWL). The RTS is connected to multiple memory cells in the memory cell array (MCA) via multiple word lines. One memory cell is connected to one word line.

[0055] For example, the line transfer switch group RTS receives a signal related to the selection of word lines from the line decoder 13, and based on the signal, electrically connects the word lines of the memory cells that are the objects of the actions performed by the memory device 1 to the global word line GWL.

[0056] During a write operation, the write driver (RWD) controls the current flowing through the global word line (GWL). The current flows through the memory cell that is the target of the write operation.

[0057] For example, during a read operation, the precharge circuit RPC applies a specific voltage from the sequencer 15 to the global word line GWL. This voltage is then transmitted, for instance, to the word line WL connected to the memory cell targeted for the read operation.

[0058] During a read operation, the read receiver RS ​​fixes the potential of the word line connected to the memory cell to be read to, for example, ground potential via the global word line GWL.

[0059] (3) Storage cell array

[0060] Figure 3 An example of the circuit structure of the memory cell array (MCA) of the memory device 1 according to the first embodiment is shown. Figure 3 In addition to the circuit structure of the memory cell array (MCA), examples of the circuit structures of the column transfer switch group (CTS) and the row transfer switch group (RTS) are also shown.

[0061] First, the circuit structure of the column transfer switch group (CTS) and the row transfer switch group (RTS) will be described.

[0062] The column transfer switch group CTS includes transistors CTr0, CTr1, ..., and CTr(m-1) (where m is an integer greater than or equal to 1). Each of these transistors is, for example, a field-effect transistor (FET) such as an n-channel metal-oxide-semiconductor (MOS) transistor. Unless otherwise stated, this also applies to the constituent elements referred to as transistors in this specification.

[0063] The first terminal of transistor CTr0 is connected to the global bit line GBL, and the second terminal of transistor CTr0 is connected to bit line BL0. The first terminal of transistor CTr1 is also connected to the global bit line GBL, and the second terminal of transistor CTr1 is connected to bit line BL1. Similarly, the first terminal of transistor CTr(m-1) is connected to the global bit line GBL, and the second terminal of transistor CTr(m-1) is connected to bit line BL(m-1). In this way, the first terminals of transistors CTr0 to CTr(m-1) are all connected to the global bit line GBL, and the second terminals of transistors CTr0 to CTr(m-1) are connected to bit lines BL0 to BL(m-1) respectively in a one-to-one relationship.

[0064] For example, a voltage based on a signal related to the selection of the bit line is applied to the control gate (hereinafter also referred to as the gate or control terminal) of transistors CTr0 to CTr(m-1). Therefore, the bit line BL and the global bit line GBL, which are connected to the memory cell to which the operation is performed as the memory device 1, are electrically connected.

[0065] The line transfer switch group RTS includes transistors RTr0, RTr1, ..., and RTr(n-1) (n is an integer greater than or equal to 1).

[0066] The first terminal of transistor RTr0 is connected to the global word line GWL, and the second terminal of transistor RTr0 is connected to word line WL0. The first terminal of transistor RTr1 is also connected to the global word line GWL, and the second terminal of transistor RTr1 is connected to word line WL1. Similarly, the first terminal of transistor RTr(n-1) is connected to the global word line GWL, and the second terminal of transistor RTr(n-1) is connected to word line WL(n-1). In this way, the first terminals of transistors RTr0 to RTr(n-1) are all connected to the global word line GWL, and the second terminals of transistors RTr0 to RTr(n-1) are connected to word lines WL0 to WL(n-1) in a one-to-one relationship.

[0067] For example, a voltage based on a signal related to the selection of a word line is applied to the gates of transistors RTr0 to RTr(n-1). Therefore, the word line WL and the global word line GWL, which are connected to the memory cells to which the operation is performed as a memory device 1, are electrically connected.

[0068] Next, the circuit structure of the memory cell array (MCA) will be described.

[0069] A memory cell array (MCA) comprises multiple memory cells (MCs). The connection relationships of these memory cells (MCs) are as follows. That is, for each combination of a single bit line BL from bit lines BL0 to BL(m-1) and a single word line WL from word lines WL0 to WL(n-1), a single memory cell (MC) is connected between a bit line BL and a word line WL. It should be noted that, in the following text, the word line WL and bit line BL connected to a memory cell (MC) are also referred to as the word line WL and bit line BL corresponding to the memory cell (MC), respectively.

[0070] Figure 4 An example of a portion of the structure of the storage cell array (MCA) of the storage device 1 according to the first embodiment is shown.

[0071] Multiple word lines WL are configured in a wiring (or cabling) layer. Each word line WL extends along a first direction D1. The multiple word lines WL are arranged sequentially as adjacent to each other with a gap along a second direction D2. The second direction D2 intersects the first direction D1 and, for example, is orthogonal to the first direction D1.

[0072] Multiple bit lines BL are configured in another wiring layer. Each bit line BL extends, for example, in a second direction D2. For example, multiple bit lines BL are configured sequentially along a first direction D1, spaced adjacent to each other.

[0073] For each combination of a single word line WL and a single bit line BL, a single memory cell MC is set between the word line WL and the bit line BL and connected to the word line WL and the bit line BL.

[0074] The memory cell MC includes MTJ elements (denoted by reference numeral MTJ in the figures) stacked along a third direction D3 and switching elements S. For example, the third direction D3 intersects with and is orthogonal to the first direction D1 and the second direction D2. The MTJ elements are connected, for example, to word line WL, and the switching elements S are connected, for example, to bit line BL.

[0075] Although Figure 4 An example of a partial structure of a memory cell array (MCA) is shown, but a wiring layer containing word lines (WL) or bit lines (BL) can be set on the upper layer. Figure 4 The illustration shows an example of a memory cell MC containing an MTJ element and a switching element S, with the MTJ element positioned on the word line WL side and the switching element S positioned on the bit line BL side. However, this embodiment is not limited to the above. The MTJ element can be positioned on the bit line BL side, and the switching element S can be positioned on the word line WL side.

[0076] (4) Storage unit

[0077] The structure of a specific memory cell in the storage device 1 according to the first embodiment will be described below. A single memory cell MC will be described as an example, but the same description applies to each of the other memory cells MC.

[0078] Figure 5 This is a cross-sectional view showing an example of the structure of a storage cell MC of the storage device 1 according to the first embodiment.

[0079] If you have already referred to Figure 4 As described, the memory cell MC includes an MTJ element as a resistance-changing element and a switching element S. For example, a first terminal of the switching element S is connected to the bit line BL, a second terminal of the switching element S is connected to the first terminal of the MTJ element, and the second terminal of the MTJ element is connected to the word line WL.

[0080] The switching element S is, for example, a switching element between two terminals. When the voltage applied between the two terminals is less than a threshold, the switching element is in a closed state, for example, a high-impedance state. When the voltage applied between the two terminals is equal to or greater than the threshold, the switching element is in an open state, for example, a low-impedance state. The switching element can have this function regardless of the polarity of the voltage.

[0081] As an example of the switching element in this embodiment, a switching element with the characteristic that its resistance value decreases sharply at a specific voltage, and therefore the applied voltage decreases sharply while the current increases (snap back) will be described. It should be noted that the material used for the switching element having this characteristic should be appropriately selected and used according to the characteristics of the memory cell. Its operation will be described later.

[0082] The MTJ element comprises a ferromagnetic material (ferromagnetic layer) SL, a non-magnetic material (non-magnetic layer) TB, and a ferromagnetic material (ferromagnetic layer) RL. These three layers, ferromagnetic material SL, non-magnetic material TB, and ferromagnetic material RL, are stacked from the first end side of the MTJ element toward the second end side in, for example, the order of ferromagnetic material SL, non-magnetic material TB, and ferromagnetic material RL.

[0083] The non-magnetic material TB acts as, for example, a tunnel barrier layer. That is, the ferromagnetic material SL, the non-magnetic material TB, and the ferromagnetic material RL form a magnetic tunnel junction. The ferromagnetic material RL has a fixed magnetization in a certain direction and serves as, for example, a reference layer. Here, "fixed magnetization" means that the magnetization direction does not change due to a current (spin torque) that can alter the magnitude of the magnetization direction of the ferromagnetic material SL. The ferromagnetic material SL is a ferromagnetic layer with a variable magnetization direction and serves as a storage layer. Here, "variable magnetization" means that the magnetization direction changes according to a current (spin torque) that can switch the magnitude of the magnetization direction of the ferromagnetic material SL.

[0084] A combination of ferromagnetic material SL, nonmagnetic material TB, and ferromagnetic material RL exhibits the TMR effect. The TMR effect refers to the phenomenon where a structure consisting of two ferromagnetic materials sandwiched by an insulator exhibits different resistance values ​​depending on whether the magnetization directions of the two ferromagnetic materials are parallel or antiparallel. When the magnetization directions of the two ferromagnetic materials are parallel, the resistance value of the structure is lower than when the magnetization directions are antiparallel.

[0085] When the magnetization directions of ferromagnetic material RL and ferromagnetic material SL are parallel, the resistance value of the MTJ element is lower than when the two magnetization directions are antiparallel. That is, the MTJ element is set to a low-impedance state LRS. The low-impedance state LRS is also called the "parallel (P) state". For example, the data "0" is defined to be stored in the memory cell MC, which includes the MTJ element in the low-impedance state LRS.

[0086] When the magnetization directions of ferromagnetic material RL and ferromagnetic material SL are antiparallel, the resistance of the MTJ element is higher than when the two magnetization directions are parallel. That is, the MTJ element is set to a high-impedance state HRS. The high-impedance state HRS is also called the "antiparallel (AP) state". For example, the data "1" is defined and stored in the memory cell MC, which includes the MTJ element in the high-impedance state HRS.

[0087] For the sake of brevity, in the following explanation, it is assumed that when the MTJ element is in a low impedance state LRS, the memory cell MC containing the MTJ element is also in a low impedance state LRS, and when the MTJ element is in a high impedance state HRS, the memory cell MC containing the MTJ element is also in a high impedance state HRS.

[0088] Figure 5 The MTJ element shown is merely an example, and an MTJ element can include other layers besides those described above. Additionally, Figure 5The connection relationship between the MTJ element and the switching element S shown is merely an example, and this embodiment is not limited thereto. For example, the stacking order of the ferromagnetic material SL, the non-magnetic material TB, and the ferromagnetic material RL of the MTJ element can be reversed from the order described above. Furthermore, the order of the switching element S and the MTJ element connected between the bit line BL and the word line WL can also be reversed from the order described above.

[0089] Next, ferromagnetic materials SL, nonmagnetic materials TB, and ferromagnetic materials RL will be further described. For example, nonmagnetic materials TB exhibit insulating properties and include nonmagnetic materials. For example, nonmagnetic materials TB include oxygen and magnesium or magnesium oxide (MgO).

[0090] Ferromagnetic materials SL are electrically conductive and include ferromagnetic materials. For example, ferromagnetic materials SL include iron cobalt boron (FeCoB) or iron boride (FeB).

[0091] The ferromagnetic material RL is conductive and comprises a ferromagnetic material having an easy magnetization axis along a direction perpendicular to the interface between the ferromagnetic material RL and other layers. For example, the ferromagnetic material RL comprises iron cobalt boron (FeCoB) as a ferromagnet with perpendicular magnetization. The ferromagnetic material RL may include at least one of cobalt platinum (CoPt), cobalt nickel (CoNi), and cobalt palladium (CoPd).

[0092] The magnetization direction of the ferromagnetic material RL is fixed, either towards the side of the ferromagnetic material SL or in the opposite direction (in...). Figure 5 In the example, the opposite side facing the ferromagnetic SL side).

[0093] The magnetization direction of the ferromagnetic material SL can be switched along the easy magnetization axis. By switching the magnetization direction of the ferromagnetic material SL, data is written to the memory cell MC. For this purpose, a spin injection writing method can be applied to the memory device 1. In the spin injection writing method, a write current is applied to the MTJ element, and the magnetization direction of the ferromagnetic material SL is controlled by the write power supply. That is, the spin-transfer torque (STT) effect generated by the write current is used.

[0094] When along Figure 5 As shown by arrow A1, when a write current is applied to the MTJ element from the direction of ferromagnetic material SL towards ferromagnetic material RL, the magnetization direction of ferromagnetic material SL becomes parallel to the magnetization direction of ferromagnetic material RL. When along... Figure 5 When the write current is applied to the MTJ element in the direction of arrow A2, which is from ferromagnetic material RL to ferromagnetic material SL, the magnetization direction of ferromagnetic material SL becomes antiparallel to the magnetization direction of ferromagnetic material RL.

[0095] Figure 6An example graph is shown to represent the current-voltage (IV) characteristics of the switching element S of the memory cell MC. The horizontal axis of the graph represents the voltage VS applied to the switching element S. The vertical axis of the graph represents the current IS flowing through the switching element S. A current IS flowing in a certain direction is defined as a positive current, and a voltage applied to the switching element S to cause the current IS to flow in that direction is defined as a positive voltage.

[0096] For example, the case where the voltage applied to the memory cell MC is changed, causing the voltage VS to gradually increase from zero volts (V), will be described.

[0097] The current IS continues to increase until the voltage VS reaches voltage V1. When voltage VS reaches voltage V1, the switching element S changes from the off state to the on state, and the resistance of the MTJ element dominates the resistance of the entire memory cell MC. Therefore, the magnitude of the voltage applied to the switching element S decreases, for example, voltage VS changes from voltage V1 to a positive voltage V2. On the other hand, when the switching element turns on, the current IS increases sharply. At this time, voltage VS and current IS can also be regarded as... Figure 6 The curve follows the negative resistance region. For example, the sense amplifier SA does not detect the current IS before a sharp increase, but it can detect the current IS after a sharp increase.

[0098] Subsequently, by changing the voltage applied to the storage cell MC to reduce the voltage VS, when the voltage VS reaches the voltage V2, the switching element S changes from the on state to the off state, and the current IS drops sharply. For example, the sense amplifier SA will not detect the sharp drop in current IS.

[0099] like Figure 6 As shown in the diagram, when the voltage VS applied to the switching element S reverses its sign, the current IS also reverses its sign. In other words, the switching element S has an IV characteristic that is symmetrical to each other in both directions (positive and negative).

[0100] Figure 7 This is an example of a graph used to represent the IV characteristics of a memory cell MC. The horizontal axis of the graph represents the voltage VMC, which represents the magnitude of the voltage applied to the memory cell MC (the potential difference between the bit line BL and the word line WL). The vertical axis of the graph represents the current IMC, which is expressed on a logarithmic scale as the magnitude of the cell current flowing through the memory cell MC. Figure 7 The dashed lines in the chart represent virtual features that do not actually appear.

[0101] First, the following explanation applies to both the case where the memory cell MC is in a high impedance state (HRS) and the case where the memory cell MC is in a low impedance state (LRS).

[0102] As the voltage VMC gradually increases, the current IMC continues to increase until the voltage VMC reaches the voltage VSB. Figure 7 (as shown in region (a)). As the voltage VMC increases further, the function of this curve becomes discontinuous at the point where VMC equals VSB. That is, when the voltage VMC reaches the voltage VSB, the current IMC increases sharply. After such a sharp increase in current IMC, the current IMC changes continuously with the magnitude of the voltage VMC; the larger the voltage VMC, the larger the current IMC. Figure 7 (as shown in region (b)). For example, the sense amplifier SA does not detect the current IMC before a sharp increase, but it can detect the current IMC after a sharp increase.

[0103] Next, a comparison and explanation will be made between the case where the memory cell MC is in a high impedance state (HRS) and the case where the memory cell MC is in a low impedance state (LRS).

[0104] Before the sharp increase in current IMC mentioned above, the current IMC was essentially the same when the memory cell MC was in a low-impedance state (LRS) and a high-impedance state (HRS). This is due to the reasons described below.

[0105] The sharp increase in current IMC mentioned above is caused by the switching element S in the memory cell MC changing from the off state to the on state, thus becoming conductive. Before the sharp increase in current IMC, the switching element S was in the off state, and therefore the resistance of the switching element S was much greater than the resistance of the MTJ element. Therefore, before the sharp increase in current IMC, the resistance of the switching element S dominated the overall resistance of the memory cell MC, and the resistance of the memory cell MC was essentially the same whether it was in the low impedance state (LRS) or the high impedance state (HRS).

[0106] On the other hand, after the aforementioned sharp increase in current IMC, the current IMC when a specific voltage is applied to the memory cell MC is larger when the MTJ element is in a low-impedance state (LRS) compared to when the MTJ element is in a high-impedance state (HRS). This is because when the switching element S is in the on state, the resistance of the MTJ element dominates the overall resistance of the memory cell MC.

[0107] The following describes the situation where the voltage VMC decreases after a sharp increase in current IMC. As the voltage VMC decreases, the curve exhibits discontinuities at points where VMC is a specific voltage, as described below.

[0108] When the memory cell MC is in a low-impedance state (LRS), the current IMC decreases sharply when the voltage VMC reaches the voltage VhldL. Conversely, when the memory cell MC is in a high-impedance state (HRS), the current IMC decreases sharply when the voltage VMC reaches the voltage VhldH. Both voltages VhldL and VhldH are less than voltage VSB. Voltage VhldH is greater than voltage VhldL. After this sharp decrease in current IMC, the current IMC changes according to the IV characteristic on which the current IMC was based before the aforementioned sharp increase in current IMC. Figure 7 (as shown in region (a)). This means that the switching element S has changed from the on state to the off state. For example, the sense amplifier SA will not detect the current IMC after this sharp drop.

[0109] (5) Circuits related to applying voltage to the memory cell

[0110] Figure 8 An example circuit structure of each of the write driver CWD, precharge circuit CPC, read amplifier SA, write driver RWD, precharge circuit RPC, and read receiver RS ​​in the storage device 1 according to the first embodiment is shown. The circuit structure described below is merely an example, and other circuit structures that achieve equivalent functions can be used. In the following description, the specific storage cell MC that is the object of a read operation or a write operation is also referred to as the selected storage cell MC.

[0111] A write driver (CWD) may include, for example, a current source CS1, a transistor Tr1, and a transistor Tr2. Transistor Tr1 may be, for example, a p-channel MOS transistor.

[0112] A voltage VHH is applied to the input terminal of current source CS1, and the output terminal of current source CS1 is connected to the first terminal of transistor Tr1. The voltage VHH is provided, for example, by an external power supply.

[0113] The second terminal of transistor Tr1 is connected to the global bit line GBL. A control signal S1 is input to the gate of transistor Tr1. Control signal S1 is provided, for example, by sequencer 15. The same applies to other control signals described below as being input to the gate of a particular transistor Tr.

[0114] The first terminal of transistor Tr2 is connected to the global bit line GBL, and the second terminal of transistor Tr2 is grounded, for example. A control signal S2 is input to the gate of transistor Tr2. Each component described as grounded in this specification does not necessarily need to be grounded, and this is sufficient, for example, if each component is at a low reference potential among several reference potentials used in storage device 1.

[0115] The precharge circuit CPC includes, for example, a transistor Tr3. A voltage VPRE is applied to the first terminal of transistor Tr3, and the second terminal of transistor Tr3 is connected to the global bit line GBL. A control signal S3 is input to the gate of transistor Tr3. The voltage VPRE is provided, for example, by an external power supply or a voltage generation circuit 151.

[0116] The readout amplifier SA includes, for example, transistor Tr4, switches SW1, SW2 and SW3, and operational amplifier circuit AMP.

[0117] For example, a voltage VHH is applied to the first terminal of transistor Tr4, and the second terminal of transistor Tr4 is connected to the first terminal of switch SW1. A voltage VCLMP is applied to the gate of transistor Tr4. For example, voltage VHH is provided by an external power supply, and voltage VCLMP is provided by voltage generation circuit 151. For example, voltages VHH and VCLMP are used to determine the voltage applied to the bit line BL corresponding to the selected memory cell MC during a read operation.

[0118] The second terminal of switch SW1 is connected to the global bit line GBL. Switch SW1 is, for example, a switching element between two terminals, which can transfer voltage between the first and second terminals when switch SW1 is in the on state. For example, switch SW1 is a field-effect transistor such as an n-channel MOS transistor. In this specification, switch SW1 will be described as an n-channel MOS transistor. Unless otherwise stated, this also applies to other switches SW.

[0119] The control gate (hereinafter also referred to as the gate or control terminal) of switch SW1 receives a specific control signal. For example, the control signal is provided by sequencer 15. The same applies to other control signals described in the following description as input to the gate of a switch SW.

[0120] The first terminal of switch SW2 is connected to the global bit line GBL, while the second terminal of switch SW2 is connected to the non-inverting input of the operational amplifier circuit AMP. A control signal is input to the gate of switch SW2. This will be explained in the description of the operation example. Figure 8 The label Vsmpl is shown in the figure.

[0121] The first terminal of switch SW3 is connected to the global bit line GBL, and the second terminal of switch SW3 is connected to the inverting input of the operational amplifier circuit AMP. A control signal is input to the gate of switch SW3. This will be explained in the description of the operational example. Figure 8 The label VVeval is shown.

[0122] The operational amplifier circuit (AMP) amplifies the voltage applied to the non-inverting input terminal based on the voltage applied to the inverting input terminal, and outputs a signal SADOUT as the amplified result. Data is read based on the SADOUT signal.

[0123] The write driver RWD includes, for example, a current source CS2, a transistor Tr5, and a transistor Tr6. Transistor Tr5 is, for example, a p-channel MOS transistor.

[0124] For example, a voltage VHH is applied to the input terminal of current source CS2, and the output terminal of current source CS2 is connected to the first terminal of transistor Tr5. The voltage VHH is provided, for example, by an external power supply.

[0125] The second terminal of transistor Tr5 is connected to the global word line GWL. Control signal S4 is input to the gate of transistor Tr5.

[0126] The first terminal of transistor Tr6 is connected to the global word line GWL, and the second terminal of transistor Tr6 is grounded, for example. Control signal S5 is input to the gate of transistor Tr6.

[0127] The precharge circuit RPC includes, for example, a transistor Tr7. For instance, a voltage VPRE is applied to the first terminal of transistor Tr7, and the second terminal of transistor Tr7 is connected to the global word line GWL. A control signal S6 is input to the gate of transistor Tr7. The voltage VPRE is provided, for example, by an external power supply or a voltage generation circuit 151.

[0128] The read receiver RS ​​includes, for example, a transistor Tr8. The first terminal of transistor Tr8 is connected to the global word line GWL, and the second terminal of transistor Tr8 is grounded, for example. A control signal S7 is input to the gate of transistor Tr8.

[0129] [Action Example]

[0130] In the following description, an example of an action performed by the storage device 1 according to the first embodiment to perform a specific read action will be described. The read action may also be referred to as, for example, a self-reference read action.

[0131] Figure 9 An example timing diagram is shown to illustrate the time variation of the voltage applied to the bit line BL and word line WL corresponding to the selected memory cell MC when the memory device 1 according to the first embodiment performs a read operation. The bit line BL and word line WL mentioned in the description of the operation example are respectively the bit line BL and word line WL corresponding to the selected memory cell MC. The read operation described below is merely an example, and the read operation according to this embodiment is not limited thereto.

[0132] During a read operation, a first sense operation, a first write operation, and a second sense operation are sequentially performed on the selected memory cell MC. After the second sense operation, the data stored in the selected memory cell MC at the start of the first sense operation is determined. The second write operation can also be performed based on the determined result.

[0133] In the following description, when describing the control of the voltage applied to a wiring, the control described with respect to the wiring continues unless it is explicitly stated that another control is subsequently performed on the wiring.

[0134] In the following description, for example, the voltage of word line WL is applied by controlling the row decoder 13, write driver RWD, precharge circuit RPC, read receiver RS, and row transfer switch group RTS via sequencer 15. For example, the voltage of bit line BL is applied by controlling the column decoder 12, write driver CWD, precharge circuit CPC, sense amplifier SA, and column transfer switch group CTS via sequencer 15.

[0135] At time T00, before the read operation begins, a voltage VPRE is applied to each of the bit line BL and word line WL. This voltage VPRE can be applied by turning on transistors Tr3 and Tr7 in the precharge circuits CPC and RPC.

[0136] First, the control performed in the first readout action will be described.

[0137] At time T01, with voltage VPRE applied to word line WL, the voltage applied to word line BL increases from voltage VPRE to voltage VBLP. Voltage VBLP can be applied by turning on switch SW1 of the sense amplifier SA. The difference between voltage VBLP and voltage VPRE is less than voltage VSB. Figure 7 ).

[0138] After the potential (hereinafter also referred to as voltage) of the bit line BL to which the applied voltage VBLP is applied stabilizes, the switch SW1 of the sense amplifier SA turns off, and the bit line BL is in a floating state at time T02.

[0139] Subsequently, at time T03, with bit line BL remaining in the floating state, the voltage applied to word line WL decreases from voltage VPRE to voltage VSS. Voltage VSS can be applied by turning on transistor Tr8 of the read receiver RS. Voltage VSS is, for example, ground.

[0140] During the process of the voltage of word line WL decreasing due to the application of voltage VSS, the voltage difference between bit line BL and word line WL exceeds voltage VSB. As described above, when the voltage difference reaches voltage VSB, the switching element S in the select memory cell MC changes from the off state to the on state, thus becoming conductive, and the cell current flowing through the select memory cell MC increases sharply. The cell current flows out from bit line BL through transistor Tr8 of word line WL and read receiver RS. Therefore, the voltage of bit line BL decreases. Figure 9 In the diagram, the time at which the decrease begins is denoted as time T04.

[0141] The decrease in voltage on bit line BL leads to a decrease in the voltage difference between bit line BL and word line WL. When the memory cell MC is selected, for example, in a high-impedance state HRS, the voltage difference decreases to reach voltage VhldH. Figure 7 When the current in the cell decreases sharply, the voltage of the bit line BL stabilizes. That is, the voltage of the bit line BL stabilizes at a voltage VhldH that is higher than the voltage of the word line WL at which the voltage VSS is applied. The following will describe the case where the selected memory cell MC is in a high-impedance state HRS at the start of the first read operation.

[0142] The control executed in the subsequent first write action will be described.

[0143] For example, at time T11, the write current supplied by the current source CS1 of the write driver CWD is controlled so that it flows sequentially through the bit line BL, the select memory cell MC, and the word line WL. This is possible when transistor Tr1 of the write driver CWD turns on and transistor Tr2 turns off, and transistor Tr6 of the write driver RWD turns on and transistor Tr5 turns off. The write current is used as the edge... Figure 5 The example shows the write current flowing in the direction of A1, so the MTJ element switches to a low-impedance state LRS, that is, the selected memory cell MC switches to a low-impedance state LRS. Figure 9 This illustrates that when the write current flows as described above, the voltage on the bit line BL becomes voltage VWT and the voltage on the word line WL becomes VSS. For example, the difference between voltage VWT and voltage VSS is greater than voltage VSB. Figure 9 The voltage of the bit line BL when the write current flows is shown as constant, but it is not necessarily constant.

[0144] Subsequently, at time T12, a voltage VPRE is applied to each of the bit line BL and word line WL. As described in conjunction with time T00, the voltage VPRE is applied via the pre-charge circuits CPC and RPC. At this time, transistor Tr1 of the write driver CWD and transistor Tr6 of the write driver RWD are turned off.

[0145] The control performed in the subsequent second readout action will be described.

[0146] At time T21, as described in conjunction with time T01, with voltage VPRE applied to word line WL, the voltage applied to bit line BL increases from voltage VPRE to voltage VBLP.

[0147] After the voltage of bit line BL is stabilized by applying voltage VBLP, bit line BL is in a floating state at time T22, as described at time T02.

[0148] Subsequently, at time T23, as described in conjunction with time T03, while the bit line BL remains in the floating state, the voltage applied to the word line WL decreases from voltage VPRE to voltage VSS.

[0149] During the process of the voltage of word line WL decreasing due to the application of voltage VSS, the voltage difference between bit line BL and word line WL exceeds voltage VSB. As described above, when the voltage difference reaches voltage VSB, the voltage of bit line BL decreases in the same way as during the first read operation. Figure 9 In the text, the time when the descent begins is indicated as time T24.

[0150] A decrease in the voltage of bit line BL causes a decrease in the voltage difference between bit line BL and word line WL. When the voltage difference decreases to voltage VhldL( Figure 7 When the voltage drops sharply, the cell current decreases drastically, thus stabilizing the voltage of the bit line BL. That is, the voltage of the bit line BL stabilizes at a voltage VhldL that is higher than the voltage of the word line WL to which the applied voltage VSS is applied.

[0151] The voltage control for each of the bit line BL and word line WL has been described above for each of the first and second read operations. When the voltage of the bit line BL decreases as described above, the rate of decrease of the bit line BL voltage and the stable voltage of the bit line BL after the decrease differ between the first and second read operations. By utilizing this difference between the first and second read operations, the data stored in the selected memory unit MC at the start of the first read operation is determined after the second read operation. The determination of this data will be described in detail below.

[0152] Figure 10 This is a diagram illustrating the timing of voltage sampling during the first and second readout operations of the readout amplifier SA of the storage device 1 according to the first embodiment.

[0153] Figure 10 It shows the Figure 9 The diagram shows a superposition of the voltage waveforms of bit line BL during the first and second readout operations. Specifically, the two waveforms are superimposed so that the discharge start times T04 and T24 of bit line BL are at the same position on the horizontal axis. Figure 10 In the example, the time from time T01 to time T03 is the same as the time from time T21 to time T23. The time from time T03 to time T04 is essentially equal to the time from time T23 to time T24. This is illustrated in this way... Figure 10 In the diagram, the horizontal axis represents the time elapsed since the start of the discharge, and the vertical axis represents the voltage of bit line BL in each of the first and second readout operations.

[0154] like Figure 10 As shown, the voltage drop of bit line BL is faster in the second readout operation compared to the first readout operation. This is because the cell current flowing through the selected memory cell MC when the selected memory cell MC is in a low impedance state (LRS) is larger than the cell current flowing through the selected memory cell MC when it is in a high impedance state (HRS) as in the first readout operation. Furthermore, the voltage of bit line BL stabilizes lower after the drop in the second readout operation compared to the first readout operation. This is because the IV characteristics of the selected memory cell MC differ between the cases where the selected memory cell MC is in a high impedance state (HRS) and the cases where it is in a low impedance state (LRS), as shown in the reference... Figure 7 As stated above.

[0155] Figure 10 The voltage difference of bit line BL between the first and second readout operations is further illustrated by dashed lines, showing how it changes according to the elapsed time at a point in time from the start of the discharge of bit line BL. The changes in voltage difference described below are based, for example, on the different voltage reductions of bit line BL as described above.

[0156] At the start of the discharge, the voltage of bit line BL in the first and second readout actions is equal, and there is no difference between these voltages.

[0157] From the start of discharge until time Δt1 has elapsed, the voltage difference increases with the increase of time.

[0158] Subsequently, the voltage difference decreases as time increases until time Δt2 elapses. At the point in time Δt1 and Δt2 elapsed since the start of discharge, the voltage of bit line BL in the second readout operation stabilizes.

[0159] Subsequently, the voltage difference decreases further with increasing time until a further time Δt3 elapses. This voltage difference decreases by the same proportion as the voltage drop of bit line BL during the first readout operation, and stabilizes at the point in time Δt1, Δt2, and the sum of time Δt3 from the start of discharge. This is because the voltage of bit line BL in the first readout operation stabilizes when the sum of time Δt1, Δt2, and Δt3 has elapsed since the start of discharge. Figure 10 In this context, the voltage difference after stabilization is expressed as voltage difference VD1x.

[0160] In the first readout action, at the moment when time Δts has elapsed since the start of discharge T04 (at Figure 10In the time interval T04, the voltage of bit line BL is sampled. For example, time Δts is the time that is greater than or equal to time Δt1 and less than the sum of Δt1, time Δt2 and time Δt3. Figure 10 This illustrates the case where time Δts is greater than or equal to time Δt1 but less than the sum of time Δt1 and time Δt2. For example, under the control of sequencer 15, this sampling is performed when switch SW2 of the sense amplifier SA becomes on and switch SW3 becomes off, thereby applying the voltage BL of the bit line to the non-inverting input of the operational amplifier circuit AMP. In this specification, the voltage sampled by the first readout action is referred to as voltage Vsmpl. Furthermore, in this specification, sampling the voltage in this manner is also referred to as sense or detection.

[0161] At time Δts after time T04, cell current flows through the selected memory cell MC, therefore the voltage of bit line BL is unstable. That is, the voltage Vsmpl is sampled during the period of voltage change of bit line BL.

[0162] In the second readout action, at the moment when time Δts has elapsed since the start of discharge T24 (at Figure 10 The sampling is performed at time T24s, sampling the voltage of bit line BL. For example, under the control of sequencer 15, this sampling is performed when switch SW2 of the sense amplifier SA turns off and switch SW3 turns on, thereby applying the voltage of bit line BL to the inverting input of operational amplifier circuit AMP. In this specification, the voltage sampled by the second readout operation is called voltage Veval. Voltage Veval is lower than voltage Vsmpl by voltage difference VD1. Voltage difference VD1 is greater than voltage difference VD1x.

[0163] When time Δts is greater than or equal to time Δt1 but less than the sum of time Δt1 and time Δt2, as time Δts elapses from time T24, cell current flows through the selected memory cell MC, therefore the voltage of bit line BL is unstable. That is, voltage Veval is sampled during the voltage variation of bit line BL.

[0164] The result of amplifying the voltage Vsmpl of the non-inverting input terminal based on the voltage Veval of the inverting input terminal is reflected in the signal SADOUT output from the operational amplifier circuit AMP, where the voltage of the signal SADOUT becomes a high level (H).

[0165] The fact that the voltage of the SADOUT signal is at level H means that the data stored in the selection memory unit MC is different at the beginning of the first read operation and at the beginning of the second read operation. Therefore, for example, the sequencer 15 determines, based on the fact that the voltage of the SADOUT signal is at level H, that data "1" which is different from the data "0" stored in the selection memory unit MC at the beginning of the first read operation is stored in the second read operation. As a result, when referring to Figure 9 and Figure 10 In the described read operation, the data "1" is read. On the other hand, for example, the sequencer 15 performs a second write operation based on this determination, so that the data "1" stored at the beginning of the first read operation is stored again in the selected memory unit MC.

[0166] The preceding text has described a time Δts that is, for example, greater than or equal to time Δt1 and less than the sum of times Δt1, Δt2, and Δt3. For example, time Δts can be less than time Δt1 as long as the voltage difference of bit line BL at the point in time Δts from the start of discharge on bit line BL in each of the first and second readout operations is greater than the voltage difference VD1x.

[0167] The above text describes the case where the select memory cell MC is in a high-impedance state (HRS) at the start of the first read operation. The following text will briefly describe the case where the select memory cell MC is in a low-impedance state (LRS) at the start of the first read operation.

[0168] In this scenario, the voltage drop of bit line BL during the first read operation is substantially the same as the voltage drop of bit line BL during the second read operation. As a result, the voltage Vsmpl sampled by the first read operation is substantially the same as the voltage Veval. Since the voltages Vsmpl and Veval are substantially the same, and taking into account the offset voltage, the voltage of signal SADOUT becomes low (L). For example, based on the fact that the voltage of signal SADOUT is at level L, sequencer 15 determines that the data "0" stored during the second read operation is also stored in the selected memory unit MC at the start of the first read operation. As a result, data "0" is read.

[0169] The foregoing has described the case where control for transitioning the selected memory cell MC to a low-impedance state LRS is performed as the first write operation. However, this embodiment is not limited to the above. The techniques disclosed in this specification are also applicable to the case where control for transitioning the selected memory cell MC to a high-impedance state HRS is performed as the first write operation.

[0170] [Beneficial Effects]

[0171] In the reading operation, the storage device 1 according to the first embodiment sequentially performs a first read operation, a first write operation, and a second read operation on the selected storage unit MC.

[0172] In each of the first and second readout operations, the storage device 1 performs the following control on the word line WL and bit line BL corresponding to the selected memory cell MC. First, the storage device 1 stabilizes the voltage of the bit line BL by applying a voltage VBLP, and then sets the bit line BL to a floating state. While keeping the bit line BL in the floating state, the storage device 1 applies a voltage VSS to the word line WL. During the decrease in the voltage of the word line WL due to the application of voltage VSS, the voltage difference between the bit line BL and the word line WL exceeds the voltage VSB. As described above, when the voltage difference reaches the voltage VSB, the switching element S within the selected memory cell MC changes from a closed state to an open state, thus becoming conductive, and the cell current flowing through the selected memory cell MC increases sharply. The cell current flows out from the bit line BL via the transistor Tr8 of the word line WL and the read receiver RS. Therefore, the voltage of the bit line BL decreases. Thus, the storage device 1 decreases the voltage of the bit line BL in each of the first and second readout operations.

[0173] In such a voltage drop of bit line BL, the rate of voltage drop of bit line BL and the voltage of bit line BL after the drop are different between the case where the selected memory cell MC is in a high impedance state (HRS) and the case where the selected memory cell MC is in a low impedance state (LRS).

[0174] In the first read operation, the reference time T04 has elapsed since the discharge from bit line BL began in storage device 1. Figure 10 The voltage Vsmpl of bit line BL is sampled at time T04s, which is described as time Δts. During the second readout operation, storage device 1 samples the voltage Veval of bit line BL at time T24s, which is Δts after the start of discharge from bit line BL. When sampling is performed in this manner, the voltage of bit line BL continues to change, at least when the selected storage cell MC is in a high-impedance state HRS.

[0175] For example, we will describe the case where the selected memory cell MC is in a high-impedance state HRS at the start of the first read operation and in a low-impedance state LRS during the second read operation. In this case, the difference between the sampled voltage Vsmpl and voltage Veval, as described above, is the voltage difference VD1. On the other hand, when the voltage on the bit line BL decreases and stabilizes after both the first and second read operations (hereinafter referred to as the comparative example), the difference between the sampled voltages is the voltage difference VD1x. (See reference...) Figure 10As described, the voltage difference VD1 is greater than the voltage difference VD1x. Based on the voltage difference VD1, the storage device 1 determines the data stored in the selected storage unit MC at the start of the first read operation.

[0176] As described above, compared to the comparative example, when the memory cell MC is selected as the high-impedance state HRS and when the memory cell MC is selected as the low-impedance state, the memory device 1 can perform read operations with a larger sense margin. For example, even when there is a reproducible deviation in the voltage of the bit line BL after discharge, the memory device 1 can accurately perform read operations. Therefore, by using the memory device 1 according to the first embodiment, the frequency of false reads can be reduced, which can help in the design of the operational amplifier circuit AMP for performing correct read operations.

[0177] Furthermore, for storage device 1, compared to the comparative example, the time from the start of the discharge of the voltage of bit line BL to the sampling of the voltage of bit line BL is shorter in each of the first and second read operations. Therefore, the speed of the read operation can be improved by using storage device 1 according to the first embodiment.

[0178] Furthermore, the storage device 1 according to the first embodiment can also achieve the following advantageous effects. Figure 11 This is a diagram illustrating the further advantageous effects that can be obtained from the storage device 1 according to the first embodiment.

[0179] exist Figure 9 In the first read operation of the example, during the voltage drop of bit line BL after time T04, cell current flows from bit line BL through select memory cell MC to word line WL. When select memory cell MC is in a high-impedance state HRS, the cell current can be used as a buffer current. Figure 5 The example shows the write current flowing in the direction of A1, therefore, the MTJ element can transition to a low-impedance state LRS, that is, the selected memory cell MC can transition to a low-impedance state LRS. This means that the data stored in the selected memory cell MC can be reversed during the first read operation (read interference). On the other hand, in Figure 9 In the second read operation of the example, this data reversal does not occur. This is because in the first write operation and the second read operation, the cell current is controlled to flow through the selected memory cell MC in the same direction.

[0180] Figure 11 It is by... Figure 10 The waveform of the bit line BL in the first readout action is replaced with the waveform obtained when this data inversion occurs in the early timing.

[0181] like Figure 11As shown, storage device 1 can perform voltage sampling before the voltage difference between bit line BL in the first read operation and the second read operation disappears due to data inversion.

[0182] Therefore, even if such data reversal occurs during the first read operation, the storage device 1 according to the first embodiment can accurately read the data stored in the selected storage unit at the start of the first read operation.

[0183] [Variation Example]

[0184] The following describes another example of a specific read operation performed by storage device 1. The differences from the example described above and the beneficial effects will be primarily described.

[0185] Figure 12 This is an example of a timing diagram showing the time variation of the voltage applied to the bit line BL and word line WL corresponding to the selected memory cell MC when the memory device 1 performs a read operation according to a modified example of the first embodiment.

[0186] Similarly, in the read operation, the first read operation, the first write operation, and the second read operation are executed sequentially on the selected storage unit MC. After the second read operation, the data stored in the selected storage unit MC at the start of the first read operation is determined. The second write operation can also be executed based on the determination result.

[0187] At time T30, before the read operation begins, the execution of bit line BL and word line WL is combined as follows. Figure 9 The control described at time T00.

[0188] First, the control performed in the first readout action will be described.

[0189] In relation to Figure 9 In the description of the first readout action up to time T04, replacing time T01 with time T31, time T02 with time T32, time T03 with time T33, and time T04 with time T34 holds true. This will describe time T34 and subsequent times. Figure 9 A similar example will be described, where the selected memory cell MC is in a high-impedance state HRS at the start of the first read operation.

[0190] At time T35, during the period when the voltage of bit line BL continues to decrease starting at time T34, voltage VPRE is applied to word line WL. The application of voltage VPRE is performed by turning off transistor Tr8 of the read receiver RS ​​and turning on transistor Tr7 of the precharge circuit RPC.

[0191] As the voltage of word line WL increases due to the application of voltage VPRE, the voltage difference between bit line BL and word line WL drops below voltage VhldH. As described above, when the voltage difference reaches voltage VhldH, the switching element S of the selected memory cell MC changes from the on state to the off state, and the cell current flowing through the selected memory cell MC decreases sharply. Therefore, no cell current flows through the selected memory cell MC, and the voltage of bit line BL is maintained.

[0192] For the subsequent first writing action, in Figure 9 The description of the first action, replacing time T11 with time T41 and time T12 with time T42, is valid.

[0193] The control performed in the subsequent second readout action will be described.

[0194] In relation to Figure 9 In the description of the second readout action up to time T04, the descriptions of replacing time T21 with time T51, time T22 with time T52, time T23 with time T53, and time T24 with time T54 are valid. Time T54 and subsequent times will then be described.

[0195] At time T55, during the period when the voltage of bit line BL continues to decrease starting at time T54, as described in conjunction with time T35, voltage VPRE is applied to word line WL.

[0196] As the voltage of word line WL increases by applying voltage VPRE, the voltage difference between bit line BL and word line WL drops below voltage VhldL. As described above, when the voltage difference reaches voltage VhldL, the switching element S in the selected memory cell MC changes from the on state to the off state, and the cell current flowing through the selected memory cell MC decreases sharply. Therefore, no cell current flows through the selected memory cell MC, and the voltage of bit line BL is maintained.

[0197] Figure 13 This is a diagram illustrating the timing of voltage sampling during the first and second readout operations of the readout amplifier SA of the storage device 1 according to a modified example of the first embodiment.

[0198] Figure 13 It shows the Figure 12 The diagram shows a superposition of the voltage waveforms of bit line BL during the first and second readout operations. Specifically, the two waveforms are superimposed so that the discharge start times T34 and T54 of bit line BL are at the same position on the horizontal axis. Figure 13In the example, the time from time T31 to time T33 is the same as the time from time T51 to time T53. The time from time T33 to time T34 is essentially equal to the time from time T53 to time T54. Furthermore, in... Figure 13 In the example, the time from time T34 to time T35 is the same as the time from time T54 to time T55.

[0199] Similar to Figure 10 , Figure 13 The dotted lines further illustrate how the voltage difference of bit line BL changes over time at the points in time from the start of the discharge of bit line BL to the start of the first readout and the second readout.

[0200] The voltage difference occurs from the moment transistor Tr8 of the read receiver RS ​​turns on (read receiver RS ​​turns on) and begins discharging, until transistor Tr8 of the read receiver RS ​​turns off (read receiver RS ​​turns off). Figure 10 The same applies to the example. The voltage difference is maintained when the read receiver RS ​​goes off and the transistor Tr7 of the precharge circuit RPC goes on. This is because the voltage on the bit line BL is maintained in each of the first and second read operations. Figure 13 In this context, the voltage difference after holding is expressed as voltage difference VD2x.

[0201] exist Figure 12 In the example operation, when the selected memory cell MC is in a high-impedance state HRS at least during the first read operation, the voltage difference VD2x is, for example, larger than the voltage difference VD1x in the comparative example described above. This is because the time Δth from the start of the discharge of the bit line BL to the read receiver RS ​​turning off is greater than or equal to time Δt1, but less than the sum of time Δt1, time Δt2, and time Δt3.

[0202] Similar to Figure 10 For example, Figure 13 This shows the time Δts elapsed from the start of discharge T34 during the first readout action (in Figure 13 The voltage of the bit line BL is sampled at time T34s. Additionally, the second readout operation is similar. Figure 10 The example shows the time Δts elapsed from the start of discharge T54 (in Figure 13 The voltage of bit line BL is sampled at time T54s. Figure 13 It is shown in reference Figure 10Examples of cases where time Δts is greater than or equal to time Δt1 but less than the sum of time Δt1 and time Δt2 within the described time range. After sampling for each of the first and second readout actions, the change of the read receiver RS ​​to the off state described above is performed. Figure 12 and Figure 13 An example is shown where time Δth is greater than or equal to time Δts but less than the sum of times Δt1 and Δt2. The voltage difference of the bit line BL sampled in each of the first and second readout operations is voltage difference VD2. Voltage difference VD2 is greater than or equal to voltage difference VD2x, and greater than voltage difference VD1x in the comparative example.

[0203] Although the above description has described the case where time Δth is greater than or equal to time Δts and less than the sum of time Δt1 and time Δt2, time Δth is not limited to this; it only needs to be greater than or equal to time Δts. In the case where time Δth is, for example, equal to or greater than the sum of time Δt1 and time Δt2 and less than the sum of time Δt1, time Δt2, and time Δt3, regarding the second readout action, and regarding... Figure 12 The situation described at time T55 in the example is different; the voltage of bit line BL is stable when the read receiver RS ​​turns off.

[0204] In the preceding text, the case where time Δts is greater than or equal to time Δt1 but less than the sum of time Δt1 and time Δt2 has been described as an example. This is provided that time Δts satisfies the reference... Figure 10 The conditions described allow for the application of the techniques disclosed in this variation. For example, the case where time Δts is greater than or equal to the sum of time Δt1 and time Δt2 but less than the sum of time Δt1, time Δt2, and time Δt3 is also described. Similarly, in this case, regarding the second readout action, and regarding... Figure 12 The case described in the example at time T55 is different; the voltage of the bit line BL is stable when the read receiver RS ​​turns off.

[0205] As described above, when the voltage of the bit line BL decreases, the read receiver RS ​​can switch to the off state without waiting for the voltage to stabilize after voltage sampling. Figure 12 and Figure 13In the example, the time from the start of the discharge of bit line BL to the read receiver RS ​​turning off is the same in both the first and second readout operations. However, the time from the start of the discharge of bit line BL to the read receiver RS ​​turning off can differ between the first and second readout operations. Furthermore, in each of the first and second readout operations, the read receiver RS ​​can turn off at the same time from the start of the discharge of bit line BL, and the voltage of bit line BL can be sampled after the read receiver RS ​​turns off.

[0206] As described above, in a variation of the first embodiment, for example, at least when the selected memory cell MC is in a high-impedance state HRS, the read receiver RS ​​turns off during the time the voltage on the bit line BL decreases. Thus, because the read receiver RS ​​turns off earlier, the time for current to flow through the selected memory cell MC is shortened, thereby suppressing memory cell degradation.

[0207] Using the storage device 1 of the modified embodiment according to the first embodiment, even if the voltage of the bit line BL is sampled after the read receiver RS ​​is turned off, it is expected that the voltage difference sampled during the first readout operation and the second readout operation will increase. However, since the discharge of the bit line BL is forcibly stopped, reproducibility deviation of the voltage of the bit line BL may occur. However, by performing sampling before the read receiver RS ​​is turned off in the event of reproducibility deviation, the storage device 1 of the modified embodiment according to the first embodiment can suppress reproducibility deviation and accurately sample the voltage of the bit line BL.

[0208] <Second Implementation Method>

[0209] The storage device 1a according to the second embodiment will be described below.

[0210] The structure of the storage device 1a according to the second embodiment will be described mainly in relation to the differences in structure between the storage device 1 according to the first embodiment and the storage device 1 according to the first embodiment.

[0211] Figure 14 This is a block diagram showing a structural example of the storage device 1a according to the second embodiment. As an explanation of the structure of the storage device 1a, the description is valid if the storage system 3 is replaced with storage system 3a, the storage device 1 is replaced with storage device 1a, and the sequencer 15 is replaced with sequencer 15a.

[0212] It should be noted that, regarding storage device 1a, in Figures 2 to 8 In the description, the description of replacing storage device 1 with storage device 1a and sequencer 15 with sequencer 15a is valid. Each of the plurality of storage cells MC in the storage cell array MCA of storage device 1a is grouped such that it is included in any of the plurality of groups.

[0213] Sequencer 15a includes group determination circuit 152. Based on the address information transmitted from command / address input circuit 14 to sequencer 15a, group determination circuit 152 determines which group the memory cell MC, the object of the read operation, belongs to among the plurality of groups. Based on the determination result, sequencer 15a performs timing control in the read operation.

[0214] Figure 15 Examples of various wiring layouts that can be used as voltage transmission paths for each memory cell MC of the memory device 1a according to the second embodiment are shown.

[0215] exist Figure 15 In the example, each of the word lines WL0 to WL(n-1) extends along a first direction D1 in a certain wiring layer, and these word lines WL are arranged adjacent to each other along a second direction D2 in the order of word line WL0, word line WL1, ... word line WL(n-1) with intervals. Figure 15 In the example, each of the bit lines BL0 to BL(m-1) extends along the second direction D2 in another wiring layer, and these bit lines BL are arranged adjacent to each other along the first direction D1 in the order of bit line BL0, bit line BL1, ..., bit line BL(m-1).

[0216] exist Figure 15 In the example, the global word line GWL is set to extend in the second direction D2, and the global bit line GBL is set to extend in the first direction D1.

[0217] For a portion of the global word line GWL connected to the read receiver RS ​​and a portion electrically connected to each of word lines WL0 to WL(n-1) via the line transfer switch group RTS, the following relationship holds, for example: The distance from the portion connected to the read receiver RS ​​to the portion electrically connected to each word line WL increases in the order of word line WL0, word line WL1, ..., and word line WL(n-1).

[0218] For example, for a portion of the global bit line GBL connected to the sense amplifier SA and a portion electrically connected to each of the bit lines BL0 to BL(m-1) via the column transfer switch group CTS, the following relationship holds, for example. That is, the distance from the portion connected to the sense amplifier SA to the portion electrically connected to each bit line BL increases in the order of bit line BL0, bit line BL1, ..., and bit line BL(m-1).

[0219] From this arrangement of various wirings, for example, the relationships described below also hold true for the path from the sense amplifier SA through each memory cell MC to the sense receiver RS. Figure 15In the diagram, such a path is represented by a double-dotted line.

[0220] The memory cell MC connected between bit line BL0 and word line WL0 (in Figure 15 In the diagram, the path associated with the reference MC(0,0) is compared to the memory cell MC (in the diagram) connected between bit line BL0 and word line WL(n-1). Figure 15 In the figure, the path associated with the reference numeral MC(n-1,0) is longer. Specifically, the path associated with the memory cell MC(n-1,0) is the length of the following: the path between the portions of bit line BL0 connected to memory cells MC(0,0) and MC(n-1,0) respectively, and the path between the portions of global word line GWL electrically connected to word lines WL0 and WL(n-1) respectively.

[0221] Furthermore, compared to the path associated with memory cell MC(0,0), the path associated with memory cell MC (in the bit line BL(m-1) and word line WL0) is more specific. Figure 15 In the figure, the path associated with the reference numeral MC(0, m-1) is longer. Specifically, the path length associated with the memory cell MC(0, m-1) is the amount of the path between the portions of the global bit line GBL that are electrically connected to the bit lines BL0 and BL(m-1), respectively, and the portion of the word line WL0 that is connected to the memory cells MC(0,0) and MC(0, m-1), respectively.

[0222] As described above, the path from the sense amplifier SA through a specific memory cell MC to the sense receiver RS ​​becomes longer as the word line WL corresponding to the memory cell MC is word line WL0, word line WL1, ..., and word line WL(n-1). In the following description, shorter paths such as word line WL0 are closer to the "near" side, and longer paths such as word line WL(n-1) are closer to the "far" side.

[0223] On the other hand, the path length increases as the bit line BL corresponding to the memory cell MC becomes bit line BL0, bit line BL1, ..., bit line BL(m-1). In the following description, shorter paths such as bit line BL0 are closer to the "near" side, and longer paths such as bit line BL(m-1) are closer to the "far" side.

[0224] Figure 16 This is a diagram illustrating the grouping of storage cells MC for performing timing control during a read operation in the storage device 1a according to the second embodiment. The grouping described below is merely an example, and the grouping according to this embodiment is not limited thereto.

[0225] First, group the description word lines WL.

[0226] Each of the word lines WL0 to WL(n-1) is included in one of the multiple word line groups WLG. Each word line group WLG includes, for example, multiple word lines WL. The number of word lines WL that make up a single word line group WLG can be the same or different in all word line groups WLG.

[0227] Group the word lines such that the word line group WLGp with a smaller integer p (p is an integer greater than or equal to 1 and less than or equal to 8) is composed of word lines WL that are closer to the "near" side, and the word line group WLGp with a larger integer p is composed of word lines WL that are closer to the "far" side.

[0228] Next, we will describe a grouping example for the bit line BL.

[0229] Each of the bit lines BL0 to BL(m-1) is included in one of a plurality of bit line groups BLG. Each bit line group BLG includes, for example, multiple bit lines BL. The number of bit lines BL that make up a single bit line group BLG may be the same or different in all bit line groups BLG.

[0230] Group the bit lines such that the bit line group BLGq with smaller integers q (q is an integer greater than or equal to 1 and less than or equal to 8) is composed of bit lines BL that are closer to the "near" side, and the bit line group BLGq with larger integers q is composed of bit lines BL that are closer to the "far" side.

[0231] Next, the grouping of storage units (MCs) will be described.

[0232] When the word line WL corresponding to a specific memory cell MC is contained in the word line group WLGt, and the bit line BL corresponding to the memory cell MC is contained in the bit line group BLGu, the value of (t+u) is assigned to that memory cell MC. This assignment is performed for each case where t is an integer from 1 to 8 and u is an integer from 1 to 8. Figure 16 The values ​​allocated in this manner are shown.

[0233] When a value assigned to a storage cell MC in this manner is, for example, 6 or less, the storage cell MC is included in the "near" group. When a value assigned to a storage cell MC in this manner is, for example, 7 or more but less than 11, the storage cell MC is included in the "middle" group. When a value assigned to a storage cell MC in this manner is, for example, 12 or more, the storage cell MC is included in the "far" group.

[0234] The following description will primarily focus on the differences between the operation of the storage device 1a according to the second embodiment and the operation of the storage device 1 according to the first embodiment.

[0235] Equivalent to reference Figure 9 and Figure 10 The given description holds true for the case where a memory cell MC in the "near" group is selected (hereinafter also referred to as the "near" case) and the case where a memory cell MC in the "far" group is selected (hereinafter also referred to as the "far" case).

[0236] Figure 17 This is a diagram illustrating the timing of voltage sampling in the first and second readout operations of the readout amplifier SA of the storage device 1a according to the second embodiment.

[0237] Figure 17 The case of "near" is equivalent to Figure 10 The image, and the case of "far" are equivalent to Figure 10 The image.

[0238] Regarding the situation of "near", it will be with Figure 10 In the example, the time corresponding to time Δt1 is denoted as time Δt1n, and similarly, the time corresponding to time Δt2 is denoted as time Δt2n, and the time corresponding to time Δt3 is denoted as time Δt3n. For the case of "far", the time corresponding to time Δt1 is denoted as time Δt1n. Figure 10 In the example, the time corresponding to time Δt1 is represented as time Δt1f. Similarly, the time corresponding to time Δt2 is represented as time Δt2f, and the time corresponding to time Δt3 is represented as time Δt3f.

[0239] Time Δt1f is longer than time Δt1n, time Δt2f is longer than time Δt2n, and time Δt3f is longer than time Δt3n. This is because, as referenced... Figure 15 The described path from the sense amplifier SA via the selected memory cell MC to the sense receiver RS ​​is longer in the "far" case than in the "near" case, resulting in a larger RC delay in the path used for bit line BL discharge.

[0240] In the "near" case, the voltage of bit line BL is sampled during either the first or second readout operation, for example, during the time period from the start of discharge to the elapsed time Δt1n, but before the sum of times Δt1n, Δt2n, and Δt3n has elapsed. In the "near" case, the time from the start of discharge to the sampling of the voltage of bit line BL is the same in both the first and second readout operations.

[0241] In the "far" case, the voltage of bit line BL is sampled during either the first or second readout operation, for example, during the time period from the start of discharge to the elapsed time Δt1f, but before the sum of times Δt1f, Δt2f, and Δt3f has elapsed. In the "far" case, the time from the start of discharge to the sampling of the voltage of bit line BL is the same in both the first and second readout operations.

[0242] The time from the start of the discharge of bit line BL to the sampling of the voltage of bit line BL can differ between the "near" and "far" cases. For example, when the voltage difference of bit line BL between the first readout operation and the second readout operation is approximately the same during the sampling of the voltage of bit line BL, the time from the start of the discharge of bit line BL to the sampling of the voltage of bit line BL is longer in the "far" case than in the "near" case.

[0243] For multiple or all memory cells MC in the "near" group, for example, even if one of these memory cells MC is the selected memory cell MC, the time from the start of the discharge of bit line BL to the voltage sampling time of bit line BL is substantially the same. Similarly, for multiple or all memory cells MC in the "far" group, even if one of these memory cells MC is the selected memory cell MC, the time from the start of the discharge of bit line BL to the voltage sampling time of bit line BL is substantially the same.

[0244] For example, based on the group determination result of the group related to the selected memory cell MC by the group determination circuit 152, this control based on the sampling timing of the group is performed under the control of the sequencer 15a.

[0245] In the above text, the cases where a memory cell MC in the "near" group and a memory cell MC in the "far" group are selected have been described as examples. (See reference...) Figure 16 As described, when the storage cell MC is divided into multiple groups, timing control similar to that described above can be performed on any two different groups of storage cell MC.

[0246] In addition to the advantageous effects described in the first embodiment, the storage device 1a according to the second embodiment can also achieve the following effects.

[0247] Storage device 1a is capable, for example, of selecting each group including storage cell MC, of ​​using a reference. Figure 10 Described in the same way, set Figure 9The example read operation uses the time from the start of the discharge of bit line BL to the sampling of the voltage of bit line BL. In each group, for example, as long as the memory cell MC in that group is the selected memory cell, the difference in RC delay in the discharge path of bit line BL described above is relatively small. That is, the memory device 1a sets the sampling timing of the voltage of bit line BL that can reliably obtain a read margin for each group. Therefore, even if the difference in RC delay may increase depending on which memory cell MC in the memory cell array MCA is the selected memory cell, the memory device 1a can reliably perform the above-described read operation with a large read margin.

[0248] Therefore, as described in the first embodiment, the storage device 1a according to the second embodiment can reduce the frequency of false reads, which can help in the design of the operational amplifier circuit AMP for performing correct read operations.

[0249] <Other Implementation Methods>

[0250] In the example of a read operation described above, also known as a self-reference read operation, in each of the first and second read operations, the voltage connected to the bit line of the selected memory cell is read, and the two read voltages are compared to determine the data to be read. The techniques disclosed in this specification can also be applied to other read operations. For example, the techniques disclosed in this specification can also be applied to a read operation that reads the value of a specific physical quantity associated with a specific component when the memory cell is in a high-impedance state, and the value of a physical quantity associated with that component or other components when the memory cell is in a low-impedance state, and determines the data stored in the memory cell based on the difference between these two values. This physical quantity can be, for example, voltage or current.

[0251] In this specification, "connection" means electrical connection, but does not exclude the insertion of other components, for example.

[0252] In this specification, the terms "same," "consistent," "certain," "maintain," etc., are intended to be used in cases where including the technology described in the implementation embodiments is incorrect within the scope of design. This also applies when the term "substantially" is used in combination with these expressions, such as "substantially the same." Furthermore, the expression "application or supply of a specific voltage" is intended to encompass both situations: performing control to apply or supply the voltage, and actually applying or supplying the voltage. Additionally, applying or supplying a specific voltage can include applying or supplying, for example, a voltage of 0V.

[0253] While certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. In fact, the novel embodiments described herein can be embodied in many other forms; furthermore, various omissions, substitutions, and changes can be made to the forms of the embodiments described herein without departing from the spirit of the invention. The appended claims and their equivalents are intended to cover such forms or modifications that fall within the scope and spirit of the invention.

[0254] Label Explanation

[0255] 1, 1a: Storage device

[0256] 11: Core Circuit

[0257] 12: Column Decoder

[0258] 13: Line Decoder

[0259] 14: Command / Address Input Circuit

[0260] 15, 15a: Sequencer

[0261] 151: Voltage Generation Circuit

[0262] 152: Group Decision Circuit

[0263] 16: Input / output circuit

[0264] 2: Memory controller

[0265] 3, 3a: Storage system

[0266] 4: Main unit

[0267] MCA: Memory Cell Array

[0268] MC: Storage Unit

[0269] MTJ: MTJ component

[0270] SL, RL: Ferromagnetic materials

[0271] TB: Non-magnetic

[0272] S: Switching element

[0273] CWD: Write Drive

[0274] RWD: Write Drive

[0275] RTS: Line Transfer Switch Group

[0276] CTS: Train Transfer Switch Group

[0277] CPC, RPC: Precharge Circuit

[0278] SA: Readout amplifier

[0279] RS: Read receiver

[0280] GBL: Global Bitline

[0281] GWL: Global Word Line

[0282] BL: Bitline

[0283] WL: Word Line

[0284] RTr, CTr, Tr: Transistor

[0285] CS: Current source

[0286] SW: Switch

[0287] AMP: Operational Amplifier Circuit

Claims

1. A storage device, comprising: The first storage cell includes a first resistance changing element and a first switching element; as well as The control circuit is configured to perform a first detection that detects a first value of a first physical quantity associated with the first storage cell, perform a first write operation for storing first data in the first storage cell, perform a second detection that detects a second value of the first physical quantity associated with the first storage cell after the first write operation, and read second data associated with the first storage cell based on the first value and the second value. At least one of the first value and the second value is a value during a change in the first physical quantity associated with the first storage cell.

2. The storage device according to claim 1, While the first physical quantity associated with the first storage unit is changing, at least one of the first value and the second value is detected.

3. The storage device according to claim 1, The second data is the data stored in the first storage unit at the start of the first detection.

4. The storage device according to claim 1, Each of the first value and the second value is a value obtained by changing the first physical quantity from the third value.

5. The storage device according to claim 4, The first time from the start of the change in the first physical quantity to the detection of the first value in the first detection is substantially equal to the second time from the start of the change in the first physical quantity to the detection of the second value in the second detection.

6. The storage device according to claim 1, The first physical quantity is the voltage of the first wiring connected to the first storage cell.

7. The storage device according to claim 6, The control circuit is further configured as follows: In the first detection, a first voltage is applied to the first wiring to make the first wiring float, and while the first wiring is in the floating state, a second voltage lower than the first voltage is applied to the second wiring connected to the first memory cell, thereby reducing the voltage of the first wiring. In the second detection, the first voltage is applied to the first wiring to make the first wiring float, and while the first wiring is in the floating state, the second voltage is applied to the second wiring to reduce the voltage of the first wiring. Each of the first and second values ​​is obtained by reducing the voltage of the first wiring from the first voltage. At least one of the first value and the second value is a value during the voltage drop period of the first wiring.

8. The storage device according to claim 7, During the voltage drop of the first wiring, at least one of the first value and the second value is detected.

9. The storage device according to claim 7, The first time in the first detection, from the start of the voltage drop in the first wiring to the detection of the first value, is substantially equal to the second time in the second detection, from the start of the voltage drop in the first wiring to the detection of the second value.

10. The storage device according to claim 7, When the first resistance changing element is in a low impedance state at the start of the first detection, the voltage of the first wiring after the drop in the first detection is lower than the voltage when the first resistance changing element is in a high impedance state.

11. The storage device according to claim 7, When the first value is the value during the voltage drop period of the first wiring, The control circuit is further configured such that, during the first detection, the second voltage is not applied to the second wiring during the voltage drop period of the first wiring. When the second value is the value during the voltage drop period of the first wiring, The control circuit is further configured such that, during the second detection, the second voltage is not applied to the second wiring during the voltage drop period of the first wiring.

12. The storage device according to claim 7, further comprising: The second storage unit includes a second resistance changing element and a second switching element. The control circuit is further configured as follows: A third detection is performed, in which the first voltage is applied to the third wiring connected to the second memory cell to make the third wiring float, and while the third wiring is in the floating state, the second voltage is applied to the fourth wiring connected to the second memory cell to reduce the voltage of the third wiring, and a third value obtained by reducing the voltage of the third wiring from the first voltage is detected. Perform a second write operation to store the first data in the second storage unit; After the second write, a fourth detection is performed, in which the first voltage is applied to the third wiring to make the third wiring float, and while the third wiring is in the floating state, the second voltage is applied to the fourth wiring to reduce the voltage of the third wiring, and a fourth value obtained by reducing the voltage of the third wiring from the first voltage is detected. as well as Based on the third and fourth values, read the third data related to the second storage unit. At least one of the third and fourth values ​​is a value during the voltage drop period of the third wiring. In the first detection, the first time from the start of the voltage drop in the first wiring to the detection of the first value is substantially equal to the second time from the start of the voltage drop in the first wiring to the detection of the second value in the second detection. The third time in the third detection, from the start of the voltage drop in the third wiring to the detection of the third value, is substantially equal to the fourth time in the fourth detection, from the start of the voltage drop in the third wiring to the detection of the fourth value. The first storage unit is included in the first group. If the second storage unit is included in the first group, the first time is substantially equal to the third time. When the second storage unit is included in the second group, the first time is different from the third time.

13. The storage device according to claim 12, When the second storage cell is included in the second group, the first time is longer than the third time, and the discharge path of the first wiring in the first detection is longer than the discharge path of the third wiring in the third detection.

14. The storage device according to claim 1, The first resistance-changing element is a magnetic tunnel junction element.

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