A VDMOS device and a manufacturing method thereof

Abstract

A VDMOS device and a manufacturing method thereof, the method comprising: providing a semiconductor substrate; sequentially forming a gate dielectric layer and a gate material layer on the semiconductor substrate; patterning the gate material layer and the gate dielectric layer to form a gate structure with a gate cut-off region, wherein the gate structure comprises at least two gate structure bodies and at least one separation structure between two adjacent gate structure bodies, and the gate cut-off region is between the gate structure body and the separation structure; depositing a sidewall material layer covering the gate structure; etching the sidewall material layer to form a gate sidewall on both sides of the gate structure and an ion implantation blocking layer in the gate cut-off region; and performing ion implantation on the semiconductor substrate with the ion implantation blocking layer as a barrier. The present application reduces the gate leakage capacitance and reduces the number of required patterning processes in the gate cut-off process.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a VDMOS device and its manufacturing method. Background Technology

[0002] Vertical double-diffused metal-oxide-semiconductor (VDMOS) field-effect transistors are widely used as a type of power device due to their advantages of high input impedance and low on-state voltage drop.

[0003] The switching speed of VDMOS is a crucial parameter in high-frequency applications, directly impacting the device's dynamic performance. For high-voltage VDMOS devices, optimizing switching speed should focus on reducing gate-drain capacitance and gate charge. Summary of the Invention

[0004] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. The summary section of this invention is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0005] To address the existing problems, one embodiment of the present invention provides a method for manufacturing a VDMOS device, comprising:

[0006] Provide semiconductor substrates;

[0007] A gate dielectric layer and a gate material layer are sequentially formed on the semiconductor substrate;

[0008] The gate material layer and the gate dielectric layer are patterned to form a gate structure with a gate cut-off region, wherein the gate structure includes at least two gate structure bodies and at least one partition structure located between two adjacent gate structure bodies, and the gate cut-off region is located between the gate structure bodies and the partition structure.

[0009] Deposit a sidewall material layer covering the gate structure;

[0010] The sidewall material layer is etched to form gate sidewalls on both sides of the gate structure and an ion implantation barrier layer in the gate cut-out region.

[0011] Ion implantation is performed on the semiconductor substrate using the ion implantation barrier layer as a barrier.

[0012] In some embodiments, the number of the partition structures is at least two, and the gate cut-off region also includes the gate cut-off region between two adjacent partition structures.

[0013] In some embodiments, the different gate cut-out regions have the same width.

[0014] In some embodiments, the aspect ratio of the gate cut-out region is greater than or equal to 2.

[0015] In some embodiments, the thickness of the sidewall material layer is greater than or equal to 0.3 micrometers.

[0016] In some embodiments, the width of the gate structure body is greater than or equal to 2 micrometers.

[0017] A second aspect of the present invention provides a VDMOS device, which is manufactured using the method described above.

[0018] A third aspect of the present invention provides a VDMOS device, the VDMOS device comprising:

[0019] A semiconductor substrate, wherein an ion implantation region is formed in the semiconductor substrate;

[0020] A gate structure having a gate cut-off region formed on the semiconductor substrate, wherein the gate structure includes at least two gate structure bodies and at least one partition structure located between two adjacent gate structure bodies, and the gate cut-off region is between the gate structure body and the partition structure;

[0021] An ion implantation barrier layer is formed in the gate cut-off region, the top of the ion implantation barrier layer being lower than the top of the gate structure;

[0022] In addition, gate sidewalls are formed on both sides of the gate structure, the material of which is the same as that of the ion implantation barrier layer.

[0023] In some embodiments, the number of the partition structures is greater than or equal to two, and the gate cut-off region further includes the gate cut-off region between two adjacent partition structures.

[0024] In some embodiments, the different gate cut-out regions have the same width.

[0025] In some embodiments, the aspect ratio of the gate cut-out region is greater than or equal to 2.

[0026] In some embodiments, the width of the gate structure body is greater than or equal to 2 micrometers.

[0027] According to the manufacturing method of the VDMOS device provided in the embodiments of the present invention, by setting a partition structure between the gate structure body and the partition structure, a gate cut-out region with a certain aspect ratio is formed between the gate structure body and the partition structure. This allows the subsequently formed sidewall material layer to be retained in the gate cut-out region as an ion implantation barrier layer, reducing the number of patterning processes required in the gate cut-out process. The VDMOS device according to the embodiments of the present invention reduces the gate-drain capacitance through gate cut-out, thereby reducing the switching speed of the VDMOS device and increasing its competitiveness in high-frequency applications. Attached Figure Description

[0028] The following drawings, which are incorporated herein by reference as part of this invention, are provided for understanding the invention. The drawings illustrate embodiments of the invention and their descriptions, serving to explain the principles of the invention.

[0029] In the attached image:

[0030] Figure 1A A schematic diagram of a conventional VDMOS device is shown;

[0031] Figure 1B A schematic diagram of a VDMOS device with a gate structure having a gate cut-off region is shown.

[0032] Figure 2 A schematic flowchart illustrating a method for manufacturing a VDMOS device according to a specific embodiment of the present invention is shown.

[0033] Figures 3A to 3D A schematic cross-sectional view of a semiconductor device obtained by sequentially performing each step of a method for manufacturing a VDMOS device according to an embodiment of the present invention is shown. Detailed Implementation

[0034] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid obscuring the invention.

[0035] It should be understood that the invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0036] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0037] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Thus, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention.

[0038] When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or parts, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0039] The switching characteristics of a VDMOS device are determined by its intrinsic capacitance and parasitic capacitance. The capacitance of a VDMOS device is mainly composed of the gate-source capacitance C. gs Gate-drain capacitance C gd and source-drain capacitance C ds It consists of three parts, such as Figure 1A As shown, the charging and discharging of the capacitor is the main factor limiting the switching speed of VDMOS devices. The gate-source capacitance C... gs It is determined by the design parameters of VDMOS itself, mainly depending on the thickness of the gate dielectric layer; the capacitance C between the drain and source. ds It is a PN junction capacitor, the size of which is determined by the voltage applied between the source and drain; the capacitance C between the gate and drain. gd It directly affects the input capacitance and switching time of the device, therefore reducing the gate-drain capacitance C gd Especially important is the capacitance C between the gate and drain. gd It is C gd(ox) and C gd(dep) The series connection of two capacitors is:

[0040] 1 / C gd =1 / C gd(ox) +1 / C gd(dep)

[0041] Gate cut-off can reduce C. gd(ox) This reduces the gate-drain capacitance C of the VDMOS device. gd . Figure 1B A schematic diagram of a VDMOS device using a gate-cut process is shown. There are two traditional implementation schemes for the gate-cut process:

[0042] The first approach is to cut the gate during the etching of the gate material layer using photolithography; however, when performing ion implantation subsequently, a mask layer needs to be added to prevent the gate cut-out area from being implanted and affecting the JFET (junction field-effect transistor) region.

[0043] The second approach involves adding a photolithography and etching process after ion implantation and before the deposition of the interlayer dielectric layer to remove the gate. This approach also requires an additional photolithography and etching process to remove the gate, increasing the cost.

[0044] The present invention addresses the aforementioned problems. To fully understand the invention, detailed structures and steps will be described below to illustrate the technical solution proposed by the invention. Preferred embodiments of the invention are described in detail below; however, in addition to these detailed descriptions, the invention may have other embodiments.

[0045] Figure 2 A flowchart illustrating the steps of a method for manufacturing a VDMOS device according to an embodiment of the present invention is shown. Figures 3A to 3D A cross-sectional schematic diagram of a semiconductor device obtained by sequentially performing each step of a method for manufacturing a VDMOS device according to an embodiment of the present invention is shown below. Figure 2 as well as Figures 3A to 3DA method for manufacturing a VDMOS device according to an embodiment of the present invention will be described in detail.

[0046] First refer to Figure 2 The method for manufacturing a VDMOS device according to embodiments of the present invention is described, such as... Figure 2 As shown, the manufacturing method 200 of the VDMOS device according to an embodiment of the present invention includes the following steps:

[0047] In step S210, a semiconductor substrate is provided;

[0048] In step S220, a gate dielectric layer and a gate material layer are sequentially formed on the semiconductor substrate;

[0049] In step S230, the gate material layer and the gate dielectric layer are patterned to form a gate structure with a gate cut-off region, wherein the gate structure includes at least two gate structure bodies and at least one partition structure located between two adjacent gate structure bodies, and the gate cut-off region is located between the gate structure body and the partition structure.

[0050] In step S240, a sidewall material layer covering the gate structure is deposited;

[0051] In step S250, the sidewall material layer is etched to form gate sidewalls located on both sides of the gate structure, and an ion implantation barrier layer located in the gate cut-out region.

[0052] In step S260, ion implantation is performed on the semiconductor substrate using the ion implantation barrier layer as a barrier.

[0053] The VDMOS device manufacturing method 200 of this embodiment reduces the gate-drain capacitance by gate cut-out, thereby reducing the switching speed of the VDMOS device and increasing its competitiveness in high-frequency applications. Furthermore, the VDMOS device manufacturing method 200 of this embodiment forms a gate cut-out region with a large depth-to-width ratio by setting a partition structure between the gate structure body and the partition structure, so that the sidewall material layer formed subsequently can be retained in the gate cut-out region as an ion implantation barrier layer, reducing the number of patterning processes required in the gate cut-out process.

[0054] The following is combined Figures 3A to 3D An exemplary description is provided of the implementation process of a method for manufacturing a VDMOS device according to an embodiment of the present invention.

[0055] First, refer to Figure 3AA semiconductor substrate 310 is provided. The semiconductor substrate 310 can be made of undoped single-crystal silicon, doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), or germanium-on-insulator (GeOI), etc. As an example, the semiconductor substrate is made of single-crystal silicon. In some embodiments, the semiconductor substrate 310 may also be implanted to form doped regions within the semiconductor substrate.

[0056] A gate dielectric layer 320 and a gate material layer 330 are sequentially formed on a semiconductor substrate 310. The gate dielectric layer 320 is a silicon oxide layer, and the silicon oxide layer can be formed by methods such as thermal oxidation and chemical vapor deposition. After forming the gate dielectric layer 320, a gate material layer 330 is formed on the gate dielectric layer 320. The gate material layer 330 includes a polysilicon layer, and the methods for forming the gate material layer include, but are not limited to, chemical vapor deposition.

[0057] Next, refer to Figure 3B The gate material layer 330 and the gate dielectric layer 320 are patterned to form a gate structure with a gate cut-off region 360. By forming the gate cut-off region 360 in the gate structure, the gate-drain capacitance and gate charge can be reduced, thereby optimizing the switching speed and increasing the competitiveness of VDMOS devices in high-frequency applications. In this embodiment of the invention, the gate cut-off and gate structure patterning are completed in the same patterning step, saving one patterning step compared to the process of cutting off the gate structure after ion implantation.

[0058] The gate structure includes at least two gate structure bodies 340 and at least one partition structure 350 located between two adjacent gate structure bodies 340. The width of the gate structure body 340 is greater than the width of the partition structure 350. The area between the gate structure body 340 and the partition structure 350 is a gate cut-out region 360. That is, the partition structure 350 is used to separate at least two gate cut-out regions 360 between the two gate structure bodies 340. In this embodiment of the invention, the gate structure is cut out in multiple segments by inserting partition structures 350 between the gate structure bodies 340, thereby reducing the width of the gate cut-out region 360 and increasing the aspect ratio of the gate cut-out region 360. This allows the sidewall material layer formed subsequently to be retained in the gate cut-out region 360 as an ion implantation barrier layer, reducing the number of photolithography steps required for the entire gate cut-out process and lowering costs.

[0059] Exemplarily, the step of patterning the gate material layer 330 and the gate dielectric layer 320 includes: first, forming a photoresist layer over the gate material layer 330. The photoresist coating method includes spin coating, in which centrifugal force causes the solvent to continuously evaporate, thereby forming a uniformly coated photoresist layer. After forming the photoresist layer, the photoresist layer is exposed and developed to form windows in the photoresist layer that expose the areas to be etched.

[0060] Subsequently, using the patterned photoresist layer as a mask, the patterned gate material layer 330 and the gate dielectric layer 320 are dry etched. The dry etching sequentially opens the gate material layer 330 and the gate dielectric layer 320, thereby forming a gate structure with a gate cut-out region 360.

[0061] The dry etching process includes, but is not limited to, reactive ion etching (RIE), ion beam etching, plasma etching, or laser ablation. A single etching method or more than one etching method may be used. The etching endpoint, at the surface of the semiconductor substrate 310, can be controlled using techniques such as endpoint detection or etching time control.

[0062] exist Figure 3B In the example, the gate structure includes two gate structure bodies 340 and at least one partition structure 350 disposed between the two gate structure bodies 340. A gate cut-out region 360 is located between the gate structure bodies 340 and the partition structure 350, and the bottom of the gate cut-out region 360 exposes the upper surface of the semiconductor substrate 310. The partition structure 350 is used to divide the cut-out portion between the two gate structure bodies 340 into at least two narrower gate cut-out regions 360.

[0063] In some embodiments, the number of separator structures 350 is at least two, and the gate cut-off region 360 included in the gate structure includes both the gate cut-off region between the gate structure body 340 and the separator structure 350, and the gate cut-off region between two adjacent separator structures. For example, in Figure 3B In the example, the gate structure includes three gate cut-out regions: a first gate cut-out region between the first gate structure body and the first partition structure, a second gate cut-out region between the first partition structure and the second partition structure, and a third gate cut-out region between the second partition structure and the second gate structure body. Increasing the number of partition structures 350 can further reduce the width of the gate cut-out region 360 and increase the aspect ratio of the gate cut-out region 360. The number of partition structures 350 can be determined according to actual needs.

[0064] To retain the sidewall material layer in the gate cut-off region 360 during etching, the gate cut-off region 360 needs to have a certain aspect ratio. Preferably, the aspect ratio of the gate cut-off region 360 is greater than or equal to 2. Since the depth of the gate cut-off region 360 is fixed, the aspect ratio of the gate cut-off region 360 can be increased by reducing the width of each gate cut-off region 360. For example, the aspect ratio of the gate cut-off region 360 can be ensured by increasing the width of the gate structure body 340, for example, the width of the gate structure body 340 is greater than or equal to 2 micrometers. Alternatively, the width of the gate cut-off region 360 can be reduced by increasing the width of the separator structure 350 or increasing the number of separator structures 350, so that the aspect ratio of the gate cut-off region 360 is greater than or equal to 2.

[0065] In some embodiments, at least two gate cut-off regions have the same width, thereby making the thickness of the ion implantation barrier layer subsequently formed in the at least two gate cut-off regions the same, so as to achieve the same ion implantation barrier effect.

[0066] Next, as Figure 3C As shown, a sidewall material layer 370 is deposited covering the gate structure. The material of the sidewall material layer 370 includes, but is not limited to, silicon oxide, and the method for depositing the sidewall material layer 370 includes chemical vapor deposition. In some embodiments, a flowable chemical vapor deposition process can be used to form the sidewall material layer 370. Flowable chemical vapor deposition has good filling capabilities and is suitable for filling openings with high aspect ratios, thus avoiding the formation of voids in the gate cut-out region 360.

[0067] For example, the thickness of the sidewall material layer 370 is greater than or equal to 0.3 micrometers to ensure that the subsequently formed ion implantation barrier layer has sufficient thickness to ensure the ion implantation blocking effect of the ion implantation barrier layer.

[0068] like Figure 3D As shown, the sidewall material layer is etched to form gate sidewalls 380 located on both sides of the gate structure, and an ion implantation barrier layer 390 located in the gate cut-out region. Due to the presence of the separator structure 350, the gate cut-out region 360 has a larger aspect ratio. A larger aspect ratio results in a lower etching rate. Therefore, the etching process can quickly remove the sidewall material layer on the outside of the gate structure, thereby forming gate sidewalls 380 on both sides of the gate structure. The etching rate of the sidewall material layer in the gate cut-out region is slower, thus allowing a certain thickness of sidewall material layer to be retained in the gate cut-out region 360 as the ion implantation barrier layer 390. Therefore, the ion implantation barrier layer 390 and the gate sidewalls 380 can be formed in the same etching pass, simplifying the process flow.

[0069] Subsequently, ion implantation is performed on the semiconductor substrate 310 using the ion implantation barrier layer 390 as a barrier. The ion implantation barrier layer 390 retained in the gate cut-off region 360 can prevent ion implantation below the gate cut-off region 360, thereby allowing ion implantation to be performed in a generalized manner without the need to form an additional mask to block the gate cut-off region 360 and prevent ion implantation below the gate cut-off region 360. The ion implantation includes body ion implantation, P+ ion implantation, and other ion implantations that require the gate structure as a barrier, and can be any ion implantation required for conventional VDMOS devices; ion implantation can be a single implantation or multiple implantations, and this embodiment of the invention does not limit this.

[0070] This completes the process steps for manufacturing a VDMOS device according to an embodiment of the present invention. It is understood that the semiconductor device manufacturing method of this embodiment includes not only the above-described steps, but may also include other necessary steps before, during, or after the above steps, all of which are included within the scope of the manufacturing method of this embodiment. The VDMOS device manufacturing method of this embodiment can be used on SGT (split-gate low-voltage field-effect transistor), SJ (superjunction), and IGBT (insulated-gate bipolar transistor) VDMOS platforms.

[0071] In summary, the VDMOS device manufacturing method 200 provided by the present invention reduces the gate-drain capacitance by gate cut-out, thereby reducing the switching speed of the VDMOS device and increasing its competitiveness in high-frequency applications. Furthermore, the VDMOS device manufacturing method 200 of the present invention forms a gate cut-out region with a large depth-to-width ratio between the gate structure body and the partition structure by setting a partition structure between the gate structure body and the partition structure, so that the sidewall material layer formed subsequently can be retained in the gate cut-out region as an ion implantation barrier layer, reducing the number of patterning processes required in the gate cut-out process.

[0072] This invention also provides a VDMOS device, which is manufactured by the VDMOS device manufacturing method 200 described above.

[0073] This invention also provides a VDMOS device, see [link to relevant documentation]. Figure 3DThe VDMOS device includes: a semiconductor substrate 310 in which an ion-implanted region (not shown) is formed; a gate structure having a gate cut-off region formed on the semiconductor substrate 310, wherein the gate structure includes at least two gate structure bodies 340 and at least one partition structure 350 located between two adjacent gate structure bodies 340, the gate cut-off region being between the gate structure bodies 340 and the partition structure 350; an ion-implanted barrier layer 390 formed in the gate cut-off region, the top of the ion-implanted barrier layer 390 being lower than the top of the gate structure; and gate sidewalls 380 formed on both sides of the gate structure, the material of the gate sidewalls 380 being the same as the material of the ion-implanted barrier layer 390.

[0074] In some embodiments, the number of partition structures 350 is greater than or equal to two, and the gate cut-off region also includes a gate cut-off region between two adjacent partition structures, that is, the number of gate cut-off regions is at least three. An ion implantation barrier layer 390 is formed in each gate cut-off region, and the height of each ion implantation barrier layer 390 is the same.

[0075] In some embodiments, the different gate cut-out regions have the same width.

[0076] In some embodiments, the aspect ratio of the gate cut-off region is greater than or equal to 2. Since the ion implantation barrier layer 390 is formed by etching the sidewall material layer in the gate cut-off region, the aspect ratio of the ion implantation barrier layer 390 is slightly less than 2.

[0077] In some embodiments, the width of the gate structure body 340 is greater than or equal to 2 micrometers to ensure that the gate cut-out region has a sufficient aspect ratio when the total width of the gate structure is constant.

[0078] In summary, the VDMOS device provided by the present invention reduces the gate-drain capacitance by gate cut-out, thereby reducing the switching speed of the VDMOS device and increasing its competitiveness in high-frequency applications.

[0079] The present invention has been described through the above embodiments. However, it should be understood that the above embodiments are for illustrative purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, those skilled in the art will understand that the present invention is not limited to the above embodiments, and many more variations and modifications can be made based on the teachings of the present invention, all of which fall within the scope of protection claimed by the present invention. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method of manufacturing a VDMOS device, characterized by, The method comprises: providing a semiconductor substrate; forming a gate dielectric layer and a gate material layer on the semiconductor substrate in sequence; patterning the gate material layer and the gate dielectric layer to form a gate structure with a gate cut-off region, wherein the gate structure comprises at least two gate structure bodies and at least one separation structure between adjacent two gate structure bodies, the gate cut-off region is between the gate structure bodies and the separation structure, and the aspect ratio of the gate cut-off region is greater than or equal to 2; depositing a sidewall material layer covering the gate structure; etching the sidewall material layer to form a gate sidewall on both sides of the gate structure and an ion implantation blocking layer in the gate cut-off region; performing ion implantation on the semiconductor substrate with the ion implantation blocking layer as a barrier.

2. The production method according to claim 1, wherein The number of the separation structures is at least two, and the gate cut-off region further comprises a gate cut-off region between adjacent two separation structures.

3. The production method according to claim 1, wherein The widths of different gate cut-off regions are the same.

4. The production method according to claim 1, wherein The thickness of the sidewall material layer is greater than or equal to 0.3 microns.

5. A VDMOS device, characterized by, The VDMOS device is manufactured by the method of any one of claims 1-4.

6. A VDMOS device, characterized by, The VDMOS device comprises: a semiconductor substrate in which an ion implantation region is formed; a gate structure with a gate cut-off region formed on the semiconductor substrate, wherein the gate structure comprises at least two gate structure bodies and at least one separation structure between adjacent two gate structure bodies, the gate cut-off region is between the gate structure bodies and the separation structure, the gate structure bodies and the separation structure each comprise a gate dielectric layer and a gate material layer formed on the gate dielectric layer, the aspect ratio of the gate cut-off region is greater than or equal to 2, and the gate cut-off region is used to reduce the gate-drain capacitance of the VDMOS device; an ion implantation blocking layer formed in the gate cut-off region, the top of the ion implantation blocking layer being lower than the top of the gate structure; and a gate sidewall formed on both sides of the gate structure, the material of the gate sidewall being the same as that of the ion implantation blocking layer.

7. The VDMOS device of claim 6, wherein, The number of the separation structures is greater than or equal to two, and the gate cut-off region further comprises a gate cut-off region between adjacent two separation structures.

8. The VDMOS device of claim 6 or 7, wherein, The widths of different gate cut-off regions are the same.

9. The VDMOS device of claim 6, wherein, The width of the gate structure body is greater than or equal to 2 microns.

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