Dual-resistance state vertical monolayer mxene memristor
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- DALIAN UNIV OF TECH
- Filing Date
- 2022-11-25
- Publication Date
- 2026-06-12
AI Technical Summary
Existing memristors exhibit a gradual multi-resistance effect during multiple signal writing processes, leading to data distortion and requiring additional write verification operations, which affects programming speed and reliability.
A two-resistance vertical monolayer MXene memristor structure is adopted, including a substrate, a top electrode, a monolayer Ti3C2Tx MXene intermediate layer, and a bottom electrode. A stepped vertical channel and an asymmetric spatial electric field distribution are formed by etching. Combined with dissimilar metal electrodes, an asymmetric Schottky barrier is formed to achieve self-rectification effect and specific gating interval.
This method achieves stability of the memristor's resistance state under voltage signal stimulation, avoids resistance drift, improves the reliability of write verification, reduces false reads and writes, and enhances the stability of array operation.
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Figure CN115835771B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor technology and relates to a fixed two-resistance memristor, specifically a two-resistance vertical single-layer MXene memristor. Background Technology
[0002] The gradient resistance of existing memristors makes signal storage a highly cumulative process, leading to data distortion during multiple writes. A significant drawback of high-speed memristor storage with multiple signal levels is the requirement for an additional write verification operation before the next reprogramming step to ensure operation within the '0 / 1' threshold range. Furthermore, supporting more levels necessitates smaller and more precise input and output pulses for setting and resetting, severely slowing down programming, reducing write performance, and causing unpredictable read / write errors and device failures due to over-threshold operations. Existing memristors, due to the gradient resistance effect under input voltage pulse signals, cannot meet the requirements of high-speed information storage and complex binary logic operations, while also introducing a significant hardware burden and algorithmic redundancy for external read circuitry. Summary of the Invention
[0003] The technical problem to be solved by this invention is to provide a dual-resistance vertical single-layer MXene memristor to solve the problem of the memristor's gradual multi-resistance effect, avoid resistance drift caused by multiple signal read and write operations, and avoid the need for additional write verification operations.
[0004] The technical solution of this invention is:
[0005] A dual-resistivity vertical monolayer MXene memristor includes a substrate, a top electrode, a monolayer Ti3C2Tx MXene intermediate layer, and a bottom electrode.
[0006] The substrate is etched with stepped vertical channels; the bottom electrode is located on the lower plane of the vertical channel, i.e., the surface of the lower step, and is attached to the sidewall of the vertical channel; the monolayer Ti3C2Tx MXene intermediate layer covers the upper surface and sidewall of the vertical channel, as well as the upper surface of the bottom electrode; the top electrode is located on the upper plane of the vertical channel, i.e., the surface of the upper step, and is located on the monolayer Ti3C2Tx MXene intermediate layer at the corresponding position.
[0007] The substrate is a non-conductive hard solid substrate, including silicon dioxide, etc.
[0008] The vertical channel has a depth of 20nm-100nm and is prepared on the substrate by reactive ion etching.
[0009] The top electrode is made of a high work function metal, including aluminum, silver, titanium, etc. The top electrode is deposited using thermal evaporation or magnetron sputtering methods, and the thickness of the top electrode is 20nm-50nm. The distance between the top electrode and the vertical edge of the vertical channel is 100nm-200nm.
[0010] The bottom electrode is made of a low work function metal, including platinum, gold, nickel, etc.; it is deposited using thermal evaporation or magnetron sputtering methods, with a bottom thickness of 20nm-50nm and a vertical distance of more than 20nm between the upper surface and the upper plane of the vertical channel.
[0011] The monolayer Ti3C2Tx MXene intermediate layer is obtained by oxidizing a monolayer Ti3C2Tx MXene solution. The preparation method is as follows: prepare a monolayer Ti3C2Tx MXene solution with a concentration of 0.01-0.02 mg / mL, stir and heat at 50-70℃ for 1.5-3 hours to complete the oxidation process, and then use polydimethylsiloxane (PDMS) to transfer the monolayer Ti3C2Tx MXene onto the surface of the vertical channel.
[0012] The beneficial effects of this invention are:
[0013] 1. This invention has only two stable resistance states, which maintain the stability of the resistance state under voltage signal stimulation, solves the memristor's gradual multi-resistance effect, and avoids the problem of resistance drift caused by multiple signal reading and writing processes, which requires additional write verification operations.
[0014] 2. This invention introduces an asymmetric spatial electric field distribution and an asymmetric intermediate layer structure through a vertical channel, thereby realizing the construction of a stable two-resistance memristor.
[0015] 3. This invention introduces an asymmetric Schottky barrier by using different top and bottom electrodes, forming a self-rectification effect and a specific gating interval, which can solve the crosstalk and misreading problem in array operation. Attached Figure Description
[0016] Figure 1 This is a schematic diagram of a two-resistance vertical single-layer MXene memristor.
[0017] In the figure: 1 top electrode, 2 monolayer Ti3C2Tx MXene intermediate layer, 3 vertical channel, 4 bottom electrode.
[0018] Figure 2 This is the IV characteristic diagram of a vertically aligned monolayer MXene memristor with the same electrodes.
[0019] Figure 3 This is the IV characteristic diagram of a single-layer MXene memristor without vertical channels.
[0020] Figure 4 This is the IV characteristic diagram of a vertical monolayer MXene memristor with insufficient oxidation of the intermediate layer.
[0021] Figure 5 This is the IV characteristic diagram of a two-resistance vertical single-layer MXene memristor.
[0022] Figure 6 This is an asymmetric Schottky IV test plot of a two-resistance vertical monolayer MXene memristor.
[0023] Figure 7 This is a stable two-resistance state IV scan diagram of a two-resistance state vertical monolayer MXene memristor. Detailed Implementation
[0024] The specific embodiments of the present invention will be further described below with reference to the accompanying drawings and technical solutions.
[0025] The structure of the two-resistance vertical single-layer MXene memristor of the present invention is as follows: Figure 1 As shown, its composition includes: a substrate, a top electrode 1, a monolayer Ti3C2Tx MXene intermediate layer 2, and a bottom electrode 4. Stepped vertical channels 3 are etched on the substrate. The top electrode 1 can be made of aluminum, or optionally, high work function metals such as silver or titanium can be used instead; the bottom electrode 4 can be made of platinum, or optionally, low work function metals such as gold or nickel can be used instead.
[0026] The bottom electrode 4 is fabricated on the lower plane of the vertical channel 3, and its end is attached to the sidewall of the vertical channel 3. A monolayer Ti3C2TxMXene intermediate layer 2 is uniformly attached to the upper plane, sidewall, and upper surface of the bottom electrode 4 of the vertical channel 3. The top electrode 1 is fabricated on the monolayer Ti3C2TxMXene intermediate layer 2 located on the upper plane of the vertical channel 3.
[0027] The vertical channel 3 has a depth of 20nm-100nm and is fabricated on the substrate using reactive ion etching. An asymmetric spatial electric field distribution and an asymmetric intermediate layer structure are introduced through the vertical channel 3. Necessarily, the upper plane of the vertical channel 3 is more than 20nm away from the upper surface of the bottom electrode 4.
[0028] A specific embodiment of fabricating a two-resistivity vertical monolayer MXene memristor is as follows:
[0029] Example 1:
[0030] The top electrode 1 is made of aluminum with a thickness of 20 nm and covers the top end of the monolayer Ti3C2Tx MXene intermediate layer 2. The monolayer Ti3C2Tx MXene intermediate layer 2 is attached to the vertical channel 3 with a depth of 40 nm. The sidewall of the vertical channel 3 is 100 nm away from the top electrode 1. The top end of the monolayer Ti3C2Tx MXene intermediate layer 2 is attached to the upper plane of the vertical channel 3 and the bottom end is attached to the upper surface of the bottom electrode 4. The bottom electrode 4 is made of platinum with a thickness of 20 nm and is fabricated on the lower plane of the vertical channel 3 to obtain a two-resistivity vertical monolayer MXene memristor.
[0031] The preparation process of the monolayer Ti3C2Tx MXene intermediate layer 2 is as follows:
[0032] A monolayer Ti3C2Tx MXene solution with a concentration of 0.01 mg / mL was prepared and stirred and heated at 50 °C for 3 hours to complete the oxidation process. Then, the monolayer Ti3C2Tx MXene was transferred to the surface of the vertical channel using polydimethylsiloxane (PDMS).
[0033] Example 2:
[0034] The top electrode 1 is made of metallic silver with a thickness of 35 nm, covering the monolayer Ti3C2Tx MXene intermediate layer 2. The monolayer Ti3C2Tx MXene intermediate layer 2 is attached to the vertical channel 3, which has a depth of 60 nm and a distance of 150 nm between the sidewall of the vertical channel 3 and the top electrode 1. The first end of the monolayer Ti3C2Tx MXene intermediate layer 2 is attached to the upper plane of the vertical channel 3, and the last end is attached to the upper surface of the bottom electrode 4. The bottom electrode 4 is made of metallic gold with a thickness of 35 nm, and is fabricated on the lower plane of the vertical channel 3 to obtain a two-resistivity vertical monolayer MXene memristor.
[0035] The preparation process of the monolayer Ti3C2Tx MXene intermediate layer 2 is as follows:
[0036] A monolayer Ti3C2Tx MXene solution with a concentration of 0.015 mg / mL was prepared and oxidized by stirring and heating at 60 °C for 2.5 hours. Then, the monolayer Ti3C2Tx MXene was transferred to the surface of the vertical channel using polydimethylsiloxane (PDMS).
[0037] Example 3:
[0038] The top electrode 1 is made of titanium with a thickness of 50 nm, covering the monolayer Ti3C2Tx MXene intermediate layer 2. The monolayer Ti3C2Tx MXene intermediate layer 2 is attached to the vertical channel 3, which has a depth of 100 nm and a distance of 200 nm between the sidewall of the vertical channel 3 and the top electrode 1. The first end of the monolayer Ti3C2Tx MXene intermediate layer 2 is attached to the upper plane of the vertical channel 3, and the last end is attached to the upper surface of the bottom electrode 4. The bottom electrode 4 is made of nickel with a thickness of 50 nm, and is fabricated on the lower plane of the vertical channel 3 to obtain a two-resistivity vertical monolayer MXene memristor.
[0039] The preparation process of the monolayer Ti3C2Tx MXene intermediate layer 2 is as follows:
[0040] A monolayer Ti3C2Tx MXene solution with a concentration of 0.02 mg / mL was prepared and stirred and heated at 70 °C for 1.5 hours to complete the oxidation process. Then, the monolayer Ti3C2Tx MXene was transferred to the surface of the vertical channel using polydimethylsiloxane (PDMS).
[0041] Comparative Example 1:
[0042] The top electrode 1 is made of aluminum with a thickness of 20 nm, covering the top end of the monolayer Ti3C2Tx MXene intermediate layer 2. The monolayer Ti3C2Tx MXene intermediate layer 2 is attached to the vertical channel 3, which has a depth of 40 nm. The sidewall of the vertical channel 3 is 100 nm away from the top electrode 1. The top end of the monolayer Ti3C2Tx MXene intermediate layer 2 is attached to the upper plane of the vertical channel 3, and the bottom end is attached to the upper surface of the bottom electrode 4. The bottom electrode 4 is made of the same aluminum as the top electrode with a thickness of 20 nm, and is fabricated on the lower plane of the vertical channel 3 to obtain a vertical monolayer MXene memristor with the same electrode material. The monolayer Ti3C2Tx MXene intermediate layer 2 is oxidized by stirring and heating a monolayer Ti3C2Tx MXene solution with a concentration of 0.01 mg / mL at 50 °C for 3 hours, and then the monolayer Ti3C2Tx MXene is transferred to the surface of the vertical channel using polydimethylsiloxane (PDMS). Vertical monolayer MXene memristors with the same electrode material cannot achieve stable memristor performance; their IV characteristic diagram is shown below. Figure 2 As shown.
[0043] Comparative Example 2:
[0044] The top electrode 1 is made of aluminum with a thickness of 20 nm and covers the top end of the monolayer Ti3C2Tx MXene intermediate layer 2. The monolayer Ti3C2Tx MXene intermediate layer 2 is attached to the vertical channel 3 with a depth of 20 nm. The sidewall of the vertical channel 3 is 100 nm away from the top electrode 1. The top end of the monolayer Ti3C2Tx MXene intermediate layer 2 is attached to the upper plane of the vertical channel 3 and the bottom end is attached to the upper surface of the bottom electrode 4. The bottom electrode 4 is made of platinum with a thickness of 20 nm and is fabricated on the lower plane of the vertical channel 3. At this time, the surface of the bottom electrode 4 is flush with the upper plane of the vertical channel 2, thus obtaining a monolayer MXene memristor without a vertical channel. In this process, the monolayer Ti3C2Tx MXene intermediate layer 2 is prepared by oxidizing a 0.01 mg / mL monolayer Ti3C2Tx MXene solution at 50°C for 3 hours with stirring. Then, polydimethylsiloxane (PDMS) is used to transfer the monolayer Ti3C2Tx MXene onto the vertical channel surface. Monolayer MXene memristors without vertical channels cannot achieve stable memristor performance; their IV characteristic diagram is shown below. Figure 3 As shown.
[0045] Comparative Example 3:
[0046] The top electrode 1 is made of aluminum with a thickness of 20 nm, covering the top end of the monolayer Ti3C2Tx MXene intermediate layer 2. The monolayer Ti3C2Tx MXene intermediate layer 2 is attached to the vertical channel 3, which has a depth of 40 nm and a sidewall distance of 100 nm from the top electrode 1. The top end of the monolayer Ti3C2Tx MXene intermediate layer 2 is attached to the upper plane of the vertical channel 3, and the bottom end is attached to the upper surface of the bottom electrode 4. The bottom electrode 4 is made of platinum with a thickness of 20 nm, and is fabricated on the lower plane of the vertical channel 3, thus obtaining a vertical monolayer MXene memristor. The monolayer Ti3C2Tx MXene intermediate layer 2 is prepared by stirring and heating the solution at 50 °C for 1 hour at a concentration of 0.01 mg / mL to ensure insufficient oxidation of the Ti3C2Tx MXene solution, followed by transfer of the monolayer Ti3C2Tx MXene to the surface of the vertical channel using polydimethylsiloxane (PDMS). At this point, the memristor cannot produce stable and excellent memristor performance, and its IV characteristic diagram is as follows: Figure 4 As shown, the switching ratio is only 10, and there is no self-rectification effect, which cannot meet the requirements for stable anti-crosstalk misreading performance.
[0047] Comparative Example 4:
[0048] The top electrode 1 is made of aluminum with a thickness of 20 nm, covering the top end of the monolayer Ti3C2Tx MXene intermediate layer 2. The monolayer Ti3C2Tx MXene intermediate layer 2 is attached to the vertical channel 3, which has a depth of 40 nm and a sidewall distance of 100 nm from the top electrode 1. The top end of the monolayer Ti3C2Tx MXene intermediate layer 2 is attached to the upper plane of the vertical channel 3, and the bottom end is attached to the upper surface of the bottom electrode 4. The bottom electrode 4 is made of platinum with a thickness of 20 nm, and is fabricated on the lower plane of the vertical channel 3, thus obtaining a vertical monolayer MXene memristor. The monolayer Ti3C2Tx MXene intermediate layer 2 is prepared by over-oxidizing the Ti3C2Tx MXene solution at a concentration of 0.01 mg / mL by stirring and heating at 50 °C for 5 hours, followed by transfer of the monolayer Ti3C2Tx MXene to the surface of the vertical channel using polydimethylsiloxane (PDMS). At this point, the single-layer Ti3C2Tx MXene intermediate layer completely loses its conductivity, and the memristor cannot conduct.
[0049] The IV characteristic diagram of the two-resistance vertical monolayer MXene memristor prepared in Example 1 is shown below. Figure 5 As shown, it exhibits obvious self-rectified bipolar resistive-state switching behavior, with an on / off ratio reaching 3×10⁻⁶. 4 The dual-resistivity vertical monolayer MXene memristor maintains a high resistance state and possesses 1×10⁻⁶ resistance within the forward scan range of 0V to +5.8V. -4 The operating current is initially low (μA), until the voltage exceeds +5.8V, at which point the resistor state instantaneously switches to a low-resistance state with an operating current of 3μA. The operating current of the two-resistance vertical monolayer MXene memristor remains stable under reverse operating voltages from +5.8V to +3.0V, and begins to decrease at a bias voltage of +3V. Then, at a reset voltage of -5.5V, it switches from a low-resistance state to a high-resistance state, restoring a current of 1×10⁻⁶. -4 A small operating current of μA; asymmetric Schottky IV test pattern formed by dissimilar metal electrodes, as shown in... Figure 6 As shown, a gating interval can be formed between +1V and +1.7V under low resistance conditions, making the conduction state of this interval different from that of the -1V to -1.7V interval, which can effectively avoid crosstalk and misreading in array operation.
[0050] During operation, for a dual-resistance vertical monolayer MXene memristor with a set voltage of +5.8V and a reset voltage of -5.5V, applying a +6V, 100ns set voltage pulse to the top electrode 1 switches the dual-resistance vertical monolayer MXene memristor to a low-resistance state. At this state, applying any read voltage from -5.5V to 0V, any positive read voltage, or a positive cyclic voltage scan will maintain a stable single-resistance state without resistance drift. Applying a -6V reset voltage switches the memristor to a high-resistance state. At this state, applying any positive read voltage from +6V to 0V, or any negative read voltage, or a negative scan will not cause resistance drift. The stable dual-resistance IV scan diagram is shown below. Figure 7 As shown.
Claims
1. A two-resistance-state vertical single-layer MXene memristor, characterized in that, The aforementioned dual-resistivity vertical monolayer MXene memristor includes a substrate, a top electrode, a monolayer Ti3C2Tx MXene intermediate layer, and a bottom electrode; The substrate is etched with stepped vertical channels; the bottom electrode is located on the lower plane of the vertical channel, i.e., the surface of the lower step, and is attached to the sidewall of the vertical channel; the monolayer Ti3C2Tx MXene intermediate layer covers the upper surface and sidewall of the vertical channel, as well as the upper surface of the bottom electrode; the top electrode is located on the upper plane of the vertical channel, i.e., the surface of the upper step, and is located on the monolayer Ti3C2Tx MXene intermediate layer at the corresponding position; The top electrode is made of a high work function metal, and the bottom electrode is made of a low work function metal; the substrate is a non-conductive hard solid substrate.
2. The dual-resistivity vertical single-layer MXene memristor according to claim 1, characterized in that, The vertical channel has a depth of 20nm-100nm and is prepared on the substrate by reactive ion etching.
3. A dual-resistivity vertical single-layer MXene memristor according to claim 1 or 2, characterized in that, The top electrode is made of aluminum, silver, or titanium; it is deposited using thermal evaporation or magnetron sputtering, and has a thickness of 20nm-50nm; the distance between the top electrode and the vertical edge of the vertical channel is 100nm-200nm.
4. A dual-resistivity vertical single-layer MXene memristor according to claim 1 or 2, characterized in that, The bottom electrode is made of platinum, gold, or nickel; it is deposited using thermal evaporation or magnetron sputtering methods, with a bottom thickness of 20nm-50nm and a vertical distance greater than 20nm between the upper surface and the upper plane of the vertical channel.
5. A dual-resistivity vertical single-layer MXene memristor according to claim 3, characterized in that, The bottom electrode is made of platinum, gold, or nickel; it is deposited using thermal evaporation or magnetron sputtering methods, with a bottom thickness of 20nm-50nm and a vertical distance greater than 20nm between the upper surface and the upper plane of the vertical channel.
6. A dual-resistivity vertical single-layer MXene memristor according to claim 1, 2, or 5, characterized in that, The monolayer Ti3C2Tx MXene intermediate layer is obtained by oxidizing a monolayer Ti3C2Tx MXene solution. The preparation method is as follows: prepare a monolayer Ti3C2Tx MXene solution with a concentration of 0.01-0.02 mg / mL, stir and heat at 50-70℃ for 1.5-3 hours to complete the oxidation process, and then use polydimethylsiloxane to transfer the monolayer Ti3C2Tx MXene onto the surface of the vertical channel.
7. A dual-resistivity vertical single-layer MXene memristor according to claim 3, characterized in that, The monolayer Ti3C2Tx MXene intermediate layer is obtained by oxidizing a monolayer Ti3C2Tx MXene solution. The preparation method is as follows: prepare a monolayer Ti3C2Tx MXene solution with a concentration of 0.01-0.02 mg / mL, stir and heat at 50-70℃ for 1.5-3 hours to complete the oxidation process, and then use polydimethylsiloxane to transfer the monolayer Ti3C2Tx MXene onto the surface of the vertical channel.
8. A dual-resistivity vertical single-layer MXene memristor according to claim 4, characterized in that, The monolayer Ti3C2Tx MXene intermediate layer is obtained by oxidizing a monolayer Ti3C2Tx MXene solution. The preparation method is as follows: prepare a monolayer Ti3C2Tx MXene solution with a concentration of 0.01-0.02 mg / mL, stir and heat at 50-70℃ for 1.5-3 hours to complete the oxidation process, and then use polydimethylsiloxane to transfer the monolayer Ti3C2Tx MXene onto the surface of the vertical channel.