Method and apparatus for processing scheduling task, and electronic device and storage medium

Abstract

The embodiments of the present application relate to the technical field of task scheduling. Provided are a method and apparatus for processing a scheduling task, and an electronic device and a storage medium. The method comprises: acquiring a directed acyclic graph task, a node layer count corresponding to the directed acyclic graph task, and the number of tasks corresponding to subtasks in the directed acyclic graph task; performing calculation on the basis of the node layer count and the number of tasks, so as to obtain a parallelism factor corresponding to the directed acyclic graph task; determining an adjustment threshold corresponding to the parallelism factor; acquiring execution time information corresponding to each subtask, and performing calculation on the basis of the execution time information, so as to obtain an execution time difference corresponding to the subtask; performing time adjustment on the directed acyclic graph task on the basis of the execution time difference and the adjustment threshold, so as to determine a target deadline corresponding to the directed acyclic graph task; and screening processors on the basis of the target deadline, so as to obtain a target processor for executing the directed acyclic graph task, and executing the directed acyclic graph task by means of the target processor. Therefore, the scheduling success rate and the execution efficiency are improved.

Description

Methods, devices, electronic equipment, and storage media for scheduling tasks.

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 2024117617394, filed on December 3, 2024, entitled “Processing Method, Apparatus, Electronic Device and Storage Medium for Scheduling Tasks”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of task scheduling technology, and in particular to a method for processing scheduled tasks, a device for processing scheduled tasks, an electronic device, and a computer-readable storage medium. Background Technology

[0004] Currently, research on DAG (Directed Acyclic Graph) scheduling problems in cloud environments focuses primarily on optimizing overall completion time, cost, and multi-objective optimization, tending to consider the optimization problem from the user's perspective. However, from the cloud service provider's perspective, resource utilization and scheduling success rate are closely related to service quality and profitability. Cloud environments contain abundant computing, storage, and network resources, and their pay-as-you-go billing model means that improving resource utilization generates greater economic benefits. Improving scheduling success rate not only enhances user satisfaction and the cloud service provider's competitiveness but also allows them to serve more users, generating greater profits. However, in the task scheduling process in cloud environments, tasks that are ready early often fail to execute quickly, while later tasks are prone to exceeding their execution deadlines, leading to overall task scheduling failures and long execution times for scheduling algorithms. Summary of the Invention

[0005] This application provides a method, apparatus, electronic device, and computer-readable storage medium for processing scheduled tasks, in order to solve or partially solve the problems of low scheduling success rate and long execution time in the task scheduling process in cloud environments.

[0006] This application discloses a method for processing scheduled tasks, including:

[0007] Obtain the directed acyclic graph task, the number of node layers corresponding to the directed acyclic graph task, and the number of tasks corresponding to subtasks in the directed acyclic graph task. The number of node layers represents the hierarchical structure of the directed acyclic graph task.

[0008] The parallelism factor corresponding to the directed acyclic graph task is obtained by calculating based on the number of node layers and the number of tasks. The parallelism factor is used to measure the degree of parallelism of the directed acyclic graph task.

[0009] Determine the adjustment threshold corresponding to the parallel factor;

[0010] Obtain the execution time information corresponding to each of the subtasks, and calculate the execution time difference corresponding to each subtask based on the execution time information;

[0011] The time of the directed acyclic graph task is adjusted based on the execution time difference and the adjustment threshold to determine the target deadline for the directed acyclic graph task.

[0012] The processors are filtered according to the target deadline to obtain the target processor for executing the directed acyclic graph task, and the directed acyclic graph task is executed by the target processor.

[0013] In some feasible implementations, the step of calculating the parallelism factor corresponding to the directed acyclic graph task based on the number of node layers and the number of tasks includes:

[0014] Obtain the number of processors corresponding to the processors used to execute the directed acyclic graph task;

[0015] The parallelism factor corresponding to the directed acyclic graph task is obtained by calculating the number of node layers, the number of tasks, and the number of processors.

[0016] In some feasible implementations, the parallelism factor corresponding to the directed acyclic graph task is calculated using the number of node layers, the number of tasks, and the number of processors, and is achieved through the following formula:

[0017] Wherein, m is the number of processors, n is the number of subtasks in the directed acyclic graph task, and ML is the number of node layers corresponding to the directed acyclic graph task.

[0018] In some feasible implementations, determining the adjustment threshold corresponding to the parallel factor includes:

[0019] Obtain the transmission duration corresponding to each of the subtasks;

[0020] Calculate the total transmission time corresponding to the directed acyclic graph task based on the transmission time of the sub-task;

[0021] The total transmission time and the parallel factor are used to calculate the corresponding adjustment threshold, which is used to adjust the deadline of the directed acyclic graph task.

[0022] In some feasible implementations, the execution time information includes at least the sub-deadline time corresponding to the subtask, the execution duration, and the transmission duration between the subtask and the directed acyclic graph task. The execution time difference corresponding to the subtask is calculated based on the execution time information using the following formula: temp = TDL j -w j -c i,j v j ∈succ(v i )

[0023] Wherein, temp is the execution time difference, and TDL is... j For the sub-deadline time, w j For the execution duration, c i,j For the transmission duration, the succ(v) i ) represents the subtasks in the directed acyclic graph task.

[0024] In some feasible implementations, the step of adjusting the time of the directed acyclic graph task based on the execution time difference and the adjustment threshold to determine the target deadline for the directed acyclic graph task includes:

[0025] The subtask with the smallest execution time difference is selected as the target subtask.

[0026] If the target transmission duration between the target subtask and the directed acyclic graph task is greater than the adjustment threshold, the first deadline corresponding to the directed acyclic graph task is obtained by calculating the target execution time difference and the target transmission duration corresponding to the target subtask.

[0027] If the target transmission time between the target subtask and the directed acyclic graph task is less than the adjustment threshold, then the target execution time difference corresponding to the target subtask is taken as the second deadline corresponding to the directed acyclic graph task.

[0028] In some feasible implementations, the step of filtering processors based on the target deadline to obtain a target processor for executing the directed acyclic graph task, and then executing the directed acyclic graph task through the target processor, includes:

[0029] Obtain the gaps corresponding to each processor, as well as the start and end times of the gaps;

[0030] Obtain the ready time and execution duration of the directed acyclic graph task on each of the processors;

[0031] Target processors are selected from the processors to perform the directed acyclic graph task, and the target processors satisfy the following conditions:

[0032] ① The length of the slot |slot| is not less than v i Execution time w i ;

[0033] ② The start time (sst) and end time (sft) of a slot can cover v. i The execution is completed, and the actual execution time does not exceed v. i Target Deadline TDL i That is, it satisfies formulas (1) and (2). avail(v i ,r p )>sst∩avail(v i ,r p And w i ≤sft∩avail(v i ,r p And w i ≤TDL i (1) avail(v i ,r p )≤sst∩sstandw i ≤sst and w i ∩sft≤TDL i (2)

[0034] Wherein, the slot is the gap, and the v i For the directed acyclic graph task, the avail(v i ,r p ) is the directed acyclic graph task in processor r p Readiness time.

[0035] This application also discloses a processing apparatus for scheduling tasks, comprising:

[0036] The data acquisition module is used to acquire the directed acyclic graph task, the number of node layers corresponding to the directed acyclic graph task, and the number of tasks corresponding to the subtasks in the directed acyclic graph task. The number of node layers represents the hierarchical structure of the directed acyclic graph task.

[0037] The factor calculation module is used to calculate the parallel factor corresponding to the directed acyclic graph task based on the number of node layers and the number of tasks. The parallel factor is used to measure the degree of parallelism of the directed acyclic graph task.

[0038] A threshold determination module is used to determine the adjustment threshold corresponding to the parallel factor;

[0039] The time difference calculation module is used to obtain the execution time information corresponding to each of the sub-tasks, and to calculate the execution time difference corresponding to the sub-tasks based on the execution time information.

[0040] The time adjustment module is used to adjust the time of the directed acyclic graph task according to the execution time difference and the adjustment threshold, and to determine the target deadline corresponding to the directed acyclic graph task.

[0041] The execution module is used to filter processors according to the target deadline, obtain a target processor for executing the directed acyclic graph task, and execute the directed acyclic graph task through the target processor.

[0042] In some feasible implementations, the factor calculation module is specifically used for:

[0043] Obtain the number of processors corresponding to the processors used to execute the directed acyclic graph task;

[0044] The parallelism factor corresponding to the directed acyclic graph task is obtained by calculating the number of node layers, the number of tasks, and the number of processors.

[0045] In some feasible implementations, the factor calculation module is specifically used to implement the following formula:

[0046] Wherein, m is the number of processors, n is the number of subtasks in the directed acyclic graph task, and ML is the number of node layers corresponding to the directed acyclic graph task.

[0047] In some feasible implementations, the threshold determination module is specifically used for:

[0048] Obtain the transmission duration corresponding to each of the subtasks;

[0049] Calculate the total transmission time corresponding to the directed acyclic graph task based on the transmission time of the sub-task;

[0050] The total transmission time and the parallel factor are used to calculate the corresponding adjustment threshold, which is used to adjust the deadline of the directed acyclic graph task.

[0051] In some feasible implementations, the execution time information includes at least the sub-deadline time corresponding to the subtask, the execution duration, and the transmission duration between the subtask and the directed acyclic graph task. The time difference calculation module is specifically used to implement this using the following formula: temp = TDL j -w j -c i,jv j ∈succ(v i )

[0052] Wherein, temp is the execution time difference, and TDL is... j For the sub-deadline time, w j For the execution duration, c i,j For the transmission duration, the succ(v) i ) represents the subtasks in the directed acyclic graph task.

[0053] In some feasible implementations, the adjustment module is specifically used for:

[0054] The subtask with the smallest execution time difference is selected as the target subtask.

[0055] If the target transmission duration between the target subtask and the directed acyclic graph task is greater than the adjustment threshold, the first deadline corresponding to the directed acyclic graph task is obtained by calculating the target execution time difference and the target transmission duration corresponding to the target subtask.

[0056] If the target transmission time between the target subtask and the directed acyclic graph task is less than the adjustment threshold, then the target execution time difference corresponding to the target subtask is taken as the second deadline corresponding to the directed acyclic graph task.

[0057] In some feasible implementations, the execution module is specifically used for:

[0058] Obtain the gaps corresponding to each processor, as well as the start and end times of the gaps;

[0059] Obtain the ready time and execution duration of the directed acyclic graph task on each of the processors;

[0060] Target processors are selected from the processors to perform the directed acyclic graph task, and the target processors satisfy the following conditions:

[0061] ① The length of the slot |slot| is not less than v i Execution time w i ;

[0062] ② The start time (sst) and end time (sft) of a slot can cover v. i The execution is completed, and the actual execution time does not exceed v. i Target Deadline TDL i That is, it satisfies formulas (1) and (2). avail(v i ,r p )>sst∩avail(vi ,r p And w i ≤sft∩avail(v i ,r p And w i ≤TDL i (1) avail(v i ,r p )≤sst∩sstandw i ≤sst and w i ∩sft≤TDL i (2)

[0063] Wherein, the slot is the gap, and the v i For the directed acyclic graph task, the avail(v i ,r p ) is the directed acyclic graph task in processor r p Readiness time.

[0064] This application also discloses an electronic device, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus;

[0065] The memory is used to store computer programs;

[0066] When the processor executes a program stored in the memory, it implements the method described in the embodiments of this application.

[0067] This application also discloses a computer-readable storage medium storing instructions that, when executed by one or more processors, cause the processors to perform the methods described in this application.

[0068] The embodiments of this application have the following advantages:

[0069] In this embodiment, during the processing of the scheduling task, the following steps are taken: First, the directed acyclic graph (DAG) task, the number of node layers corresponding to the DAG task, and the number of subtasks within the DAG task are obtained. The number of node layers represents the hierarchical structure of the DAG task. Then, a parallelism factor corresponding to the DAG task is calculated based on the number of node layers and the number of tasks. This parallelism factor measures the degree of parallelism of the DAG task, and an adjustment threshold corresponding to the parallelism factor is determined. Next, the execution time information of each subtask is obtained, and the execution time difference of the subtasks is calculated based on this information. Finally, the DAG task is adjusted according to the execution time difference and the adjustment threshold. By adjusting the time frame and determining the target deadline for the directed acyclic graph (DAG) task, and by calculating the corresponding adjustment threshold and parallel factor, the deadline for the DAG task is relaxed. This facilitates the allocation of scheduled tasks to the same processor, improves the success rate of task scheduling, and saves the algorithm's execution time. At the same time, based on the adjusted target deadline, the processor is selected to execute the DAG task. Executing the DAG task through the target processor effectively solves the problem that tasks that are ready earlier in DAG scheduling cannot be executed quickly, while tasks that are later are likely to exceed their deadlines, thus ensuring the success rate of DAG scheduling.

[0070] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0071] Figure 1 is a flowchart of the steps of a scheduling task processing method provided in an embodiment of this application;

[0072] Figure 2 is a structural block diagram of a task scheduling processing device provided in an embodiment of this application;

[0073] Figure 3 is a block diagram of an electronic device provided in an embodiment of this application. Specific Implementation

[0074] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0075] To enable those skilled in the art to better understand the technical solutions in the embodiments of this application, some technical features involved in the embodiments of this application are explained and described below:

[0076] SDWS (Subtasks Deadlines Workflow Scheduling) is a workflow scheduling algorithm based on subtask deadlines.

[0077] DAG (Directed Acyclic Graph): refers to a directed graph without cycles. In graph theory, if a directed graph cannot start from a certain node, pass through several nodes, and return to the initial node, it is called a directed acyclic graph.

[0078] FCFS (First Come First Serve) algorithm: A unidirectional acyclic graph workflow scheduling algorithm. It processes tasks sequentially based on their arrival time, from smallest to largest.

[0079] HEFT (Heterogeneous Earliest Finish Time) algorithm: another unidirectional acyclic graph workflow scheduling algorithm. At each step, the task with the highest upward rank is selected and assigned to a processor.

[0080] PW (Processor Weight): One of the reference standards for selecting a processor for a task.

[0081] TDL (time deadlines): The latest end time calculated from the bottom up of a parent task of the exit task.

[0082] As an example, based on a review of workflow scheduling methods with deadline constraints, list scheduling algorithms can achieve good results with relatively low complexity, making them one of the important methods for studying workflow scheduling problems. Among related technologies, list scheduling algorithms mainly include:

[0083] The core idea of ​​the FCFS algorithm is First-Come, First-Served. Once a task is ready, it is added to the ready queue. The algorithm prioritizes the task that was added to the ready queue earliest, calculates the earliest start time of that task on each processor, and schedules it to the processor with the earliest start time. This algorithm is simple to implement, and its core "first-come, first-served" principle is frequently used to solve various problems.

[0084] The HEFT algorithm is an important algorithm for scheduling problems in directed acyclic graphs, mainly consisting of two steps: task priority sorting and processor allocation. First, the upweight (Rank) of each task is calculated. u To determine task priority, where Rank u A higher rank indicates a higher task priority. u The calculation method is shown in formula (4-1), where It is task v i Average execution time across all processors For task v i and v j The average data transmission time between them The communication startup time with the processor is highly correlated with the data transfer time between processors. A bottom-up approach is used to calculate the Rank. u .

[0085] After calculating the Rank corresponding to each task u Then, Rank u The task priority queue is used as the basis for task scheduling. The earliest execution time of the current task on each processor is calculated, and the task is scheduled to the processor with the smallest earliest execution time.

[0086] The main steps of the Min-Min algorithm are to calculate the earliest execution time (eft) of all ready tasks on each processor, prioritize scheduling the task with the smallest eft to its corresponding processor, update the ready queue after scheduling, and recalculate the eft of ready tasks.

[0087] The Max-Min algorithm is similar to the Min-Min algorithm, both first calculating the EFT (Effective Time Scale) of all ready tasks on each processor. The difference is that the Max-Min algorithm prioritizes scheduling the task with the largest EFT to its corresponding processor. After scheduling, it updates the ready queue and recalculates the EFT of all ready tasks.

[0088] In workflow scheduling, users often only provide the deadline for the directed acyclic graph (DAG) without explicitly specifying the sub-deadlines for each task. However, if only the DAG deadline is considered as a sub-deadline for each task during scheduling, tasks at the beginning of the DAG may not be executed quickly enough, while tasks at the end are highly likely to exceed their deadlines, leading to DAG scheduling failure. Such scheduling algorithms are extremely ineffective.

[0089] In this application, by calculating the sub-deadlines of each task and ignoring gaps after the deadline, we can ensure that ready tasks are executed as early as possible, improving the scheduling success rate, while avoiding scanning useless gaps and quickly determining whether the directed acyclic graph (DAG) scheduling has failed, thus saving the algorithm's execution time. Specifically, in the process of processing the scheduling task, we obtain the DAG task, the number of node layers corresponding to the DAG task, and the number of tasks corresponding to the subtasks within the DAG task. The number of node layers represents the hierarchical structure of the DAG task. Then, based on the number of node layers and the number of tasks, we calculate the parallelism factor corresponding to the DAG task. The parallelism factor measures the degree of parallelism of the DAG task and determines the adjustment threshold corresponding to the parallelism factor. Next, we obtain the execution time information of each subtask and calculate the execution time difference of the subtasks based on this information. Finally, we adjust the DAG task based on the execution time difference and the adjustment threshold. The algorithm adjusts the time between tasks to determine the target deadline for each directed acyclic graph (DAG) task. By calculating the corresponding adjustment threshold and parallel factor, the deadline for the DAG task is relaxed, which helps to allocate the scheduled tasks to the same processor, improves the success rate of task scheduling, and saves the execution time of the algorithm. At the same time, the processor is selected based on the adjusted target deadline to obtain the target processor for executing the DAG task. The DAG task is then executed by the target processor, which can effectively solve the problem that the tasks that are ready earlier in the DAG scheduling cannot be executed as soon as possible, while the tasks that are later are very likely to exceed the deadline, thus ensuring the success rate of DAG scheduling.

[0090] Referring to Figure 1, a flowchart of the steps of a task scheduling method provided in an embodiment of this application is shown, which may specifically include the following steps:

[0091] Step 101: Obtain the directed acyclic graph task, the number of node layers corresponding to the directed acyclic graph task, and the number of tasks corresponding to subtasks in the directed acyclic graph task. The number of node layers represents the hierarchical structure of the directed acyclic graph task.

[0092] In this embodiment, the directed acyclic graph (DAG) task is a task flow constructed using a DAG, which may include several nodes, each corresponding to a subtask. Different subtasks can be connected by directed edges (dependencies). The node level can represent the hierarchical structure of the DAG task. The node level can be determined by identifying a starting node, traversing downwards along the directed edges, incrementing the level by 1 for each node visited, and recording the level for each node.

[0093] Step 102: Calculate the parallelism factor corresponding to the directed acyclic graph task based on the number of node layers and the number of tasks. The parallelism factor is used to measure the degree of parallelism of the directed acyclic graph task.

[0094] In this embodiment of the application, after determining the number of node layers and the number of tasks, the corresponding parallelism factor can be calculated. The parallelism factor is used to measure the degree of parallelism of the directed acyclic graph task. The larger the parallelism factor, the higher the degree of parallelism of the directed acyclic graph task. Conversely, the smaller the parallelism factor, the lower the degree of parallelism of the directed acyclic graph task.

[0095] In some feasible implementations, the parallelism factor corresponding to the directed acyclic graph task can be obtained by acquiring the number of processors corresponding to the processors used to execute the task, and then calculating using the number of node layers, the number of tasks, and the number of processors.

[0096] In practical implementation, the parallelism factor can be calculated using the following formula:

[0097] Wherein, m is the number of processors, n is the number of subtasks in the directed acyclic graph task, and ML is the number of node layers corresponding to the directed acyclic graph task.

[0098] Step 103: Determine the adjustment threshold corresponding to the parallel factor;

[0099] Once the parallelism factor is determined, an adjustment threshold for adjusting the deadline of directed acyclic graph (DAG) tasks can be calculated. This adjustment threshold allows for a more relaxed deadline for DAG tasks, which is beneficial for allocating scheduling tasks to the same processor, improving the success rate of task scheduling, and saving algorithm execution time.

[0100] In some feasible implementations, the transmission duration of each subtask can be obtained first. Then, the total transmission duration of the directed acyclic graph (DAG) task can be calculated based on the transmission duration of each subtask. Finally, the total transmission duration is used in conjunction with a parallelism factor to obtain a corresponding adjustment threshold. This threshold is used to adjust the deadline of the DAG task. Here, the transmission duration can be the data transmission duration of each subtask. By summing the transmission durations of each subtask, the total transmission duration of the DAG task can be obtained.

[0101] In one example, the maximum number of layers ML and the parallelism factor η corresponding to the directed acyclic graph task are calculated. The parallelism factor η is used to measure the degree of parallelism of the directed acyclic graph structure, and its calculation is as follows: As shown in the figure. Here, m is the number of processors, n is the number of tasks in the directed acyclic graph, and ML is the number of directed acyclic layers.

[0102] After obtaining the parallel factor, it can be calculated according to the formula. and the formula should(v i ) = c out (v i )×(1-η) calculate subtask v i Total transmission time c out By calculating the total transmission time and the threshold, we can further combine the parallel factor to calculate the adjustment threshold for adjusting the deadline of the directed acyclic graph (DAG) task. This allows us to relax the overall deadline of the DAG task by adjusting the threshold, so that the scheduled tasks can be allocated to the same processor for execution, thereby improving the success rate of task scheduling and saving the execution time of the algorithm.

[0103] Step 104: Obtain the execution time information corresponding to each of the subtasks, and calculate the execution time difference corresponding to the subtasks based on the execution time information;

[0104] After calculating the corresponding adjustment threshold, for each subtask involved in the directed acyclic graph task, the execution time information of the subtask can be further obtained. Then, the execution time difference of each subtask can be determined based on the execution time difference, so as to determine how to adjust the deadline of the directed acyclic graph task.

[0105] The execution time information includes at least the sub-deadline, execution duration, and transmission duration between the sub-task and the directed acyclic graph (DAG) task. This can be achieved using the following formula: temp = TDL j -w j -c i,j v j ∈succ(v i )

[0106] Where temp is the execution time difference, TDL j For the sub-deadline, w j For execution duration, c i,j For transmission duration, succ(v i ) represents a subtask in a directed acyclic graph task.

[0107] Step 105: Adjust the time of the directed acyclic graph task according to the execution time difference and the adjustment threshold, and determine the target deadline corresponding to the directed acyclic graph task;

[0108] In this embodiment, after calculating the execution time difference, the subtask with the smallest execution time difference can be taken as the target subtask. Then, the transmission duration between each subtask and the directed acyclic graph task is determined. The execution time difference is compared with the transmission duration. If the target transmission duration between the target subtask and the directed acyclic graph task is greater than the adjustment threshold, the target execution time difference and target transmission duration corresponding to the target subtask are used to calculate the first deadline corresponding to the directed acyclic graph task. If the target transmission duration between the target subtask and the directed acyclic graph task is less than the adjustment threshold, the target execution time difference corresponding to the target subtask is taken as the second deadline corresponding to the directed acyclic graph task. Thus, by calculating the corresponding adjustment threshold and parallel factor, the deadline of the directed acyclic graph task is relaxed, which is beneficial to allocate the scheduled tasks to the same processor for execution, improve the success rate of task scheduling, and save the execution time of the algorithm.

[0109] In one example, for the directed acyclic graph task v i All subtasks v j According to the formula: temp = TDL j -w j -c i,j v j ∈succ(v i )

[0110] Calculate the intermediate value temp for each subtask in turn, and then record the one with the smallest intermediate value temp. min subtask v min If v i and v min Data transmission duration c i,min If it exceeds the threshold, then TDL i for temp min +c i,j Otherwise TDL i =temp min By calculating the corresponding adjustment threshold and parallel factor, the deadline for directed acyclic graph tasks can be relaxed, which is beneficial to allocate scheduling tasks to the same processor for execution, improve the success rate of task scheduling, and save the execution time of the algorithm.

[0111] In one example, the relaxation of sub-deadlines for directed acyclic graph tasks can be shown in the following code:

[0112] The algorithm process described above is explained as follows:

[0113] 1. Initialization:

[0114] DL is the deadline for the entire directed acyclic graph, n is the total number of tasks, and TDL is the time limit for the entire directed acyclic graph. exit This is the latest end time for the export task, initialized to DL.

[0115] 2. Calculate the maximum number of layers and the value of η:

[0116] ML is the maximum level of a directed acyclic graph, representing the hierarchical structure of tasks.

[0117] W exit It refers to the execution time of the export task.

[0118] formula Calculate the value of η.

[0119] 3. Topological sorting:

[0120] Perform a topological sort on the tasks in the directed acyclic graph to obtain a topologically sorted list, TopoTaskList. Topological sorting ensures that tasks are arranged according to their dependencies. exit This is the last task.

[0121] 4. Calculate the latest end time from bottom to top:

[0122] Starting from the second-to-last task in the topologically sorted list TopoTaskList, iterate backwards through each task v. i .

[0123] succ is v i The set of subtasks, representing v i The follow-up tasks.

[0124] according to Computational subtask v i Total transmission time c out .

[0125] Initialize temp min The maximum value is c, and c is -1.

[0126] 5. Traverse subtasks:

[0127] For v i Each subtask v j Calculate temp←TDL j -w j -c i,j , indicating v j Latest end time minus v j Execution time and v i With v j The communication time between them.

[0128] If temp is less than temp minThen update temp min Set temp, and update c to c. i,j .

[0129] 6. Adjust the latest end time:

[0130] If c>c out ×(1-η), then temp min Adding 'c' indicates that additional time is needed to handle communication delays.

[0131] Update TDL i for temp min , indicating v i The latest end time.

[0132] Step 106: Filter the processors according to the target deadline to obtain the target processor for executing the directed acyclic graph task, and execute the directed acyclic graph task through the target processor.

[0133] In this embodiment of the application, after relaxing the deadline for the directed acyclic graph task, the directed acyclic graph task can be assigned to a suitable processor for execution according to the adjusted deadline.

[0134] It should be noted that in the process of selecting processors, overhead (execution time + output time) other than task execution and data transfer can be ignored, such as computation startup, communication startup, etc. It is assumed that the data transfer time between tasks is independent of the task execution time, and that the processor's execution process and data transfer process do not affect each other. That is, the processor can execute tasks while transferring data to other processors.

[0135] In the specific implementation, the gaps corresponding to each processor, as well as the start and end times of the gaps, can be obtained. The ready time and execution duration of the directed acyclic graph (DAG) task on each processor can also be obtained. Then, based on the determined parameters, the target processor for executing the DAG task can be selected from the processors. The target processor must satisfy the following conditions:

[0136] ① The length of the slot |slot| is not less than v i Execution time w i ;

[0137] ② The start time (sst) and end time (sft) of a slot can cover v. i The execution is completed, and the actual execution time does not exceed v. i Target Deadline TDL i That is, it satisfies formulas (1) and (2). avail(v i ,rp )>sst∩avail(v i ,r p And w i ≤sft∩avail(v i ,r p And w i ≤TDL i (1) avail(v i ,r p )≤sst∩sstandw i ≤sst and w i ∩sft≤TDL i (2)

[0138] Where slot is an empty space, v i For a directed acyclic graph task, avail(v i ,r p For directed acyclic graph tasks in processor r p Readiness time.

[0139] Optionally, the directed acyclic graph task v i When allocating processors, only processors with suitable gaps for insertion are considered. Forcibly assigning a processor to an unsuitable one is highly likely to cause the scheduling to exceed the deadline. Even if the current processor has the lowest power, it will not be considered if there is no suitable gap. Thus, processors are filtered based on the adjusted target deadline to obtain the target processor for executing directed acyclic graph (DAG) tasks. By executing DAG tasks through the target processor, the problem of tasks that are ready earlier in DAG scheduling cannot be executed as soon as possible, while tasks that are later are highly likely to exceed the deadline is effectively solved, thus ensuring the success rate of DAG scheduling.

[0140] It should be noted that the embodiments of this application include, but are not limited to, the examples described above. It is understood that those skilled in the art can make further settings according to actual needs under the guidance of the ideas in the embodiments of this application, and this application does not impose any restrictions on this.

[0141] In this embodiment, during the processing of the scheduling task, the following steps are taken: First, the directed acyclic graph (DAG) task, the number of node layers corresponding to the DAG task, and the number of subtasks within the DAG task are obtained. The number of node layers represents the hierarchical structure of the DAG task. Then, a parallelism factor corresponding to the DAG task is calculated based on the number of node layers and the number of tasks. This parallelism factor measures the degree of parallelism of the DAG task, and an adjustment threshold corresponding to the parallelism factor is determined. Next, the execution time information of each subtask is obtained, and the execution time difference of the subtasks is calculated based on this information. Finally, the DAG task is adjusted according to the execution time difference and the adjustment threshold. By adjusting the time frame and determining the target deadline for the directed acyclic graph (DAG) task, and by calculating the corresponding adjustment threshold and parallel factor, the deadline for the DAG task is relaxed. This facilitates the allocation of scheduled tasks to the same processor, improves the success rate of task scheduling, and saves the algorithm's execution time. At the same time, based on the adjusted target deadline, the processor is selected to execute the DAG task. Executing the DAG task through the target processor effectively solves the problem that tasks that are ready earlier in DAG scheduling cannot be executed quickly, while tasks that are later are likely to exceed their deadlines, thus ensuring the success rate of DAG scheduling.

[0142] It should be noted that, for the sake of simplicity, the method embodiments are all described as a series of actions. However, those skilled in the art should understand that the embodiments of this application are not limited to the described order of actions, because according to the embodiments of this application, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also understand that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of this application.

[0143] Referring to Figure 2, a structural block diagram of a task scheduling processing device provided in an embodiment of this application is shown, which may specifically include the following modules:

[0144] The data acquisition module 201 is used to acquire the directed acyclic graph task, the number of node layers corresponding to the directed acyclic graph task, and the number of tasks corresponding to the subtasks in the directed acyclic graph task, wherein the number of node layers represents the hierarchical structure of the directed acyclic graph task.

[0145] The factor calculation module 202 is used to calculate based on the number of node layers and the number of tasks to obtain the parallel factor corresponding to the directed acyclic graph task. The parallel factor is used to measure the degree of parallelism of the directed acyclic graph task.

[0146] Threshold determination module 203 is used to determine the adjustment threshold corresponding to the parallel factor;

[0147] The time difference calculation module 204 is used to obtain the execution time information corresponding to each of the sub-tasks, and to calculate the execution time difference corresponding to the sub-tasks based on the execution time information.

[0148] The time adjustment module 205 is used to adjust the time of the directed acyclic graph task according to the execution time difference and the adjustment threshold, and determine the target deadline corresponding to the directed acyclic graph task.

[0149] The execution module 206 is used to filter processors according to the target deadline, obtain a target processor for executing the directed acyclic graph task, and execute the directed acyclic graph task through the target processor.

[0150] In some feasible implementations, the factor calculation module 202 is specifically used for:

[0151] Obtain the number of processors corresponding to the processors used to execute the directed acyclic graph task;

[0152] The parallelism factor corresponding to the directed acyclic graph task is obtained by calculating the number of node layers, the number of tasks, and the number of processors.

[0153] In some feasible implementations, the factor calculation module 202 is specifically used to implement the following formula:

[0154] Wherein, m is the number of processors, n is the number of subtasks in the directed acyclic graph task, and ML is the number of node layers corresponding to the directed acyclic graph task.

[0155] In some feasible implementations, the threshold determination module 203 is specifically used for:

[0156] Obtain the transmission duration corresponding to each of the subtasks;

[0157] Calculate the total transmission time corresponding to the directed acyclic graph task based on the transmission time of the sub-task;

[0158] The total transmission time and the parallel factor are used to calculate the corresponding adjustment threshold, which is used to adjust the deadline of the directed acyclic graph task.

[0159] In some feasible implementations, the execution time information includes at least the sub-deadline time corresponding to the subtask, the execution duration, and the transmission duration between the subtask and the directed acyclic graph task. The time difference calculation module 204 is specifically used to implement this through the following formula: temp = TDL j -wj -c i,j v j ∈succ(v i )

[0160] Wherein, temp is the execution time difference, and TDL is... j For the sub-deadline time, w j For the execution duration, c i,j For the transmission duration, the succ(v) i ) represents the subtasks in the directed acyclic graph task.

[0161] In some feasible implementations, the adjustment module is specifically used for:

[0162] The subtask with the smallest execution time difference is selected as the target subtask.

[0163] If the target transmission duration between the target subtask and the directed acyclic graph task is greater than the adjustment threshold, the first deadline corresponding to the directed acyclic graph task is obtained by calculating the target execution time difference and the target transmission duration corresponding to the target subtask.

[0164] If the target transmission time between the target subtask and the directed acyclic graph task is less than the adjustment threshold, then the target execution time difference corresponding to the target subtask is taken as the second deadline corresponding to the directed acyclic graph task.

[0165] In some feasible implementations, the execution module 206 is specifically used for:

[0166] Obtain the gaps corresponding to each processor, as well as the start and end times of the gaps;

[0167] Obtain the ready time and execution duration of the directed acyclic graph task on each of the processors;

[0168] Target processors are selected from the processors to perform the directed acyclic graph task, and the target processors satisfy the following conditions:

[0169] ① The length of the slot |slot| is not less than v i Execution time w i ;

[0170] ② The start time (sst) and end time (sft) of a slot can cover v. i The execution is completed, and the actual execution time does not exceed v. i Target Deadline TDL i That is, it satisfies formulas (1) and (2). avail(v i,r p )>sst∩avail(v i ,r p And w i ≤sft∩avail(v i ,r p And w i ≤TDL i (1) avail(v i ,r p )≤sst∩sstandw i ≤sst and w i ∩sft≤TDL i (2)

[0171] Wherein, the slot is the gap, and the v i For the directed acyclic graph task, the avail(v i ,r p ) is the directed acyclic graph task in processor r p Readiness time.

[0172] As the device embodiment is basically similar to the method embodiment, the description is relatively simple, and relevant parts can be found in the description of the method embodiment.

[0173] In addition, this application also provides an electronic device, including: a processor, a memory, and a computer program stored in the memory and executable on the processor. When the computer program is executed by the processor, it implements the various processes of the above-described processing method embodiment for scheduling tasks and achieves the same technical effect. To avoid repetition, it will not be described again here.

[0174] This application also provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it implements the various processes of the above-described scheduling task processing method embodiment and achieves the same technical effect. To avoid repetition, it will not be described again here. The computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, etc.

[0175] Figure 3 is a schematic diagram of the hardware structure of an electronic device that implements various embodiments of the present invention.

[0176] The electronic device 300 includes, but is not limited to, components such as: a radio frequency unit 301, a network module 302, an audio output unit 303, an input unit 304, a sensor 305, a display unit 306, a user input unit 307, an interface unit 308, a memory 309, a processor 310, and a power supply 311. Those skilled in the art will understand that the electronic device structure described in the embodiments of this application does not constitute a limitation on the electronic device. An electronic device may include more or fewer components than illustrated, or combine certain components, or have different component arrangements. In the embodiments of this application, the electronic device includes, but is not limited to, mobile phones, tablet computers, laptops, PDAs, in-vehicle terminals, wearable devices, and pedometers.

[0177] It should be understood that, in this embodiment, the radio frequency unit 301 can be used for receiving and transmitting signals during information transmission or calls. Specifically, it receives downlink data from the base station and processes it with the processor 310; additionally, it transmits uplink data to the base station. Typically, the radio frequency unit 301 includes, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a low-noise amplifier, and a duplexer. Furthermore, the radio frequency unit 301 can also communicate with networks and other devices via a wireless communication system.

[0178] The electronic device provides users with wireless broadband internet access through the network module 302, such as helping users send and receive emails, browse web pages, and access streaming media.

[0179] The audio output unit 303 can convert audio data received by the radio frequency unit 301 or the network module 302 or stored in the memory 309 into audio signals and output them as sound. Furthermore, the audio output unit 303 can also provide audio output related to specific functions performed by the electronic device 300 (e.g., call signal reception sound, message reception sound, etc.). The audio output unit 303 includes a speaker, a buzzer, and a receiver, etc.

[0180] Input unit 304 is used to receive audio or video signals. Input unit 304 may include a graphics processing unit (GPU) 3041 and a microphone 3042. The GPU 3041 processes image data of still images or videos acquired by an image capture device (such as a camera) in video capture mode or image capture mode. The processed image frames can be displayed on display unit 306. The image frames processed by GPU 3041 can be stored in memory 309 (or other storage media) or transmitted via radio frequency unit 301 or network module 302. Microphone 3042 can receive sound and process such sound into audio data. The processed audio data can be converted into a format that can be transmitted to a mobile communication base station via radio frequency unit 301 in telephone call mode.

[0181] The electronic device 300 also includes at least one sensor 305, such as a light sensor, a motion sensor, and other sensors. Specifically, the light sensor includes an ambient light sensor and a proximity sensor. The ambient light sensor can adjust the brightness of the display panel 3061 according to the ambient light level, and the proximity sensor can turn off the display panel 3061 and / or backlight when the electronic device 300 is moved to the ear. As a type of motion sensor, an accelerometer sensor can detect the magnitude of acceleration in various directions (generally three axes). When stationary, it can detect the magnitude and direction of gravity and can be used to identify the posture of the electronic device (such as landscape / portrait switching, related games, magnetometer posture calibration), vibration recognition related functions (such as pedometer, tapping), etc. The sensor 305 may also include a fingerprint sensor, pressure sensor, iris sensor, molecular sensor, gyroscope, barometer, hygrometer, thermometer, infrared sensor, etc., which will not be described in detail here.

[0182] The display unit 306 is used to display information input by the user or information provided to the user. The display unit 306 may include a display panel 3061, which may be configured in the form of a liquid crystal display (LCD), an organic light-emitting diode (OLED), or the like.

[0183] User input unit 307 can be used to receive input numerical or character information, and generate key signal inputs related to user settings and function control of electronic devices. Specifically, user input unit 307 includes a touch panel 3071 and other input devices 3072. Touch panel 3071, also known as a touch screen, can collect touch operations performed by the user on or near it (such as operations performed by the user using a finger, stylus, or any suitable object or accessory on or near touch panel 3071). Touch panel 3071 may include two parts: a touch detection device and a touch controller. The touch detection device detects the user's touch position and the signal generated by the touch operation, and transmits the signal to the touch controller; the touch controller receives touch information from the touch detection device, converts it into touch point coordinates, and sends it to the processor 310, which receives and executes commands from the processor 310. In addition, touch panel 3071 can be implemented using various types such as resistive, capacitive, infrared, and surface acoustic wave. In addition to touch panel 3071, user input unit 307 may also include other input devices 3072. Specifically, other input devices 3072 may include, but are not limited to, physical keyboards, function keys (such as volume control buttons, power buttons, etc.), trackballs, mice, joysticks, etc., which will not be described in detail here.

[0184] Furthermore, the touch panel 3071 can cover the display panel 3061. When the touch panel 3071 detects a touch operation on or near it, it transmits the information to the processor 310 to determine the type of touch event. Subsequently, the processor 310 provides corresponding visual output on the display panel 3061 according to the type of touch event. It is understood that in one embodiment, the touch panel 3071 and the display panel 3061 are implemented as two independent components to realize the input and output functions of the electronic device. However, in some embodiments, the touch panel 3071 and the display panel 3061 can be integrated to realize the input and output functions of the electronic device. The specific implementation is not limited here.

[0185] Interface unit 308 serves as an interface for connecting external devices to electronic device 300. For example, external devices may include a wired or wireless headphone port, an external power supply (or battery charger) port, a wired or wireless data port, a memory card port, a port for connecting a device with an identification module, an audio input / output (I / O) port, a video I / O port, a headphone port, and so on. Interface unit 308 can be used to receive input from external devices (e.g., data, power, etc.) and transmit the received input to one or more components within electronic device 300, or it can be used to transmit data between electronic device 300 and external devices.

[0186] The memory 309 can be used to store software programs and various data. The memory 309 may primarily include a program storage area and a data storage area. The program storage area may store the operating system, applications required for at least one function (such as sound playback, image playback, etc.), etc.; the data storage area may store data created based on the use of the mobile phone (such as audio data, phonebook, etc.). Furthermore, the memory 309 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device.

[0187] The processor 310 is the control center of the electronic device. It connects various parts of the electronic device via various interfaces and lines. By running or executing software programs and / or modules stored in the memory 309, and by calling data stored in the memory 309, it performs various functions and processes data, thereby providing overall monitoring of the electronic device. The processor 310 may include one or more processing units; preferably, the processor 310 may integrate an application processor and a modem processor. The application processor mainly handles the operating system, user interface, and applications, while the modem processor mainly handles wireless communication. It is understood that the modem processor may not be integrated into the processor 310.

[0188] The electronic device 300 may also include a power supply 311 (such as a battery) for supplying power to various components. Preferably, the power supply 311 can be logically connected to the processor 310 through a power management system, thereby enabling functions such as managing charging, discharging, and power consumption through the power management system.

[0189] In addition, the electronic device 300 includes some functional modules not shown, which will not be described in detail here.

[0190] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0191] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0192] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

[0193] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed in this application can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0194] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0195] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0196] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0197] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0198] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0199] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A processing method of scheduling a task, characterized by, include: Obtain the directed acyclic graph task, the number of node layers corresponding to the directed acyclic graph task, and the number of tasks corresponding to subtasks in the directed acyclic graph task. The number of node layers represents the hierarchical structure of the directed acyclic graph task. The parallelism factor corresponding to the directed acyclic graph task is obtained by calculating based on the number of node layers and the number of tasks. The parallelism factor is used to measure the degree of parallelism of the directed acyclic graph task. Determine the adjustment threshold corresponding to the parallel factor; Obtain the execution time information corresponding to each of the subtasks, and calculate the execution time difference corresponding to each subtask based on the execution time information; The time of the directed acyclic graph task is adjusted based on the execution time difference and the adjustment threshold to determine the target deadline for the directed acyclic graph task. The processors are filtered according to the target deadline to obtain the target processor for executing the directed acyclic graph task, and the directed acyclic graph task is executed by the target processor.

2. The method according to claim 1, characterized in that, The step of calculating the parallelism factor corresponding to the directed acyclic graph task based on the number of node layers and the number of tasks includes: Obtain the number of processors corresponding to the processors used to execute the directed acyclic graph task; The parallelism factor corresponding to the directed acyclic graph task is obtained by calculating the number of node layers, the number of tasks, and the number of processors.

3. The method of claim 2, wherein, The parallelism factor corresponding to the directed acyclic graph task is obtained by calculating the number of node layers, the number of tasks, and the number of processors, using the following formula: Wherein, m is the number of processors, n is the number of subtasks in the directed acyclic graph task, and ML is the number of node layers corresponding to the directed acyclic graph task.

4. The method of claim 1, wherein, Determining the adjustment threshold corresponding to the parallel factor includes: Obtain the transmission duration corresponding to each of the subtasks; Calculate the total transmission time corresponding to the directed acyclic graph task based on the transmission time of the sub-task; The total transmission time and the parallel factor are used to calculate the corresponding adjustment threshold, which is used to adjust the deadline of the directed acyclic graph task.

5. The method according to claim 1, characterized in that, The execution time information includes at least the sub-deadline time, execution duration, and transmission duration between the sub-task and the directed acyclic graph task. The execution time difference for the sub-task is calculated based on the execution time information using the following formula: temp = TDL j -w j -c i,j v j ∈succ(v i ) Wherein, temp is the execution time difference, and TDL is... j For the sub-deadline time, w j For the execution duration, c i,j For the transmission duration, the succ(v) i ) represents the subtasks in the directed acyclic graph task.

6. The method according to claim 1 or 5, characterized in that, The step of adjusting the time of the directed acyclic graph task based on the execution time difference and the adjustment threshold, and determining the target deadline for the directed acyclic graph task, includes: The subtask with the smallest execution time difference is selected as the target subtask. If the target transmission duration between the target subtask and the directed acyclic graph task is greater than the adjustment threshold, the first deadline corresponding to the directed acyclic graph task is obtained by calculating the target execution time difference and the target transmission duration corresponding to the target subtask. If the target transmission time between the target subtask and the directed acyclic graph task is less than the adjustment threshold, then the target execution time difference corresponding to the target subtask is taken as the second deadline corresponding to the directed acyclic graph task.

7. The method according to claim 1, characterized in that, The step of filtering processors according to the target deadline to obtain a target processor for executing the directed acyclic graph task, and executing the directed acyclic graph task through the target processor, includes: Obtain the gaps corresponding to each processor, as well as the start and end times of the gaps; Obtain the ready time and execution duration of the directed acyclic graph task on each of the processors; Target processors are selected from the processors to perform the directed acyclic graph task, and the target processors satisfy the following conditions: The length of the slot is not less than v i The execution duration w i ; ② The start time (sst) and end time (sft) of a slot can cover v. i The execution is completed, and the actual execution time does not exceed v. i Target Deadline TDL i That is, it satisfies formula (1) and formula (2). avail(v i ,r p )>sst∩avail(v i ,r p And w i ≤sft∩avail(v i ,r p And w i ≤TDL i (1) avail(v i ,r p )≤sst∩sstandw i ≤sst and w i ∩sft≤TDL i (2) Wherein, the slot is the gap, and the v i For the directed acyclic graph task, the avail(v i ,r p The directed acyclic graph task is performed on processor r. p Readiness time.

8. A processing apparatus for scheduling tasks, characterized in that, include: The data acquisition module is used to acquire the directed acyclic graph task, the number of node layers corresponding to the directed acyclic graph task, and the number of tasks corresponding to the subtasks in the directed acyclic graph task. The number of node layers represents the hierarchical structure of the directed acyclic graph task. The factor calculation module is used to calculate the parallel factor corresponding to the directed acyclic graph task based on the number of node layers and the number of tasks. The parallel factor is used to measure the degree of parallelism of the directed acyclic graph task. A threshold determination module is used to determine the adjustment threshold corresponding to the parallel factor; The time difference calculation module is used to obtain the execution time information corresponding to each of the sub-tasks, and to calculate the execution time difference corresponding to the sub-tasks based on the execution time information. The time adjustment module is used to adjust the time of the directed acyclic graph task according to the execution time difference and the adjustment threshold, and to determine the target deadline corresponding to the directed acyclic graph task. The execution module is used to filter processors according to the target deadline, obtain a target processor for executing the directed acyclic graph task, and execute the directed acyclic graph task through the target processor.

9. An electronic device, characterized in that, It includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; The memory is used to store computer programs; When the processor executes a program stored in the memory, it implements the method as described in any one of claims 1-7.

10. A computer-readable storage medium having instructions stored thereon that, when executed by one or more processors, cause the processors to perform the method as described in any one of claims 1-7.

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