A power supply system and control method for an MPSoC+FPGA heterogeneous computing platform

Abstract

The application provides a power supply system and control method for an MPSoC+FPGA heterogeneous computing platform, comprising an MPSoC processor, an FPGA processor, a first-stage power supply module, a second-stage power supply module, a third-stage power supply module, a fourth-stage power supply module, a power output control circuit and an anti-surge circuit; the power supply requirements of the MPSoC and the FPGA are integrated to form a system power supply system with eight power supply voltages and four power supply sequences. According to the system, an integrated power supply architecture of the MPSoC+FPGA is designed; the power supply requirements of different processors are comprehensively considered to realize a simple, efficient, easy-to-debug and flexible heterogeneous platform power supply scheme, and the overall power supply requirements of the MPSoC+FPGA heterogeneous system are met.

Description

Technical Field

[0001] This invention relates to the field of power system design, and more specifically, to a power supply system and control method for MPSoC+FPGA heterogeneous computing platforms. Background Technology

[0002] Heterogeneous computing platforms combining Multi-Processor System-on-Chip (MPSoC) and Field-Programmable Gate Array (FPGA) offer advantages such as high energy efficiency, high reliability, and strong adaptability, making them the mainstream architecture balancing computing specialization and versatility. While achieving diverse computing characteristics, the numerous heterogeneous cores within the chip also impose more complex design requirements on the system's power supply type and logic sequence. Taking Xilinx's UltraScale series of high-performance MPSoC processors as an example, a single chip requires the simultaneous supply of six different voltages. These six voltages must be divided into approximately 12 groups in different orders to power different functional units such as the chip core, clock, memory, and I / O in a fixed time sequence. Introducing an FPGA processor to form a heterogeneous computing system further complicates the power supply system.

[0003] Currently, power supply circuits in MPSoC+FPGA heterogeneous computing systems typically exhibit large circuit areas, complex inter-module startup relationships, and difficulty in debugging. Furthermore, the numerous power supply chips introduce additional dynamic and static power losses, reducing the overall energy efficiency of the heterogeneous computing system to some extent. Moreover, the additional power supply sequence control circuitry poses potential risks to the safety and reliability of the onboard system. As a critical component in the design of MPSoC+FPGA heterogeneous computing platforms, the power supply system directly affects the platform's functionality and overall performance. However, existing power supply systems rarely utilize integrated design solutions specifically for MPSoC+FPGA heterogeneous systems, often employing separate power supply solutions for individual processors. This significantly increases the circuit area and complexity of multi-processor heterogeneous systems, reduces power conversion efficiency and system integration, and hinders the miniaturization and energy-efficient design of high-performance heterogeneous devices. Therefore, to meet the miniaturization design requirements of power supply systems at the edge of heterogeneous computing platforms, this paper designs a power supply system suitable for MPSoC+FPGA heterogeneous computing platforms, using a simple, efficient, and easy-to-debug and assemble circuit design to meet the complex and diverse power supply needs of heterogeneous computing platforms. Summary of the Invention

[0004] To address the aforementioned problems, this invention proposes a power supply system and control method for MPSoC+FPGA heterogeneous computing platforms. It comprehensively considers the power supply requirements of different processors, realizing a simple, efficient, easy-to-debug, and flexibly customizable heterogeneous platform power supply solution to meet the overall power supply requirements of MPSoC+FPGA heterogeneous systems.

[0005] This invention is achieved through the following scheme:

[0006] A power supply system for MPSoC+FPGA heterogeneous computing platforms:

[0007] The power supply system specifically includes an MPSoC processor, an FPGA processor, a first-level power supply module, a second-level power supply module, a third-level power supply module, a fourth-level power supply module, a power output control circuit, and a surge protection circuit.

[0008] The MPSoC processor and FPGA processor are connected to the first-level power supply module, the second-level power supply module, the third-level power supply module, and the fourth-level power supply module through a power output control circuit.

[0009] The surge protection circuit is connected to the first-level power supply module, the second-level power supply module, the third-level power supply module, and the fourth-level power supply module.

[0010] Furthermore,

[0011] The FPGA processor includes a digital-to-analog conversion module, a system status management unit, a soft-core processor, and a standard communication interface module;

[0012] The MPSoC processor includes a standard communication interface module, an ARM main control processor, a data conversion module, a data interface bus, and general-purpose I / O interface modules 1, 2, and 3;

[0013] The digital-to-analog converter module in the FPGA processor transmits the voltage value to the soft core processor of the FPGA processor through the system status management unit;

[0014] The digital-to-analog converter module in the MPSoC processor collects voltage signals and transmits them to the ARM main processor through the data interface bus;

[0015] The three general-purpose I / O interfaces 1, 2, and 3 correspond to the power supply control circuits of the second-level power supply module, the third-level power supply module, and the fourth-level power supply module, respectively.

[0016] Furthermore,

[0017] The first-stage power supply module provides core power for the MPSoC processor and FPGA processor;

[0018] After the power supply system is started, the first-stage power supply module outputs two voltages simultaneously, 0.85V and 0.95V, through a DC / DC voltage converter;

[0019] The peak current corresponding to a voltage of 0.85V is 25A, and the peak current corresponding to a voltage of 0.95V is 40A.

[0020] 0.85V corresponds to the VCCINT power supply unit, VCCINT_IO power supply unit, VCCBRAM power supply unit, VCCPSINTFP power supply unit, VCC_PSINTFP_DDR power supply unit, and VCCPS_INTLP power supply unit of the MPSoC processor;

[0021] The 0.95V voltage corresponds to the VCCINT power supply unit, VCCINT_IO power supply unit, and VCCBRAM power supply unit of the FPGA processor.

[0022] Furthermore,

[0023] The second-stage power supply module outputs three voltages: 0.85V, 0.9V, and 1.0V.

[0024] The peak current corresponding to a voltage of 0.85V is 4A, the peak current corresponding to a voltage of 0.9V is 4A, and the peak current corresponding to a voltage of 1.0V is 8A.

[0025] 0.85V corresponds to the VCC_PSMGTRAVCC power supply unit of the MPSoC processor;

[0026] 0.9V corresponds to the VCCINT_VCU power supply unit and VMGTAVCC power supply unit of the MPSoC processor;

[0027] The 1.0V voltage corresponds to the VMGTAVCC power supply unit of the FPGA processor.

[0028] Furthermore,

[0029] The third-stage power supply module outputs two voltages, 1.8V and 1.2V, with a peak current of 20A for both voltages.

[0030] The 1.8V voltage corresponds to the VCC_PSAUX power supply unit, VCC_PSADC power supply unit, VCC_PSDDR_PLL power supply unit, VPS_MGTRAVTT power supply unit, VCCAUX power supply unit, VCCAUX_IO power supply unit, VCC_ADC power supply unit, and VMGTVCCAUX power supply unit of the MPSoC processor.

[0031] The 1.2V voltage corresponds to the VMGTAVTT power supply unit, VMGTAVTTRCAL power supply unit, and VCCO power supply unit of the FPGA processor.

[0032] Furthermore,

[0033] The fourth-stage power supply module outputs four voltages: 1.2V, 1.25V, 1.8V, and 3.3V.

[0034] The peak current corresponding to 1.2V voltage is 8A, the peak current corresponding to 1.25V voltage is 25mA, and the peak current corresponding to 1.8V and 3.3V voltage is 4A.

[0035] The 1.2V voltage corresponds to the VCCO_PSDDR power supply unit, DDR_VDD power supply unit, VMGTAVTT power supply unit, and VCC_PSPLL power supply unit;

[0036] 1.25V voltage corresponds to the VREFP / N power supply unit;

[0037] The 1.8V and 3.3V voltages correspond to the VCCO_HPIO power supply unit and the VCCPSIO power supply unit, respectively.

[0038] Furthermore,

[0039] The power output control circuit has the following two operating modes:

[0040] Default mode: After the voltage output of the previous stage power supply module is stabilized, the power output control circuit automatically enables the power output function of the next stage power supply module.

[0041] Operating mode: The power output control circuit is controlled by the general-purpose processor embedded in the MPSoC processor, which shuts down and turns on the specified power supply modules according to the running status and performance requirements.

[0042] A control method applied to the power supply system:

[0043] The control method specifically includes the following steps:

[0044] Step 1: After the soft-core processor in the FPGA starts running, it performs initialization;

[0045] Step 2: The system status management unit compares the current voltage value rd1_v of the first-level power supply module with the standard voltage value nom1_v of the first-level power supply module, and feeds the result back to the control information fusion module in the soft core processor.

[0046] Step 3: Read the voltage values ​​and operating status of the second-level power supply module, the third-level power supply module, and the fourth-level power supply module respectively, compare the current voltage value of the power supply module with the standard voltage value of the power supply module, and feed the result back to the information fusion module;

[0047] Step 4: The information fusion module fuses the voltage and logic block operating status of the four-level power supply module to generate dynamic control information data packets, which are then sent to the MPSoC processor through the standard communication interface module.

[0048] Step 5: Initialize the ARM main controller processor in the MPSoC processor;

[0049] Step Six: Read the dynamic control information data packet transmitted in Step Four and unpack it;

[0050] Step 7: Read the power supply voltage value and corresponding operating status of the MPSoC section through the digital-to-analog converter module;

[0051] Step 8: Merge the information from the FPGA and MPSoC to generate control instructions for the general I / O module, and control the power enable / disable states of the second-level power supply module, the third-level power supply module, and the fourth-level power supply module.

[0052] Furthermore,

[0053] The first-level power supply module supplies the processor core voltage and is never shut down during operation.

[0054] Beneficial effects of the invention

[0055] (1) This invention relates to an integrated power supply system for Xilinx UltraScale series MPSoC and FPGA heterogeneous computing platforms;

[0056] (2) The circuit area of ​​the present invention is reduced by more than 35% compared with the conventional solution;

[0057] (3) The number of components used in this invention is reduced by more than 40% compared with the traditional solution;

[0058] (4) The heat loss of the power supply of the present invention is reduced by 16% compared with the traditional solution;

[0059] (5) This invention greatly simplifies the power-on timing control process, integrates the power supply channels and sequences, and the actual system only requires 4 levels of power supply;

[0060] (6) This invention has the ability to monitor the voltage of the power supply system, with a voltage sampling accuracy of 10 bits;

[0061] (7) The present invention has power supply system management capability, and can enable or disable independent power supply paths according to the actual system operating status, thereby dynamically reducing the actual operating power consumption. Attached Figure Description

[0062] Figure 1 This is a block diagram illustrating the integrated power supply architecture of the present invention.

[0063] Figure 2 This is a block diagram illustrating the dynamic monitoring and control principle of the power supply system output of the present invention.

[0064] Figure 3 This is a diagram of the power supply monitoring and control software for the soft-core processor of the present invention;

[0065] Figure 4 Flowchart for ARM main control processor power system detection and management software. Detailed Implementation

[0066] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0067] Combination Figures 1 to 4 ,

[0068] A power supply system for MPSoC+FPGA heterogeneous computing platforms:

[0069] The power supply system specifically includes an MPSoC processor, an FPGA processor, a first-level power supply module, a second-level power supply module, a third-level power supply module, a fourth-level power supply module, a power output control circuit, and a surge protection circuit.

[0070] The MPSoC processor and FPGA processor are connected to the first-level power supply module, the second-level power supply module, the third-level power supply module, and the fourth-level power supply module through a power output control circuit.

[0071] The surge protection circuit is connected to the first-level power supply module, the second-level power supply module, the third-level power supply module, and the fourth-level power supply module. The surge protection circuit is inserted into the output and input terminals of each power supply system to prevent the circuit system from being impacted and damaged by the instantaneous peak surge caused by the power output.

[0072] The FPGA processor includes a digital-to-analog conversion module, a system status management unit, a soft-core processor, and a standard communication interface module;

[0073] The MPSoC processor includes a standard communication interface module, an ARM main control processor, a data conversion module, a data interface bus, and general-purpose I / O interface modules 1, 2, and 3;

[0074] The digital-to-analog converter module in the FPGA processor transmits the voltage value to the soft core processor of the FPGA processor through the system status management unit;

[0075] The digital-to-analog converter module in the MPSoC processor collects voltage signals and transmits them to the ARM main processor through the data interface bus;

[0076] The general-purpose I / O module is an intermediate component connecting the ARM main control processor and the power output control circuit. It is used to generate electrical signals that act on the enable or disable terminals of the power supply system, thereby enabling the main control processor to control the power supply system. The three general-purpose I / O interfaces 1, 2, and 3 correspond to the power supply control circuits of the second-level power supply module, the third-level power supply module, and the fourth-level power supply module, respectively, and can realize independent output control.

[0077] In heterogeneous computing platforms, the standard communication interface module is a crucial medium for establishing information exchange between MPSoC and FPGA. It mainly consists of a standardized protocol communication interface and a data transceiver controller, responsible for enabling information exchange between the embedded ARM main controller processor in the MPSoC and the soft-core processor in the FPGA. Its primary function is to transmit power monitoring and control information data packets.

[0078] The ARM main control processor embedded in the MPSoC is an application-specific integrated circuit with features such as low power consumption, high performance and flexible programming. It can also operate independently of the PL section as the main control unit of the heterogeneous platform power supply system.

[0079] The first-stage power supply module provides core power for the MPSoC processor and FPGA processor;

[0080] After the power supply system is started, the first-stage power supply module outputs two voltages simultaneously, 0.85V and 0.95V, through a DC / DC voltage converter;

[0081] The peak current corresponding to a voltage of 0.85V is 25A, and the peak current corresponding to a voltage of 0.95V is 40A.

[0082] 0.85V corresponds to the VCCINT power supply unit, VCCINT_IO power supply unit, VCCBRAM power supply unit, VCCPSINTFP power supply unit, VCC_PSINTFP_DDR power supply unit, and VCCPS_INTLP power supply unit of the MPSoC processor;

[0083] The 0.95V voltage corresponds to the VCCINT power supply unit, VCCINT_IO power supply unit, and VCCBRAM power supply unit of the FPGA processor.

[0084] The second-stage power supply module outputs three voltages: 0.85V, 0.9V, and 1.0V.

[0085] The peak current corresponding to a voltage of 0.85V is 4A, the peak current corresponding to a voltage of 0.9V is 4A, and the peak current corresponding to a voltage of 1.0V is 8A.

[0086] 0.85V corresponds to the VCC_PSMGTRAVCC power supply unit of the MPSoC processor;

[0087] 0.9V corresponds to the VCCINT_VCU power supply unit and VMGTAVCC power supply unit of the MPSoC processor;

[0088] The 1.0V voltage corresponds to the VMGTAVCC power supply unit of the FPGA processor.

[0089] The third-stage power supply module outputs two voltages, 1.8V and 1.2V, with a peak current of 20A for both voltages.

[0090] The 1.8V voltage corresponds to the VCC_PSAUX power supply unit, VCC_PSADC power supply unit, VCC_PSDDR_PLL power supply unit, VPS_MGTRAVTT power supply unit, VCCAUX power supply unit, VCCAUX_IO power supply unit, VCC_ADC power supply unit, and VMGTVCCAUX power supply unit of the MPSoC processor.

[0091] The 1.2V voltage corresponds to the VMGTAVTT power supply unit, VMGTAVTTRCAL power supply unit, and VCCO power supply unit of the FPGA processor.

[0092] The fourth-stage power supply module outputs four voltages: 1.2V, 1.25V, 1.8V, and 3.3V.

[0093] The peak current corresponding to 1.2V voltage is 8A, the peak current corresponding to 1.25V voltage is 25mA, and the peak current corresponding to 1.8V and 3.3V voltage is 4A.

[0094] The 1.2V voltage corresponds to the VCCO_PSDDR power supply unit, DDR_VDD power supply unit, VMGTAVTT power supply unit, and VCC_PSPLL power supply unit;

[0095] 1.25V voltage corresponds to the VREFP / N power supply unit;

[0096] The 1.8V and 3.3V voltages correspond to the VCCO_HPIO power supply unit and the VCCPSIO power supply unit, respectively.

[0097] The power output control circuit has the following two operating modes:

[0098] Default mode: After the voltage output of the previous stage power supply module is stabilized, the power output control circuit automatically enables the power output function of the next stage power supply module.

[0099] Operating mode: The power output control circuit is controlled by the general-purpose processor embedded in the MPSoC processor, which shuts down and turns on the specified power supply modules according to the running status and performance requirements.

[0100] To address the power supply requirements of high integration and easy debugging in heterogeneous computing systems, a unified power supply architecture with 8 power supply voltages and 4 power supply sequences is developed by decomposing and then re-integrating the power supply voltages and startup timing of MPSoC and FPGA processors. This architecture combines the 6 voltages and 12 power supply levels of MPSoC, as well as the 6 voltages and 8 power supply levels of FPGA, into a single power supply architecture with 8 power supply voltages and 4 power supply sequences.

[0101] Meanwhile, in order to meet the startup timing and control requirements of power supply modules at all levels, a power output control circuit was designed to ensure that the automatic sequential stable startup of the system in the early stage of operation and the power output power consumption during operation are controllable.

[0102] In addition, to ensure the safety of the power supply system and the powered equipment, surge protection circuits are inserted at the power input and output terminals to reduce the impact of the large current at startup on the circuit system.

[0103] MPSoC+FPGA heterogeneous computing platforms, designed for high-energy-efficiency edge computing scenarios, play a crucial role in reducing system energy consumption and improving overall operational energy efficiency through power monitoring and control.

[0104] The method for dynamic monitoring and control of power supply system output power is based on the built-in voltage sampling module and power output control circuit of MPSoC and FPGA. The block diagram of the dynamic monitoring and control principle of power supply system output is as follows: Figure 2 As shown.

[0105] Xilinx UltraScale series processors have an embedded digital-to-analog converter (DAC) module that can sample and monitor the internal voltage of the chip. Based on this module, input voltage values ​​are acquired within both the MPSoC and FPGA. For the MPSoC, the DAC module, located in the Programmable Logic (PL) section, acquires the voltage signal and transmits it to the ARM main processor in the Processing System (PS) section via the data interface bus. For the FPGA, the DAC module acquires the voltage value and transmits it to the soft-core processor inside the FPGA through the system status management unit.

[0106] Based on the soft-core processor IP core provided by Xilinx, this system acquires and interprets the voltage values ​​of the digital-to-analog converter module. While monitoring the FPGA system's power supply voltage, it determines the enable and disable states of corresponding power supply paths based on the current operating status of the FPGA's internal logic functions, generating dynamic control information data packets, which are then sent to the heterogeneous platform's main control processor via a standard communication interface module. The software flow for soft-core processor power supply monitoring and control is as follows: Figure 3 As shown.

[0107] A control method applied to the power supply system:

[0108] Step 1: After the soft-core processor in the FPGA starts running, it initializes the internal logic devices;

[0109] Step 2: The system status management unit compares the current voltage value rd1_v of the first-level power supply module with the standard voltage value nom1_v of the first-level power supply module, and feeds the result back to the control information fusion module in the soft core processor.

[0110] Step 3: Read the voltage values ​​and operating status of the second-level power supply module, the third-level power supply module, and the fourth-level power supply module respectively, compare the current voltage value of the power supply module with the standard voltage value of the power supply module, perform logical operations on the operating status, and feed the results back to the information fusion module;

[0111] Step 4: The information fusion module fuses the voltage and logic block operating status of the four-level power supply module to generate dynamic control information data packets, which are then sent to the MPSoC processor through the standard communication interface module.

[0112] Step 5: Initialize the ARM main controller processor in the MPSoC processor;

[0113] Step Six: Read the dynamic control information data packet transmitted in Step Four and unpack it;

[0114] Step 7: Read the power supply voltage value and corresponding operating status of the MPSoC section through the digital-to-analog converter module;

[0115] Step 8: Merge the information from the FPGA and MPSoC to generate control instructions for the general I / O module, and control the power enable / disable states of the second-level power supply module, the third-level power supply module, and the fourth-level power supply module.

[0116] The first-level power supply module supplies the processor core voltage and is never shut down during operation.

[0117] This embodiment uses a heterogeneous computing platform consisting of Xilinx's Zynq Ultrascale+ architecture MPSoC and Kintex Ultrascale architecture FPGA for power supply system design and specific implementation.

[0118] (1) Based on the power supply requirements of MPSoC and FPGA, their voltage types, currents, and power-on sequences are evaluated and decomposed. The power supply levels are merged according to voltage values ​​and time sequence, and the corresponding power supply currents are accumulated to form a sequence as follows: Figure 1 As shown, this is the overall design scheme of an integrated power supply system that includes 8 voltages and 4 power supply levels;

[0119] (2) Design the first-stage power supply module. The first-stage power supply includes two power outputs: the first output has a voltage of 0.85V and a peak current of 25A, using a TPS548B22 DC / DC converter chip; the second output has a voltage of 0.95V and a peak current of 40A, using a TPS548D22 DC / DC converter chip.

[0120] (3) Design the second-stage power supply module. The first-stage power supply includes three power outputs: the first output has a voltage of 0.85V and a peak current of 4A, using a TPS22970 DC / DC converter chip; the second output has a voltage of 0.9V and a peak current of 4A, using a TPS54424RNVT DC / DC converter chip; and the third output has a voltage of 1.0V and a peak current of 8A, using a TPS568215RNNT DC / DC converter chip.

[0121] (4) Design the third-level power supply module. The first-level power supply includes two power outputs: the first output has a voltage of 1.8V and a peak current of 20A, using a TPS54424RNVT DC / DC converter chip; the second output has a voltage of 1.2V and a peak current of 20A, using a TPS53353DQPT DC / DC converter chip.

[0122] (5) Design the fourth-stage power supply module. The first-stage power supply includes four power outputs: the first output has a voltage of 1.2V and a peak current of 8A, using a TPS568215RNNT DC / DC converter chip; the second output has a voltage of 1.25V and a peak current of 25mA, using a REF3012 DC / DC converter chip; the third output has a voltage of 1.8V and a peak current of 4A, using a TPS54424RNVT DC / DC converter chip; and the fourth output has a voltage of 3.3V and a peak current of 4A, using a TPS54424RNVT DC / DC converter chip.

[0123] (6) Implement sequential startup and control of the power supply system. Design a power output control circuit. Based on the power-on sequence requirements, according to... Figure 1 In the startup scheme, the enable pins of the power conversion chips are connected to the power output control circuit sequentially, from the first stage to the fourth stage.

[0124] (7) Voltage value acquisition is implemented based on the Xilinx digital-to-analog converter module. The corresponding interface logic of the digital-to-analog converter module is deployed inside the processor, such as... Figure 2 Based on the shown connections, construct the corresponding logic firmware. Then, write voltage acquisition functions in both the soft-core processor and the ARM main control processor to read voltage values.

[0125] (8) Using Microblaze or other soft-core processors, implement power supply system monitoring and decision-making information, as well as data transmission and reception functions of the standard communication interface module in the FPGA. Write the corresponding C language program and generate the corresponding executable file using a compiler.

[0126] (9) Write corresponding C language programs for the ARM main controller processor in MPSoC to implement standard communication interface transmission and reception, power supply system monitoring and management, and general I / O module output functions. Generate the corresponding executable file using compilation tools;

[0127] (10) Based on the above software and logic design, the executable file is packaged and burned into the processor's configuration memory. After power-on, the power-on system starts up sequentially according to the predetermined timing. Then, the processor reads the configuration file from the configuration memory and starts running the power supply system monitoring and management software. Finally, the dynamic monitoring and control of the integrated power supply system of the heterogeneous computing platform is realized.

[0128] The above provides a detailed description of the power supply system and control method for the MPSoC+FPGA heterogeneous computing platform proposed in this invention, and elucidates the principles and implementation methods of this invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this invention. Therefore, the content of this specification should not be construed as a limitation of this invention.

Claims

1. A power supply system for an MPSoC+FPGA heterogeneous computing platform, characterized in that: The power supply system specifically includes an MPSoC processor, an FPGA processor, a first-level power supply module, a second-level power supply module, a third-level power supply module, a fourth-level power supply module, a power output control circuit, and a surge protection circuit. The MPSoC processor and FPGA processor are connected to the first-level power supply module, the second-level power supply module, the third-level power supply module, and the fourth-level power supply module through a power output control circuit. The surge protection circuit is connected to the first-level power supply module, the second-level power supply module, the third-level power supply module, and the fourth-level power supply module; The FPGA processor includes a digital-to-analog converter module, a system status management unit, a soft-core processor, and a standard communication interface module; The MPSoC processor includes a standard communication interface module, an ARM main control processor, a data conversion module, a data interface bus, and general-purpose I / O interface modules 1, 2, and 3; The analog-to-digital converter in the FPGA processor transmits the voltage value to the soft core processor of the FPGA processor through the system status management unit; The digital-to-analog converter module in the MPSoC processor collects voltage signals and transmits them to the ARM main processor through the data interface bus; The three general-purpose I / O interfaces 1, 2 and 3 correspond to the power supply control circuits of the second-level power supply module, the third-level power supply module and the fourth-level power supply module, respectively.

2. The power supply system according to claim 1, characterized in that: The first-stage power supply module provides core power for the MPSoC processor and FPGA processor; After the power supply system is started, the first-stage power supply module outputs two voltages simultaneously, 0.85V and 0.95V, through a DC / DC voltage converter; The peak current corresponding to a voltage of 0.85V is 25A, and the peak current corresponding to a voltage of 0.95V is 40A. 0.85V corresponds to the VCCINT power supply unit, VCCINT_IO power supply unit, VCCBRAM power supply unit, VCCPSINTFP power supply unit, VCC_PSINTFP_DDR power supply unit, and VCCPS_INTLP power supply unit of the MPSoC processor; The 0.95V voltage corresponds to the VCCINT power supply unit, VCCINT_IO power supply unit, and VCCBRAM power supply unit of the FPGA processor.

3. The power supply system according to claim 1, characterized in that: The second-stage power supply module outputs three voltages: 0.85V, 0.9V, and 1.0V. The peak current corresponding to a voltage of 0.85V is 4A, the peak current corresponding to a voltage of 0.9V is 4A, and the peak current corresponding to a voltage of 1.0V is 8A. 0.85V corresponds to the VCC_PSMGTRAVCC power supply unit of the MPSoC processor; 0.9V corresponds to the VCCINT_VCU power supply unit and VMGTAVCC power supply unit of the MPSoC processor; The 1.0V voltage corresponds to the VMGTAVCC power supply unit of the FPGA processor.

4. The power supply system according to claim 1, characterized in that: The third-stage power supply module outputs two voltages, 1.8V and 1.2V, with a peak current of 20A for both voltages. The 1.8V voltage corresponds to the VCC_PSAUX power supply unit, VCC_PSADC power supply unit, VCC_PSDDR_PLL power supply unit, VPS_MGTRAVTT power supply unit, VCCAUX power supply unit, VCCAUX_IO power supply unit, VCC_ADC power supply unit, and VMGTVCCAUX power supply unit of the MPSoC processor. The 1.2V voltage corresponds to the VMGTAVTT power supply unit, VMGTAVTTRCAL power supply unit, and VCCO power supply unit of the FPGA processor.

5. The power supply system according to claim 1, characterized in that: The fourth-stage power supply module outputs four voltages: 1.2V, 1.25V, 1.8V, and 3.3V. The peak current corresponding to 1.2V voltage is 8A, the peak current corresponding to 1.25V voltage is 25mA, and the peak current corresponding to 1.8V and 3.3V voltage is 4A. The 1.2V voltage corresponds to the VCCO_PSDDR power supply unit, DDR_VDD power supply unit, VMGTAVTT power supply unit, and VCC_PSPLL power supply unit; 1.25V voltage corresponds to the VREFP / N power supply unit; The 1.8V and 3.3V voltages correspond to the VCCO_HPIO power supply unit and the VCCPSIO power supply unit, respectively.

6. The power supply system according to claim 1, characterized in that: The power output control circuit has the following two operating modes: Default mode: After the voltage output of the previous stage power supply module is stabilized, the power output control circuit automatically enables the power output function of the next stage power supply module. Operating mode: The power output control circuit is controlled by the general-purpose processor embedded in the MPSoC processor, which shuts down and turns on the specified power supply modules according to the running status and performance requirements.

7. A control method applied to a power supply system as described in any one of claims 1-6, characterized in that: The control method specifically includes the following steps: Step 1: After the soft-core processor in the FPGA starts running, it performs initialization; Step 2: The system status management unit compares the current voltage value rd1_v of the first-level power supply module with the standard voltage value nom1_v of the first-level power supply module, and feeds the result back to the control information fusion module in the soft core processor. Step 3: Read the voltage values ​​and operating status of the second-level power supply module, the third-level power supply module, and the fourth-level power supply module respectively, compare the current voltage value of the power supply module with the standard voltage value of the power supply module, and feed the result back to the information fusion module; Step 4: The information fusion module fuses the voltage and logic block operating status of the four-level power supply module to generate dynamic control information data packets, which are then sent to the MPSoC processor through the standard communication interface module. Step 5: Initialize the ARM main controller processor in the MPSoC processor; Step Six: Read the dynamic control information data packet transmitted in Step Four and unpack it; Step 7: Read the power supply voltage value and corresponding operating status of the MPSoC section through the digital-to-analog converter module; Step 8: Merge the information from the FPGA and MPSoC to generate control instructions for the general I / O module, and control the power enable / disable states of the second-level power supply module, the third-level power supply module, and the fourth-level power supply module.

8. The control method according to claim 7, characterized in that: The first-level power supply module supplies the processor core voltage and is never shut down during operation.

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