Musical sound signal generation device, musical sound signal generation method, and storage medium

Abstract

A musical tone signal generation apparatus, method, and storage medium that utilizes an all-pass filter for efficient processing. The method involves setting a first delay unit that generates a delay corresponding to a specified pitch, setting its pre-stage delay unit as a 0th delay unit, and its post-stage delay unit as a 2nd delay unit. At least three fractional delay blocks are connected to the first, 0th, and 2nd delay units, respectively. In a scenario where, based on a change in the specified pitch, one of the 0th and 2nd delay units is set as a new first delay unit, and the pre-stage delay unit of the new first delay unit is set as a new 0th delay unit, and the post-stage delay unit of the new first delay unit is set as a new 2nd delay unit, one of the 0th and 2nd delay units continues to be connected to the fractional delay blocks, and at least one of the new 0th and new 2nd delay units is then changed to be connected to at least one of the fractional delay blocks other than the fractional delay block connected to the new first delay unit.

Description

[0001] Citation of relevant applications

[0002] This application claims priority to Japanese Patent Application No. 2021-153006, filed on September 21, 2021, and Japanese Patent Application No. 2022-98190, filed on June 17, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to a musical sound signal generating apparatus, a musical sound signal generating method, and a storage medium. Background Technology

[0004] The number of delay units that make up a sound source in waveguide modeling is an integer and discrete. Therefore, in order to determine the exact frequencies, techniques are needed to implement delay lengths that are more precise than the integer equivalent of the number of delay units.

[0005] As a prior art for continuously achieving fractional delay lengths across a wide frequency band, for example, Japanese Patent Application Publication No. 6-348277 discloses a technique of inserting an all-pass filter before the final stage of a delay circuit. This technique implements a musical tone signal synthesis apparatus comprising: a first all-pass filter APF1; a second all-pass filter APF2; a variable connection unit that connects the first and second all-pass filters to different stages with selected delay elements; a control unit that controls the all-pass filters and the variable connection unit in the outputs of the first and second all-pass filters to make the delay times equal; and a weighted summing unit that performs a weighted summation of the outputs of the first and second all-pass filters. In this prior art, by using an all-pass filter, amplitude reduction in the high-frequency band can be prevented. Furthermore, in this prior art, a fractional delay length is generated by weighted summation of two all-pass filters. Thus, when the pitch frequency changes with time, such as in pitch bend, and the integer delay length in the waveguide-modeled sound source is switched over time, the generation of noise caused by the discontinuous transition of the coefficients of the all-pass filters between 0.0 and 1.0 is suppressed. Summary of the Invention

[0006] The problem the invention aims to solve

[0007] However, in the aforementioned prior art, the two all-pass filters need to operate with equal delay times, and the outputs of the two all-pass filters are weighted and summed. Therefore, the operation of the two all-pass filters always involves multiplying each filter coefficient twice, and the weighted summation also requires multiplication operations, resulting in at least six multiplication operations per sample. Thus, in waveguide modeling techniques that use a large number of multiplication operations, such as simultaneously emitting 256 polyphonic musical tones (e.g., a piano modeling source), each sample requires, for example, at least 6 × 256 polyphonic = 1,536 multiplication operations, leading to an overall increase in the computational load for musical tone generation.

[0008] Therefore, one of the advantages of this disclosure is that it generates musical tones with less computation.

[0009] Problem-solving methods

[0010] An example of a musical tone signal generating apparatus includes: a delay line having a plurality of delay units cascaded together, each delaying an input signal by a first delay length; at least three fractional delay blocks, each connected corresponding to one of the plurality of delay units, delaying the input signal by a second delay length less than or equal to the first delay length; and at least one processor that sets any one of the plurality of delay units to generate a first delay unit corresponding to a specified pitch, sets the delay unit preceding the first delay unit to a 0 delay unit, and sets the delay unit following the first delay unit to a 2 delay unit; the at least one processor sets the at least three fractional delay units to... The block is connected to the first delay unit, the 0th delay unit, and the 2nd delay unit respectively. When one of the connected 0th delay unit and the connected 2nd delay unit is set as a new 1st delay unit according to the change of the specified pitch, and the delay unit before the new 1st delay unit is set as a new 0th delay unit, and the delay unit after the new 1st delay unit is set as a new 2nd delay unit, one of the connected 0th delay unit and the connected 2nd delay unit continues to be connected to the fractional delay block, and at least one of the new 0th delay unit and the new 2nd delay unit is changed to be connected to at least one of the fractional delay blocks other than the fractional delay block connected to the new 1st delay unit.

[0011] The effects of the invention

[0012] According to this disclosure, musical tones can be generated with minimal computation. Attached Figure Description

[0013] Figure 1 This is a block diagram illustrating a hardware example of an embodiment of the musical sound signal generating device of this disclosure.

[0014] Figure 2 This is a block diagram representing a functional example implemented by a DSP or waveguide model circuit.

[0015] Figure 3 This is a diagram illustrating an example of the block structure of the computational unit in a waveguide model.

[0016] Figure 4 This is a diagram showing a connection example of three sets of APF to the delay line.

[0017] Figure 5 This is an explanatory diagram illustrating the reduction effect of computational load in the implementation method.

[0018] Figure 6 This is a graph showing the change in the connection of the three APFs to the delay line as the integer part of the delay length, i.e., the number of delay units k, increases.

[0019] Figure 7 This is an illustration of the continuous control method for filter coefficients.

[0020] Figure 8 This is a diagram showing the change in the connection of the three APFs to the delay line as the integer part of the delay length, i.e., the number of delay units k, decreases.

[0021] Figure 9 This is a flowchart (1) illustrating an example of pitch bend control processing.

[0022] Figure 10 This is a flowchart (2) illustrating an example of pitch bend control processing.

[0023] Figure 11 This is a diagram illustrating other implementations of the waveguide model computation unit. Detailed Implementation

[0024] Hereinafter, the methods for implementing this disclosure will be described in detail with reference to the accompanying drawings. The electronic device includes a musical tone signal generating device 100, a playing operation component (not shown), and a speaker. If the electronic device is a keyboard such as an electronic piano, the playing operation component is equivalent to the keyboard; if the electronic device is a wind instrument, the playing operation component is equivalent to the mouthpiece. Figure 1This is a block diagram illustrating a hardware example of an embodiment of the musical tone signal generating device 100 of this disclosure. The musical tone signal generating device 100 includes at least one CPU (central processing unit) 101 serving as a processor, ROM (read-only memory) 102, RAM (random access memory) 103, DSP (digital signal processor) or waveguide model circuit 104, pitch bend sensor 110 and ADC (analog-to-digital converter) 106 connected to its output, volume sensor 109 and ADC or digital input port 105 for detecting it, pitch designation switch 111 and digital input port 107 connected to its output, DAC (digital-to-analog converter) / amplifier 108, and a system bus 112. The CPU 101, ROM 102, RAM 103, DSP or waveguide model circuit 104, ADC 106, ADC or digital input port 105, digital input port 107, and DAC / amplifier 108 are interconnected via the system bus 112. Here, the volume sensor 109 and the pitch designation switch 111 may be the same component. For example, if the musical signal generating device 100 is an electronic piano, then the switch that senses the condition of the keyboard being played is both a pitch sensor and a volume sensor.

[0025] In this embodiment, an example of implementing the present disclosure through software is described using CPU 101 and DSP 104. However, CPU 101 can function as DSP 104. Alternatively, the functionality of DSP 104 can also be implemented by a hardware waveguide model circuit 104. Figure 2 This is a block diagram representing a functional example implemented by the DSP or waveguide model circuit 104.

[0026] The waveguide model control unit 201, as a control circuit, receives data from... Figure 1 The pitch assignment switch 111 inputs pitch information 203 (e.g., note numbers on the keyboard if it's an electronic piano), and from... Figure 1 The bending information (pitch change) 204 sent by the bend sensor 110 is used as the input signal to calculate the delay length of the waveguide model corresponding to the frequency f to be emitted, and to calculate the integer part of the delay length, i.e., the number of delayers k, and to determine the fractional part of the delay length. The filter coefficients g of the all-pass filter (fractional delay block) are calculated, and the number of delay units k and the filter coefficients g are output to the waveguide model calculation unit 202.

[0027] Here, in the fractional part of the delay length The following relationship is known between the filter coefficients g of the all-pass filter and the filter:

[0028]

[0029] Furthermore, the waveguide model control unit 201, based on the data from... Figure 1 The volume information 205 input by the volume sensor 109 calculates the volume 207 of the excitation tone 206. Then, the multiplier 208 multiplies the excitation tone 206 by the volume 207. Here, the excitation tone 206 is the signal that becomes the source of resonance in the waveguide modeling, and is pre-recorded and stored in, for example... Figure 1 The signals copied from ROM102 to RAM103 during system startup, read from RAM103 when voice control begins, or synthesized through computation are included in ROM102.

[0030] The waveguide model computation unit 202 receives the delay length (number of delayers k and filter coefficients g) and the excitation tone 206 multiplied by the volume 207 as input signal x(n), and performs... Figure 3 The subsequent calculations output musical tone signal 209. Musical tone signal 209 is input to... Figure 1 The DAC / amplifier 108 plays sound through the speakers of electronic devices (electronic musical instruments).

[0031] Figure 3 It means Figure 2 A diagram illustrating the block structure of the waveguide model computation unit 202. Figure 3 In the circuit, delay line 301 has N (or more) cascaded (vertically connected) delay units 302, numbered #0 to #N-1. Each delay unit 302 outputs the input signal after a one-sampling-time delay. Figure 3 The mark z in each delay unit 302 -1 This indicates a delay operation on one sample size during the z-transform. The following signal is input to the delay unit 302 (#0) at the beginning of this delay line 301: this signal is the input signal x(n) generated based on the excitation tone 206 (see reference 201) by the adder 311. Figure 2 The signal is obtained by adding the feedback signal 303 multiplied by the multiplier 304 with a predetermined gain. The outputs of each delay unit 302 in the delay line 301 can be taken from the delay line switch terminals d1 to dN.

[0032] Furthermore, in this embodiment, the waveguide model calculation unit 202 includes three all-pass filter circuits (hereinafter referred to as "APFs") 305, namely #0, #1, and #2. These APFs 305 operate as all-pass filters by being connected to both ends of a delay unit 302 in the delay line 301. Each APF 305 includes: a multiplier 306 that multiplies the signal at the input side of the connected delay unit 302 by a feedforward gain g (g0, g1, or g2); an adder 309 that adds the signal at the output side of the connected delay unit 302, the output signal of the multiplier 306, and the output signal of the multiplier 308 (described later), and selectively outputs the added output signal to a switch 310; a feedback delay unit 307 that delays the added output signal by one sampling time; and a multiplier 308 that multiplies the output signal of the feedback delay unit 307 by a feedback gain -g (-g0, -g1, or -g2), and outputs the multiplied output signal to the adder 309.

[0033] Each set of connection terminals i00 and i01 of APF305(#0), connection terminals i10 and i11 of APF305(#1), and connection terminals i20 and i21 of APF305(#2) are respectively connected to the delay line switch terminals at both ends of the same delayer 302 of delay line 301.

[0034] In addition, APF305(#0), APF305(#1) and APF305(#2) have feedforward gain and feedback gain g0 and -g0, g1 and -g1, and g2 and -g2, respectively. In the following text, the feedforward gain and feedback gain are collectively referred to as the filter coefficients of the all-pass filter.

[0035] APF305(#0), APF305(#1), and APF305(#2) must be connected to the adjacent delay unit 302 in delay line 301, but their order is controlled by pitch bend control processing described later to be replaced in the order of annular rings.

[0036] Each output destination of APF305(#0), APF305(#1), or APF305(#2) is connected to each output selection terminal o0, o1, or o2 of switch 310, and one of them is selected as the output signal y(n) to output the musical tone signal 209. In addition, the output signal y(n) is multiplied by the output feedback gain by multiplier 304, and the result of the multiplication operation is added to the input signal x(n) by adder 311.

[0037] Figure 4 It means having Figure 3 Structure Figure 2The diagram shows an example of a connection between the three APF305 groups (#0, #1, and #2) in the waveguide model computation unit 202 and the delay line 301. As described above, Figure 2 The waveguide model control unit 201, for example, is based on the playing operation of an electronic musical instrument. Figure 1 The pitch information 203 input to the pitch specification switch 111 is used to calculate the delay length of the waveguide model corresponding to the frequency f to be emitted. Then, the integer part of this delay length, i.e., the number of delay units k, is assigned to the waveguide model calculation unit 202. Additionally, Figure 2 The waveguide model control unit 201 determines the fractional part of the delay length through the calculation shown in equation (1) above. The filter coefficients g of the APF305 are assigned to the waveguide model computation unit 202.

[0038] As a result, in Figure 4 In the waveguide model calculation unit 202, the connection terminals i10 and i11 of APF305(#1) are connected to the delay line switch terminals dk and dk+1 at both ends of the delay unit 302(#k) in the delay line 301, which is the first delay unit. The first delay unit generates a delay of an integer part corresponding to the delay length specified by the waveguide model control unit 201.

[0039] Furthermore, the connection terminals i00 and i01 of APF305(#0) are respectively connected to the delay line switch terminals dk-1 and dk at both ends of the delay line switch 302(#k-1), which is the stage before the delay line 302(#k) that is the first delay line.

[0040] Furthermore, the connection terminals i20 and i21 of APF305(#2) are respectively connected to the delay line switch terminals dk+1 and dk+2 at both ends of the delay line switch 302(#k+1), which is the second delay unit after the delay unit 302(#k) which is the first delay unit, within the delay line 301.

[0041] On the other hand, for multipliers 306(#1) and 308(#1) of APF305(#1), the feedforward gain g and feedback gain -g of the filter coefficient g are set respectively. The filter coefficient g is determined by... Figure 2 The waveguide model control unit 201 corresponds to the fractional part of the delay length corresponding to the specified pitch. And calculated by the operation shown in equation (1).

[0042] Furthermore, for multipliers 306(#0) and 308(#0) of APF305(#0), a value of 0 is set to delay the value of 1 in the fractional part as the feedforward gain and feedback gain of the filter coefficients.

[0043] Furthermore, for the multipliers 306(#2) and 308(#2) of APF305(#2), the values ​​1 and -1, which cause a delay in the fractional part of the value 0, are respectively set as the feedforward gain and feedback gain of the filter coefficients.

[0044] Furthermore, switch 310 turns on the output selection terminal o1. As a result, the output signal of APF305(#1) is selected as the output signal y(n) via switch 310, and the musical tone signal 209 is output. In addition, the output signal y(n) is multiplied by the output feedback gain by multiplier 304 and added to the input signal x(n) by adder 311.

[0045] As a result of the above control actions, the musical tone signal 209 is generated by the delay unit 302 (#0 to #k-1) within the delay line 301, which produces an integer part k of the delay length corresponding to the specified pitch. The fractional part of the delay length is generated by the APF305(#1), which operates based on the filter coefficient g calculated by the operation shown in equation (1). .

[0046] In this case, since the frequency characteristics of the circuit consisting of delay line 301 and APF305(#1) are flat, the reduction of amplitude in the high-frequency band can be prevented.

[0047] Figure 5 This is an explanatory diagram illustrating the reduction effect of computational load in this embodiment. As described above, multipliers 306(#0) and 308(#0) of the APF305(#0) are both set to a value of 0 that delays the fractional part value of 1, serving as the feedforward gain and feedback gain of the filter coefficients. Therefore, multipliers 306(#0) and 308(#0) do not actually need to perform large-load multiplication operations, and Figure 4 APF305(#0) is Figure 5 The equivalent circuit shown is as follows. That is, in APF305(#0), it is only necessary to perform the operation of outputting the output from the delay unit 302(#k-1) in delay line 301 via the delay line switch terminal dk to the output selection terminal o0 of switch 310 as is.

[0048] On the other hand, as described above, for multipliers 306(#2) and 308(#2) of the APF305(#2), values ​​of 1 and -1, which delay the fractional part of 0, are respectively set as the feedforward gain and feedback gain of the filter coefficients. Therefore, multipliers 306(#2) and 308(#2) do not actually need to perform heavy multiplication operations, and Figure 4 APF305(#2) is Figure 5The equivalent circuit shown is as follows. That is, in APF305(#2), the following operations can be performed: the output of delay unit 302(#k) in delay line 301 via delay line switch terminal dk+1 is directly input to adder 309(#2), and the output of feedback delay unit 307(#2) is changed by sign through multiplier 308(#2) and input to adder 309(#2).

[0049] As described above, in this embodiment, multiplication is essentially only necessary in APF305(#1), while it is not required in APF305(#0) and APF305(#2). Therefore, compared to the technique disclosed in Japanese Patent Application Publication No. 6-348277 which uses two all-pass filters, the computational load can be significantly reduced, especially in the generation of musical tones in waveguide modeling with a high number of complex tones.

[0050] Next, it will be explained how the performer operates the instrument's pitch bend sensor 110 ( Figure 1 The principle of pitch bend control processing when the pitch of the playing note being played is changed.

[0051] exist Figure 2 In the process, the waveguide model control unit 201 calculates the delay length of a new specified pitch sequentially based on the sequentially input bending information 204, and calculates the integer part of the delay length, i.e., the number of delayers k, and the fractional part corresponding to the delay length. The filter coefficients g calculated by the operation shown in equation (1) are sequentially output to the waveguide model operation unit 202.

[0052] Here, if the value of the delay number k remains unchanged, only the filter coefficient g changes. This means that the change in wavelength of the musical tone signal 209 converges within one sampling time. For example, the fractional part of the delay length corresponding to the new specified pitch is achieved through pitch bend operation by the performer. As the values ​​of the filter coefficients g, calculated by the operation shown in equation (1) above, are specified to decrease sequentially.

[0053] Figure 6 This diagram shows the change in the connection of the three APF305s to the delay line 301 when the integer part of the delay length (i.e., the number of delay units k) increases. It also shows the fractional part of the delay length corresponding to the new specified pitch, achieved through pitch bend operation by the player. When the value increases sequentially and reaches 1, Figure 2 The waveguide model control unit 201 increments the integer part of the delay length for the specified pitch, i.e., the number of delay units k, by 1, which is output to the waveguide model calculation unit 202. At this time, due to the fractional part of the delay length... As the number of delay units k increases, it becomes 0, so the value of the filter coefficient g calculated by the operation shown in equation (1) becomes 1.

[0054] Thus, when the value of the number of delayers k, specified by the waveguide model control unit 201, changes by incrementing by 1, in Figure 6 In the waveguide model operation unit 202 shown, the new delay 302 (#k+1) in the delay line 301 corresponding to the changed number of delay 302 is used as the new first delay 302, and the operation of the full-pass filter is transferred to the APF305 (#2) which is currently connected to the delay line switch terminals dk+1 and dk+2 at both ends of it.

[0055] In addition, Figure 6 In the above handover, the result is that switch 310 turns off the output selection terminal o1 and turns on the output selection terminal o2 again.

[0056] At this time, as described above, for multipliers 306(#2) and 308(#2) of APF305(#2), the feedforward gain and feedback gain, which are the filter coefficients, are set to values ​​of 1 and -1, respectively, to delay the fractional part of the value 0, and then the operation is performed. Therefore, the operation of the all-pass filter is switched from APF305(#1) to the above-mentioned operation and control of APF305(#2) by... Figure 2 The fractional part specified in the waveguide model control section 201 The movements are well-matched.

[0057] Furthermore, the APF305(#2) operates continuously based on the actual signals from the delay line switch terminals dk+1 and dk+2, so it can be controlled to prevent noise from being generated during the switching of the APF305.

[0058] Here, as mentioned above, in APF305(#1), with the fractional part... As the value of increases, the value of the filter coefficient g, calculated by the operation shown in equation (1), decreases toward 0. However, when the control is switched from APF305(#1) to APF305(#2), the fractional part... The value of is reset to 0 at the beginning, therefore, at that instant, the value of the filter coefficient g needs to jump from near 0 to near 1. Such discontinuous jumps in value are less desirable when the filter coefficient g is envelope-controlled.

[0059] Therefore, in this embodiment, when the delay 302 that operates as the first delay is, for example, the even-numbered delay, the filter coefficient g is calculated by the operation shown in the aforementioned equation (1).

[0060] On the other hand, if the delay 302, which operates as the first delay, is, for example, the odd-numbered delay, the filter coefficient g is calculated by the operation process shown in equation (2) below.

[0061]

[0062] Moreover, in this case, the coefficients (1-g) and -(1-g) calculated using the coefficients g calculated by the operation shown in equation (2) above are set as the feedforward gain and feedback gain in multipliers 306 and 308, respectively.

[0063] exist Figure 6 For example, when the operation of the full-pass filter is currently being performed by APF305(#1), and the feedforward gain and feedback gain in multipliers 306(#1) and 308(#1) are set to g and -g, as described above, when the operation of the full-pass filter is switched from APF305(#1) to APF305(#2), it is possible to control the feedforward gain and feedback gain in multipliers 306(#2) and 308(#2) to be set to (1-g) and -(1-g).

[0064] Figure 7 This is an illustration of the continuous control method for the filter coefficients g. For example, consider the following... Figure 7 (a) shows the interval where the integer part of the delay length, i.e., the number of delay units, is k. In 1, such as Figure 7 (b) shows the filter coefficient g decreasing as the decimal of the delay length increases through the operation shown in equation (1). When in the interval... When the value of filter coefficient g in 1 reaches 0, such as Figure 7 As shown in (a), the integer part of the delay length, i.e., the value of the delay unit number, switches from the interval k+1. 2. In this new interval In section 2, through the above control methods, such as Figure 7 (b) shows the control so that the value of the filter coefficient g starts from the minimum value of 0 and increases with the increase of the decimal of the delay length according to the operation shown in (2).

[0065] As described above, in this embodiment, depending on whether the delay 302, which operates as the first delay, is the even-numbered (or odd-numbered) delay or the odd-numbered (or even-numbered) delay, the operations shown in equation (1) and equation (2) are switched to calculate the filter coefficient g. By switching whether the multipliers 306 and 308 in the APF305 are set to the g and -g group or the (1-g) and -(1-g) group, the filter coefficient g can be calculated. Figure 2The filter coefficients g assigned by the waveguide model control unit 201 to the waveguide model calculation unit 202 are as follows: Figure 7 (b) shows the continuous change.

[0066] The result is that, using an envelope generator circuit with techniques typically used in electronic musical instruments, through a fractional part of the delay length... The operation processing shown in equation (1) or (2) is performed on the input, and the envelope value can be output as follows: Figure 7 (b) shows the changing filter coefficients g.

[0067] As explained above, in Figure 6 In the case where the integer part of the delay length, i.e., the number of delay units k, increases, and the object of the all-pass filter operation, which is the first delay unit, is switched from the current APF305(#1) to the new APF305(#2), as follows: Figure 6 As shown, the delay 302(#k) that has been operating as the first delay 302 so far is identified as the 0th delay 302(#k+1) that is the previous stage of the new first delay 302(#k+1). For the multipliers 306(#1) and 308(#1) of the APF305(#1) connected to the delay line switch terminals dk and dk+1 on both sides, they are set to generate a delayed value of 0 as the value of the fractional part of the all-pass filter circuit connected to the 0th delay 302(#k) and the value of the feedback, respectively.

[0068] In addition, Figure 6 In this circuit, delay unit 302(#k+2) is identified as the second delay unit after delay unit 302(#k+1), which is the new first delay unit. The connection terminals i00 and i01 of APF305(#0) are newly connected to the delay line switch terminals dk+2 and dk+3 on both sides of it, respectively. For the multipliers 306(#0) and 308(#0) of APF305(#0), the values ​​1 and -1 are set to delay the value 0 of the fractional part of the all-pass filter circuit connected to the second delay unit, respectively, as the feedforward gain and feedback gain of the filter coefficients.

[0069] Additionally, as mentioned above, the output of the feedback delay unit 307 can be cleared to 0 before switching the connection of each APF305.

[0070] Figure 8 This diagram illustrates the change in the connection of the three APF305s to the delay line 301 when the integer part of the delay length, i.e., the number of delay units k, decreases. It also shows the fractional part of the delay length corresponding to the new specified pitch, achieved through pitch bending operations performed by the player. When the value decreases sequentially and reaches 0, Figure 2The waveguide model control unit 201 outputs to the waveguide model calculation unit 202 the integer part of the delay length for the specified pitch, i.e., the decrement value of the delay unit number k, which is 1. At this time, due to the fractional part of the delay length... As the number of delay units k decreases, it becomes the maximum value of 1, so the value of the filter coefficient g calculated by the operation shown in equation (1) becomes 0.

[0071] Thus, when the value of the number of retarders k specified by the waveguide model control unit 201 changes by decreasing by 1, Figure 8 In the waveguide model calculation unit 202 shown, the new delay 302 (#k-1) in the delay line 301 corresponding to the changed number of delay 302 is used as the new first delay 302, and the operation of the full-pass filter is transferred to the APF305 (#0) which is currently connected to the delay line switch terminals dk-1 and dk at both ends of it.

[0072] In addition, Figure 8 In the above handover, the result is that switch 310 cuts off the conduction of output selection terminal o1 and turns on output selection terminal o0 again.

[0073] At this time, as described above, for multipliers 306(#0) and 308(#0) of APF305(#0), the feedforward gain and feedback gain, which are the filter coefficients, are both set to a value of 0 that causes a delay in the fractional part of the value 1, and then operate accordingly. Therefore, the operation of the all-pass filter is switched from APF305(#1) to the aforementioned operation and control of APF305(#0) by... Figure 2 The fractional part specified in the waveguide model control section 201 The movements are well-matched.

[0074] Furthermore, the APF305(#0) operates continuously based on the actual signals from the delay line switch terminals dk-1 and dk, so it can be controlled to prevent noise from being generated during the switching of the APF305.

[0075] Here, as mentioned above, in APF305(#1), with the fractional part... The decrease in the value of causes the value of the filter coefficient g, calculated by the operation shown in equation (1), to increase toward 1. However, when the control is switched from APF305(#1) to APF305(#0), the fractional part... The value of is set to 1 at the beginning, so at that instant, the value of the filter coefficient g needs to jump from near 1 to near 0. This non-linear jump in value is similar to the case where the integer part of the delay length, i.e., the value of the number of delay units k, increases; conversely, the case where the integer part of the delay length, i.e., the value of the number of delay units k, decreases is also less desirable when the filter coefficient g is envelope-controlled.

[0076] Therefore, in this embodiment, similar to the case where the integer part of the delay length, i.e. the number of delayers k, increases, the operation shown in equation (1) and the operation shown in equation (2) above are switched to calculate the filter coefficient g, and the control of setting the g and -g groups or the (1-g) and -(1-g) groups of the multipliers 306 and 308 in APF305 is switched to be set, depending on whether the delayer 302 that operates as the first delayer is the even-numbered (or odd-numbered) delayer or the odd-numbered (or even-numbered) delayer.

[0077] exist Figure 8 For example, when the operation of the full-pass filter is currently being performed by APF305(#1), and g and -g are set as the feedforward gain and feedback gain in multipliers 306(#1) and 308(#1), as described above, when the operation of the full-pass filter is switched from APF305(#1) to APF305(#0), it is possible to control the feedforward gain and feedback gain in multipliers 306(#0) and 308(#0) to be set to (1-g) and -(1-g).

[0078] For example, in the aforementioned Figure 7 In the meantime, consider in such Figure 7 (a) shows the integer part of the delay length, i.e., the interval where the number of delay units is k. In 1, such as Figure 7 (b) shows the filter coefficient g increasing as the decimal of the delay length decreases through the operation shown in equation (1). When in the interval... When the value of filter coefficient g in 1 reaches 1, such as Figure 7 As shown in (a), the integer part of the delay length, i.e., the value of the delay unit number, switches from the interval k to k-1. 0. In this new interval In 0, through the above control methods, such as Figure 7 (b) shows the control so that the value of the filter coefficient g starts from the maximum value of 1 and decreases as the decimal of the delay length decreases according to the operation shown in (2).

[0079] As described above, in this embodiment, similar to the case where the integer part of the delay length, i.e., the number of delay units k, increases, even when the integer part of the delay length, i.e., the number of delay units k, decreases, the filter coefficient g is calculated by switching the operations shown in equation (1) and equation (2) depending on whether the delay unit 302 operating as the first delay unit is the even-numbered (or odd-numbered) delay unit or the odd-numbered (or even-numbered) delay unit. By switching whether to set the g and -g groups or the (1-g) and -(1-g) groups for the multipliers 306 and 308 within the APF305, the filter coefficient g can be calculated. Figure 2The filter coefficients g assigned by the waveguide model control unit 201 to the waveguide model calculation unit 202 are as follows: Figure 7 (b) shows the continuous change.

[0080] As a result, using an envelope generator circuit employing techniques commonly used in electronic musical instruments, through a fractional part of the delay length... The operation processing shown in equation (1) or (2) is performed on the input, and the envelope value can be output as follows: Figure 7 (b) shows the changing filter coefficients g.

[0081] As explained above, in Figure 8 In the case where the integer part of the delay length, i.e., the number of delayers k, decreases, and the object performing the all-pass filter operation as the first delayer switches from the current APF305(#1) to the new APF305(#0), the delayer 302(#k) that has been operating as the first delayer so far... Figure 8 As shown, the second delay unit, which is identified as the next stage of the delay unit 302(#k-1) as the new first delay unit, has multipliers 306(#1) and 308(#1) of APF305(#1) connected to the delay line switch terminals dk and dk+1 on both sides of it, respectively set to a value of 1 and a value of -1 that delay the value 0 of the fractional part of the all-pass filter circuit connected to the second delay unit, as the feedforward gain and feedback gain of the filter coefficients.

[0082] In addition, Figure 8 In this context, delay unit 302(#k-2) is identified as the 0th delay unit preceding delay unit 302(#k-1) which is the new 1st delay unit. On the delay line switch terminals dk-2 and dk-1 on both sides of it, the connection terminals i20 and i21 of APF305(#2) are newly connected respectively. For the multipliers 306(#2) and 308(#2) of APF305(#2), they are both set to generate a delayed value of 0 from the fractional part of the all-pass filter circuit connected to the 0th delay unit, which is the feedforward gain and feedback gain of the filter coefficient.

[0083] and Figure 6 Similarly, before switching the connection of each APF305 as described above, the output of the feedback delay unit 307 can be cleared to 0.

[0084] Figure 9 and Figure 10 This is a flowchart illustrating an example of pitch control processing performed based on the principles described above. This processing is... Figure 1 The CPU 101 loads the pitch control processing program stored in ROM 102 into RAM 103 for execution. Figure 9 and Figure 10 The flowchart shows that when APF305(#0) is connected to the two ends of delay unit 302(#k-1), APF305(#1) is connected to delay unit 302(#k), and APF305(#2) is connected to delay unit 302(#k+1), after the sound is produced, the pitch bend sensor 110 will determine the integer part of the delay length of the specified pitch, i.e., the delay unit number k, and the fractional part. The value changes from L1 to L2. Figure 2 The flowchart shows the control time sequence of the waveguide model control unit 201 and the waveguide model calculation unit 202.

[0085] When the bend begins, CPU101 determines in step S1 whether L2 is greater than or less than L1, that is, whether L2 is a downward bend or an upward bend.

[0086] When L1 < L2, i.e., when a downward bend occurs, CPU101 in step S2 calculates the fractional part of the rate r relative to the delay length. Add. Additionally, "+=" indicates an operation that adds the value of the right-hand variable to the value of the variable on the left.

[0087] If L is greater than the target value in step S3, CPU 101 will adjust the fractional part in step S4. and 2. Consistent, so as to be consistent with the target value.

[0088] Next, in step S5, CPU101 determines whether the number of delay units k is even or odd. Additionally, the "%" operator is used to calculate the remainder when the value of the number of delay units k is divided by 2. If the result of this operation is 0, the number of delay units k is even; otherwise, it is odd.

[0089] When k is even, in step S6, CPU101 sets the filter coefficient g by the operation shown in equation (1) based on the fractional part. The calculated coefficients.

[0090] When k is odd, CPU 101 sets 1-g according to the fractional part through the operation shown in equation (2) in step S8. The calculated coefficients.

[0091] Then, in step S7 or S9, the case where g < 0 or 1 - g < 0 is the case where there is no carry in the integer part of the delay length, i.e., the number of delay units k. Therefore, CPU 101 performs the full-pass filter operations of APF305(#0), APF305(#1), and APF305(#2) as is in step S10, and then updates the samples in step S11. Updating the samples means staggering the data input to each delay unit 302 of the delay line 301 one by one, so that the waveform advances.

[0092] If CPU101 determines in step S12 that L has reached the target value, it ends the processing. If it determines that L has not reached the target value, it repeatedly processes L while adding the rate r until L is reached.

[0093] In step S7 or S9, the case where g < 0 or 1 - g < 0 occurs when there is a carry-over in the integer part of the delay length, i.e., the number of delay units k. In this case, CPU 101 sets g = 0 in step S13.

[0094] In this state, in step S14, CPU101 executes the full-pass filter operations of APF305(#0), APF305(#1), and APF305(#2). In this case, APF305(#1) performs the operation with delay number k and filter coefficient 0, while APF305(#2) performs the operation with delay number k+1 and filter coefficient 1. Since APF305(#2) starts its operation with the feedback delay value being 0, it outputs the signal i20 as is, according to the properties of the full-pass filter. On the other hand, in APF305(#1), since the operation is performed with g=0, the signal i11 is output as is. The signals i20 and i11 are identical. Therefore, at this timing, the signals output to the output selection terminals o1 and o2 are equal. Therefore, even if switch 310 switches the output selection terminal from o1 to o2 in step S16, no noise is generated.

[0095] Then, CPU101 performs the same sample update as in step S11 in step S15.

[0096] Next, CPU101 switches switch 310 to output selection terminal o2.

[0097] Then, in step S17, CPU101 clears the data input to the feedback delay unit 307(#0) of APF305(#0) to 0.

[0098] Then, in step S18, CPU101 changes the connection terminals i00 and i01 of APF305(#0) to the delay line switch terminals dk+2 and dk+3, respectively. Furthermore, the filter coefficient g0 of APF305(#0) is changed from 0 to 1.

[0099] The state of waveguide model computation unit 202 after the connection switch of APF305(#0) is as follows: Figure 6 The process described above, step S18, is the same as incrementing the integer part of the delay length, i.e., the number of delay units k, by +1. In the diagram, "++" represents the +1 increment operation.

[0100] After the processing in step S18, CPU 101 returns to the processing in step S2 and repeats the operation of increasing the delay length. At this time, APF305(#2) becomes the object of changing the filter coefficients. Subsequently, whenever the number of delay units k increases, APF305(#0), APF305(#1), and APF305(#2) become the objects of filter coefficient calculation one by one in ascending order of the ring.

[0101] exist Figure 9 In step S1, when L1 > L2, i.e., during an uphill curve, the following steps are executed: Figure 10 The processing after step S19 in the flowchart. The case of L1 > L2 differs from the case of L1 < L2 in the following ways.

[0102] First, in step S19, CPU101 decomposes the fractional part... Subtract the rate r from the middle. In the diagram, "-=" indicates the operation of subtracting the value of the variable on the right from the value on the left.

[0103] Additionally, in step S24 or S26, regardless of whether g > 1 or 1 - g > 1, it is determined whether the integer part of the delay length, i.e., the number of delay units k, has been de-indexed.

[0104] The case where g > 1 or 1 - g > 1 indicates a case where the delay unit number k is borrowed. In this case, CPU 101 sets g = 1 in step S30.

[0105] CPU101 further executes the operations and sample updates of APF305(#0), APF305(#1), and APF305(#2) in steps S31 and S32. In the subsequent state, APF305(#1) performs the operation with filter coefficient g = 1. Although there is some feedback effect, the signal of i10 is output almost unchanged. APF305(#0) continues the operation with filter coefficient 0, so it outputs the value of i01 unchanged. The signals of i10 and i01 are approximately the same. Therefore, in step S33, even when the output selection terminal is switched from output selection terminal o1 to output selection terminal o0 in switch 310, no noise is generated.

[0106] In step S33, CPU101 switches switch 310 to output selection terminal o0.

[0107] Then, in step S34, CPU101 clears the data input to the feedback delay unit 307(#2) of APF305(#2) to 0.

[0108] Then, in step S35, CPU101 connects the connection terminals i20 and i21 of APF305(#2) to the delay line switch terminals dk-2 and dk-1, respectively.

[0109] The state of waveguide model computation unit 202 after the connection switch of APF305(#2) is as follows: Figure 8 As described above. Step S35 is the same as decrementing the integer part of the delay length, i.e., the number of delay units k, by 1. In the figure, "--" indicates the decrementing operation.

[0110] After the processing in step S35, CPU 101 returns to the processing in step S19 and repeats the operation of reducing the delay length. At this time, APF305(#0) becomes the object of changing the filter coefficients. Subsequently, whenever the number of delay units k decreases, APF305(#0), APF305(#1), and APF305(#2) become the objects of filter coefficient calculation in descending order of the ring.

[0111] In the processing of pitch changes with decreasing delay length, such as Figure 10 As described in step S35, the filter coefficients of the APF305 are set to 0 and the connection is changed. When the rate r is sufficiently small, operation begins with small filter coefficients. Therefore, even if the value on the feedback side is uncertain (discontinuous), the noise emitted in the next sample is small. Therefore, as a variation of this embodiment, such as... Figure 11 As shown, APF305(#1) and APF305(#2) are calculated in the form where APF305(#0) has been removed. Figure 9 In step S18, APF305(#1) is connected instead of APF305(#0). Figure 10 In step S35, even if APF305(#2) is reconnected to the delay line switch terminals dk-1 and dk, the number of delay units can be changed with minimal noise impact. In this case, the number of multiplications can be reduced by two.

[0112] exist Figure 5 The text explains that the number of multiplications can be reduced in APF305(#0) and APF305(#2), but multiplication operations can also be retained to prioritize algorithm and hardware uniformity. The final output signal y(n) is connected to o1 when there is no bend in the pronunciation. In this case, the output signals of APF305(#0) and APF305(#2) are not output from the output selection terminals o0 and o2, but are prepared in advance for operations to be performed when a bend occurs in the aforementioned pronunciation.

[0113] As described above, in this embodiment, by pre-connecting multiple APF305s to adjacent delayers 302 in delay line 301, uncertain data is prevented from entering delayers 302, thus suppressing noise when the number of delayers 302 changes during waveguide model rendering. Furthermore, in this embodiment, the number of multiplications in the two APF305s other than the one connected to the first delayer can be reduced.

[0114] Thus, according to this embodiment, in waveguide-modeled sound sources, by using fractional delay blocks such as all-pass filters, it is possible to eliminate the frequency dependence of amplitude and suppress noise generation when the number of connections to the delay unit changes with less computation. Specifically, it is advantageous to reduce the number of multiplications by a maximum of 4 per waveguide model. This is because, for example, in a piano, there are approximately 230 strings, so if all strings are modeled and made to move, the number of multiplication operations is reduced by 920.

[0115] Furthermore, according to this embodiment, since the filter coefficients can be continuously varied, envelope control can be easily applied to the filter coefficients.

[0116] The block diagrams shown in the accompanying figures described above can be replaced by software. For example, after replacing them with software... Figure 3 In the case of the complete structure, the processor calculates and outputs filter coefficients based on the mathematical formulas derived from the delay lengths of pairs of delayers 0-2 and each APF305 (#0-#2). It then uses the filter coefficients of the pair of delayers 1 and APF305 (#1) to calculate the waveform and applies it to the output, thereby enabling software processing. Furthermore, regarding... Figure 6 The switching operation of APF305, as described, involves the processor periodically outputting filter coefficients based on a mathematical formula derived from the delay lengths of pairs of delay units 0-2 and each APF305 (#0-#2) before the switch. A switch is considered complete when the filter coefficient corresponding to APF305 (#1) exceeds a specified range. After the switch, the processor outputs filter coefficients based on a mathematical formula derived from the delay lengths of pairs of delay units 0-2 and each APF305 (#0-#2). The waveform is then calculated using the filter coefficients of the new pair of delay units 1 and APF305 (#1) and applied to the output, thus enabling software processing. Furthermore, the embodiment using the circuit can be combined with software, allowing software to replace a portion of the circuit.

[0117] In the above embodiment, the control program is stored in ROM 102, but it is not limited to this. It can also be stored in a removable storage medium such as a USB memory, CD, DVD, or a server. The music signal generating device 100 can obtain the control program from such a storage medium or from a server via a network.

[0118] Furthermore, the all-pass filters shown in the above embodiments are not limited to three; four or more can also be provided.

[0119] Furthermore, this disclosure is not limited to the above-described embodiments, and various modifications can be made during the implementation phase without departing from its spirit. Moreover, the functions performed in the above embodiments can be implemented by combining them appropriately as much as possible. The above embodiments include various stages, and various inventions can be extracted through appropriate combinations of the disclosed constituent elements. For example, even if several constituent elements are deleted from all the constituent elements shown in the embodiments, as long as the desired effect is achieved, the structure with the deleted constituent elements can still be extracted as an invention.

Claims

1. A musical tone signal generating device, wherein, have: A delay line having multiple delay units cascaded together, each delaying the input signal by a first delay length; At least three fractional delay blocks are respectively connected to one of the plurality of delay units, so that the input signal is delayed by a second delay length that is less than or equal to the first delay length; as well as At least one processor configures any one of the plurality of delay units as a first delay unit that generates a delay corresponding to a specified pitch, configures the delay unit preceding the first delay unit as a 0th delay unit, and configures the delay unit following the first delay unit as a second delay unit. The at least one processor, The at least three fractional delay blocks are respectively connected to the first delay unit, the 0th delay unit, and the second delay unit. When, based on the change in the specified pitch, one of the connected 0th delay unit and the connected 2nd delay unit is set as a new 1st delay unit, and the delay unit before the new 1st delay unit is set as a new 0th delay unit, and the delay unit after the new 1st delay unit is set as a new 2nd delay unit, one of the connected 0th delay unit and the connected 2nd delay unit continues to be connected to the fractional delay block, and at least one of the new 0th delay unit and the new 2nd delay unit is changed to be connected to at least one of the fractional delay blocks other than the fractional delay block connected to the new 1st delay unit.

2. The musical tone signal generating device according to claim 1, wherein, The at least three fractional delay blocks, together with the delay units corresponding to the fractional delay blocks, operate as an all-pass filter block.

3. The musical tone signal generating device according to claim 2, wherein, The at least one processor, For the all-pass filter block, which is the fractional delay block corresponding to the first delay unit, filter coefficients corresponding to the second delay length are set, where the second delay length is the fractional part of the delay length corresponding to the specified pitch. For the all-pass filter block that corresponds to the fractional delay block of the 0th delay unit and the all-pass filter block that corresponds to the fractional delay block of the 2nd delay unit, filter coefficients with values ​​of 0 and 1 corresponding to the second delay lengths of values ​​1 and 0 are respectively set. The output of the all-pass filter block, which is the fractional delay block corresponding to the first delay unit, is output as a musical tone signal and a feedback signal to the input of the delay line.

4. The musical tone signal generating device according to any one of claims 1 to 3, wherein, The at least one processor, It also has an envelope generator circuit. The envelope generator circuit is as follows: When the fractional part of the delay length is set to l, if the first delay unit is an even-numbered or odd-numbered delay unit, the coefficient g calculated by the operation expressed by equation (1) is set to the filter coefficient corresponding to the fractional part of the delay length corresponding to the specified pitch, i.e., the second delay length. g＝（1-l） / （1+l）…（1）， In the case that the first delay unit is the odd-numbered or even-numbered delay unit, the coefficient (1-g) calculated using the coefficient g obtained by the operation expressed by equation (2) is set as the filter coefficient. g＝2×l / （1+l）…（2）， Take the fractional part l of the delay length as input, and output the coefficient g, which is the change represented by the operation expression of the above (1) or (2), as the envelope value.

5. The musical tone signal generating apparatus according to any one of claims 1 to 3, wherein, The fractional delay block connected to both ends of the 0th delay performs the operation of outputting the output of the 0th delay as is. The fractional delay block connected to both ends of the second delay unit performs the following operation: instead of multiplying each multiplication operation by a value of 1 or -1 corresponding to a filter coefficient of value 1 corresponding to the value of 0 of the second delay length, the input value in the multiplication operation is output as the output value in each multiplication operation, either as is or with a different sign.

6. An electronic device, wherein, have: The musical tone signal generating apparatus according to any one of claims 1 to 5; and Operating components.

7. A method for generating musical tone signals, wherein, Connect at least three fractional delay blocks to the first delay unit, the 0th delay unit, and the second delay unit, respectively. The at least three fractional delay blocks are respectively connected to one of the delay lines having multiple delay units, thereby delaying the input signal by a second delay length that is less than or equal to the first delay length. The multiple delay units in the delay line are cascaded together, each delaying the input signal by the first delay length. The first delay unit is the delay unit among the plurality of delay units that generates a delay corresponding to a specified pitch. The 0th delay unit is the delay unit that precedes the 1st delay unit among the plurality of delay units. The second delay unit is the delay unit that corresponds to the stage following the first delay unit among the plurality of delay units. When, based on the change in the specified pitch, one of the connected 0th delay unit and the connected 2nd delay unit is set as a new 1st delay unit, and the delay unit before the new 1st delay unit is set as a new 0th delay unit, and the delay unit after the new 1st delay unit is set as a new 2nd delay unit, one of the connected 0th delay unit and the connected 2nd delay unit continues to be connected to the fractional delay block, and at least one of the new 0th delay unit and the new 2nd delay unit is changed to be connected to at least one of the fractional delay blocks other than the fractional delay block connected to the new 1st delay unit.

8. The method for generating musical tone signals according to claim 7, wherein, The at least three fractional delay blocks, together with the delay units corresponding to the fractional delay blocks, are configured to operate as an all-pass filter block.

9. The method for generating musical tone signals according to claim 8, wherein, For the all-pass filter block, which is the fractional delay block corresponding to the first delay unit, filter coefficients corresponding to the second delay length are set, where the second delay length is the fractional part of the delay length corresponding to the specified pitch. For the all-pass filter block that corresponds to the fractional delay block of the 0th delay unit and the all-pass filter block that corresponds to the fractional delay block of the 2nd delay unit, filter coefficients with values ​​of 0 and 1 corresponding to the second delay lengths of values ​​1 and 0 are respectively set. The output of the all-pass filter block, which is the fractional delay block corresponding to the first delay unit, is output as a musical tone signal and a feedback signal to the input of the delay line.

10. The method for generating musical tone signals according to any one of claims 7 to 9, wherein, When the fractional part of the delay length is set to l When the first delay unit is an even-numbered or odd-numbered delay unit, the coefficient g calculated by the operation expressed by equation (1) is set to the filter coefficient corresponding to the fractional part of the delay length corresponding to the specified pitch, i.e., the second delay length. g＝（1-l） / （1+l）…（1）， In the case that the first delay unit is the odd-numbered or even-numbered delay unit, the coefficient (1-g) calculated using the coefficient g obtained by the operation expressed by equation (2) is set as the filter coefficient. g＝2×l / （1+l）…（2）， Take the fractional part l of the delay length as input, and output the coefficient g, which is the change represented by the operation expression of the above (1) or (2), as the envelope value.

11. The method for generating musical tone signals according to any one of claims 7 to 9, wherein, The fractional delay block connected to both ends of the 0th delay performs the operation of outputting the output of the 0th delay as is. The fractional delay block connected to both ends of the second delay unit performs the following operation: instead of multiplying each multiplication operation by a value of 1 or -1 corresponding to a filter coefficient of value 1 corresponding to the value of 0 of the second delay length, the input value in the multiplication operation is output as the output value in each multiplication operation, either as is or with a different sign.

12. A storage medium storing program code, wherein, The program code causes the computer to perform the following steps: Connect at least three fractional delay blocks to the first delay unit, the 0th delay unit, and the second delay unit, respectively. The at least three fractional delay blocks are respectively connected to one of the delay lines having multiple delay units, thereby delaying the input signal by a second delay width with a length less than or equal to the first delay length. The multiple delay units in the delay line are cascaded together, each delaying the input signal by the first delay length. The first delay unit is the delay unit among the plurality of delay units that generates a delay corresponding to a specified pitch. The 0th delay unit is the delay unit that precedes the 1st delay unit among the plurality of delay units. The second delay unit is the delay unit that corresponds to the stage following the first delay unit among the plurality of delay units. When, based on the change in the specified pitch, one of the connected 0th delay unit and the connected 2nd delay unit is set as a new 1st delay unit, and the delay unit before the new 1st delay unit is set as a new 0th delay unit, and the delay unit after the new 1st delay unit is set as a new 2nd delay unit, one of the connected 0th delay unit and the connected 2nd delay unit continues to be connected to the fractional delay block, and at least one of the new 0th delay unit and the new 2nd delay unit is changed to be connected to at least one of the fractional delay blocks other than the fractional delay block connected to the new 1st delay unit.

13. The storage medium according to claim 12, wherein, The at least three fractional delay blocks, together with the delay units corresponding to the fractional delay blocks, are configured to operate as an all-pass filter block.

14. The storage medium according to claim 13, wherein, For the all-pass filter block, which is the fractional delay block corresponding to the first delay unit, filter coefficients corresponding to the second delay length are set, where the second delay length is the fractional part of the delay length corresponding to the specified pitch. For the all-pass filter block, which is the fractional delay block corresponding to the 0th delay unit, and the all-pass filter block, which is the fractional delay block corresponding to the 2nd delay unit, filter coefficients with values ​​of 0 and 1 corresponding to the second delay lengths of values ​​1 and 0 are respectively set. The output of the all-pass filter block, which is the fractional delay block corresponding to the first delay unit, is output as a musical tone signal and a feedback signal to the input of the delay line.

15. The storage medium according to any one of claims 12 to 14, wherein, When the fractional part of the delay length is set to l When the first delay unit is an even-numbered or odd-numbered delay unit, the coefficient g calculated by the operation expressed by equation (1) is set to the filter coefficient corresponding to the fractional part of the delay length corresponding to the specified pitch, i.e., the second delay length. g＝（1-l） / （1+l）…（1）， In the case that the first delay unit is the odd-numbered or even-numbered delay unit, the coefficient (1-g) calculated using the coefficient g obtained by the operation expressed by equation (2) is set as the filter coefficient. g＝2×l / （1+l）…（2）， Take the fractional part l of the delay length as input, and output the coefficient g, which is the change represented by the operation expression of the above (1) or (2), as the envelope value.

16. The storage medium according to any one of claims 12 to 14, wherein, The fractional delay block connected to both ends of the 0th delay unit performs an operation that outputs the output of the 0th delay unit as is. The fractional delay block connected to both ends of the second delay unit performs the following operation: instead of multiplying each multiplication operation by a value of 1 or -1 corresponding to a filter coefficient of value 1 corresponding to the value of 0 of the second delay length, the input value in the multiplication operation is output as the output value in each multiplication operation, either as is or with a different sign.

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