Package structure, electronic device and packaging method

Abstract

The application discloses a packaging structure, an electronic device and a packaging method. The packaging structure comprises a first packaging module and a second packaging module. The first packaging module comprises a first chip and a second chip. The first chip and the second chip are arranged along the thickness direction of the first chip, and the first chip is electrically connected with the second chip. The second packaging module is arranged along the thickness direction of the first packaging module. The second packaging module comprises a third chip and a fourth chip. The third chip and the fourth chip are arranged along the thickness direction, and the third chip is electrically connected with the fourth chip. The fourth chip is electrically connected with the first chip.

Description

Technical Field

[0001] This application relates to the field of chip packaging technology, and more specifically, to a packaging structure, electronic device, and packaging method. Background Technology

[0002] In related technologies, multiple chips can be arranged vertically during packaging. When multiple chips are arranged perpendicular to each other, adjacent chips are interconnected via copper pillars, and data is transmitted between the chips through these pillars. However, in this type of chip packaging structure, the copper pillars occupy a certain amount of vertical space, resulting in a relatively large package thickness. Summary of the Invention

[0003] This application aims to provide a packaging structure, electronic device, and packaging method that at least solves the problem of large packaging structure size.

[0004] To solve the above-mentioned technical problems, this application is implemented as follows:

[0005] In a first aspect, embodiments of this application propose a packaging structure, including a first packaging module and a second packaging module; the first packaging module includes a first chip and a second chip, the first chip and the second chip are arranged along the thickness direction of the first chip, and the first chip and the second chip are electrically connected; the second packaging module is arranged along the thickness direction with the first packaging module, and the second packaging module includes a third chip and a fourth chip, the third chip and the fourth chip are arranged along the thickness direction, and the third chip and the fourth chip are electrically connected; the fourth chip is electrically connected to the first chip.

[0006] Secondly, embodiments of this application provide an electronic device including the packaging structure of the first aspect.

[0007] Thirdly, embodiments of this application propose a packaging method for packaging the packaging structure of the first aspect. The packaging method includes: dicing a first wafer to obtain a first chip; placing the first chip on a substrate; dicing a second wafer to obtain a second chip; bonding the second chip to the first chip to obtain a first packaging module; dicing a third wafer to obtain a third chip; bonding the third chip to a fourth chip on a fourth wafer; dicing the fourth wafer to obtain a second packaging module; arranging the first packaging module and the second packaging module in the thickness direction; and electrically connecting the first chip and the fourth chip.

[0008] The packaging structure provided in this application includes a first packaging module and a second packaging module. The first packaging module includes a first chip and a second chip, and the second packaging module includes a third chip and a fourth chip. The first chip and the second chip in the first packaging module are bonded together, and the third chip and the fourth chip in the second packaging module are bonded together. Then the first packaging module and the second packaging module are connected to modularize the multiple chips in the packaging structure.

[0009] When connecting the first and second packaging modules, the first and fourth chips located on opposite sides in the vertical direction can be connected to achieve electrical connection between them. Since the electrical connection components between the first and fourth chips can occupy the space occupied by the second and third chips during bonding, and no further electrical connection components are needed between the second and third chips, the vertical space occupied by the electrical connection components between the first and second packaging modules is reduced. This reduces the thickness of the packaging module and the vertical space occupied, contributing to a thinner and lighter packaging module.

[0010] The electronic device provided in this application includes the above-described packaging structure, and the packaging method provided in this application is used to manufacture the above-described packaging structure. Therefore, the electronic device and packaging method provided in this application have the beneficial effects of the above-described packaging structure.

[0011] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0012] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0013] Figure 1 This is one of the schematic diagrams of the packaging structure according to an embodiment of this application;

[0014] Figure 2 This is one of the schematic diagrams illustrating the packaging process of the packaging structure according to an embodiment of this application;

[0015] Figure 3 This is a second schematic diagram of the packaging process according to the packaging structure of the embodiment of this application;

[0016] Figure 4 This is a third schematic diagram of the packaging process according to the packaging structure of the embodiment of this application;

[0017] Figure 5 This is a second schematic diagram of the packaging structure according to an embodiment of this application;

[0018] Figure 6 This is a fourth schematic diagram of the packaging process according to the packaging structure of the embodiment of this application;

[0019] Figure 7 This is the fifth schematic diagram of the packaging process according to the packaging structure of the embodiment of this application;

[0020] Figure 8 This is a schematic diagram of the packaging process according to the packaging structure of the embodiment of this application;

[0021] Figure 9 This is Schematic diagram seven of the packaging process according to the packaging structure of the embodiment of this application;

[0022] Figure 10 This is the eighth schematic diagram of the packaging process according to the packaging structure of the embodiment of this application;

[0023] Figure 11 This is diagram nine of the packaging process according to the packaging structure of the embodiment of this application;

[0024] Figure 12 This is diagram ten of the encapsulation process of the encapsulation structure according to an embodiment of this application;

[0025] Figure 13 This is eleventh of a schematic diagram illustrating the packaging process of the packaging structure according to an embodiment of this application;

[0026] Figure 14 This is a flowchart of a packaging method according to an embodiment of this application.

[0027] Figure label:

[0028] 100 First packaging module, 110 First chip, 120 Second chip, 200 Second packaging module, 210 Third chip, 220 Fourth chip, 302 First metal ball, 304 First dielectric layer, 306 First wiring layer, 308 First bump, 310 Second bump, 312 Second metal ball, 314 Second dielectric layer, 316 Second wiring layer, 318 Third metal ball, 320 Third dielectric layer, 322 Third wiring layer, 324 Third bump, 326 Fourth bump, 328 Packaging part, 330 First colloid, 332 Second colloid, 334 Fifth bump, 336 Fourth dielectric layer, 338 Substrate, 340 First wafer, 342 Second wafer, 344 Third wafer, 346 Fourth wafer, 348 Adhesive film. Detailed Implementation

[0029] The embodiments of this application will now be described in detail. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0030] The terms "first" and "second" in the specification and claims of this application may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise stated, "multiple" means two or more. Furthermore, "and / or" in the specification and claims indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0031] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0032] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0033] The following is combined Figures 1 to 14 This application describes a packaging structure, an electronic device, and a packaging method according to embodiments thereof.

[0034] like Figure 1As shown, the packaging structure according to some embodiments of this application includes a first packaging module 100 and a second packaging module 200; the first packaging module 100 includes a first chip 110 and a second chip 120, the first chip 110 and the second chip 120 are arranged along the thickness direction of the first chip 110, and the first chip 110 and the second chip 120 are electrically connected; the second packaging module 200 is arranged along the thickness direction of the first packaging module 100, and the second packaging module 200 includes a third chip 210 and a fourth chip 220, the third chip 210 and the fourth chip 220 are arranged along the thickness direction, and the third chip 210 and the fourth chip 220 are electrically connected; the fourth chip 220 is electrically connected to the first chip 110.

[0035] In this embodiment, the packaging structure includes a first packaging module 100 and a second packaging module 200. The first packaging module 100 includes a first chip 110 and a second chip 120. The second packaging module 200 includes a third chip 210 and a fourth chip 220. The first chip 110 and the second chip 120 in the first packaging module 100 are bonded together, and the third chip 210 and the fourth chip 220 in the second packaging module 200 are bonded together. Then, the first packaging module 100 and the second packaging module 200 are connected to modularize the multiple chips in the packaging structure.

[0036] When connecting the first packaging module 100 and the second packaging module 200, they can be connected through the first chip 110 and the fourth chip 220 located on both sides in the vertical direction, thereby realizing the electrical connection between the first packaging module 100 and the second packaging module 200. Since the electrical connection components between the first chip 110 and the fourth chip 220 can occupy the space occupied by the second chip 120 and the third chip 210 during bonding, and no further electrical connection components are needed between the second chip 120 and the third chip 210, the vertical space occupied by the electrical connection components between the first packaging module 100 and the second packaging module 200 is reduced, thus reducing the thickness of the packaging module and minimizing its vertical space occupation, which is beneficial for the thinning and lightening of the packaging module.

[0037] Specifically, in the vertical direction, the first chip 110, the second chip 120, the third chip 210, and the fourth chip 220 are arranged sequentially. The vertical arrangement of the first chip 110, the second chip 120, the third chip 210, and the fourth chip 220 makes the signal transmission path between the chips shorter and the transmission speed faster, further improving the performance of the packaging module.

[0038] Furthermore, the packaging structure may also include a third packaging module, which may include a fifth chip and a sixth chip, the fifth chip and the sixth chip being electrically connected, and the sixth chip being electrically connected to the fourth chip 220.

[0039] The packaging structure may also include a fourth packaging module or more packaging modules.

[0040] Furthermore, the first packaging module 100 may also include a seventh chip, which is electrically connected to the second chip 120, and the first packaging module 100 may also include more chips.

[0041] The second packaging module 200 may also include other chips besides the third chip 210 and the fourth chip 220. For example, the second packaging module 200 may include three or four chips.

[0042] Specifically, such as Figure 2 As shown, during the packaging process, the first wafer 340 and the second wafer 342 are first cut to obtain the first chip 110 and the second chip 120, and the third wafer 344 is cut to obtain the third chip 210. Figure 3 As shown, the third chip 210 is bonded to the fourth chip 220, which is in a wafer state. After bonding, the fourth wafer 346 is diced to obtain the second packaging module 200. Figure 4 As shown, the first chip 110 and the second chip 120 are then bonded together to obtain the first packaging module 100. The first packaging module 100 is then electrically connected to the second packaging module 200 to obtain the packaging structure.

[0043] According to some embodiments of this application, such as Figure 1 and Figure 5 As shown, the packaging structure also includes a first metal ball 302. The first side of the first metal ball 302 is connected to the first chip 110, and the second side is connected to the fourth chip 220. The first side and the second side of the first metal ball 302 are opposite sides in the thickness direction.

[0044] In this embodiment, the first chip 110 and the fourth chip 220 are connected by a first metal ball 302. The first metal ball 302 can be mass-produced as a separate component. During the bonding process of the first chip 110 and the fourth chip 220, the first metal ball 302 is simply fixed to the packaging structure. This eliminates the need to manufacture components such as copper pillars for electrical connection within the packaging structure through processes like electroplating, thus simplifying the packaging process and reducing the manufacturing difficulty of the packaging structure. Furthermore, since the first metal ball 302 can be mass-produced independently, it does not occupy the processing time of the packaging structure, accelerating the manufacturing speed of the packaging structure and improving its production efficiency. Mass-producing the first metal ball 302 can also reduce the material and process costs of the packaging structure.

[0045] According to some embodiments of this application, such as Figure 1 and Figure 5As shown, the packaging structure also includes a first dielectric layer 304 and a first wiring layer 306; the first dielectric layer 304 is disposed between the first chip 110 and the second chip 120; the first wiring layer 306 is disposed on the first dielectric layer 304 and is electrically connected to the first metal ball 302 and the first chip 110.

[0046] In this embodiment, the first dielectric layer 304 is located between the first chip 110 and the second chip 120. The first wiring layer 306 is disposed on the first dielectric layer 304. The first wiring layer 306 is electrically connected to the first metal ball 302 and the first chip 110, thereby realizing the electrical connection between the first metal ball 302 and the first chip 110, so that the first chip 110 can transmit data to the fourth chip 220 through the first metal ball 302.

[0047] Furthermore, the first wiring layer 306 is provided with pads, and the first metal ball 302 is soldered to the pads of the first wiring layer 306, thereby realizing the connection between the first wiring layer 306 and the first metal ball 302, as well as the installation and positioning of the first metal ball 302 by the first wiring layer 306.

[0048] According to some embodiments of this application, such as Figure 1 and Figure 5 As shown, the packaging structure also includes a first bump 308 and a second bump 310; the first bump 308 is disposed on the side of the first dielectric layer 304 near the second chip 120 and is electrically connected to the first wiring layer 306; the second bump 310 is disposed on the side of the second chip 120 near the first chip 110, is electrically connected to the second chip 120, and is in contact with the first bump 308.

[0049] In this embodiment, a first bump 308 is disposed on the side of the first dielectric layer 304 near the second chip 120 and electrically connected to the first wiring layer 306, thereby enabling the first bump 308 to be electrically connected to the first chip 110 through the first wiring layer 306. A second bump 310 is disposed on the side of the second chip 120 near the first chip 110, electrically connected to the second chip 120, and in contact with the first bump 308, thereby achieving bonding between the first chip 110 and the second chip 120, and thus enabling signal transmission between the first chip 110 and the second chip 120.

[0050] Furthermore, the first bump 308 and the second bump 310 can be micro-bumps or copper pillars.

[0051] Furthermore, the packaging structure also includes a fifth bump 334, which is disposed on the side of the first chip 110 near the first dielectric layer 304 and connected to the first wiring layer 306.

[0052] An adhesive film 348 is also provided on the side of the first chip 110 away from the first dielectric layer 304, which facilitates the bonding of the first chip 110 to the substrate 338 and realizes wafer reconstruction.

[0053] Furthermore, the packaging structure also includes a fourth dielectric layer 336, which is disposed between the second bump 310 and the second chip 120.

[0054] According to some embodiments of this application, such as Figure 1 and Figure 5 As shown, the packaging structure also includes a second metal ball 312, a second dielectric layer 314, a second wiring layer 316, and a third metal ball 318; the second metal ball 312 is disposed on the side of the first dielectric layer 304 near the first chip 110 and is electrically connected to the first wiring layer 306; the second dielectric layer 314 is disposed on the side of the first chip 110 away from the second chip 120; the second wiring layer 316 is disposed on the second dielectric layer 314 and is electrically connected to the second metal ball 312; the third metal ball 318 is disposed on the side of the second dielectric layer 314 away from the first chip 110 and is electrically connected to the second dielectric layer 314.

[0055] In this embodiment, the second metal ball 312 is disposed on the side of the first dielectric layer 304 near the first chip 110 and electrically connected to the first wiring layer 306, so that the second metal ball 312 is electrically connected to the first chip 110 through the first wiring layer 306. The second dielectric layer 314 is disposed on the side of the first chip 110 away from the second chip 120; the second wiring layer 316 is disposed on the second dielectric layer 314 and electrically connected to the second metal ball 312, thereby enabling the second wiring layer 316 to be electrically connected to the first chip 110. The third metal ball 318 is disposed on the side of the second dielectric layer 314 away from the first chip 110 and electrically connected to the second dielectric layer 314, so that the third metal ball 318 can be connected to the first chip 110, thereby enabling the first chip 110 to transmit data through the third metal ball 318.

[0056] Furthermore, there are multiple third metal balls 318, which are arranged in an array on the side of the second dielectric layer 314 away from the first chip 110 to serve as pins of the packaging structure.

[0057] According to some embodiments of this application, such as Figure 1 and Figure 5 As shown, at least one of the first metal ball 302, the second metal ball 312 and the third metal ball 318 is a copper ball; or at least one of the first metal ball 302, the second metal ball 312 and the third metal ball 318 is a tin ball; or at least one of the first metal ball 302, the second metal ball 312 and the third metal ball 318 includes a copper ball core and a tin layer, with the tin layer covering the copper ball core.

[0058] In this embodiment, the first metal ball 302, the second metal ball 312, or the third metal ball 318 can be a copper ball, a tin ball, or a copper-core ball. Copper and tin balls can be processed to smaller sizes, while copper-core balls are less expensive and have better conductivity than tin balls.

[0059] According to some embodiments of this application, such as Figure 1 and Figure 5 As shown, the packaging structure also includes a third dielectric layer 320 and a third wiring layer 322; the third dielectric layer 320 is disposed between the third chip 210 and the fourth chip 220; the third wiring layer 322 is disposed on the third dielectric layer 320, electrically connected to the first metal ball 302, and electrically connected to the fourth chip 220.

[0060] In this embodiment, the third dielectric layer 320 is disposed between the third chip 210 and the fourth chip 220, and the third wiring layer 322 is disposed on the third dielectric layer 320. The third wiring layer 322 is electrically connected to both the first metal ball 302 and the fourth chip 220, thereby enabling the fourth chip 220 to be electrically connected to the first chip 110 through the first metal ball 302, thus achieving bonding between the first chip 110 and the fourth chip 220.

[0061] According to some embodiments of this application, such as Figure 1 and Figure 5 As shown, the packaging structure also includes a third bump 324 and a fourth bump 326; the third bump 324 is disposed on the side of the third chip 210 near the fourth chip 220 and is electrically connected to the third chip 210; the fourth bump 326 is disposed on the side of the third dielectric layer 320 near the third chip 210, is electrically connected to the third wiring layer 322, and is in contact with the third bump 324.

[0062] In this embodiment, the fourth bump 326 is disposed on the side of the third dielectric layer 320 near the third chip 210 and electrically connected to the third wiring layer 322, so that the fourth bump 326 is electrically connected to the fourth chip 220 through the third wiring layer 322. The third bump 324 is disposed on the side of the third chip 210 near the fourth chip 220 and electrically connected to the third chip 210. The third bump 324 is in contact with the fourth bump 326, realizing the bonding between the third chip 210 and the fourth chip 220, thereby realizing the transmission of signals between the third chip 210 and the fourth chip 220.

[0063] Furthermore, the third bump 324 and the fourth bump 326 can be microbumps or copper pillars.

[0064] According to some embodiments of this application, such as Figure 1 and Figure 5As shown, the packaging structure also includes a packaging section 328, which covers the first packaging module 100 and the second packaging module 200.

[0065] In this embodiment, the encapsulation part 328 covers the first encapsulation module 100 and the second encapsulation module 200, thereby encapsulating the first encapsulation module 100 and the second encapsulation module 200. While protecting the first encapsulation module 100 and the second encapsulation module 200, it also improves the heat dissipation rate of the first encapsulation module 100 and the second encapsulation module 200, enhances the stability of the first encapsulation module 100 and the second encapsulation module 200 during operation, and extends the service life of the first encapsulation module 100 and the second encapsulation module 200.

[0066] Furthermore, the package 328 can effectively protect the active area of ​​the chip, preventing it from being bumped or damaged.

[0067] According to some embodiments of this application, such as Figure 5 As shown, the encapsulation structure also includes a first colloid 330 and a second colloid 332; the first colloid 330 is filled between the first chip 110 and the second chip 120; the second colloid 332 is filled between the third chip 210 and the fourth chip 220.

[0068] In this embodiment, the first colloid 330 is filled between the first chip 110 and the second chip 120, and the second colloid 332 is filled between the third chip 210 and the fourth chip 220, thereby improving the packaging effect between the chips and avoiding insufficient filling of the encapsulation material due to the small gap between the chips in the same packaging module.

[0069] The first colloid 330 and the second colloid 332 can be used as bottom filler adhesives.

[0070] According to some embodiments of this application, the packaging structure provided in this application can be packaged by the following packaging method.

[0071] like Figure 6 As shown, before the first metal ball 302 and the first chip 110 are bonded to the second chip 120, the pads on the substrate 338 have been prepared. The main function of the pads is to fix the position of the first metal ball 302. The fifth bump 334 has been prepared on the first chip 110. The bottom of the first chip 110 is covered with an adhesive film and is fixed to the substrate 338 with its surface facing upwards.

[0072] like Figure 7As shown, wafer-level molding is performed. After the molding compound has cured, the wafer is ground to expose the surfaces of the first metal ball 302 and the fifth bump 334. Then, a first dielectric layer 304 and a first wiring layer 306 are fabricated on the exposed surfaces. The first wiring layer 306 enables the interconnection between the first metal ball 302 and the first chip 110. Finally, the first bump 308 is fabricated through an electroplating process.

[0073] like Figure 8 As shown, the second chip 120 is bonded to the first chip 110 with its face downwards. After bonding, the first chip 110 and the second chip 120 are interconnected. Alternatively, a first colloid 330 can be filled between the first chip 110 and the second chip 120.

[0074] like Figure 9 As shown, a first metal ball 302 is arranged on the first wiring layer 306.

[0075] like Figure 10 As shown, the third chip 210 and the fourth chip 220 modules are bonded to the copper core ball. At this point, after the bonding is completed, the first chip 110, the second chip 120, the third chip 210, and the fourth chip 220 are interconnected.

[0076] like Figure 11 As shown, the entire package is encapsulated using molding compound.

[0077] like Figure 12 As shown, the package is milled to thin the back substrate of the fourth chip 220 and remove the back molding compound.

[0078] like Figure 13 As shown, the substrate 338 is first debonded and removed, then the back substrate of the first chip 110 is removed by grinding, exposing the second metal ball 312. Next, the third dielectric layer 320 and the third wiring layer 322 are fabricated, and the third metal ball 318 is arranged. If the first chip 110 can still be thinned, the back substrate and molding compound of the fourth chip 220 can be removed again by grinding until the required thickness is met. Finally, dicing is performed to cut the package into individual chips.

[0079] An electronic device according to some embodiments of this application includes a packaging structure as described in any of the above embodiments, and therefore the electronic device possesses all the beneficial effects of the packaging structure described in any of the above embodiments.

[0080] Specifically, electronic devices include mobile phones, tablets, laptops, watches, or smart wristbands.

[0081] According to some embodiments of this application, the packaging method is used to package a packaging structure as described in any of the above embodiments, such as... Figure 14 As shown, the encapsulation method includes:

[0082] Step 402: Cut the first wafer to obtain the first chip;

[0083] Step 404: Place the first chip on the substrate;

[0084] Step 406: Cut the second wafer to obtain the second chip;

[0085] Step 408: Bond the second chip to the first chip to obtain the first package module;

[0086] Step 410: Cut the third wafer to obtain the third chip;

[0087] Step 412: Bond the third chip to the fourth chip on the fourth wafer;

[0088] Step 414: Cut the fourth wafer to obtain the second packaging module;

[0089] Step 416: Arrange the first packaging module and the second packaging module in the thickness direction;

[0090] Step 418: Electrically connect the first chip and the fourth chip.

[0091] In this embodiment, the first and second wafers are first diced to obtain the first and second chips, and the third wafer is then diced to obtain the third chip. The third chip is bonded to a fourth chip in a wafer state, and after bonding, the fourth wafer is diced to obtain the second packaging module. Then, the first and second chips are bonded to obtain the first packaging module, and the first and second packaging modules are electrically connected to obtain the packaging structure.

[0092] When connecting the first and second packaging modules, the first and fourth chips located on opposite sides in the vertical direction can be connected to achieve electrical connection between them. Since the electrical connection components between the first and fourth chips can occupy the space occupied by the second and third chips during bonding, and no further electrical connection components are needed between the second and third chips, the vertical space occupied by the electrical connection components between the first and second packaging modules is reduced. This reduces the thickness of the packaging module and the vertical space occupied, contributing to a thinner and lighter packaging module.

[0093] When bonding the first packaging module, the first chip is attached to the substrate, thereby reconstructing the first wafer, so that the subsequent packaging process is carried out in the wafer state, further improving the packaging efficiency of the packaging structure.

[0094] Furthermore, the substrate is a glass carrier.

[0095] According to some embodiments of this application, before arranging the first packaging module and the second packaging module in the thickness direction, the packaging method further includes: preparing a first dielectric layer on the first chip; preparing a first wiring layer on the first dielectric layer; arranging a first metal ball on the first wiring layer; preparing a third dielectric layer on the fourth chip; preparing a third wiring layer on the third dielectric layer; and electrically connecting the first chip and the fourth chip includes connecting the third wiring layer to the first metal ball.

[0096] In this embodiment, a first dielectric layer is located between a first chip and a second chip. A first wiring layer is disposed on the first dielectric layer and electrically connected to a first metal ball and the first chip, thereby achieving an electrical connection between the first metal ball and the first chip. A third dielectric layer is disposed between a third chip and a fourth chip. A third wiring layer is disposed on the third dielectric layer and is electrically connected to both the first metal ball and the fourth chip, thereby enabling the fourth chip to be electrically connected to the first chip through the first metal ball, achieving bonding between the first chip and the fourth chip, and enabling the first chip to transmit data to the fourth chip through the first metal ball.

[0097] According to some embodiments of this application, before bonding the second chip to the first chip, the packaging method further includes: arranging a second metal ball on a substrate, wherein the two metal balls are electrically connected to a first wiring layer.

[0098] After electrically connecting the first chip and the fourth chip, the packaging method further includes: packaging the first packaging module and the second packaging module; separating the substrate from the first packaging module; preparing a second dielectric layer on the first packaging module; preparing a second wiring layer on the second dielectric layer, the second wiring layer being electrically connected to a second metal ball; arranging a third metal ball on the second dielectric layer, the third metal ball being electrically connected to the second wiring layer; grinding the packaged first packaging module and the second packaging module; and cutting the packaged first packaging module and the second packaging module to obtain a packaging structure.

[0099] In this embodiment, a second metal ball is disposed on the substrate and electrically connected to the first wiring layer, allowing the second metal ball to be embedded within the packaged structure. The second metal ball is disposed on the side of the first dielectric layer closest to the first chip and electrically connected to the first wiring layer, enabling the second metal ball to be electrically connected to the first chip via the first wiring layer. The second dielectric layer is disposed on the side of the first chip furthest from the second chip; the second wiring layer is disposed on the second dielectric layer and electrically connected to the second metal ball, thereby enabling the second wiring layer to be electrically connected to the first chip. A third metal ball is disposed on the side of the second dielectric layer furthest from the first chip and electrically connected to the second dielectric layer, enabling the third metal ball to be connected to the first chip, thereby allowing the first chip to transmit data via the third metal ball.

[0100] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0101] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A packaging structure, characterized in that, include: A first packaging module, comprising a first chip and a second chip, wherein the first chip and the second chip are arranged along the thickness direction of the first chip, and the first chip and the second chip are electrically connected. A second packaging module is arranged along the thickness direction with the first packaging module. The second packaging module includes a third chip and a fourth chip, which are arranged along the thickness direction and are electrically connected. The fourth chip is electrically connected to the first chip; A first metal ball, with a first side connected to the first chip and a second side connected to the fourth chip, the first chip and the fourth chip are connected through the first metal ball to realize the electrical connection between the first packaging module and the second packaging module; Wherein, the first side and the second side of the first metal ball are two opposite sides in the thickness direction.

2. The packaging structure according to claim 1, characterized in that, Also includes: A first dielectric layer is disposed between the first chip and the second chip; A first wiring layer is disposed on the first dielectric layer and is electrically connected to the first metal ball and the first chip.

3. The packaging structure according to claim 2, characterized in that, Also includes: The first bump is disposed on the side of the first dielectric layer near the second chip and is electrically connected to the first wiring layer; The second bump is disposed on the side of the second chip close to the first chip, is electrically connected to the second chip, and is in contact with the first bump.

4. The packaging structure according to claim 2, characterized in that, Also includes: The second metal ball is disposed on the side of the first dielectric layer near the first chip and is electrically connected to the first wiring layer; A second dielectric layer is disposed on the side of the first chip away from the second chip; The second wiring layer is disposed on the second dielectric layer and electrically connected to the second metal ball; A third metal ball is disposed on the side of the second dielectric layer away from the first chip and is electrically connected to the second dielectric layer.

5. The packaging structure according to claim 4, characterized in that, At least one of the first metal sphere, the second metal sphere, and the third metal sphere is a copper sphere; or At least one of the first metal ball, the second metal ball, and the third metal ball is a tin ball; or At least one of the first metal ball, the second metal ball, and the third metal ball includes a copper core and a tin layer, wherein the tin layer covers the copper core.

6. The packaging structure according to claim 1, characterized in that, Also includes: A third dielectric layer is disposed between the third chip and the fourth chip; The third wiring layer is disposed on the third dielectric layer and is electrically connected to the first metal ball and the fourth chip.

7. The packaging structure according to claim 6, characterized in that, Also includes: The third bump is disposed on the side of the third chip near the fourth chip and is electrically connected to the third chip; The fourth bump is disposed on the side of the third dielectric layer near the third chip, electrically connected to the third wiring layer, and in contact with the third bump.

8. The packaging structure according to any one of claims 1 to 7, characterized in that, Also includes: The packaging section covers the first packaging module and the second packaging module.

9. The packaging structure according to any one of claims 1 to 7, characterized in that, Also includes: A first colloid is filled between the first chip and the second chip; The second colloid is filled between the third chip and the fourth chip.

10. An electronic device, characterized in that, The packaging structure includes any one of claims 1 to 9.

11. A packaging method, characterized in that, The encapsulation method is used to encapsulate the encapsulation structure as described in any one of claims 1 to 9, the encapsulation method comprising: The first wafer is diced to obtain the first chip; The first chip is placed on the substrate; The second wafer is cut to obtain the second chip; The second chip is bonded to the first chip to obtain the first package module; The third wafer is diced to obtain the third chip; The third chip is bonded to the fourth chip on the fourth wafer; The fourth wafer is cut to obtain the second packaging module; The first packaging module and the second packaging module are arranged along the thickness direction; The first chip is electrically connected to the fourth chip; Before arranging the first packaging module and the second packaging module along the thickness direction, the packaging method further includes: A first dielectric layer is fabricated on the first chip; A first wiring layer is fabricated on the first dielectric layer; A first metal ball is arranged on the first wiring layer; A third dielectric layer is fabricated on the fourth chip; A third wiring layer is fabricated on the third dielectric layer; The step of electrically connecting the first chip and the fourth chip includes connecting the third wiring layer to the first metal ball.

12. The packaging method according to claim 11, characterized in that, Before bonding the second chip to the first chip, the packaging method further includes: A second metal ball is disposed on the substrate, and the second metal ball is electrically connected to the first wiring layer; After electrically connecting the first chip and the fourth chip, the packaging method further includes: The first packaging module and the second packaging module are packaged together; Separate the substrate from the first packaging module; A second dielectric layer is fabricated on the first packaging module; A second wiring layer is fabricated on the second dielectric layer, and the second wiring layer is electrically connected to the second metal ball; A third metal ball is disposed on the second dielectric layer, and the third metal ball is electrically connected to the second wiring layer; The first packaging module and the second packaging module after grinding and packaging; The first and second packaging modules are cut and sealed to obtain the packaging structure.

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