A multi-channel adaptive ARINC818 multimode transceiver SiP chip

Abstract

The application discloses a multi-channel adaptive ARINC818 multimode transceiving SiP chip, wherein if an ARINC818 port transceiving module receives an ARINC 818 data frame, the ARINC818 port transceiving module sends the ARINC 818 data frame to a video format conversion functional module in the form of an RGB parallel video stream after unpacking, the video format conversion functional module drives the RGB parallel video stream to be transmitted on an AXI bus, a pixel resolution of an AXI4-Stream data stream is read by an adaptive functional module, timing parameters of the video stream and a dot frequency of a video clock are configured according to the resolution, video data storage control module reads the AXI4-Stream data stream and stores the AXI4-Stream data stream in a DDR3, the video format conversion functional module sends a data request to the video data storage control module, then reads the AXI4-Stream data stream from the DDR3, reorganizes the AXI4-Stream data stream into a required video format and outputs the AXI4-Stream data stream to outside of the chip.

Description

Technical Field

[0001] This invention belongs to the field of chip design technology and relates to a multi-channel adaptive ARINC818 multimode transceiver SiP chip. Background Technology

[0002] The ARINC818 protocol bus, or Avionics Digital Video Bus (ADVB), is the core protocol in airborne video transmission networks. Compared to traditional video transmission solutions, it features high bandwidth, low latency, long-distance transmission, and high anti-interference capabilities. This protocol is widely used in numerous military and civilian avionics fields both domestically and internationally. In my country's military and civilian aircraft market, ARINC818 transceivers are core components of video processors.

[0003] Currently, ARINC818 products on the market are mainly FPGA (Field Programmable Gate Array) boards implementing the ARINC818 protocol. This product form is currently constrained by two factors. First, in recent years, my country's semiconductor industry chain and supply chain have been severely suppressed by foreign countries, and since FPGAs, as the protocol carrier, use chips supplied by foreign vendors, the cost and channel difficulties are self-evident. Second, due to factors such as area and power consumption, the application scenarios of FPGA boards are also relatively limited. Therefore, providing an ARINC818 transceiver integrated SiP (System in a Package) chip can solve the current ARINC818 board miniaturization design needs, while also realizing the localization and independent control of ARINC818 products, as well as the technological research and development and market expansion of SiP type products in the aerospace field. Summary of the Invention

[0004] The purpose of this invention is to provide a multi-channel adaptive ARINC818 multi-mode transceiver SiP chip to enhance the distribution and processing capabilities of airborne video signals in the field of avionics, improve the integration level of airborne electronic equipment, and at the same time improve the localization level of airborne video transmission networks. It is the first video processing SiP chip in the aviation field.

[0005] The objective of this invention is achieved through the following technical solution:

[0006] A multi-channel adaptive ARINC818 multimode transceiver SiP chip includes a video processing module, DDR3, FLASH, and DVI decoding module. The video processing module includes an ARINC818 port transceiver module, a video format conversion module, an adaptive function module, and a video data storage control module.

[0007] If the ARINC818 port transceiver module receives an ARINC 818 data frame, it unpacks it and sends it to the video format conversion module in RGB parallel video stream format. The video format conversion module drives the RGB parallel video stream to be transmitted on the AXI bus. The adaptive function module reads the pixel resolution of the AXI4-Stream data stream from the AXI bus and configures the timing parameters of the output video stream and the frequency of the output video clock according to the resolution. The video data storage control module reads the AXI4-Stream data stream from the AXI bus and stores it in DDR3. The video format conversion module sends a data request to the video data storage control module according to the configuration of the adaptive function module, and then reads the AXI4-Stream data stream from DDR3 through the AXI bus to reassemble it into the required video format and output it outside the chip.

[0008] Preferably, the video format conversion function module includes an AXI driver unit and a video driver unit;

[0009] In the AXI driver unit, the video receiver identifies the valid DE signal in the RGB parallel video stream, acquires the valid video pixel buffer, and the AXI4-Stream driver in the AXI driver unit drives the valid video pixels in the buffer to the AXI bus for subsequent processing.

[0010] After the bus receiver in the video driver unit sends a data request to the video direct storage module, it obtains a line of valid video pixels from DDR3 through the AXI bus. After caching the valid video pixels, the video driver in the video driver unit module drives the valid video pixels to output one of the following formats: TMDS, LVDS, MIPI, or RGB, according to the configured video timing.

[0011] Preferably, the adaptive video processing function module includes a video resolution detection unit, a video timing reconfiguration unit, and a PLL clock dynamic reconfiguration unit;

[0012] The video resolution detection unit module obtains the line and field resolution of the current video stream by parsing Vsync, Hsync, and DE in the AXI4-Stream data stream and shares it with the video timing reconfiguration unit and the PLL clock dynamic reconfiguration unit.

[0013] When the video timing reconfiguration unit is working, it searches the configuration table for video timing parameters that match the changed video resolution, uses the new timing parameters to configure the video driver unit and video data storage control module in the video format conversion function module, and resets the video processing module until the video timing reconfiguration is complete.

[0014] When the PLL clock dynamic reconfiguration unit is working, it looks up the clock configuration parameters that match the changed video resolution in the configuration table, and reconfigures the PLL clock division ratio through the APB bus, so that the PLL generates a video pixel clock under the VESA timing corresponding to the resolution for use by the video format conversion function module.

[0015] Preferably, after the video timing reconfiguration unit and the PLL clock dynamic reconfiguration unit detect a change in the video stream resolution, they will only operate if the changed resolution conforms to the video format supported by the configuration table.

[0016] Preferably, the video data storage control module includes a video direct storage control unit, a storage routing unit, and a DD3 controller;

[0017] The video direct storage control unit receives AXI4-Stream video stream data, converts it into AXI4 data, and routes it through the storage routing unit. Then, the DDR3 controller stores the video data in the off-chip DDR3 memory. The video direct storage control unit sends a data retrieval request through the storage routing unit, retrieves the video data from the DDR3 memory, parses the AXI4 bus data, and drives it to the AXI4-Stream bus for transmission to the video format conversion module for output.

[0018] Preferably, the storage routing unit receives video data read and write requests from the preceding video direct storage control module, collects read and write addresses and data, performs routing operations based on the arbitration result of the read and write arbitrator, and completes the read and write operations under the drive of the interface driver.

[0019] Preferably, if the ARINC818 port transceiver module receives the parallel video stream in RGB format output by the DVI decoding module, it converts it into ARINC 818 data frames and sends them out.

[0020] The beneficial effects of this invention are as follows:

[0021] 1. Compared with the traditional implementation using FPGA boards, this invention significantly reduces the size and power consumption of airborne video transceiver modules based on the ARINC818 protocol, and improves the integration level of airborne electronic equipment; at the same time, it can also reduce product costs to a certain extent during the mass production stage.

[0022] 2. Compared with the conventional ARINC818 protocol video signal transceiver design, this method designs multi-mode video signal interfaces such as TMDS, LVDS, MIPI, and RGB, which can realize adaptive conversion of various video formats and greatly enhance the versatility of transceiver chips. Attached Figure Description

[0023] Figure 1This is a schematic diagram of the overall structure of the multi-channel adaptive ARINC818 multimode transceiver SiP chip.

[0024] Figure 2 This is a schematic diagram of the video processing module in the multi-channel adaptive ARINC818 multimode transceiver SiP chip.

[0025] Figure 3 This is a structural diagram of the video format conversion function module.

[0026] Figure 4 This is a structural diagram of the adaptive function module.

[0027] Figure 5 This is a schematic diagram of the video data storage and control module.

[0028] Figure 6 This is a schematic diagram of the storage routing unit. Detailed Implementation

[0029] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0030] See Figure 1 , Figure 2 As shown in this embodiment, a multi-channel adaptive ARINC818 multimode transceiver SiP chip includes a video processing module, DDR3, FLASH, and a DVI decoding module. The video processing module supports receiving two DVI video streams, decoding them into two high-speed signals conforming to the ARINC818-2 protocol standard as data to be transmitted; it also supports receiving two high-speed signals conforming to the ARINC818-2 protocol standard and converting them into two RGB video streams as data to be displayed.

[0031] See Figure 2 As shown, the video processing module includes an ARINC818 port transceiver module, a video format conversion function module, an adaptive function module, and a video data storage control module.

[0032] If the ARINC818 port transceiver module receives an RGB parallel video stream output from the DVI decoding module, it converts it into ARINC 818 data frames and sends them out. If it receives an ARINC 818 data frame, it unpacks it and sends it to the video format conversion module in RGB parallel video stream format. The video format conversion module drives the RGB parallel video stream to be transmitted on the AXI bus. The adaptive function module reads the pixel resolution of the AXI4-Stream data stream from the AXI bus and configures the timing parameters (including horizontal / vertical sync width, front and back shoulders, etc.) and the frequency of the output video stream according to the resolution. The video data storage control module reads the AXI4-Stream data stream from the AXI bus and stores it in DDR3. The video format conversion module sends a data request to the video data storage control module according to the configuration of the adaptive function module, and then reads the AXI4-Stream data stream from DDR3 through the AXI bus to reassemble it into the required video format and output it outside the chip.

[0033] See Figure 3 As shown, since the video processing module uses the AXI bus for video stream data transmission, the video format conversion module includes an AXI driver unit and a video driver unit.

[0034] The AXI driver unit converts the RGB parallel video stream parsed by the ARINC818 port transceiver module into an AXI4-Stream data stream. In the AXI driver unit, the video receiver identifies the valid DE signals in the RGB parallel video stream, acquires valid video pixels, and buffers them. The AXI4-Stream driver in the AXI driver unit then drives the buffered valid video pixels onto the AXI bus for further processing.

[0035] The video driver unit converts the AXI4-Stream data stream into a multi-mode video stream signal conforming to VESA timing, in TMDS, LVDS, MIPI, or RGB formats. In the video driver unit, after the bus receiver sends a data request to the video direct storage module, it retrieves a line of valid video pixels from DDR3 via the AXI bus. After buffering the valid video pixels, the video driver in the video driver unit module drives the valid video pixels to one of the TMDS, LVDS, MIPI, or RGB formats for output according to the configured video timing.

[0036] See Figure 4 As shown, the adaptive video processing function module consists of three parts: a video resolution detection unit, a video timing reconfiguration unit, and a PLL clock dynamic reconfiguration unit.

[0037] The video resolution detection unit module obtains the line and field resolution of the current video stream by parsing Vsync, Hsync, and DE in the AXI4-Stream data stream and shares the information with the video timing reconfiguration unit and the PLL clock dynamic reconfiguration unit.

[0038] After the video timing reconfiguration unit and the PLL clock dynamic reconfiguration unit detect changes in video stream resolution, they will only operate if the changed resolution matches the video format supported by the configuration table. This control mechanism effectively resists receiver link interruptions caused by brief external video noise. The resolutions supported by the configuration table are shown in Table 1:

[0039] Table 1

[0040]

[0041] When the video timing reconfiguration unit is working, it searches the configuration table for video timing parameters that match the changed video resolution, and uses the new timing parameters (line / field synchronization width, front shoulder, back shoulder, line resolution and field resolution) to configure the video driver unit and video data storage control module in the video format conversion function module. At the same time, it resets the video processing module until the video timing reconfiguration is complete.

[0042] When the PLL clock dynamic reconfiguration unit is working, it looks up the clock configuration parameters that match the changed video resolution in the configuration table, and reconfigures the PLL clock division ratio through the APB bus so that the PLL generates a video pixel clock under the VESA timing corresponding to the resolution for use by the video driver unit.

[0043] See Figure 5 The video data storage control module shown mainly consists of a video direct storage control unit, a storage routing unit, and a DD3 controller.

[0044] The video direct storage control unit receives AXI4-Stream video stream data, converts it into AXI4 data, routes it through the storage routing unit, and then the DDR3 controller stores the video data in the off-chip DDR3 memory. The video direct storage control unit sends a data retrieval request through the storage routing unit, retrieves the video data from the DDR3 memory, parses the AXI4 bus data, drives it to the AXI4-Stream bus, and transmits it to the video driver unit for output.

[0045] The storage routing unit can route read and write data from multiple video streams. The routing of multi-channel read and write operations is independent and does not interfere with each other, improving video data transmission efficiency and ensuring video stream continuity. The storage routing unit receives video data read and write requests from the preceding video direct storage control module, collects its read and write addresses and data, performs routing operations based on the arbitration result of the read and write arbitrator, and completes the read and write operations under the drive of the interface driver. The structure of the storage routing unit is as follows: Figure 6 As shown.

[0046] It is understood that those skilled in the art can make equivalent substitutions or modifications to the technical solution and inventive concept of the present invention, and all such substitutions or modifications should fall within the protection scope of the appended claims.

Claims

1. A multi-channel adaptive ARINC818 multimode transceiver SiP chip, comprising a video processing module, two DDR3 modules, one Flash memory module, and two DVI decoding modules, wherein the video processing module includes an ARINC818 port transceiver module, a video format conversion module, an adaptive function module, and a video data storage control module, characterized in that: If the ARINC818 port transceiver module receives an ARINC 818 data frame, it unpacks it and sends it to the video format conversion module in RGB parallel video stream format. The video format conversion module drives the RGB parallel video stream to be transmitted on the AXI bus. The adaptive function module reads the pixel resolution of the AXI4-Stream data stream from the AXI bus and configures the timing parameters of the output video stream and the frequency of the output video clock according to the resolution. The video data storage control module reads the AXI4-Stream data stream from the AXI bus and stores it in DDR3. The video format conversion module sends a data request to the video data storage control module according to the configuration of the adaptive function module, and then reads the AXI4-Stream data stream from DDR3 through the AXI bus to reassemble it into the required video format and output it outside the chip. If the ARINC818 port transceiver module receives an RGB format parallel video stream decoded and output by the DVI decoding module, it converts it into an ARINC 818 data frame and sends it out. The video format conversion module includes an AXI driver unit and a video driver unit. In the AXI driver unit, the video receiver identifies the valid DE signal in the RGB parallel video stream, acquires the valid video pixel buffer, and the AXI4-Stream driver in the AXI driver unit drives the valid video pixels in the buffer to the AXI bus for subsequent processing. After the bus receiver in the video driver unit sends a data request to the video direct storage module, it obtains a line of valid video pixels from DDR3 through the AXI bus. After caching the valid video pixels, the video driver in the video driver unit module drives the valid video pixels to output one of the following formats: TMDS, LVDS, MIPI, or RGB, according to the configured video timing. The adaptive video processing module includes a video resolution detection unit, a video timing reconfiguration unit, and a PLL clock dynamic reconfiguration unit. The video resolution detection unit module obtains the line and field resolution of the current video stream by parsing Vsync, Hsync, and DE in the AXI4-Stream data stream and shares it with the video timing reconfiguration unit and the PLL clock dynamic reconfiguration unit. When the video timing reconfiguration unit is working, it searches the configuration table for video timing parameters that match the changed video resolution, uses the new timing parameters to configure the video driver unit and video data storage control module in the video format conversion function module, and resets the video processing module until the video timing reconfiguration is complete. When the PLL clock dynamic reconfiguration unit is working, it looks up the clock configuration parameters that match the changed video resolution in the configuration table, and reconfigures the PLL clock division ratio through the APB bus, so that the PLL generates a video pixel clock under the VESA timing corresponding to the resolution for use by the video format conversion function module; The video data storage control module includes a video direct storage control unit, a storage routing unit, and a DD3 controller; The video direct storage control unit receives AXI4-Stream video stream data, converts it into AXI4 data, and routes it through the storage routing unit. Then, the DDR3 controller stores the video data in the off-chip DDR3 memory. The video direct storage control unit sends a data retrieval request through the storage routing unit to retrieve video data from the DDR3 memory, parses the AXI4 bus data, and drives it to the AXI4-Stream bus for transmission to the video format conversion module for output. The storage routing unit receives video data read and write requests from the previous-stage video direct storage control module, collects read and write addresses and data, performs routing operations based on the arbitration result of the read and write arbitrator, and completes the read and write operations under the drive of the interface driver.

2. The multi-channel adaptive ARINC818 multimode transceiver SiP chip according to claim 1, characterized in that... After the video timing reconfiguration unit and the PLL clock dynamic reconfiguration unit detect changes in the video stream resolution, they will only operate if the changed resolution matches the video format supported by the configuration table.

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