A cpu post-silicon verification system and method

Abstract

The application provides a CPU post-silicon verification system and method, and relates to the technical field of post-silicon verification. The CPU post-silicon verification system comprises an editable CPU simulation component, an interposer, a socket and a verification platform, and the editable CPU simulation component, the interposer, the socket and the verification platform are electrically connected in sequence; wherein the interposer is used for mapping the signals of the editable CPU simulation component into preset CPU pin definitions; the editable CPU simulation component is used for performing read-write operations on the verification platform, and when the read-write operations are successful, it is determined that the verification platform is in a non-fault state. The CPU post-silicon verification system and method provided by the application have the advantage that the principle of the verification platform can be verified.

Description

Technical Field

[0001] This application relates to the field of post-silicon verification technology, and more specifically, to a CPU post-silicon verification system and method. Background Technology

[0002] Commercial server CPUs have high integration levels and are very difficult to design. Post-silicon verification of server CPUs requires a dedicated verification platform.

[0003] Because the pin definitions often differ between generations of CPUs, a corresponding verification platform lacks available CPUs before a new CPU is manufactured. This makes it impossible to 100% confirm the correctness of the verification platform's schematic. Therefore, when a new CPU is first tested on a new verification platform, if it fails to power on, it's impossible to determine whether the failure is due to a defect in the CPU or the verification platform. Thus, how to test the schematics of a new verification platform is a technical problem that needs to be solved by those skilled in the art.

[0004] In summary, existing technologies have the problem of being unable to verify the principles of the verification platform. Summary of the Invention

[0005] The purpose of this application is to provide a CPU post-silicon verification system and method to solve the problem in the prior art that the principle of the verification platform cannot be verified.

[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows:

[0007] On one hand, embodiments of this application provide a CPU post-silicon verification system, which includes a programmable CPU emulation component, an inserter, a socket, and a verification platform, wherein the programmable CPU emulation component, the inserter, the socket, and the verification platform are electrically connected in sequence; wherein,

[0008] The inserter is used to map the signals of the editable CPU emulation component to preset CPU pin definitions;

[0009] The editable CPU simulation component is used to perform read and write operations on the verification platform, and when the read and write operations are successful, the verification platform is determined to be in a fault-free state.

[0010] Optionally, the editable CPU emulation component includes an FPGA, a PCB board, and a communication interface. Both the FPGA and the communication interface are mounted on the PCB board, and the FPGA is communicatively connected to the communication interface. The PCB board is also electrically connected to the inserter.

[0011] The communication interface is used to perform firmware upgrades or issue commands to the FPGA.

[0012] Optionally, the communication interface includes a JTAG interface, a USB Type-C interface, a USB Type-B interface, and / or a MicroUSB interface; wherein,

[0013] The JTAG interface is used for firmware upgrades of the FPGA;

[0014] The USB Type-C interface, the USB Type-B interface, and the Micro USB interface are used to send instructions to the FPGA.

[0015] Optionally, the CPU post-silicon verification system further includes a board-to-board connector, with its two ends connected to the PCB board and the inserter, respectively.

[0016] Optionally, both the FPGA and the communication interface are soldered to the PCB board.

[0017] Optionally, the verification platform includes a main body and multiple functional modules, wherein the main body and the multiple functional modules are electrically connected; wherein,

[0018] The editable CPU simulation component is used to perform read and write operations on each of the functional modules, and when the read and write operations of each functional module are successful, the verification platform is determined to be in a fault-free state.

[0019] Optionally, the functional modules include programmable logic devices, I / O devices, DDR, and PCIe devices. The programmable CPU emulation component is used to issue test commands to different functional modules through I3C, I2C, SPI, UART, JTAG, TPIU, GPIO, DDR, and PCIe signals.

[0020] On the other hand, this application embodiment also provides a CPU post-silicon verification method, applied to the above-mentioned CPU post-silicon verification system, the method comprising:

[0021] The editable CPU emulation component is refreshed and firmware is burned.

[0022] The verification platform is read and written using an editable CPU emulation component;

[0023] When the read / write operation is successful, the verification platform is determined to be in a fault-free state.

[0024] When a read / write operation fails, the verification platform is determined to be in a fault state, and the firmware and / or the pin definitions of the editable CPU emulation component are modified until the read / write operation succeeds.

[0025] Optionally, after a successful read / write operation, the method includes:

[0026] Obtain the output signal waveform of the editable CPU simulation component, or obtain the input signal waveform of the verification platform;

[0027] When the signal waveform meets the preset waveform quality, the signal integrity of the verification platform is determined to be qualified.

[0028] When the signal waveform does not meet the preset waveform quality, modify the firmware and / or modify the pin drive capability of the editable CPU emulation component and / or modify the resistance parameters on the verification platform until the signal waveform meets the preset waveform quality.

[0029] Optionally, when a read / write operation fails, the method further includes:

[0030] When a read / write operation succeeds after modifying the firmware and / or the pin definitions of the editable CPU emulation component, the reason for the read / write operation failure is recorded.

[0031] Compared with the prior art, this application has the following advantages:

[0032] This application provides a CPU post-silicon verification system and method. The CPU post-silicon verification system includes a programmable CPU emulation component, an inserter, a socket, and a verification platform, which are electrically connected sequentially. The inserter maps the signals of the programmable CPU emulation component to preset CPU pin definitions. The programmable CPU emulation component performs read and write operations on the verification platform, and determines the verification platform to be in a fault-free state when the read and write operations are successful. Since this application can simulate real read and write operations of the CPU on the verification platform using the programmable CPU emulation component, it can detect whether the verification platform is faulty. Furthermore, the programmable CPU emulation component can guarantee accuracy; therefore, when a read or write operation fails, it can be clearly determined that the verification platform is faulty.

[0033] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0034] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a schematic diagram of the CPU post-silicon verification system provided in an embodiment of this application.

[0036] Figure 2 An exemplary flowchart of the CPU post-silicon verification method provided in this application embodiment.

[0037] Figure 3 This is another exemplary flowchart of the CPU post-silicon verification method provided in the embodiments of this application.

[0038] In the picture:

[0039] 100-CPU post-silicon verification system; 110-Editable CPU simulation component; 111-FPGA; 112-PCB board; 113-Communication interface; 120-Insertion device; 130-Socket; 140-Verification platform; 141-Main body; 142-Functional module; 150-Board to board connector. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0041] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0042] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0043] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0044] In the description of this application, it should be noted that the terms "upper", "lower", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship that the product of this application is usually placed in. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0045] In the description of this application, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0046] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0047] As described in the background section, post-silicon verification of server CPUs requires a dedicated verification platform. Furthermore, the pin definitions often differ between CPU generations, necessitating a one-to-one correspondence between each generation and its corresponding verification platform. For example, the first-generation CPU corresponds to a specific verification platform, as do the second and third-generation CPUs. This platform allows verification of faulty first-generation, second-generation, and third-generation CPUs. However, due to the different pin definitions, it is impossible to verify the faultiness of a second-generation CPU using the same platform, and similarly, the same platform cannot be used to verify the faultiness of a third-generation CPU.

[0048] Based on this implementation, when a new CPU is manufactured, a new verification platform needs to be built simultaneously to verify it. For example, when manufacturing a fourth-generation CPU, a verification platform for the fourth-generation CPU also needs to be built. However, since the schematic diagram of the verification platform cannot be guaranteed to be correct when it is built, the accuracy of the verification result cannot be guaranteed regardless of whether the verification result is faulty or not. For example, when using the verification platform to verify a fourth-generation CPU, the CPU fails to power on. In this case, it cannot be determined whether the CPU or the verification platform is defective, so it cannot be determined whether the CPU is faulty. Similarly, if a CPU powers on, it could also be due to a defect in the verification platform, causing all CPUs to power on during testing.

[0049] Therefore, to solve this problem, it is necessary to first verify the principle of the new verification platform to ensure its correctness. Currently, established server chip companies generally use CPU adapter cards to adapt their previous-generation CPUs to the new generation's interface definition. This allows for the verification of the new CPU verification platform before the new generation CPU is fabricated and returned to the chip, completing the principle verification of the new platform and ensuring it has no fundamental problems. This enables it to be quickly powered on after the new CPU is fabricated and returned to the chip. If it fails to power on, this also speeds up the identification and analysis of the problem. For example, a CPU adapter card can be installed on a new verification platform. Then, the third-generation CPU can be verified on the platform to determine if it is faulty. At this time, a third-generation CPU that has been verified to be without defects can be placed on the verification platform, and the verification result can be determined. At the same time, a third-generation CPU that has been verified to be defective can also be placed on the verification platform, and the verification structure can be determined. When both verification results match the preset verification results, it means that the principle of the verification platform is correct, and it can be used to verify the fourth-generation CPU. When at least one of the two verification results does not match the preset verification result, it means that the principle of the verification platform may be faulty, and the verification platform needs to be repaired.

[0050] However, the above-mentioned methods for testing new verification platforms are not applicable to startups because startups do not have CPUs available before the first-generation CPUs are taped out. In other words, the CPUs produced by startups are first-generation CPUs, and they do not have previous-generation CPUs available. Therefore, they cannot use the above methods to verify new verification platforms.

[0051] In view of this, this application provides a CPU post-silicon verification system that uses an editable CPU simulation component to perform fault verification on the verification platform.

[0052] The CPU post-silicon verification system provided in this application is illustrated below:

[0053] As an optional implementation, please refer to Figure 1 The CPU post-silicon verification system 100 includes an editable CPU emulation component 110, an inserter 120, a socket 130, and a verification platform 140, which are electrically connected in sequence. The inserter 120 is used to map the signals of the editable CPU emulation component 110 to preset CPU pin definitions. The editable CPU emulation component 110 is used to perform read and write operations on the verification platform 140, and when the read and write operations are successful, it is determined that the verification platform 140 is in a fault-free state.

[0054] This application utilizes an editable CPU simulation component 110 to simulate a CPU performing real read and write operations on a verification platform 140, thereby enabling the detection of whether the verification platform 140 is faulty. Furthermore, the editable CPU simulation component 110 can guarantee accuracy, so when a read or write operation fails, it can be clearly determined that the verification platform 140 is faulty.

[0055] It should be noted that the fault detection of the verification platform 140 described in this application includes verifying the correctness of the circuit function and the integrity of the signals of the verification platform 140. Furthermore, the read / write operations described in this application include both read and write operations.

[0056] In one implementation, the programmable CPU emulation component 110 includes an FPGA 111 (Field Programmable Gate Array), a PCB board 112 (Printed Circuit Board), and a communication interface 113. Both the FPGA 111 and the communication interface 113 are mounted on the PCB board 112. For example, both the FPGA 111 and the communication interface 113 are soldered onto the PCB board 112, and the FPGA 111 and the communication interface 113 are communicatively connected. The PCB board 112 is also electrically connected to the inserter 120. The communication interface 113 is used to perform firmware upgrades or issue commands to the FPGA 111.

[0057] The communication interface 113 includes a JTAG interface, a USB Type-C interface, a USB Type-B interface, and / or a MicroUSB interface. The JTAG interface is used for firmware upgrades of the FPGA111; the USB Type-C, USB Type-B, and MicroUSB interfaces are used for issuing commands to the FPGA111. The JTAG interface (Joint Test Action Group) is an international standard test protocol (IEEE 1149.1 compliant), primarily used for internal chip testing. Most advanced devices now support the JTAG protocol, such as DSPs and FPGA111 devices. A standard JTAG interface has four lines: TMS, TCK, TDI, and TDO, representing mode selection, clock, data input, and data output, respectively. USB Type-C is a USB interface form factor standard, smaller than both Type-A and Type-B, and can be used with both PCs (master devices) and external devices (slave devices, such as mobile phones).

[0058] Of the above interfaces, one or more can be set. For example, a JTAG interface and a USB Type-C interface can be set on PCB board 112, or a JTAG interface and a USB Type-B interface can be set, or all four interfaces can be set on PCB board 112 at the same time. No limitation is made here.

[0059] In one implementation, the CPU post-silicon verification system 100 further includes a board-to-board connector 150, with its two ends connected to a PCB board 112 and an inserter 120, respectively.

[0060] like Figure 1 As shown, the CPU post-silicon verification system 100 includes two board-to-board connectors 150. The FPGA 111 is soldered onto the PCB, and its pin signals are connected to an inserter 120 via the board-to-board connectors 150. The inserter 120 is ultimately assembled in a socket 130. The inserter 120 is a signal conversion PCB that maps the signals of the FPGA 111 to the pin definitions of the CPU. These pin definitions include, but are not limited to, I3C, I2C, SPI, UART, JTAG, TPIU, GPIO, DDR, and PCIe signals.

[0061] The firmware of the FPGA111 can be upgraded via the JTAG interface, and commands can be sent to the FPGA111 via the USB Type-C interface, TypcB interface, or Micro USB interface to adjust the driving capabilities of signals such as I3C, I2C, SPI, UART, JTAG, TPIU, GPIO, DDR, and PCIe, as well as to issue different test codes to achieve the required signal integrity.

[0062] In one implementation, the verification platform 140 includes a main body 141 and multiple functional modules 142, which are electrically connected. A programmable CPU emulation component 110 performs read and write operations on each functional module 142, and determines that the verification platform 140 is in a fault-free state when all read and write operations on each functional module 142 are successful. Furthermore, the functional modules 142 include programmable logic devices, I / O devices, DDR, and PCIe devices. The programmable CPU emulation component 110 issues test commands to different functional modules 142 via I3C, I2C, SPI, UART, JTAG, TPIU, GPIO, DDR, and PCIe signals to determine whether the verification platform 140 is faulty.

[0063] Based on the above implementation, this application also provides a CPU post-silicon verification method, applied to the aforementioned CPU post-silicon verification system. Please refer to [link to relevant documentation]. Figure 2 The method includes:

[0064] S102 refreshes the editable CPU emulation component and burns the firmware.

[0065] S104 utilizes an editable CPU emulation component to perform read and write operations on the verification platform.

[0066] S106. When the read / write operation is successful, the verification platform is determined to be in a fault-free state.

[0067] S108: When a read / write operation fails, the verification platform is determined to be in a fault state, and the firmware and / or the pin definitions of the editable CPU emulation component are modified until the read / write operation succeeds.

[0068] Furthermore, the method also includes the following when read / write operations fail:

[0069] When a read / write operation succeeds after modifying the firmware and / or the pin definitions of the editable CPU emulation component, the reason for any failure is recorded. Recording the reason for failure allows users to quickly identify the problem with the verification platform and thus quickly adjust that type of verification platform.

[0070] Furthermore, after successful read / write operations, signal integrity testing is also required. Please refer to [link / reference needed] for further information. Figure 3 The method includes:

[0071] S, obtain the output signal waveform of the editable CPU simulation component, or obtain the input signal waveform of the verification platform.

[0072] S112, when the signal waveform meets the preset waveform quality, the signal integrity of the verification platform is determined to be qualified.

[0073] S114, when the signal waveform does not meet the preset waveform quality, modify the firmware and / or modify the pin drive capability of the editable CPU emulation component and / or modify the resistance parameters on the verification platform until the signal waveform meets the preset waveform quality.

[0074] The following example uses I2C bus verification. Before verification begins, the FPGA needs to be flashed with the firmware of the I2C module, enabling the FPGA to read and write various I2C devices on the MB, such as... Figure 1 The I / O devices shown, such as the FPGA, can be read and written via the I2C bus. It should be noted that when programming the firmware, each module can be programmed separately. For example, when verifying the I2C bus function, the firmware for the I2C module is programmed into the FPGA; while when verifying the I3C bus function, the firmware for the I3C module is programmed into the FPGA. Alternatively, multiple firmware modules can be programmed into the FPGA simultaneously; for example, the firmware for both the I2C and I3C modules can be programmed at the same time. This is not a limitation.

[0075] In actual testing, the first step is to verify the correctness of the electrical connections to determine if the FPGA can correctly recognize the I2C device. If it can, the electrical connection is correct. If it cannot, the cause needs to be identified. If the electrical connection is incorrect, such as SCL and SDA being reversed, the FPGA firmware can be modified to swap the pin definitions of SCL and SDA, and the firmware can be reprogrammed before retesting the electrical connectivity. If the FPGA can correctly recognize the I2C device after firmware modification, the cause of the error is recorded, and the verification platform schematic design is modified to correct the problem.

[0076] The signal integrity verification method involves connecting an oscilloscope near the input / output pins of the I / O device or near the input / output pins of the FPGA. The FPGA issues read / write commands to the I2C device, and the oscilloscope measures the SCL and SDA signal waveforms of the I2C to determine if the signal quality meets the electrical parameters required by the device datasheet. If it does, there is no need to modify the FPGA pin drive capability. If it does not meet the requirements, the signal waveform quality is adjusted by modifying the FPGA firmware or adjusting the FPGA pin drive capability, or by modifying the resistance values ​​on the verification platform, until the signal quality meets the electrical parameters required by the device datasheet. After adjustment, the FPGA firmware or verification platform schematic design is modified to correct the problem.

[0077] Understandably, based on the above implementation method, due to the programmability of the FPGA, the FPGA can implement the transmit and receive operations of CPU signals such as I3C, I2C, SPI, UART, JTAG, TPIU, GPIO, DDR, and PCIe, completing the testing and verification of the correctness of the CPU verification platform circuit connection function and signal integrity. This ensures that when the CPU is fabricated and returned to the die for power-on, the verification platform is free of fundamental errors, reducing the time wasted due to the need for redesigning the verification platform due to errors, accelerating CPU testing and verification, and ensuring that the product can be launched and sold as soon as possible.

[0078] In summary, this application provides a CPU post-silicon verification system and method. The CPU post-silicon verification system includes a programmable CPU emulation component, an inserter, a socket, and a verification platform, which are electrically connected sequentially. The inserter maps the signals of the programmable CPU emulation component to preset CPU pin definitions. The programmable CPU emulation component performs read and write operations on the verification platform, and determines the verification platform to be in a fault-free state when the read and write operations are successful. Since this application can simulate real read and write operations of the CPU on the verification platform using the programmable CPU emulation component, it can detect whether the verification platform is faulty. Furthermore, the programmable CPU emulation component guarantees accuracy; therefore, when a read or write operation fails, it can be clearly determined that the verification platform is faulty.

[0079] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0080] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A CPU post-silicon verification system, characterized in that, The CPU post-silicon verification system includes a programmable CPU emulation component, an inserter, a socket, and a verification platform. The programmable CPU emulation component, the inserter, the socket, and the verification platform are electrically connected sequentially. The programmable CPU emulation component includes an FPGA. The inserter is used to map the signals of the FPGA in the editable CPU emulation component to preset CPU pin definitions; The editable CPU simulation component is used to simulate the CPU performing real read and write operations on the verification platform, and determines that the verification platform is in a fault-free state when the read and write operations are successful.

2. The CPU post-silicon verification system as described in claim 1, characterized in that, The editable CPU emulation component also includes a PCB board and a communication interface. Both the FPGA and the communication interface are mounted on the PCB board, and the FPGA is communicatively connected to the communication interface. The PCB board is also electrically connected to the inserter. The communication interface is used to perform firmware upgrades or issue commands to the FPGA.

3. The CPU post-silicon verification system as described in claim 2, characterized in that, The communication interfaces include a JTAG interface, a USB Type-C interface, a USB Type-B interface, and a Micro USB interface; among which, The JTAG interface is used for firmware upgrades of the FPGA; The USB Type-C interface, the USB Type-B interface, and the Micro USB interface are used to send instructions to the FPGA.

4. The CPU post-silicon verification system as described in claim 2, characterized in that, The CPU post-silicon verification system also includes a board-to-board connector, with its two ends connected to the PCB board and the inserter, respectively.

5. The CPU post-silicon verification system as described in claim 2, characterized in that, Both the FPGA and the communication interface are soldered to the PCB board.

6. The CPU post-silicon verification system as described in claim 1, characterized in that, The verification platform includes a main body and multiple functional modules, wherein the main body and the multiple functional modules are electrically connected; wherein... The editable CPU simulation component is used to perform read and write operations on each of the functional modules, and when the read and write operations on each functional module are successful, the verification platform is determined to be in a fault-free state.

7. The CPU post-silicon verification system as described in claim 6, characterized in that, The functional modules include programmable logic devices, I / O devices, DDR and PCIe devices. The programmable CPU emulation component is used to issue test commands to different functional modules through I3C, I2C, SPI, UART, JTAG, TPIU, GPIO, DDR and PCIe signals.

8. A method for post-silicon verification of CPUs, characterized in that, Applied to the CPU post-silicon verification system as described in any one of claims 1 to 7, the method comprises: The editable CPU emulation component is refreshed and firmware is burned. The verification platform is read and written using an editable CPU emulation component; When the read / write operation is successful, the verification platform is determined to be in a fault-free state. When a read / write operation fails, the verification platform is determined to be in a fault state, and the firmware and / or the pin definitions of the editable CPU emulation component are modified until the read / write operation succeeds.

9. The CPU post-silicon verification method as described in claim 8, characterized in that, After a successful read / write operation, the method includes: Obtain the output signal waveform of the editable CPU simulation component, or obtain the input signal waveform of the verification platform; When the output signal waveform or input signal waveform meets the preset waveform quality, the signal integrity of the verification platform is determined to be qualified. When the output signal waveform or input signal waveform does not meet the preset waveform quality, modify the firmware and / or modify the pin drive capability of the editable CPU emulation component and / or modify the resistance parameters on the verification platform until the output signal waveform or input signal waveform meets the preset waveform quality.

10. The CPU post-silicon verification method as described in claim 8, characterized in that, When a read / write operation fails, the method further includes: When a read / write operation succeeds after modifying the firmware and / or the pin definitions of the editable CPU emulation component, the reason for the read / write operation failure is recorded.

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