A cpu post-silicon verification system and method

By combining editable CPU simulation components and communication interfaces, the problem of verifying the principle of the verification platform is solved, ensuring that the verification platform is fault-free and improving the accuracy and efficiency of CPU testing. It is especially suitable for startups to test the verification platform when they do not have the previous generation of CPUs.

CN115878403BActive Publication Date: 2026-07-24GUANGDONG HONGJUN MICROELECTRONICS CO LTD
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Patent Information

Application Number
CN202310032594.3
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2023-01-10
Publication Date
2026-07-24
Estimated Expiration
2043-01-10

AI Technical Summary

Technical Problem

Existing technologies cannot effectively verify the principles of the verification platform, making it impossible to determine whether the CPU failure is due to a CPU defect or a verification platform defect. This is especially problematic for startups that do not have a previous generation CPU available before the first generation CPU is tape-out, making it impossible to verify the verification platform.

Method used

A combination of an editable CPU emulation component, inserter, socket, and verification platform is used. The editable CPU emulation component simulates CPU read and write operations, ensuring that the signal mapping is to the preset CPU pin definitions. When the read and write operation is successful, it is determined that the verification platform is not faulty. Firmware upgrades and command issuance are performed using FPGA and communication interface to realize fault detection of the verification platform.

Benefits of technology

It enables accuracy testing of the verification platform, ensuring that the verification platform is fault-free, reducing time wastage caused by verification platform errors, and improving the efficiency and accuracy of CPU testing and verification.

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Abstract

The application provides a CPU post-silicon verification system and method, and relates to the technical field of post-silicon verification. The CPU post-silicon verification system comprises an editable CPU simulation component, an interposer, a socket and a verification platform, and the editable CPU simulation component, the interposer, the socket and the verification platform are electrically connected in sequence; wherein the interposer is used for mapping the signals of the editable CPU simulation component into preset CPU pin definitions; the editable CPU simulation component is used for performing read-write operations on the verification platform, and when the read-write operations are successful, it is determined that the verification platform is in a non-fault state. The CPU post-silicon verification system and method provided by the application have the advantage that the principle of the verification platform can be verified.
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