Computing processing device, computing device, computing processing method and integrated circuit chip

Abstract

The present disclosure provides a kind of computing processing device, it is related to artificial intelligence technical field, especially it is related to integrated circuit technical field and deep learning technical field.The specific implementation scheme is: control unit is configured to generate computing instruction and control signal;Buffer unit is electrically connected with the control unit, configured to receive computing instruction and control signal, and under the control of control signal, output computing instruction;And computing unit is electrically connected with buffer unit, configured to respond to computing instruction, executes computing operation.The present disclosure also provides a kind of computing device, computing processing method and integrated circuit chip.

Description

Technical Field

[0001] This disclosure relates to the field of artificial intelligence technology, and more particularly to the field of integrated circuit technology and deep learning technology. More specifically, this disclosure provides a computing processing apparatus, a computing device, a computing processing method, and an integrated circuit chip. Background Technology

[0002] With the development of artificial intelligence technology, deep learning models can be widely applied in various scenarios. Deep learning models include various neural network models. Processors can be used to perform a large number of operations on neural network models. Summary of the Invention

[0003] This disclosure provides a computing processing device, computing equipment, computing processing method, and integrated circuit chip.

[0004] According to one aspect of this disclosure, a computing processing apparatus is provided, the apparatus comprising: a control unit configured to generate computing instructions and control signals; a cache unit electrically connected to the control unit configured to receive computing instructions and control signals, and output computing instructions under the control of the control signals; and a computing unit electrically connected to the cache unit configured to perform computing operations in response to computing instructions.

[0005] According to another aspect of this disclosure, a computing device is provided, the device comprising: N computing processing devices according to this disclosure, wherein N is an integer greater than 1; and a reset signal line electrically connected to the N computing processing devices, wherein the reset signal line is used to apply a reset signal to the N computing processing devices.

[0006] According to another aspect of this disclosure, a computational processing method is provided, applied to the computational processing apparatus provided in this disclosure. The method includes: a control unit generating computational instructions and control signals; a buffer unit receiving computational instructions and control signals, and outputting computational instructions under the control of the control signals; and a computational unit performing computational operations in response to the computational instructions.

[0007] According to another aspect of this disclosure, a computational processing method is provided, applied to the computational device provided in this disclosure. The method includes: for each of N computational processing devices, a control unit generates computational instructions and a control signal; a buffer unit receives the computational instructions and the control signal, and outputs the computational instructions under the control of the control signal; and a computational unit performs a computational operation in response to the computational instructions.

[0008] According to another aspect of this disclosure, an integrated circuit chip is provided, the chip comprising: at least one computing device according to this disclosure.

[0009] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0010] The accompanying drawings are provided to better understand this solution and do not constitute a limitation of this disclosure. Wherein:

[0011] Figure 1A This is an exemplary system architecture diagram of an integrated circuit chip according to an embodiment of the present disclosure;

[0012] Figure 1B This is a schematic diagram illustrating the relationship between current and time in an integrated circuit chip according to an embodiment of the present disclosure;

[0013] Figure 1C This is a schematic diagram illustrating the relationship between voltage and time in an integrated circuit chip according to an embodiment of the present disclosure;

[0014] Figure 2 This is a schematic diagram of a computing processing apparatus according to an embodiment of the present disclosure;

[0015] Figure 3 This is a schematic diagram of a computing processing apparatus according to an embodiment of the present disclosure;

[0016] Figure 4 This is a flowchart of a calculation processing method according to an embodiment of the present disclosure;

[0017] Figure 5 This is a structural block diagram of a computing device according to another embodiment of the present disclosure;

[0018] Figure 6 This is a schematic diagram of a computing device according to an embodiment of the present disclosure;

[0019] Figure 7 This is a flowchart of a calculation processing method according to an embodiment of the present disclosure;

[0020] Figure 8A This is a timing diagram of a computational processing method according to an embodiment of the present disclosure;

[0021] Figure 8B This is a schematic diagram illustrating the relationship between current and time in an integrated circuit chip according to an embodiment of the present disclosure; and

[0022] Figure 9 This is a block diagram of an integrated circuit chip according to an embodiment of the present disclosure. Detailed Implementation

[0023] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0024] In artificial intelligence scenarios based on deep learning models, matrix multiplication can be a very high-frequency operator. The computation speed of matrix multiplication has a crucial impact on the overall performance of the relevant models. Dedicated processors for AI scenarios can accommodate a large number of multiply accumulator (MAC) units.

[0025] Figure 1A Figure 1 is an exemplary system architecture diagram of an integrated circuit chip according to an embodiment of the present disclosure. It should be noted that the system architecture shown in Figure 1 is only an example of a system architecture that can be applied to the embodiments of the present disclosure to help those skilled in the art understand the technical content of the present disclosure, but it does not mean that the embodiments of the present disclosure cannot be used in other devices, systems, environments or scenarios.

[0026] like Figure 1A As shown, the integrated circuit chip 100 according to this embodiment may include multiple computing processing devices. For example, the multiple computing processing devices may include a first computing processing device 101, a second computing processing device 102, and a third computing processing device 103. The integrated circuit chip 100 may also include a memory unit 104.

[0027] The computing processing apparatus may include a computing instruction generator and computing units. The computing units may also include multiply-accumulate units or convolution units. The computing processing apparatus may include multiple computing units. For example, the first computing processing apparatus 101 may include a computing instruction generator 1011 and a computing unit 1012.

[0028] The second computing processing device 102 may include a computing instruction generator 1021 and a computing unit 1022.

[0029] The third computing processing device 103 may include a computing instruction generator 1031 and a computing unit 1032. The computing instruction generator can send computing instructions to the computing unit. Setting up multiple computing processing devices with identical or similar structures in the integrated circuit chip 100 makes the chip physically simpler to implement, allows for more flexible scheduling, and is more conducive to improving the utilization rate of the multiply-accumulate unit.

[0030] An array formed by multiple computing units has a relatively large logic scale and a high flip-flop rate, which can generate significant power consumption. For example, taking a multiply-accumulate unit as the computing unit, flip-flop can refer to the multiply-accumulate unit transitioning from an active state to an idle state, or vice versa. When transitioning from an idle state to an active state after receiving a computing instruction, the power consumption level of the multiply-accumulate unit increases rapidly within a short period, and its current also increases rapidly. The relationship between current and time in integrated circuit chip 100 is as follows: Figure 1B As shown. The relationship between voltage and time of integrated circuit chip 100 is as follows. Figure 1C As shown.

[0031] Figure 1B This is a schematic diagram illustrating the relationship between current and time in an integrated circuit chip according to an embodiment of the present disclosure. Figure 1C This is a schematic diagram illustrating the relationship between voltage and time in an integrated circuit chip according to an embodiment of the present disclosure.

[0032] like Figure 1B As shown, after time t_0, multiple computing units transition from an idle state to an active state. The current in the integrated circuit chip increases rapidly within a short period.

[0033] like Figure 1C As shown, after time t_0, the voltage of the integrated circuit chip fluctuates downwards. The faster the current increases, the greater the magnitude of the downward voltage fluctuation. Figure 1C As shown, after a downward fluctuation, the actual voltage of the integrated circuit chip may be lower than the minimum voltage V_Low required for the chip to function properly, leading to errors in the chip's calculation results or even more serious chip functional problems.

[0034] Furthermore, as described above, the integrated circuit chip 100 may include multiple computing processing devices. These computing processing devices may operate independently. Consequently, the computing units of multiple computing processing devices may be in the same processing cycle, or different computing units may simultaneously enter a working state from an idle state within several close processing cycles. In this case, the current changes caused by different computing units can be superimposed, leading to a more drastic increase in current and further increasing the risk of the voltage dropping below the minimum voltage.

[0035] In some embodiments, the operating frequency of the computing unit can be reduced to decrease its power consumption, thereby slowing down the rate of change of operating current and reducing drastic voltage fluctuations. However, reducing the operating frequency of the computing unit can directly reduce the peak computing power of the chip, which can significantly impair performance in real-world scenarios.

[0036] In some embodiments, a central scheduler can be set up in the integrated circuit chip. When planning to start a computing unit, a relevant request can be sent to the central scheduler. Based on the number of multiply-accumulate units started in a nearby time period, the central scheduler can determine whether to start the computing unit corresponding to the request immediately or delay its start. This allows different multiply-accumulate units to coordinate with each other through unified scheduling, avoiding the simultaneous start of a large number of multiply-accumulate units in a short period, thereby suppressing rapid current rise and reducing risk. However, the large size of integrated circuit chips and the significant physical distance between different multiply-accumulate units on the chip result in a large interaction delay between the multiply-accumulate units and the central scheduler. Multiply-accumulate units require a long idle time to wait for a response from the central scheduler before being started. This reduces the working efficiency of the multiply-accumulate units and consequently reduces the actual performance of the chip.

[0037] In some embodiments, a mixed-signal monitoring module can be provided. This module can monitor the current or voltage of each multiply-accumulate unit to achieve feedback-based adjustment of the operating intensity of each unit, preventing it from falling below the minimum voltage during voltage fluctuations. However, current and voltage change rapidly. To monitor the current or voltage of each multiply-accumulate unit, the monitoring module needs very high real-time monitoring capabilities. Furthermore, introducing mixed-signal circuitry into the chip presents a certain technical hurdle and increases the design complexity of the chip.

[0038] To effectively reduce current or voltage fluctuations, the computing processing unit can be adjusted by incorporating a cache unit. This will be discussed in the following section. Figure 2 Please provide an explanation.

[0039] Figure 2 This is a schematic diagram of a computing processing apparatus according to an embodiment of the present disclosure.

[0040] like Figure 2 As shown, the computing processing device 210 may include a control unit 211, a cache unit 213, and a computing unit 212. In this embodiment, the computing processing device 210 may be implemented using a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), or the like.

[0041] Control unit 211 is configured to generate calculation instructions and control signals. For example, control unit 211 may include a calculation instruction generator and a control signal generator. The calculation instruction generator may be configured to generate calculation instructions. The control signal generator may be configured to generate control signals. It is understood that the calculation instructions and control signals may be generated asynchronously.

[0042] The buffer unit 213, electrically connected to the control unit, is configured to receive calculation instructions and control signals, and output calculation instructions under the control of the control signals. For example, after the calculation instruction generator of the control unit 211 generates calculation instructions, the calculation instructions can be sent to the buffer unit 213 first. The buffer unit 213 can buffer multiple calculation instructions. After receiving the control signal from the control signal generator, the buffer unit 213 can output a calculation instruction to the calculation unit 212.

[0043] The calculation unit 212, electrically connected to the cache unit, is configured to perform a calculation operation in response to a calculation instruction. For example, the calculation operation may include a multiply-accumulate operation.

[0044] Through the embodiments of this disclosure, the control unit can generate control signals and is equipped with a buffer unit. The control unit and the buffer unit can be implemented using digital circuits, resulting in relatively simple digital logic and low resource overhead. Upon receiving the control signal, the buffer unit outputs calculation instructions, facilitating the activation of different calculation units. This slows down the rapid rise of current, allowing it to increase in a stepwise manner, reducing voltage fluctuations, and improving the stability of the relevant integrated circuit chips.

[0045] It is understood that the computing processing apparatus of this disclosure has been described above, and the control unit of this disclosure will be further described below.

[0046] Figure 3 This is a schematic diagram of a computing processing apparatus according to an embodiment of the present disclosure.

[0047] like Figure 3 As shown, the computing processing device 310 may include a control unit 311, a cache unit 313, and a computing unit 312.

[0048] In this embodiment of the disclosure, the control unit may also be electrically connected to the computing unit. For example, the control unit 311 may be electrically connected to the computing unit 312.

[0049] In this embodiment of the disclosure, the computing unit may also be provided with a cache. The cache may store at least one computing instruction.

[0050] In this embodiment of the disclosure, the control unit may also be configured to determine the current state of the computing unit. For example, the current state of computing unit 313 may include an operating state and an idle state. In the operating state, the computing unit may perform computing operations. In the idle state, the computing unit may wait for computing instructions. The control unit 311 may determine the current state of computing unit 312. It is understood that in the idle state, there may be no computing instructions in the buffer of the computing unit.

[0051] In this embodiment, when the current state of the computing unit is determined to be idle, the computing instruction is sent to the cache unit. Through this embodiment, the computing instruction is sent to the cache unit when the computing unit is idle. This avoids multiple idle computing units receiving computing instructions simultaneously, and also avoids multiple computing units switching from idle to active states simultaneously. This allows the current of the chip with the computing processing device to increase in a stepped manner, and also reduces voltage fluctuations.

[0052] In this embodiment, the control unit is further configured to output calculation instructions to the computing unit when it is determined that the current state of the computing unit is an operating state. It can be understood that, in the operating state, calculation instructions can be output by the calculation instruction generator to the buffer of the computing unit. Through this embodiment, in the operating state, the current of the computing unit is stable, preventing voltage fluctuations, and calculation instructions can be directly sent to the computing unit so that the computing unit can perform relevant calculations according to the calculation instructions. This improves the computing power of the chip.

[0053] In this embodiment, the trigger signal is a periodic signal, and the period of the trigger signal is equal to one processing cycle of the computing unit. For example, the period of the trigger signal may be related to the deep learning model corresponding to the integrated circuit chip. As another example, the duration of the trigger signal may include the duration of an active level and the duration of an inactive level. The duration of the active level (slot_pluse) can be one clock cycle. The clock cycle is relatively short, on the order of nanoseconds. The duration of the inactive level can be multiple clock cycles.

[0054] As can be understood, the control unit of this disclosure has been described above, and the control signal generator and calculation instruction generator of the control unit will be described below.

[0055] In embodiments of this disclosure, the control unit may include a calculation instruction generator. The calculation instruction generator is configured to generate calculation instructions based on a call instruction received. For example, control unit 311 may include a calculation instruction generator 3111. The call instruction may indicate a calculation unit corresponding to a related calculation operation. The call instruction may also include input data related to the calculation operation.

[0056] In embodiments of this disclosure, the control unit may include a control signal generator. The control signal generator may be configured to reset to an initial state in response to receiving a reset signal. For example, control unit 311 may include a control signal generator 3112. The reset signal may cause control signal generator 3112 to return to its initial state. Control signal generators of different computing processing devices may all reset to their initial states in response to receiving a reset signal, thereby synchronizing the control signal generators of different computing processing devices.

[0057] In embodiments of this disclosure, the control signal generator may further be configured to generate a trigger signal in response to determining that the initial state has lasted for a predetermined initial state duration. For example, during the predetermined initial state duration, the computing processing device may perform a series of preparatory operations. Thus, after the predetermined initial state duration has elapsed, the computing unit may execute operations according to computing instructions. Furthermore, the predetermined initial state duration may be different for different computing processing devices.

[0058] As can be understood, the control unit, its control signal generator, and calculation instruction generator of this disclosure have been described above. The cache unit will be described below.

[0059] In this embodiment, the cache unit is further configured to store received computation instructions to the tail of the computation instruction queue. In response to receiving a trigger signal with a valid level, the computation instruction at the head of the computation instruction queue is output to the computation unit. For example, in the cache unit 313, the computation instruction queue can be a First-In-First-Out (FIFO) queue. Through this embodiment, when the computation unit is idle, multiple received computation instructions can be stored in the cache unit, preventing multiple computation instructions from causing multiple computation units to simultaneously switch to the working state.

[0060] As can be understood, the cache unit of this disclosure has been described above, and the computing unit will be described below.

[0061] In this embodiment of the disclosure, the calculation unit 312 may include a multiply-accumulate unit. For example, the multiply-accumulate unit may perform a multiply-accumulate operation.

[0062] In another embodiment of this disclosure, the computation unit may include a convolution unit. For example, the convolution unit may perform a convolution operation.

[0063] It is understood that the computing processing apparatus of this disclosure has been described above, and the computing processing method that can be applied to the above computing processing apparatus will be described below.

[0064] Figure 4 This is a flowchart of a calculation processing method according to an embodiment of the present disclosure.

[0065] like Figure 4 As shown, the method 400 may include operations S410 to S430.

[0066] When operating S410, the control unit generates calculation instructions and control signals.

[0067] When operating the S420, the buffer unit receives calculation instructions and control signals, and outputs calculation instructions under the control of the control signals.

[0068] When operating S430, the computing unit responds to the computing instruction and performs the computing operation.

[0069] In this embodiment of the disclosure, the method 400 can be implemented using the computing processing device 200 described above.

[0070] In some embodiments, method 400 may further include: determining the current state of the computing unit. If the current state of the computing unit is determined to be an operating state, a computing instruction is output to the computing unit.

[0071] In some embodiments, the control signal includes a trigger signal; the method further includes: determining the current state of the computing unit. If the current state of the computing unit is determined to be an idle state, a computing instruction is sent to a cache unit.

[0072] In some embodiments, the cache unit receives calculation instructions and control signals, and under the control of the control signals, outputting calculation instructions further includes: storing the received calculation instructions to the tail of the calculation instruction queue. In response to receiving a trigger signal with a valid level, the calculation instruction at the head of the calculation instruction queue is output to the calculation unit.

[0073] In some embodiments, the trigger signal is a periodic signal, and the period of the trigger signal is equal to one processing cycle of the computing unit.

[0074] In some embodiments, method 400 further includes: in response to receiving a reset signal, resetting a control signal generator to an initial state. In response to determining that the initial state has lasted for a predetermined initial state duration, the control signal generator generates a trigger signal.

[0075] It is understood that the above text has described the computing processing device and the computing processing method applied to the device. The following text will describe a computing device that includes at least one computing processing device.

[0076] Figure 5 This is a structural block diagram of a computing device according to another embodiment of the present disclosure.

[0077] like Figure 5As shown, device 5001 may include N computing processing units and reset signal lines.

[0078] N computing processing devices. In this embodiment, N is an integer greater than 1. The N computing processing devices may include a first computing processing device 510, a second computing processing device 520, and a third computing processing device 530. It is understood that this embodiment uses N=3 as an example, but this disclosure is not limited thereto; N can be 2 or other values ​​greater than 3, and this disclosure does not impose any restrictions on this. It is also understood that for a detailed description of computing processing devices 510 to 530, please refer to the above-described computing processing device 210, and this disclosure will not repeat it here.

[0079] A reset signal line 540 is electrically connected to N computing processing devices. In embodiments of this disclosure, the reset signal line can apply reset signals to the N computing processing devices. For example, as described above, the control signal generator of the control unit can reset to its initial state in response to receiving a reset signal.

[0080] As you can understand, the above text has described the computing device, and the following text will provide a further explanation of the computing device.

[0081] Figure 6 This is a schematic diagram of a computing device according to an embodiment of the present disclosure.

[0082] like Figure 6 As shown, the computing device 6001 may include a first computing processing unit 610, a second computing processing unit 620, a third computing processing unit 630, and a reset signal line 640. It can be understood that in this embodiment, N = 3.

[0083] The first computing processing device 610 may include a control unit 611, a cache unit 613, and a computing unit 612. The control unit 611 may include a control signal generator 6112 and a computing instruction generator 6111. The second computing processing device 620 may include a control unit 621, a cache unit 623, and a computing unit 622. The control unit 621 may include a control signal generator 6212 and a computing instruction generator 6211. The third computing processing device 630 may include a control unit 631, a cache unit 633, and a computing unit 632. The control unit 631 may include a control signal generator 6312 and a computing instruction generator 6311. For a detailed description of the first to third computing processing devices 610, please refer to the computing processing device 210 or the computing processing device 310 described above; further details will not be repeated here.

[0084] In this embodiment of the disclosure, N computing processing devices are configured such that the duration of the nth predetermined initial state of the nth computing processing device is less than the duration of the (n+1)th predetermined initial state of the (n+1)th computing processing device. In this embodiment, n is an integer greater than or equal to 1 and less than N. For example, the duration of the initial state of the nth computing processing device can be the duration of the nth predetermined initial state. The duration of the initial state of the (n+1)th computing processing device can be the duration of the (n+1)th predetermined initial state. The duration of the nth predetermined initial state can be less than the duration of the (n+1)th predetermined initial state. For example, as described above, a trigger signal is generated in response to determining that the initial state has lasted for the predetermined initial state duration. The N computing processing devices can simultaneously receive a reset signal. The control signal generators of the N computing processing devices can simultaneously reset to their initial states. Next, after determining that the initial state of the control signal generator of the nth computing processing device has lasted for the nth predetermined initial state duration, the control signal generator of the nth computing processing device can generate a trigger signal. Next, the cache unit of the nth computing device can send computing instructions to the computing unit of the nth processing device.

[0085] like Figure 6As shown, the reset signal line 640 can simultaneously apply reset signals to the first computing processing unit 610, the second computing processing unit 620, and the third computing processing unit 630, respectively. Control signal generators 6112, 6212, and 6312 can each respond to the reset signal and reset to their initial states. The predetermined initial state durations of control signal generators 6112, 6212, and 6312 can be respectively designated as the first, second, and third predetermined initial state durations. The first predetermined initial state duration is shorter than the second predetermined initial state duration. The second predetermined initial state duration is shorter than the third predetermined initial state duration. After determining that the initial state of control signal generator 6112 has lasted for the first predetermined initial state duration, control signal generator 6112 can generate a trigger signal. Next, after determining that the control signal generator 6212 has maintained the second predetermined initial state duration, the control signal generator 6212 can generate a trigger signal. After determining that the control signal generator 6312 has maintained the third predetermined initial state duration, the control signal generator 6312 can generate a trigger signal. Thus, the control signal generators 6112, 6212, and 6312 can generate trigger signals at different times, allowing the cache units 613, 623, and 633 to output calculation instructions to the computing unit at different times, thereby enabling the computing units 613, 623, and 633 to enter the working state from the idle state at different times. Through this embodiment, the computing units of different computing devices can enter the working state at different times, effectively avoiding a rapid rise in current and improving the stability of the chip.

[0086] In this embodiment of the disclosure, the periods and effective durations of the trigger signals of the N computing processing devices are all equal. For example, the periods of the trigger signals of the first computing processing device 610, the second computing processing device 620, and the first computing processing device 630 can be equal. The effective durations of the trigger signals of the first computing processing device 610, the second computing processing device 620, and the first computing processing device 630 can also be equal, and can be one clock cycle.

[0087] In this embodiment, the difference between the (n+1)th predetermined initial state duration and the nth predetermined initial state duration is M times the effective level duration of the trigger signal. For example, M is an integer greater than 1. Another example is that the effective level duration can be one clock cycle. The difference between the (n+1)th predetermined initial state duration and the nth predetermined initial state duration can be M clock cycles. In one example, M is an integer greater than or equal to 2 and less than or equal to 5. Therefore, current variations can be further reduced, voltage fluctuations can be effectively mitigated, and chip stability can be improved.

[0088] As we have already provided a detailed explanation of the computing processing unit and reset signal line of the computing device, the main processor of the computing device will be explained below.

[0089] In embodiments of this disclosure, the computing device may further include a main processor. The main processor is configured to generate invocation instructions and send these instructions to a target computing processing device among N computing processing devices. For example, the invocation instructions may include input data related to a computational operation. The main processor can send the invocation instructions to the target computing processing device, enabling a computational instruction generator of the computing processing device to generate computational instructions based on the invocation instructions.

[0090] As you can understand, the above text has described the computing device, and the following text will describe the computing processing methods applied to this computing device.

[0091] Figure 7 This is a flowchart of a calculation processing method according to an embodiment of the present disclosure.

[0092] like Figure 7 As shown, the method 700 may include: for each of the N computing processing devices, operations S710 to S730 may be performed.

[0093] When operating the S710, the control unit generates calculation instructions and control signals.

[0094] When operating the S720, the buffer unit receives calculation instructions and control signals, and outputs calculation instructions under the control of the control signals.

[0095] When operating the S730, the computing unit responds to the computing instructions and performs computing operations.

[0096] For example, the method 700 can be implemented using the aforementioned device 500.

[0097] It is understood that the method of this disclosure has been described above, and the calculation and processing method of this disclosure will be further described below in conjunction with relevant embodiments.

[0098] Figure 8AThis is a timing diagram of a computational processing method according to an embodiment of the present disclosure.

[0099] In this embodiment of the disclosure, in response to a reset signal applied to N computing processing devices via a reset signal line, the control signal generators in the N computing processing devices are all reset to their initial state. For example... Figure 8A As shown, at time t_0, a reset signal (trigger) can be applied to N computing processing devices via the reset signal line. In response to this reset signal (trigger), the control signal generators of each of the N computing processing devices are reset to their initial state.

[0100] In this embodiment of the disclosure, the duration of the nth initial state of the nth computing processing device is less than the duration of the (n+1)th initial state of the (n+1)th computing processing device. For example, n is an integer greater than or equal to 1 and less than N. Figure 8A As shown, the duration of the first predetermined initial state, int_delay1, can be less than the duration of the second predetermined initial state, int_delay2. The duration of the second predetermined initial state, int_delay2, can be less than the duration of the third predetermined initial state, int_delay3.

[0101] In this embodiment of the disclosure, in response to determining that the initial state has lasted for a predetermined initial state duration, the control signal generator generates a trigger signal. For example... Figure 8A As shown, in response to the initial state of the control signal generator for determining the first computing processing unit lasting for a first predetermined initial state duration int_delay1, the control signal generator can generate a trigger signal. The duration of the effective level slot_pulsel of the trigger signal can be one clock cycle.

[0102] After the control signal generator of the first computing processing unit generates the trigger signal, such as Figure 8A As shown, in response to the initial state of the control signal generator of the second computing processing unit lasting for a second predetermined initial state duration int_delay2, the control signal generator of the second computing processing unit can generate a trigger signal. The duration of the effective level slot_pulse2 of this trigger signal can also be one clock cycle.

[0103] After the control signal generator of the second computing processing unit generates the trigger signal, such as Figure 8A As shown, in response to the initial state of the control signal generator of the third computing processing unit lasting for a third predetermined initial state duration int_delay3, the control signal generator of the third computing processing unit can generate a trigger signal. The duration of the effective level slot_pulse3 of this trigger signal can also be one clock cycle.

[0104] In this embodiment of the disclosure, the trigger signal is a periodic signal. The period of the trigger signal is equal to one processing cycle of the computing unit. The periods and effective level durations of the trigger signals of the N computing processing devices are all equal to each other. For example, the periods of the trigger signals of the first, second, and third computing processing devices can all be durations of period. The duration of period can be multiple clock cycles. As another example, the effective level duration of slot_pulse1 of the trigger signal of the first computing processing device, the effective level duration of slot_pulse2 of the trigger signal of the second computing processing device, and the effective level duration of slot_pulse3 of the trigger signal of the third computing processing device can all be one clock cycle.

[0105] In this embodiment of the disclosure, the difference between the duration of the (n+1)th initial state and the duration of the nth initial state is M times the effective level duration of the trigger signal, where M is an integer greater than 1. For example, M is an integer greater than 1. In one example, M can be an integer greater than or equal to 2 and less than or equal to 5. Figure 8A As shown, the difference between the duration of the second initial state int_delay2 and the duration of the first initial state int_delay1 can be M times the duration of the effective level.

[0106] As can be understood, the generation of trigger signals has been explained above, and the generation of calculation instructions will be explained below.

[0107] In this embodiment of the disclosure, the main processor of the computing processing device can generate invocation instructions. The main processor can send the invocation instructions to a target computing processing device among N computing processing devices. For example, the main processor can generate three invocation instructions and send them to three computing processing devices respectively. Alternatively, the invocation instructions can be generated within a predetermined initial state duration.

[0108] In this embodiment of the disclosure, in response to receiving a call instruction, the computation instruction generator of the computing processing device can generate computation instructions according to the call instruction. For example, within the first initial state duration int_delay1, the computation instruction generator of the first computing processing device can generate a first computation instruction according to the call instruction. Within the second initial state duration int_delay2, the computation instruction generator of the second computing processing device can generate a second computation instruction according to the call instruction. Within the third initial state duration int_delay3, the computation instruction generator of the third computing processing device can generate a third computation instruction according to the call instruction.

[0109] As we have explained above, some methods for generating trigger signals and calculation instructions will now be explained below.

[0110] In embodiments of this disclosure, the current state of a computing unit can be determined for each of the N computing processing devices. For example, the current state of a computing unit may be an idle state during a predetermined initial state duration.

[0111] In this embodiment of the disclosure, when it is determined that the current state of the computing unit is idle, a computing instruction is sent to a cache unit. For example, a first computing instruction may be sent to the cache unit of a first computing processing device. A second computing instruction may be sent to the cache unit of a second computing processing device. A third computing instruction may be sent to the cache unit of a third computing processing device.

[0112] In this embodiment of the present disclosure, the cache unit can store the received computation instructions to the tail of the computation instruction queue. For example, the computation instruction queue can be a first-in-first-out queue. The first computation instruction, the second computation instruction, and the third computation instruction can be at the tail of their respective computation instruction queues. It is understood that the cache unit of the computing processing device can include one computation instruction during a predetermined duration.

[0113] Next, after the control signal generator generates the trigger signal, the following operations can be performed.

[0114] In this embodiment of the present disclosure, in response to receiving a trigger signal with a valid level, the computation instruction at the head of the computation instruction queue is output to the computation unit. For example, after receiving a trigger signal with a valid level of slot_pluse1, the buffer unit of the first computation processing device may output the first computation instruction at the head of its computation instruction queue to the computation unit of the first computation processing device. After receiving a trigger signal with a valid level of slot_pluse2, the buffer unit of the second computation processing device may output the second computation instruction at the head of its computation instruction queue to the computation unit of the second computation processing device. After receiving a trigger signal with a valid level of slot_pluse3, the buffer unit of the third computation processing device may output the third computation instruction at the head of its computation instruction queue to the computation unit of the third computation processing device.

[0115] As we have explained above, some ways of outputting computation instructions from the cache unit will now be explained below.

[0116] In this embodiment of the present disclosure, the computing unit can perform a computing operation in response to a computing instruction. For example, the computing unit of the first computing processing device can perform a computing operation in response to a first computing instruction and enter a working state. The computing unit of the second computing processing device can perform a computing operation in response to a second computing instruction and enter a working state. The computing unit of the third computing processing device can perform a computing operation in response to a third computing instruction and enter a working state. The following will be combined with... Figure 8B This will illustrate the changes in chip current after the computing units of the three computing devices enter the working state.

[0117] Figure 8B This is a schematic diagram illustrating the relationship between current and time in an integrated circuit chip according to an embodiment of the present disclosure.

[0118] like Figure 8B As shown, at time t_0, each computing processing unit receives a reset signal, and the computing unit is in an idle state. The duration of the time interval between time t_0 and time t_1 can be the first predetermined initial state duration int_delay1. At time t_1, it can be determined that the initial state of the control signal generator of the first computing processing unit lasts for the first predetermined initial state duration int_delay1, and the buffer unit of the first computing processing unit can receive a trigger signal with a valid level slot_pulsel.

[0119] The time period between time t_1 and time t_2 can be the duration of the effective level slot_pulsel. During this period, the current of the integrated circuit chip rises and stabilizes.

[0120] Next, during the time interval between time t_2 and time t_3, the computing units of the second and third computing processing devices successively enter the working state. For example... Figure 8B As shown, the current increases in a stepwise manner during this period.

[0121] After time t_3, the next cycle of the trigger signal begins. Through this embodiment, a step-like increase in current is achieved, which can effectively mitigate voltage fluctuations.

[0122] During the trigger signal period (e.g., from time t_1 to time t_3), the main processor can continue to generate or send call instructions to the target computing device. For example, after the computing unit of the first computing device enters the working state, the main processor can generate or send call instructions to the first computing device. In response to receiving the call instruction, the computing instruction generator of the first computing device can generate a fourth computing instruction based on the call instruction. After generating the fourth computing instruction, the following operations can be performed.

[0123] In this embodiment, the operating state of the computing unit is determined. If the current state of the computing unit is determined to be operating, a computing instruction is output to the computing unit. For example, when the computing unit of the first computing processing device executes a computing operation according to a first computing instruction, the computing unit is in an operating state. A fourth computing instruction can be directly output to the buffer of the computing unit. After completing the computing operation related to the first computing instruction, the computing unit can execute a computing operation according to the fourth computing instruction.

[0124] After completing the calculation operation according to the first and fourth calculation instructions, the first computing processing unit can enter an idle state. For the first computing processing unit, after the first cycle of its trigger signal, the control signal generator of the first computing processing unit can generate another trigger signal with a valid level of slot_pluse1. For example, after completing the calculation operation according to the second calculation instruction, the second computing processing unit can enter an idle state. For the second computing processing unit, after the first cycle of its trigger signal, the control signal generator of the second computing processing unit can generate another trigger signal with a valid level of slot_pluse2. For example, after completing the calculation operation according to the third calculation instruction, the third computing processing unit can enter an idle state. For the third computing processing unit, after the first cycle of its trigger signal, the control signal generator of the third computing processing unit can generate another trigger signal with a valid level of slot_pluse3.

[0125] Figure 9 This is a schematic diagram of an integrated circuit chip according to an embodiment of the present disclosure.

[0126] like Figure 9 As shown, the chip 900 may include at least one computing device 9001. In embodiments of this disclosure, the computing device may be a computing device provided in this disclosure. For example, the computing device may be the computing device 5001 or 6001 described above.

[0127] The collection, storage, use, processing, transmission, provision, and disclosure of user personal information involved in the technical solution disclosed herein comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0128] In embodiments of this disclosure, integrated circuit chips can be deployed in a computing system. The computing system is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The computing system can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing systems. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0129] Multiple components in a computing system connect to I / O interfaces. These components may include: input units, such as keyboards and mice; output units, such as various types of displays and speakers; storage units, such as hard disks and optical disks; and communication units, such as network interface cards (NICs), modems, and wireless transceivers. Communication units allow the computing system to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0130] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0131] In embodiments of this disclosure, the computing system may include a machine-readable medium. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media may include, but are not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0132] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0133] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A computing device, comprising: There are N computing processing devices, where N is an integer greater than 1; and A reset signal line is electrically connected to the N computing processing devices, wherein, The reset signal line is used to apply the reset signal to the N computing processing devices; The computing processing device includes: a control unit configured to generate computing instructions and control signals; A cache unit, electrically connected to the control unit, is configured to receive the calculation instructions and the control signal, and, under the control of the control signal, output the calculation instructions; and A computing unit, electrically connected to the cache unit, is configured to perform a computing operation in response to the computing instruction; The control signal includes a trigger signal; the trigger signal is a periodic signal, and the period of the trigger signal is equal to one processing cycle of the computing unit. The control unit includes a control signal generator; the control signal generator is configured to: In response to receiving a reset signal, the system resets to its initial state; and The trigger signal is generated in response to determining that the initial state has lasted for a predetermined initial state duration; The N computing processing devices are configured as follows: The duration of the nth predetermined initial state of the nth computing processing device is less than the duration of the (n+1)th predetermined initial state of the (n+1)th computing processing device, where n is an integer greater than or equal to 1 and less than N; The period of the trigger signal of each of the N computing processing devices and the duration of the effective level of the trigger signal are all equal.

2. The device according to claim 1, wherein, The control unit is also electrically connected to the computing unit; the control unit is further configured to: Determine the current state of the computing unit; and If the current state of the computing unit is determined to be working, the computing instruction is output to the computing unit.

3. The device according to claim 2, wherein, The control unit is also configured to: Determine the current state of the computing unit; and If the current state of the computing unit is determined to be idle, the computing instruction is sent to the cache unit.

4. The device according to any one of claims 1-3, wherein, The control unit includes a calculation instruction generator; the calculation instruction generator is configured to: In response to receiving a call instruction, a calculation instruction is generated based on the call instruction.

5. The device according to claim 1, wherein, The computational unit includes a multiply-accumulate unit or a convolution unit.

6. The device according to claim 1, wherein, The difference between the (n+1)th predetermined initial state duration and the nth predetermined initial state duration is M times the effective level duration of the trigger signal, where M is an integer greater than 1.

7. The device according to claim 6, wherein, M is an integer greater than or equal to 2 and less than or equal to 5.

8. The device according to claim 1 further includes a main processor, the main processor being configured to generate a calling instruction and send the calling instruction to a target computing processing device among the N computing processing devices.

9. A computational processing method applied to a computing device according to any one of claims 1-8, the method comprising: For each of the N computing processing devices, the control unit generates computing instructions and control signals; The cache unit receives the calculation instruction and the control signal, and outputs the calculation instruction under the control of the control signal; as well as The computing unit responds to the computing instruction and performs a computing operation; The control signal includes a trigger signal; The trigger signal is a periodic signal, and the period of the trigger signal is equal to one processing cycle of the computing unit; The duration of the nth predetermined initial state of the nth computing processing device is less than the duration of the (n+1)th predetermined initial state of the (n+1)th computing processing device, where n is an integer greater than or equal to 1 and less than N; The period of the trigger signal of each of the N computing processing devices and the duration of the effective level of the trigger signal are all equal to each other; In response to a reset signal applied to the N computing devices via the reset signal line, the control signal generators in the N computing devices are all reset to their initial states; and In response to determining that the initial state has lasted for a predetermined initial state duration, the control signal generator generates the trigger signal.

10. The method of claim 9, further comprising: For each of the N computing processing devices, determine the current state of the computing unit; as well as If the current state of the computing unit is determined to be working, the computing instruction is output to the computing unit.

11. The method according to claim 9, wherein, The method further includes: For each of the N computing processing devices, determine the current state of the computing unit; and If the current state of the computing unit is determined to be idle, the computing instruction is sent to the cache unit; The cache unit receives the calculation instruction and the control signal, and outputs the calculation instruction under the control of the control signal, further comprising: The received calculation instructions are stored at the tail of the calculation instruction queue; In response to receiving the trigger signal with a valid level, the calculation instruction at the head of the calculation instruction queue is output to the calculation unit.

12. The method according to claim 9, wherein, The difference between the (n+1)th predetermined initial state duration and the nth predetermined initial state duration is M times the effective level duration of the trigger signal, where M is an integer greater than 1.

13. The method according to claim 12, wherein, M is an integer greater than or equal to 2 and less than or equal to 5.

14. The method of claim 9, further comprising: The main processor generates a call instruction and sends the call instruction to the target computing processing device among the N computing processing devices.

15. An integrated circuit chip, comprising: At least one computing device according to any one of claims 1-8.

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