Detection device

Abstract

A detection device is provided to improve detection accuracy. The detection device includes: a substrate; a plurality of transistors disposed on the substrate; a plurality of scan lines extending along a first direction; a plurality of signal lines extending along a second direction intersecting the first direction; a plurality of photodiodes respectively disposed in a region surrounded by the plurality of scan lines and the plurality of signal lines, and including a p-type semiconductor layer, an i-type semiconductor layer, and an n-type semiconductor layer; and shielding wiring overlapping the scan lines and extending along the first direction, the shielding wiring being electrically connected to a power signal line among the plurality of signal lines that supplies power potential to the transistors.

Description

Technical Field

[0001] This invention relates to a detection device. Background Technology

[0002] Patent Document 1 describes an optical imaging device having a light-shielding layer with an opening between a microlens and a light sensor. As such a light sensor, a PIN-type photodiode is known. A PIN-type photodiode has a structure consisting of stacked p-type semiconductor layers, i-type semiconductor layers, and n-type semiconductor layers.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: U.S. Patent Application Publication No. 2020 / 0089928 Summary of the Invention

[0006] The technical problem that the invention aims to solve

[0007] PIN photodiodes can increase photocurrent and thus improve detection sensitivity by increasing the sensor area. However, increasing the sensor area reduces the distance between the photodiode and the scan line, potentially increasing parasitic capacitance. This parasitic capacitance can cause deviations in the output signal from the photodiode, leading to decreased detection accuracy.

[0008] The purpose of this invention is to provide a detection device that can improve detection accuracy.

[0009] Solutions for solving technical problems

[0010] One aspect of the detection device of the present invention includes: a substrate; a plurality of transistors disposed on the substrate; a plurality of scan lines extending along a first direction; a plurality of signal lines extending along a second direction intersecting the first direction; a plurality of photodiodes respectively disposed in a region surrounded by the plurality of scan lines and the plurality of signal lines, and including a p-type semiconductor layer, an i-type semiconductor layer and an n-type semiconductor layer; and a shielding wiring overlapping the scan lines and extending along the first direction, the shielding wiring being electrically connected to a power signal line among the plurality of signal lines that supplies power potential to the transistors.

[0011] One aspect of the detection device of the present invention includes: a substrate; a plurality of transistors disposed on the substrate; a plurality of scan lines extending along a first direction; a plurality of signal lines extending along a second direction intersecting the first direction; a plurality of photodiodes respectively disposed in a region surrounded by the plurality of scan lines and the plurality of signal lines, and including a p-type semiconductor layer, an i-type semiconductor layer and an n-type semiconductor layer; and shielding wiring extending along the first direction in a manner overlapping with the scan lines and supplied with a fixed potential. Attached Figure Description

[0012] Figure 1A This is a cross-sectional view showing the schematic cross-sectional structure of a detection device with an illumination device that has the detection apparatus according to the first embodiment.

[0013] Figure 1B This is a cross-sectional view showing the schematic cross-sectional structure of a detection device with an illumination device that has the detection apparatus involved in Modified Example 1.

[0014] Figure 1C This is a cross-sectional view showing the schematic cross-sectional structure of a detection device with an illumination device that has the detection apparatus involved in Modified Example 2.

[0015] Figure 1D This is a cross-sectional view showing the schematic cross-sectional structure of a detection device with an illumination device that has the detection apparatus involved in Modified Example 3.

[0016] Figure 2 This is a top view showing the detection device according to the first embodiment.

[0017] Figure 3 This is a block diagram illustrating a structural example of the detection device according to the first embodiment.

[0018] Figure 4 This is a circuit diagram representing the detection element.

[0019] Figure 5 It is a timing waveform diagram representing the action example of the detection element.

[0020] Figure 6 This is a top view showing multiple detection elements.

[0021] Figure 7 This is a top view of a photodiode, which is part of a detection element.

[0022] Figure 8 yes Figure 6 Sectional view of VIII-VIII'.

[0023] Figure 9This is a circuit diagram showing the connection relationship between the multiple detection elements, the scan line drive circuit, and the signal line selection circuit of the detection device according to the first embodiment.

[0024] Figure 10 This is a timing waveform diagram representing the action example during the reading of the detection element.

[0025] Figure 11 This is a top view showing the multiple detection elements involved in the second embodiment.

[0026] Figure 12 yes Figure 11 Sectional view of XII-XII'.

[0027] Figure 13 This is a circuit diagram illustrating the detection element involved in the second embodiment. Detailed Implementation

[0028] The embodiments for carrying out the present invention will be described in detail with reference to the accompanying drawings. This disclosure is not limited to the contents described in the following embodiments. Furthermore, the constituent elements described below include elements readily conceived by those skilled in the art, and substantially the same elements. Moreover, the constituent elements described below can be appropriately combined. In addition, this disclosure is merely an example, and content readily conceived by those skilled in the art with respect to appropriate modifications that maintain the spirit of this disclosure is naturally included within the scope of this disclosure. Furthermore, in order to make the description clearer, the drawings may schematically show the width, thickness, shape, etc., of various parts compared to the actual embodiments; however, this is merely an example and does not limit the interpretation of this disclosure. Additionally, in this disclosure and the various figures, sometimes the same reference numerals are used for elements that are the same as those previously described with respect to previously seen figures, and detailed descriptions are appropriately omitted.

[0029] In this specification and claims, when describing the arrangement of other structures on top of a certain structure, the use of the word "on" alone, unless otherwise specified, includes both the case of arranging other structures directly above a certain structure in connection with it, and the case of arranging other structures above a certain structure via another structure.

[0030] (First Implementation)

[0031] Figure 1A This is a cross-sectional view showing the schematic cross-sectional structure of a detection device with an illumination device that has the detection apparatus according to the first embodiment. Figure 1B This is a cross-sectional view showing the schematic cross-sectional structure of a detection device with an illumination device that has the detection apparatus involved in Modified Example 1. Figure 1CThis is a cross-sectional view showing the schematic cross-sectional structure of a detection device with an illumination device that has the detection apparatus involved in Modified Example 2. Figure 1D This is a cross-sectional view showing the schematic cross-sectional structure of a detection device with an illumination device that has the detection apparatus involved in Modified Example 3.

[0032] like Figure 1A As shown, the detection device 120 with illumination includes a detection device 1 and an illumination device 121. The detection device 1 includes an array substrate 2, an optical filter 7, an adhesive layer 125, and a cover member 122. That is, the array substrate 2, the optical filter 7, the adhesive layer 125, and the cover member 122 are sequentially stacked in a direction perpendicular to the surface of the array substrate 2. The adhesive layer 125 only needs to be light-transmitting and to bond the optical filter 7 to the cover member 122. Alternatively, the adhesive layer 125 may not be present in the area corresponding to the detection area AA. In the case where the adhesive layer 125 is absent in the detection area AA, the adhesive layer 125 bonds the cover member 122 to the optical filter 7 in the peripheral area GA corresponding to the outer side of the detection area AA, resulting in a structure where an air layer is provided in the detection area AA. In addition, the adhesive layer 125 provided in the detection area AA can also be simply referred to as a protective layer for the optical filter 7.

[0033] exist Figure 1A In this illumination device 121, the lighting device 121 is a so-called side-lit type front light, which has a light guide plate that also serves as a detection device 1 and multiple light sources 123 arranged side-by-side at one or both ends of the cover member 122 (light guide plate). The cover member 122 has a light irradiation surface 121a. According to this illumination device 121, light L1 is irradiated from the light irradiation surface 121a of the cover member 122 onto the finger Fg, which is the object to be detected. As a light source, for example, a light-emitting diode (LED) that emits light of a specified color is used.

[0034] In addition, such as Figure 1B As shown, the lighting device 121 may also have one or more light sources (e.g., LEDs) directly above the detection area AA of the detection device 1, and the lighting device 121 with light sources also functions as a cover component 122.

[0035] In addition, the lighting device 121 is not limited to Figure 1B Examples, such as Figure 1C As shown, the light source can be placed on the side or above the cover component 122, or the light L1 can be shone on the finger Fg from the side or above.

[0036] Furthermore, such as Figure 1DAs shown, the lighting device 121 can also be a so-called direct-down backlight with a light source (e.g., an LED) located in the detection area of ​​the detection device 1. In this case, the light guide plate of the lighting device 121 becomes a different component from the cover component 122 of the detection device 1 and is disposed below the detection device 1.

[0037] Light L1 emitted from the illumination device 121 is reflected as light L2 by the finger Fg, which is the object of detection. The detection device 1 detects the surface irregularities (e.g., fingerprints) of the finger Fg by detecting the light L2 reflected by the finger Fg (the shadow of light L2 or the intensity of the reflected light). Furthermore, in addition to detecting fingerprints, the detection device 1 can also detect bio-related information by detecting the light L2 reflected from inside the finger Fg. Bio-related information includes, for example, vascular images such as veins, pulse, and pulse waves. The color of the light L1 from the illumination device 121 can also vary depending on the object of detection. In addition, in this embodiment, the detection device 1 uses the finger Fg (fingerprint) as the object of detection, but the object of detection is not limited to the finger Fg; any part of a biological body such as the palm, wrist, or foot is acceptable.

[0038] The cover component 122 is used to protect the array substrate 2 and the optical filter 7, covering both. As described above, the cover component 122 can also be configured to serve as a light guide plate for the illumination device 121. Figure 1C as well as Figure 1D In the configuration shown where the cover component 122 is separated from the illumination device 121, the cover component 122 is, for example, a glass substrate. However, the cover component 122 is not limited to a glass substrate; it can also be a resin substrate, a resin film, or a multilayer structure composed of these substrates or films stacked together. Alternatively, the cover component 122 may not be provided. In this case, a protective layer such as an insulating film is provided on the surface of the array substrate 2 and the optical filter 7, and the finger Fg contacts the protective layer of the detection device 1.

[0039] The optical filter 7 directs the component of light L2 reflected by the object being detected, such as a finger Fg, that travels in the third direction Dz toward the photodiode 30 (see reference) on the array substrate 2. Figure 6 , Figure 7 An optical filter 7 is an optical element that allows light to pass through and blocks light from components traveling in the oblique direction. It is also called a collimating aperture or collimator. Alternatively, an optical filter 7 may not be provided.

[0040] In addition, such as Figure 1BAs shown, the detection device 120 with illumination can also replace illumination device 121 with display panel 126. Display panel 126 can be, for example, an organic EL display panel (OLED, Organic Light Emitting Diode) or an inorganic EL display panel (micro-LED, mini-LED). Alternatively, display panel 126 can be a liquid crystal display panel (LCD, Liquid Crystal Display) using liquid crystal elements as display elements, or an electrophoretic display panel (EPD, Electrophoretic Display) using electrophoretic elements as display elements. In this case, the display light (light L1) irradiated from display panel 126 is reflected by finger Fg, and the reflected light passes through display panel 126 to reach optical filter 7. Therefore, it is preferable that display panel 126 has a light-transmitting portion composed of a light-transmitting substrate and laminated films, at least in the detection area AA. Then, based on this light L2, fingerprints and biometric information of finger Fg can be detected.

[0041] Figure 2 This is a top view showing the detection device according to the first embodiment. Furthermore, Figure 2 The first direction Dx shown below is a direction in a plane parallel to the substrate 21. The second direction Dy is a direction in a plane parallel to the substrate 21 and is orthogonal to the first direction Dx. Alternatively, the second direction Dy may not be orthogonal to the first direction Dx. The third direction Dz is a direction orthogonal to both the first direction Dx and the second direction Dy, and is the normal direction of the substrate 21. Furthermore, the top view shows the positional relationship when viewed from a third-party direction towards Dz.

[0042] like Figure 2 As shown, the detection device 1 includes an array substrate 2 (substrate 21), a sensor unit 10, a scan line drive circuit 15, a signal line selection circuit 16, a detection circuit 48, a control circuit 102, and a power supply circuit 103.

[0043] The control board 101 is electrically connected to the substrate 21 via a wiring board 110. The wiring board 110 is, for example, a flexible printed circuit board or a rigid substrate. A detection circuit 48 is provided on the wiring board 110. The control board 101 includes a control circuit 102 and a power supply circuit 103. The control circuit 102 is, for example, an FPGA (Field Programmable Gate Array) or other IC chip. The control circuit 102 supplies control signals to the sensor unit 10, the scan line drive circuit 15, and the signal line selection circuit 16 to control the operation of the sensor unit 10. The power supply circuit 103 transmits power supply potential VDD and reference potential VCOM (referencing...) to the sensor unit 21. Figure 4The voltage signal is supplied to the sensor unit 10, the scan line drive circuit 15, and the signal line selection circuit 16. Furthermore, in this embodiment, the detection circuit 48 is illustrated as being disposed on the wiring substrate 110, but it is not limited thereto. The detection circuit 48 may also be disposed on the substrate 21. Additionally, a structure in which part or all of the control circuit 102 and the power supply circuit 103 are assembled within the detection circuit 48 may also be used.

[0044] The substrate 21 has a detection area AA and a peripheral area GA. Each element (detection element 3) of the sensor unit 10 is disposed within the detection area AA. The peripheral area GA is the area outside the detection area AA, where no elements (detection elements 3) are disposed. That is, the peripheral area GA is the area between the outer periphery of the detection area AA and the outer edge of the substrate 21. A scan line drive circuit 15 and a signal line selection circuit 16 are disposed within the peripheral area GA. The scan line drive circuit 15 is disposed along one of the left or right sides of the detection area AA in a region extending in the second direction Dy within the peripheral area GA. Alternatively, the scan line drive circuit 15 may be disposed on both sides of the detection area AA along the second direction Dy, as described later. The signal line selection circuit 16 is disposed along the lower edge of the detection area AA, between the sensor unit 10 and the detection circuit 48.

[0045] The sensor unit 10 comprises multiple detection elements 3, each having one or more photodiodes 30 as a photosensitive element. The photodiode 30 is a photoelectric conversion element that outputs an electrical signal corresponding to the light it is respectively illuminated. More specifically, the photodiode 30 is a PIN (Positive Intrinsic Negative) photodiode. Alternatively, the photodiode 30 may also be referred to as an OPD (Organic Photo Diode). The detection elements 3 are arranged in a matrix in the detection area AA. The photodiode 30 of each detection element 3 is detected according to a gate drive signal (e.g., reset control signal RST, read control signal RD) supplied from the scan line drive circuit 15. Each photodiode 30 causes a change in its electrical signal according to the light it is respectively illuminated, and this change in electrical signal is output to the signal line selection circuit 16 as a detection signal Vdet from each detection element 3. The detection device 1 detects information related to the organism based on the detection signals Vdet from each detection element 3.

[0046] Figure 3 This is a block diagram illustrating a structural example of the detection device according to the first embodiment. For example... Figure 3As shown, the detection device 1 includes a detection control circuit 11 and a detection unit 40. Some or all of the functions of the detection control circuit 11 are included in the control circuit 102. Similarly, some or all of the functions of the detection unit 40 other than the detection circuit 48 are included in the control circuit 102.

[0047] The detection control circuit 11 supplies control signals to the scan line drive circuit 15, the signal line selection circuit 16, and the detection unit 40, and controls their operation. The detection control circuit 11 supplies various control signals, such as the start signal STV and the clock signal CK, to the scan line drive circuit 15. Additionally, the detection control circuit 11 supplies various control signals, such as the selection signal ASW, to the signal line selection circuit 16.

[0048] The scan line drive circuit 15 drives multiple scan lines based on various control signals (read control scan line GLrd, reset control scan line GLrst (refer to...)). Figure 4 The scan line drive circuit 15 selects multiple scan lines sequentially or simultaneously, supplying gate drive signals (e.g., reset control signal RST, read control signal RD) to the selected scan lines. Thus, the scan line drive circuit 15 selects the detection element 3 connected to the scan line.

[0049] Signal line selection circuit 16 selects multiple output signal lines SL sequentially or simultaneously (see reference). Figure 4 The switching circuit is as follows: The signal line selection circuit 16 is, for example, a multiplexer. The signal line selection circuit 16 connects the selected output signal line SL to the detection circuit 48 based on the selection signal ASW supplied from the detection control circuit 11. Thus, the signal line selection circuit 16 outputs the detection signal Vdet of the photodiode 30 to the detection unit 40.

[0050] The detection unit 40 includes a detection circuit 48, a signal processing circuit 44, a coordinate extraction circuit 45, a storage circuit 46, and a detection timing control circuit 47. The detection timing control circuit 47 controls the detection circuit 48, the signal processing circuit 44, and the coordinate extraction circuit 45 to operate synchronously based on the control signal supplied from the detection control circuit 11.

[0051] The detection circuit 48 is, for example, an analog front-end circuit (AFE). The detection circuit 48 is a signal processing circuit that at least has the functions of a detection signal amplification circuit 42 and an A / D conversion circuit 43. The detection signal amplification circuit 42 is a circuit that amplifies the detection signal Vdet, for example, an integrating circuit. The A / D conversion circuit 43 converts the analog signal output from the detection signal amplification circuit 42 into a digital signal.

[0052] The signal processing circuit 44 is a logic circuit that detects a specified physical quantity input to the sensor unit 10 based on the output signal of the detection circuit 48. The signal processing circuit 44 can detect the surface features (fingerprints, palm prints) of the finger Fg and the palm based on the signal from the detection circuit 48 when the finger Fg contacts or approaches the detection surface. Furthermore, the signal processing circuit 44 can also detect bio-related information based on the signal from the detection circuit 48. Bio-related information includes, for example, the vascular image of the finger Fg and the palm, pulse wave, pulse rate, and blood oxygen saturation.

[0053] The storage circuit 46 temporarily stores the signal processed by the signal processing circuit 44. The storage circuit 46 can also be, for example, RAM (Random Access Memory), register circuit, etc.

[0054] The coordinate extraction circuit 45 combines the detection signals Vdet output from each detection element 3 of the sensor unit 10 to generate two-dimensional information representing the shape of the surface of the finger Fg, etc. Alternatively, the coordinate extraction circuit 45 can output the detection signal Vdet as the sensor output Vo without calculating the detection coordinates.

[0055] Next, the circuit structure of the detection device 1 will be described as an example. Figure 4 This is a circuit diagram representing the detection element. For example... Figure 4 As shown, the detection element 3 includes a photodiode 30, a reset transistor Mrst, a readout transistor Mrd, and a source follower transistor Msf. The reset transistor Mrst, the readout transistor Mrd, and the source follower transistor Msf are arranged corresponding to a photodiode 30. The reset transistor Mrst, the readout transistor Mrd, and the source follower transistor Msf are each constructed from n-type TFTs (Thin Film Transistors). However, this is not a limitation; each transistor may also be constructed from a p-type TFT. Furthermore, in... Figure 4 A photodiode 30 is shown, but the detection element 3 may also have a structure with multiple photodiodes 30 as described later. Alternatively, these multiple photodiodes 30 can be understood as a single photodiode 30 by connecting them in parallel (in this case, the multiple photodiodes 30 will be described as partial photodiodes 30S as shown below).

[0056] A reference potential VCOM is applied to the anode of photodiode 30. The cathode of photodiode 30 is connected to node N1. Node N1 is connected to capacitor Cs, one of the source or drain terminals of reset transistor Mrst, and the gate of source follower transistor Msf. Furthermore, parasitic capacitances Cp and C1, and input capacitances Crst and Csf exist at node N1. When light is incident on photodiode 30, the signal (charge) output from photodiode 30 is stored in capacitor Cs.

[0057] Here, the capacitor Cs is, for example, located between the p-type semiconductor layer 33 and the n-type semiconductor layer 32 of the photodiode 30 (see reference). Figure 7 The parasitic capacitances Cp and C1 are capacitances added to the capacitor Cs, and are formed between various wirings and electrodes provided on the array substrate 2. More specifically, the parasitic capacitance C1 is the capacitance formed between the cathode (n-type semiconductor layer 32) of the photodiode 30 and the scan line (e.g., the read control scan line GLrd). In addition, the input capacitances Crst and Csf are the capacitances of the reset transistor Mrst and the source follower transistor Msf as viewed from the input side, respectively, and more specifically, are the capacitances formed by combining the gate-source capacitance and the gate-drain capacitance.

[0058] The gate of the reset transistor Mrst is connected to the reset control scan line GLrst. A reset potential Vrst is supplied to either the source or drain of the reset transistor Mrst. When the reset transistor Mrst becomes on (conducting) in response to the reset control signal RST, the potential of node N1 is reset to the reset potential Vrst. The reference potential VCOM has a lower potential than the reset potential Vrst, and the photodiode 30 is reverse biased.

[0059] The source follower transistor Msf is connected between the terminal supplied with the power supply potential VDD and the readout transistor Mrd (node ​​N2). The gate of the source follower transistor Msf is connected to node N1. A signal (charge) generated by the photodiode 30 is supplied to the gate of the source follower transistor Msf. Therefore, the source follower transistor Msf outputs a voltage signal corresponding to the signal (charge) generated by the photodiode 30 to the readout transistor Mrd. Furthermore, below, a fixed potential (DC potential) with a specified potential is used as the power supply potential VDD, but a potential with an AC waveform oscillating at a specified period within a specified potential range may also be used as the power supply potential.

[0060] The read transistor Mrd is connected between the source (node ​​N2) of the source follower transistor Msf and the output signal line SL (node ​​N3). The gate of the read transistor Mrd is connected to the read control scan line GLrd. When the read transistor Mrd is turned on in response to the read control signal RD, the signal output from the source follower transistor Msf, i.e., the voltage signal corresponding to the signal (charge) occurring in the photodiode 30, is output as the detection signal Vdet to the output signal line SL.

[0061] In addition, Figure 4 In the example shown, the reset transistor Mrst and the read transistor Mrd are respectively configured as dual-gate structures formed by connecting two transistors in series. However, this is not a limitation; the reset transistor Mrst and the read transistor Mrd can be single-gate structures or multi-gate structures formed by connecting three or more transistors in series. Furthermore, the circuit of a detection element 3 is not limited to a structure having only three transistors: the reset transistor Mrst, the source follower transistor Msf, and the read transistor Mrd. The detection element 3 can also have two or four or more transistors.

[0062] Figure 5 This is a timing waveform diagram representing the operation of the detection element. For example... Figure 5 As shown, the detection element 3 performs detection in the order of reset period Prst, exposure period Pch, and readout period Pdet. The power supply circuit 103 supplies the reference potential VCOM to the anode of the photodiode 30 throughout the entire reset period Prst, exposure period Pch, and readout period Pdet.

[0063] The scan line drive circuit 15 sets the reset control signal RST supplied to the reset control scan line GLrst to high (high level voltage) at time t0, and the reset period Prst begins. During the reset period Prst, the reset transistor Mrst becomes on (conducting state), and the potential of node N1 rises to the reset potential Vrst.

[0064] At time t1, the scan line drive circuit 15 sets the read control signal RD supplied to the read control scan line GLrd to high (high level voltage). As a result, the read transistor Mrd becomes turned on (conducted state).

[0065] The scan line drive circuit 15 sets the reset control signal RST low (low-level voltage) at time t2, and the reset period ends at Prst. At time t2, the reset transistor Mrst becomes off (non-conducting state). The potential of node N1 decreases to (Vrst - ΔVn1) due to the accumulation of a signal corresponding to the light illuminating the photodiode 30. Furthermore, ΔVn1 is the signal (voltage fluctuation) corresponding to the light illuminating the photodiode 30.

[0066] At time t3, the potential of the detection signal Vdet output from the output signal line SL is (Vrst - Vthsf - Vrdon). Furthermore, Vthsf is the threshold voltage Vthsf of the source follower transistor Msf. Vrdon is the voltage drop caused by the on-resistance of the read transistor Mrd.

[0067] At time t3, the scan line drive circuit 15 sets the read control signal RD low (low level voltage). As a result, the read transistor Mrd becomes off (non-conducting state), the potential of node N2 becomes constant, and the potential of the detection signal Vdet output from the output signal line SL also becomes low (low level voltage).

[0068] At time t4, the scan line drive circuit 15 sets the read control signal RD high (high-level voltage) again. This turns on the read transistor Mrd (conducts), ending the exposure period Pch and starting the read period Pdet. During the read period, the potential of the detection signal Vdet2 output by Pdet decreases by the amount of the potential reduction signal ΔVn1 from the detection signal Vdet1 obtained at time t3, becoming (Vrst - Vthsf - Vrdon - ΔVn1).

[0069] The detection unit 40 can detect the light illuminating the photodiode 30 based on the signal (ΔVn1) representing the difference between the detection signal Vdet1 at time t3 and the detection signal Vdet2 at time t5. For example, Figure 5 The signal ΔVn1a shown is a signal (voltage variation) generated under low illuminance conditions, and the signal ΔVn1b is a signal (voltage variation) generated under high illuminance conditions. The detection device 1 can detect the intensity of light L2 based on the difference between signals ΔVn1a and ΔVn1b, unit by unit of detection element 3. By aggregating the detection results of each of the detection elements 3, it is possible to detect, for example, fingerprints, vascular images (vein patterns), etc., of fingers in contact with or near the detection surface.

[0070] In addition, Figure 5 The diagram shows an example of the operation of a detection element 3. However, the scan line drive circuit 15 can detect the entire detection area AA by sequentially scanning and resetting the control scan line GLrst and reading the control scan line GLrd in a time-division manner. Furthermore, the signal line selection circuit 16 sequentially or simultaneously selects multiple output signal lines SL and connects the selected output signal lines SL to the detection circuit 48, thereby enabling detection of the entire detection area AA by the detection element 3. The structure and operation example of the signal line selection circuit 16 will be described later.

[0071] Here, when the total capacitance attached to the photodiode 30 is defined as capacitance Cn1, capacitance Cn1 is represented by the following equation (1). Furthermore, capacitance Cs, parasitic capacitance Cp, input capacitance Crst, and Csf are related to... Figure 4 Various capacitors are equivalently connected to the cathode (node ​​N1) of the aforementioned photodiode 30.

[0072] Cn1=Cs+Crst+Csf+Cp+C1...(1)

[0073] The signal ΔVn1 is represented by the following equation (2). In addition, ΔQ represents the charge accumulated in Pch during the exposure period, Ip represents the photocurrent flowing according to the light irradiated onto the photodiode 30, and T represents the exposure time (the period from time t3 to time t4).

[0074] ΔVn1=ΔQ / Cn1=(Ip×T) / Cn1...(2)

[0075] As shown in equation (2), by decreasing the capacitance Cn1, the signal ΔVn1 can be increased. That is, even when the same object is detected under the same detection conditions, the detection sensitivity of the detection device 1 can be improved by decreasing the capacitance Cn1. Alternatively, by decreasing the deviation of the capacitance Cn1, the deviation of the signal ΔVn1 can be reduced. That is, by suppressing the parasitic capacitance C1, the detection deviation of the detection device 1 can be suppressed.

[0076] Next, the planar structure and cross-sectional structure of the detection element 3 will be described. Figure 6 This is a top view showing multiple detection elements. Furthermore, in Figure 6 In order to make it easier to observe the attached diagram, the structure of the photodiode 30 and a portion of each transistor has been omitted.

[0077] like Figure 6 As shown, a detection element 3 includes two scan lines (read control scan line GLrd and reset control scan line GLrst) and four signal lines (output signal line SL, power signal line SLsf, reset signal line SLrst, and reference signal line SLcom). The detection element 3 also includes a first shielded wiring SLsf-a and a second shielded wiring SLrst-a.

[0078] The read control scan line GLrd and the reset control scan line GLrst are configured to extend along the first direction Dx and be arranged side by side along the second direction Dy. The output signal line SL, the power signal line SLsf, the reset signal line SLrst, and the reference signal line SLcom are configured to extend along the second direction Dy and be arranged side by side along the first direction Dx.

[0079] The detection element 3 is defined by an area enclosed by two scan lines (read control scan line GLrd and reset control scan line GLrst) and two signal lines (e.g., two power signal lines SLsf of adjacent detection elements 3).

[0080] like Figure 6 As shown, photodiode 30 has multiple partial photodiodes 30S-1, 30S-2, ..., 30S-8. The partial photodiodes 30S-1, 30S-2, ..., 30S-8 are arranged in a triangular lattice shape.

[0081] More specifically, some photodiodes 30S-1, 30S-2, and 30S-3 are arranged along the second direction Dy. Some photodiodes 30S-4 and 30S-5 are arranged along the second direction Dy, adjacent to the element column formed by some photodiodes 30S-1, 30S-2, and 30S-3 in the first direction Dx. Some photodiodes 30S-6, 30S-7, and 30S-8 are arranged along the second direction Dy, adjacent to the element column formed by some photodiodes 30S-4 and 30S-5 in the first direction Dx. Among adjacent element columns, the positions of some photodiodes 30S in the second direction Dy are configured to be distinct.

[0082] Light L2 passes through optical filter 7 and is incident on partial photodiodes 30S-1, 30S-2, ..., 30S-8 respectively. Partial photodiodes 30S-1, 30S-2, ..., 30S-8 are electrically connected and function as a single photodiode 30. That is, the signals output by each of partial photodiodes 30S-1, 30S-2, ..., 30S-8 are combined and a detection signal Vdet is output from photodiode 30. Furthermore, in the following description, unless it is necessary to distinguish between partial photodiodes 30S-1, 30S-2, ..., 30S-8, they will only be referred to as partial photodiode 30S.

[0083] like Figure 6 As shown, power signal lines SLsf, output signal lines SL, reset signal lines SLrst, reference signal lines SLcom, power signal lines SLsf, ... are arranged sequentially and repeatedly along the first direction Dx. Some photodiodes 30S-1, 30S-2, and 30S-3 are positioned along the first direction Dx between the reference signal line SLcom and the power signal line SLsf connected to the adjacent detection element 3. Some photodiodes 30S-4, 30S-5, ..., 30S-8 are positioned along the first direction Dx between the output signal line SL and the reset signal line SLrst. Furthermore, some photodiodes 30S are positioned along the second direction Dy between the read control scan line GLrd and the reset control scan line GLrst.

[0084] The first shielding wiring SLsf-a and the second shielding wiring SLrst-a overlap with the read control scan line GLrd and extend along the first direction Dx. The first shielding wiring SLsf-a and the second shielding wiring SLrst-a are located on the same layer as each signal line (power signal line SLsf, output signal line SL, reset signal line SLrst, and reference signal line SLcom), and are electrically connected to the signal lines that supply a fixed potential (power potential VDD or reset potential Vrst) to each transistor. Thus, a predetermined fixed potential is supplied to the first shielding wiring SLsf-a and the second shielding wiring SLrst-a.

[0085] More specifically, the first shielded wiring SLsf-a is connected to the power signal line SLsf and extends in a direction intersecting the power signal line SLsf (first direction Dx). A signal having the same potential (power potential VDD) as the power signal line SLsf is supplied to the first shielded wiring SLsf-a. The first shielded wiring SLsf-a includes a portion extending from the power signal line SLsf towards the first direction Dx. Figure 6 The portion extending to the right (in the +Dx direction) and the portion extending towards the other side of the first direction Dx ( Figure 6 The portion extending to the left (in the -Dx direction). Therefore, the first shielding wiring SLsf-a extends to one side of the first direction Dx ( Figure 6 The right side covers the read control scan line GLrd located between the power signal line SLsf and the output signal line SL, and on the other side of the first direction Dx ( Figure 6 The left side covers the read control scan line GLrd located between the power signal line SLsf and the reference signal line SLcom. Additionally, the first shielded wiring SLsf-a is configured to be separate from the output signal line SL and the reference signal line SLcom.

[0086] The second shielded wiring SLrst-a is connected to the reset signal line SLrst and extends along the direction intersecting the reset signal line SLrst, i.e., the first direction Dx. A signal with the same potential as the reset signal line SLrst (reset potential Vrst) is supplied to the second shielded wiring SLrst-a. The second shielded wiring SLrst-a extends to the other side of the first direction Dx (… Figure 6 The left-side shielding extends to cover the read control scan line GLrd located between the reset signal line SLrst and the output signal line SL. Additionally, the second shielding wiring SLrst-a is configured to be separate from the output signal line SL.

[0087] In other words, the output signal line SL, which outputs the detection signal Vdet from the photodiode 30, is positioned between the first shielded wiring SLsf-a and the second shielded wiring SLrst-a in the first direction Dx, and is set to be separate from both the first shielded wiring SLsf-a and the second shielded wiring SLrst-a. Additionally, the reference signal line SLcom, which supplies the reference potential VCOM to the photodiode 30, is positioned between the first shielded wiring SLsf-a and the second shielded wiring SLrst-a in the first direction Dx, and is set to be separate from both the first shielded wiring SLsf-a and the second shielded wiring SLrst-a.

[0088] Furthermore, the width of the first shielding wiring SLsf-a and the second shielding wiring SLrst-a in the second direction Dy is greater than the width of the read control scan line GLrd in the second direction Dy. A recessed portion SLsf-b, which is recessed in the width direction (second direction Dy), is formed in the first shielding wiring SLsf-a in the region adjacent to a portion of the photodiode 30S-3. Similarly, a recessed portion SLrst-b, which is recessed in the width direction (second direction Dy), is formed in the second shielding wiring SLrst-a in the region adjacent to a portion of the photodiode 30S-8. Thus, the first shielding wiring SLsf-a and the second shielding wiring SLrst-a are designed not to overlap with the portion of the photodiode 30S, thereby suppressing short circuits with the portion of the photodiode 30S.

[0089] A branch GLrd-a extending along the second direction Dy is connected to the read control scan line GLrd, and the gate electrode 84 of the read transistor Mrd is connected to the branch GLrd-a (see reference). Figure 7 The branch GLrd-a is configured to overlap with the power signal line SLsf.

[0090] The power signal line SLsf has a widened portion SLsf-c, which has a wider width in the portion overlapping with the branch GLrd-a than in the portion not overlapping with the branch GLrd-a. Thus, the entire branch GLrd-a is covered by the widened portion SLsf-c.

[0091] With this configuration, the first shielding wiring SLsf-a is configured to cover the read control scan line GLrd and is supplied with a fixed potential from the power signal line SLsf. The second shielding wiring SLrst-a is configured to cover the read control scan line GLrd and is supplied with a fixed potential from the reset signal line SLrst. The first shielding wiring SLsf-a and the second shielding wiring SLrst-a cover most of the area of ​​the read control scan line GLrd.

[0092] Therefore, it is possible to suppress the parasitic capacitance C1 formed between the read control scan line GLrd and the photodiode 30 (especially some photodiodes 30S-3 and 30S-8) (refer to...). Figure 4 As a result, as shown in equation (2) above, the detection sensitivity of the detection device 1 can be improved. Even when the potential of the read control scan line GLrd changes due to the supply of the read control signal RD to the read control scan line GLrd, the parasitic capacitance C1 can be suppressed, thus suppressing the potential change of node N1 (cathode of photodiode 30). In addition, the deviation of the parasitic capacitance C1 caused by the deviation of the configuration relationship (distance) between the read control scan line GLrd and the plurality of partial photodiodes 30S can be suppressed, and as a result, the detection deviation of the detection device 1 can be suppressed.

[0093] Next, the detailed structure of the photodiode 30 and each transistor will be explained. Figure 7 This is a top view of a photodiode, a component of a detection element. Figure 7 In the image, a magnified view shows the planar structure of the photodiode 30 and the transistors of the detection element 3. Furthermore, in... Figure 7 In the middle, the opening OP1, which is arranged overlapping with some of the photodiodes 30S-1, 30S-2, ..., 30S-8, corresponds to the light guide part of the optical filter 7 (refer to the figures in Figure 1), and light L2 is irradiated in the area that overlaps with the opening OP1.

[0094] Some photodiodes 30S include an i-type semiconductor layer 31, an n-type semiconductor layer 32, and a p-type semiconductor layer 33. The i-type semiconductor layer 31 and the n-type semiconductor layer 32 are, for example, amorphous silicon (a-Si). The p-type semiconductor layer 33 is, for example, polycrystalline silicon (p-Si). Furthermore, the material of the semiconductor layer is not limited to these, and can also be polycrystalline silicon, microcrystalline silicon, etc.

[0095] The n-type semiconductor layer 32 is formed by doping impurities in a-Si to create an n+ region. The p-type semiconductor layer 33 is formed by doping impurities in p-Si to create a p+ region. The i-type semiconductor layer 31 is, for example, an undoped intrinsic semiconductor with lower conductivity than the n-type semiconductor layer 32 and the p-type semiconductor layer 33.

[0096] In addition, Figure 7 In the diagram, the first region R1, which serves as an effective sensor region, is represented by a dashed line. This region comprises an overlapping and directly connected p-type semiconductor layer 33, an i-type semiconductor layer 31 (and an n-type semiconductor layer 32). Some photodiodes 30S are configured to have at least the first region R1. In other words, multiple (in...) Figure 7 The first region R1 (which consists of eight sections) is arranged in a triangular lattice shape when viewed from above. The opening OP1 of the optical filter 7 is set to overlap with the first region R1.

[0097] When viewed from above, some of the photodiodes 30S are formed in a circular or semi-circular shape. However, they are not limited to this; some of the photodiodes 30S can also be polygonal or the like. Furthermore, multiple photodiodes 30S can have different shapes.

[0098] The n-type semiconductor layers 32 of some photodiodes 30S-1, 30S-2, and 30S-3 arranged in the second direction Dy are electrically connected through the connecting portion CA1. The p-type semiconductor layers 33 of some photodiodes 30S-1, 30S-2, and 30S-3 are electrically connected through the connecting portion CA2.

[0099] Furthermore, the n-type semiconductor layer 32 (i-type semiconductor layer 31) of some photodiodes 30S-4, 30S-5, 30S-6, 30S-7, and 30S-8 is electrically connected via base BA1. The p-type semiconductor layer 33 of some photodiodes 30S-4, 30S-5, 30S-6, 30S-7, and 30S-8 is electrically connected via base BA2. Bases BA1 and BA2 are formed in a generally pentagonal shape, with some photodiodes 30S-4, 30S-5, 30S-6, 30S-7, and 30S-8 located at their vertices. However, bases BA1 and BA2 are not limited to a continuously formed pentagonal shape and can be other shapes. Bases BA1 and BA2 may also be formed in a ring shape in the central portion, without forming the n-type semiconductor layer 32 and the p-type semiconductor layer 33.

[0100] The base BA1 is configured to be separated from the i-type semiconductor layer 31 and n-type semiconductor layer 32 of some photodiodes 30S-1, 30S-2, and 30S-3 along the first direction Dx. On the other hand, the base BA2, which is connected to the p-type semiconductor layer 33 of some photodiodes 30S-4, 30S-5, 30S-6, 30S-7, and 30S-8, and the p-type semiconductor layer 33 of some photodiodes 30S-1, 30S-2, and 30S-3, are electrically connected via a connection CA2a below the reset signal line SLrst and the reference signal line SLcom along the first direction Dx. Thus, multiple photodiodes 30S constituting one photodiode 30 are electrically connected.

[0101] A lower conductive layer 35 is disposed in the region overlapping with a portion of the photodiode 30S, the connecting portions CA1, CA2, CA2a, and the bases BA1, BA2. The portion of the lower conductive layer 35 overlapping with the portion of the photodiode 30S is formed in a circular shape. However, the lower conductive layer 35 may also have a different shape than the portion of the photodiode 30S. Furthermore, the lower conductive layer 35 need only be disposed in the portion overlapping at least with the first region R1. A reference potential VCOM, the same as that of the p-type semiconductor layer 33, is supplied to the lower conductive layer 35 to suppress parasitic capacitance between the lower conductive layer 35 and the p-type semiconductor layer 33.

[0102] The upper conductive layer 34 electrically connects the n-type semiconductor layers 32 of the plurality of partial photodiodes 30S. Specifically, the upper conductive layer 34, at the position overlapping with the partial photodiodes 30S-1 and 30S-3, is connected via an insulating film 27 (see reference). Figure 8 The contact holes H1 and H2 of the upper conductive layer 34 are electrically connected to each n-type semiconductor layer 32. The connecting portion 34a of the upper conductive layer 34 overlaps with the connecting portions CA1, CA2, CA2a and part of the photodiode 30S-2 to form a T-shape, and is connected to the connecting portion 34b. In addition, the connecting portion 34b of the upper conductive layer 34 overlaps with the base BA1 via the insulating film 27 (see reference). Figure 8 The contact hole H3 is electrically connected to the n-type semiconductor layer 32 of the base BA1.

[0103] Furthermore, the upper conductive layer 34 extends from the connection portion 34b to the region that does not overlap with the photodiode 30, and connects to the connection portion 34c. The connection portion 34c of the upper conductive layer 34 connects to each transistor (reset transistor Mst and source follower transistor Msf) via the contact hole H4. Figure 4 Electrical connection. Furthermore, the upper conductive layer 34 can be arbitrarily configured; for example, it can be configured to cover a portion of the photodiode 30S, or it can be configured to cover the entire photodiode 30S.

[0104] The reset transistor Mrst, the source follower transistor Msf, and the readout transistor Mrd are located in a region that does not overlap with the photodiode 30. The source follower transistor Msf and the readout transistor Mrd are positioned, for example, adjacent to the photodiode 30 in the first direction Dx. Furthermore, the reset transistor Mrst is configured to be adjacent to a portion of the photodiode 30S-4 in the second direction Dy, and is positioned in the first direction Dx between a portion of the photodiodes 30S-1 and a portion of the photodiodes 30S-6.

[0105] One end of the semiconductor layer 61 of the reset transistor Mrst is connected to the reset signal line SLrst. The other end of the semiconductor layer 61 is connected to the connection wiring SLcn3 (node ​​N1) via a contact hole. The portion of the reset signal line SLrst connected to the semiconductor layer 61 functions as the source electrode, and the portion of the connection wiring SLcn3 connected to the semiconductor layer 61 functions as the drain electrode 63. The semiconductor layer 61 is formed in a U-shape, intersecting with the reset control scan line GLrst at two locations. A channel region is formed in the portion of the semiconductor layer 61 that overlaps with the reset control scan line GLrst, and the portions of the reset control scan line GLrst that overlap with the semiconductor layer 61 function as gate electrodes.

[0106] The source follower transistor Msf has a semiconductor layer 65, a source electrode 66, a drain electrode 67, and a gate electrode 68. One end of the semiconductor layer 65 is connected to the power signal line SLsf via a contact hole. The other end of the semiconductor layer 65 is connected to the connection wiring SLcn1 (node ​​N2) via a contact hole. The portion of the power signal line SLsf connected to the semiconductor layer 65 functions as the drain electrode 67, and the portion of the connection wiring SLcn1 connected to the semiconductor layer 65 functions as the source electrode 66.

[0107] One end of the gate electrode 68 extends along the first direction Dx and overlaps with the semiconductor layer 65. The other end of the gate electrode 68 extends along the second direction Dy and is electrically connected to the connection wiring SLcn3. Thus, the reset transistor Mrst is electrically connected to the gate of the source follower transistor Msf via the connection wiring SLcn3.

[0108] The read transistor Mrd has a semiconductor layer 81, a source electrode 82, a drain electrode 83, and a gate electrode 84. One end of the semiconductor layer 81 is connected via a contact hole H16 (see reference). Figure 8 And connected to the connection wiring SLcn1. The other end of the semiconductor layer 81 is connected via contact hole H15 (see reference). Figure 8 The connection is made to the connection wiring SLcn2, which branches from the output signal line SL in the first direction Dx. The portion of the connection wiring SLcn1 that connects to the semiconductor layer 81 functions as the drain electrode 83, and the portion of the connection wiring SLcn2 that connects to the semiconductor layer 81 functions as the source electrode 82. Two gate electrodes 84 are arranged side by side in the second direction Dy and overlap with the semiconductor layer 81. The two gate electrodes 84 are connected via a branch GLrd-a extending along the second direction Dy and overlapping with the power signal line SLsf (see reference). Figure 6 It is electrically connected to the read control scan line GLrd. In this structure, the source follower transistor Msf and the read transistor Mrd are connected to the output signal line SL.

[0109] The output signal line SL is positioned between the source follower transistor Msf, the readout transistor Mrd, and some photodiodes 30S-6, 30S-7, and 30S-8. The output signal line SL is arranged in a zigzag pattern along some photodiodes 30S-6, 30S-7, and 30S-8.

[0110] The reset signal line SLrst and the reference signal line SLcom are disposed between some photodiodes 30S-1, 30S-2, and 30S-3 and some photodiodes 30S-4 and 30S-5. The reset signal line SLrst and the reference signal line SLcom are arranged in a zigzag pattern along some photodiodes 30S and intersect with the connecting part CA2a. Since some photodiodes 30S-1, 30S-2, and 30S-3 and some photodiodes 30S-4 and 30S-5 are connected through the connecting part CA2a, the parasitic capacitance of the reset signal line SLrst and the reference signal line SLcom can be suppressed compared to the structure in which the bases BA1 and BA2 are overlapped with the reset signal line SLrst and the reference signal line SLcom.

[0111] The reference signal line SLcom is electrically connected to the lower conductive layer 35 via contact hole H11. Additionally, the reference signal line SLcom is electrically connected to the connecting portion CA2 via contact hole H12. Thus, the reference signal line SLcom is electrically connected to the p-type semiconductor layer 33 of each photodiode 30S.

[0112] In this embodiment, each of the plurality of openings OP1 in the optical filter 7 is provided with a partial photodiode 30S. Therefore, since the area of ​​the photodiode 30 in the region not directly illuminated by light, i.e., the area of ​​the three-layer structure constituting the photodiode 30, is reduced, parasitic capacitance of the photodiode 30 can be suppressed. Furthermore, since the structure distributes the plurality of partial photodiodes 30S within the element, the flexibility in the arrangement of transistors and wiring is increased, and transistors and wiring are arranged to be as non-overlapping as possible with the photodiode 30. Therefore, in this embodiment, compared to the case where the photodiode 30 is arranged to overlap with transistors and wiring, parasitic capacitance of the photodiode 30 can be suppressed.

[0113] also, Figure 6 The planar configuration of the photodiode 30 and each transistor shown is merely an example and can be modified accordingly. For instance, the number of partial photodiodes 30S in a single photodiode 30 can be seven or fewer, or nine or more. The arrangement of the partial photodiodes 30S is not limited to a triangular lattice pattern; for example, it can also be configured in a matrix pattern.

[0114] Figure 8 yes Figure 6 Sectional view VIII-VIII'. Furthermore, in Figure 8 The diagram shows cross-sectional structures of some photodiodes 30S-1, 30S-2, and 30S-7, and also shows a cross-sectional structure of the readout transistor Mrd of the detection element 3. Furthermore, in... Figure 8 The cross-sectional structures of the source follower transistor Msf and the reset transistor Mrst, which are not shown in the figure, are the same as those of the read transistor Mrd.

[0115] like Figure 8 As shown, substrate 21 is an insulating substrate, such as a glass substrate made of quartz or alkali-free glass, or a resin substrate made of polyimide. Gate electrode 84 is disposed on substrate 21. Insulating films 22 and 23 cover gate electrode 84 and are disposed on substrate 21. Insulating films 22, 23, 24, 25, and 26 are inorganic insulating films, such as silicon oxide (SiO2) or silicon nitride (SiN).

[0116] Semiconductor layer 81 is disposed on insulating film 23. Semiconductor layer 81 may be polycrystalline silicon, for example. However, semiconductor layer 81 is not limited to this, and may also be microcrystalline oxide semiconductor, amorphous oxide semiconductor, low-temperature polycrystalline silicon (LTPS), etc. The read transistor Mrd has a bottom gate structure with gate electrode 84 disposed on the lower side of semiconductor layer 81, but may also have a top gate structure with gate electrode 84 disposed on the upper side of semiconductor layer 81, or a dual gate structure with gate electrode 84 disposed on both the upper and lower sides of semiconductor layer 81.

[0117] Insulating films 24 and 25 cover the semiconductor layer 81 and are disposed on the insulating film 23. A source electrode 82 and a drain electrode 83 are disposed on the insulating film 25. The source electrode 82 is connected to a high-concentration impurity region of the semiconductor layer 81 via a contact hole H15. Similarly, the drain electrode 83 is connected to a high-concentration impurity region of the semiconductor layer 81 via a contact hole H16. The source electrode 82 and the drain electrode 83 are, for example, composed of a TiAlTi or TiAl laminated film, which is a laminated structure of titanium and aluminum.

[0118] Next, the cross-sectional structure of the photodiode 30 will be described. Figure 8 This document describes some photodiodes 30S-1, 30S-2, and 30S-7, but the description of some photodiodes 30S-1, 30S-2, and 30S-7 can also be applied to other photodiodes 30S. For example... Figure 8As shown, the lower conductive layer 35 is disposed on the substrate 21 in the same layer as the gate electrode 84. Insulating films 22 and 23 are disposed on the lower conductive layer 35. The photodiode 30 is disposed on the insulating film 23. In other words, the lower conductive layer 35 is disposed between the substrate 21 and the p-type semiconductor layer 33. The lower conductive layer 35 functions as a light-shielding layer by being formed of the same material as the gate electrode 84, and it can suppress the intrusion of light from the substrate 21 side towards the photodiode 30.

[0119] On the third-party Dz, the i-type semiconductor layer 31 is disposed between the p-type semiconductor layer 33 and the n-type semiconductor layer 32. In this embodiment, the p-type semiconductor layer 33, the i-type semiconductor layer 31, and the n-type semiconductor layer 32 are sequentially stacked on the insulating film 23.

[0120] Specifically, the p-type semiconductor layer 33 and the semiconductor layer 81 are disposed on the insulating film 23 in the same layer. Insulating films 24, 25, and 26 are configured to cover the p-type semiconductor layer 33. Insulating films 24 and 25 have contact holes H13 at positions overlapping with the p-type semiconductor layer 33. Insulating film 26 is disposed on insulating film 25, covering the inner walls of insulating film 24 and the side surfaces of insulating film 25 that form the contact hole H13. Furthermore, a contact hole H14 is provided on insulating film 26 at a position overlapping with the p-type semiconductor layer 33.

[0121] The i-type semiconductor layer 31 is disposed on the insulating film 26 and is connected to the p-type semiconductor layer 33 through a contact hole H14 that extends from the insulating film 24 through the insulating film 26. The n-type semiconductor layer 32 is disposed on the i-type semiconductor layer 31.

[0122] More specifically, the photodiode 30 has a first region R1, a second region R2, and a third region R3. Multiple first regions R1 are configured to correspond to a portion of the photodiode 30S. The multiple first regions R1 are stacked in a manner where they are in direct contact with the p-type semiconductor layer 33, the i-type semiconductor layer 31, and the n-type semiconductor layer 32, respectively. In other words, the first region R1 is the area defined by the bottom surface of the contact hole H14.

[0123] A second region R2 is disposed between multiple first regions R1. In the second region R2, at least a p-type semiconductor layer 33 and an i-type semiconductor layer 31 are separately stacked in a direction perpendicular to the substrate 21 (third direction Dz). More specifically, the second region R2 has insulating films 24, 25, and 26 disposed between the p-type semiconductor layer 33 and the i-type semiconductor layer 31. However, this is not a limitation; the second region R2 may have one or two insulating films between the p-type semiconductor layer 33 and the i-type semiconductor layer 31, or it may have four or more insulating films.

[0124] In the second region R2, the thickness of the insulating films 24, 25, and 26 disposed between the p-type semiconductor layer 33 and the i-type semiconductor layer 31 (the total thickness of the insulating films 24, 25, and 26, ti1, and ti2, respectively) is greater than the thickness ti3 of the i-type semiconductor layer 31. The thickness ti1 of the insulating films 24 and 25 is greater than the thickness ti2 of the insulating film 26. Furthermore, the distance between the p-type semiconductor layer 33 and the n-type semiconductor layer 32 in the second region R2 is greater than the distance between the p-type semiconductor layer 33 and the n-type semiconductor layer 32 in the first region R1. Moreover, the thickness relationship of the i-type semiconductor layer 31 and each of the insulating films 24, 25, and 26 is not limited to the above; a structure in which the total thickness of the three insulating films 24, 25, and 26 is smaller than the thickness of the i-type semiconductor layer 31 can also be adopted. In the second region R2, there needs to be an insulating film 24, 25, 26 of a specified thickness between the i-type semiconductor layer 31 (and / or the n-type semiconductor layer 32) and the p-type semiconductor layer 33. On the other hand, the thickness of the insulating film 24, 25, 26 can be of various thicknesses.

[0125] The second region R2, when viewed from above, is located around the first region R1 and includes connecting portions CA1 and CA2, as well as base portions BA1 and BA2. Some photodiodes 30S-1, 30S-2, and 30S-3 are connected via connecting portion CA1, which is composed of an i-type semiconductor layer 31 and an n-type semiconductor layer 32 stacked on the insulating film 26, and connecting portion CA2, which is composed of a p-type semiconductor layer 33 formed on the insulating film 23. Similarly, some photodiodes 30S-4 to some photodiodes 30S-8 are connected via base portion BA1, which is composed of an i-type semiconductor layer 31 and an n-type semiconductor layer 32 stacked on the insulating film 26, and base portion BA2, which is composed of a p-type semiconductor layer 33 formed on the insulating film 23.

[0126] With this structure, the capacitance per unit area formed between the i-type semiconductor layer 31 and the p-type semiconductor layer 33 in the second region R2 is smaller than the capacitance per unit area formed between the i-type semiconductor layer 31 and the p-type semiconductor layer 33 in the first region R1. Therefore, compared to the case where the i-type semiconductor layer 31 and the n-type semiconductor layer 32 of the second region R2 are stacked on the p-type semiconductor layer 33 without passing through insulating films 25 and 26, as in the first region R1, the photodiode 30 of this embodiment can reduce the capacitance Cs of a single photodiode 30 (see reference). Figure 4As a result, as shown in equation (2) above, even under the same detection conditions of irradiating the same light and exposing for the same exposure time T, the signal ΔVn1 can be increased, thereby improving the detection sensitivity of the detection device 1. Furthermore, the capacitance formed between the i-type semiconductor layer 31 and the p-type semiconductor layer 33 was mentioned above. However, given that the i-type semiconductor layer 31 and the n-type semiconductor layer 32 are in direct contact, and the p-type semiconductor layer and the n-type semiconductor layer are opposite each other across the i-type semiconductor layer 31, the mention of the aforementioned capacitance can naturally be replaced by the capacitance between the p-type semiconductor layer 33 and the n-type semiconductor layer 32.

[0127] The third region R3 is provided with a p-type semiconductor layer 33, and the i-type semiconductor layer 31 and n-type semiconductor layer 32 are configured not to overlap with the p-type semiconductor layer 33. The third region R3 is a region with a connection portion CA2a formed by the aforementioned p-type semiconductor layer 33. That is, in the third region R3, adjacent first regions R1 are connected by at least the p-type semiconductor layer 33. In addition, in the third region R3, insulating films 24 and 25 are provided on the p-type semiconductor layer 33, and a reset signal line SLrst and a reference signal line SLcom are provided on the insulating films 24 and 25 provided on the p-type semiconductor layer 33. In other words, gaps SP of the i-type semiconductor layer 31 and the n-type semiconductor layer 32 are provided on the reset signal line SLrst and the reference signal line SLcom. With this structure, compared to a structure in which the i-type semiconductor layer 31 and the n-type semiconductor layer 32 are configured to overlap with the reset signal line SLrst and the reference signal line SLcom, insulation between each signal line and the n-type semiconductor layer 32 can be ensured.

[0128] An insulating film 27 is disposed on top of an insulating film 26, covering the photodiode 30. The insulating film 27 is positioned to be directly connected to both the photodiode 30 and the insulating film 26. The insulating film 27 is made of organic materials such as photosensitive acrylic acid. The insulating film 27 is thicker than the insulating film 26. Furthermore, their thicknesses can be interchanged. Compared to inorganic insulating materials, the insulating film 27 provides good coverage of the step difference and is positioned to cover the sides of the i-type semiconductor layer 31 and the n-type semiconductor layer 32.

[0129] An upper conductive layer 34 is disposed on the insulating film 27. The upper conductive layer 34 is, for example, a transparent conductive material such as ITO (Indium Tin Oxide). The upper conductive layer 34 is disposed in accordance with the surface of the insulating film 27 and is connected to the n-type semiconductor layer 32 via contact holes H1 and H3 provided in the insulating film 27. Thus, the signals (photocurrent Ip) output from the multiple partial photodiodes 30S are integrated by the common upper conductive layer 34 and transmitted via the source follower transistor Msf and the readout transistor Mrd (see reference). Figure 4 The output is a detection signal Vdet.

[0130] Furthermore, contact hole H1 is located at a position overlapping with the first region R1, and the n-type semiconductor layer 32 of some photodiodes 30S-1 is connected to the upper conductive layer 34 on the bottom surface of contact hole H1. Additionally, contact holes H1 and H3 are not formed in the first region R1 of some photodiodes 30S-2 and 30S-7. Contact hole H3 is located at a position overlapping with the second region R2. The width of the first region R1 of some photodiodes 30S-1 is greater than the width of the first region R1 of some photodiodes 30S-2 and 30S-7. However, the upper conductive layer 34 can be connected to the n-type semiconductor layer 32 at any location, and the width and shape of the first region R1 of multiple photodiodes 30S can also be formed to be equal.

[0131] An insulating film 28 is disposed on top of the upper conductive layer 34 and covers the insulating film 27. The insulating film 28 is an inorganic insulating film. The insulating film 28 is configured as a protective layer to inhibit the intrusion of moisture toward the photodiode 30.

[0132] A protective film 29 is disposed on top of the insulating film 28. The protective film 29 is an organic protective film. The protective film 29 is formed to planarize the surface of the detection device 1.

[0133] In this embodiment, since the p-type semiconductor layer 33 and the lower conductive layer 35 of the photodiode 30 are disposed on the same layer as each transistor, the manufacturing process can be simplified compared to the case where the photodiode 30 is formed on a different layer than each transistor.

[0134] also, Figure 8 The cross-sectional structure of the photodiode 30 shown is merely an example. It is not limited to this; for example, the photodiode 30 may be disposed on a different layer than the individual transistors. Furthermore, the stacking order of the p-type semiconductor layer 33, the i-type semiconductor layer 31, and the n-type semiconductor layer 32 is not limited to... Figure 8 Alternatively, the layers can be stacked in the order of n-type semiconductor layer 32, i-type semiconductor layer 31, and p-type semiconductor layer 33.

[0135] The first shielding wiring SLsf-a overlaps with the readout control scan line GLrd and is disposed on the same layer as each signal line (e.g., output signal line SL). That is, the first shielding wiring SLsf-a is disposed on the insulating film 25 and in a layer different from the i-type semiconductor layer 31 and n-type semiconductor layer 32 of the adjacent portion of the photodiode 30S. Furthermore, in Figure 8 The second shielding wiring SLrst-a is not shown in the figure, but it is also disposed on the same layer as the first shielding wiring SLsf-a on the insulating film 25.

[0136] Next, the structure and operation example of the signal line selection circuit 16 will be explained. Figure 9 This is a circuit diagram showing the connection relationship between the multiple detection elements, the scan line drive circuit, and the signal line selection circuit of the detection device according to the first embodiment. Figure 10 This is a timing waveform diagram representing the action example during the reading of the detection element.

[0137] like Figure 9 As shown, multiple detection elements 3 are arranged in the first direction Dx and the second direction Dy. The multiple detection elements 3 arranged in the first direction Dx are referred to as detection elements 3(m), 3(m+1), 3(m+2), and 3(m+3). However, unless it is necessary to distinguish between detection elements 3(m), 3(m+1), 3(m+2), and 3(m+3), they are simply referred to as detection element 3. Similarly, the output signal line SL, the read control scan line GLrd, and the reset control scan line GLrst are also represented.

[0138] like Figure 9 As shown, the detection device 1 has a first scan line driving circuit 15A and a second scan line driving circuit 15B. The read control scan lines GLrd(n) and GLrd(n+1) are connected to the first scan line driving circuit 15A. The reset control scan lines GLrst(n) and GLrst(n+1) are connected to the second scan line driving circuit 15B.

[0139] The output signal lines SL(m), SL(m+1), SL(m+2), and SL(m+3) are set to correspond to the detection elements 3(m), 3(m+1), 3(m+2), and 3(m+3), respectively.

[0140] The signal line selection circuit 16 has multiple switching elements SW(m), SW(m+1), SW(m+2), and SW(m+3). These switching elements SW(m), SW(m+1), SW(m+2), and SW(m+3) are configured to correspond to each of the multiple output signal lines SL(m), SL(m+1), SL(m+2), and SL(m+3). Specifically, the multiple switching elements SW(m), SW(m+1), SW(m+2), and SW(m+3) switch the connection and non-connection of the multiple output signal lines SL(m), SL(m+1), SL(m+2), and SL(m+3) with the detection circuit 48.

[0141] Figure 10 Magnification Figure 5 The read period shown is Pdet. Furthermore, in Figure 10 In order to facilitate understanding, the potentials Vn1 and Vn1' at node N1 are emphasized and schematically represented when each detection element 3 is irradiated with light L2 of the same intensity.

[0142] like Figure 10 As shown, the signal line selection circuit 16 is based on the selection signal ASW from the control circuit 102 (refer to...). Figure 3 Multiple switching elements SW(m), SW(m+1), SW(m+2), and SW(m+3) are sequentially set to ON (connected state) in a time-sharing manner.

[0143] During the reading period Pdet1, the switching element SW(m) is turned on, and the output signal line SL(m) is connected to the detection circuit 48. At time t41, the switching element SW(m) is turned off (not connected). After a specified period, during the reading period Pdet2, the switching element SW(m+1) is turned on, and the output signal line SL(m+1) is connected to the detection circuit 48. At time t42, the switching element SW(m+1) is turned off. After a specified period, during the reading period Pdet3, the switching element SW(m+2) is turned on, and the output signal line SL(m+2) is connected to the detection circuit 48. At time t43, the switching element SW(m+2) is turned off. After a specified period, during the reading period Pdet4, the switching element SW(m+3) is turned on, and the output signal line SL(m+3) is connected to the detection circuit 48. At time t44, the switching element SW(m+3) becomes open, ending the reading of the detection signal Vdet from the detection element 3(m).

[0144] As described above, the detection device 1 of this embodiment is provided with shielded wiring (first shielded wiring SLsf-a and second shielded wiring SLrst-a), and the parasitic capacitance C1 is suppressed (see reference). Figure 4 Therefore, the potential Vn1' at node N1 in the case of parasitic capacitance C1 due to unshielded wiring (in...) Figure 10 The time variation (represented by a double-dotted line) is suppressed, and the potential Vn1 at node N1 at times t41, t42, t43, and t44 ideally represents a constant value.

[0145] Therefore, in this embodiment, even if the timing of reading multiple detection elements 3 is deviated due to the operation of the signal line selection circuit 16, the potential fluctuation caused by the parasitic capacitance C1 can be suppressed, thereby improving the detection accuracy.

[0146] As described above, the detection device 1 of this embodiment includes: a substrate 21 (array substrate 2); a plurality of transistors (e.g., a reset transistor Mrst, a readout transistor Mrd, and a source follower transistor Msf) disposed on the substrate 21; a plurality of scan lines (e.g., a readout control scan line GLrd) extending along a first direction Dx; a plurality of signal lines (e.g., a power signal line SLsf, an output signal line SL, a reset signal line SLrst, and a reference signal line SLcom) extending along a second direction Dy intersecting the first direction Dx; a plurality of photodiodes 30, each disposed in a region surrounded by the plurality of scan lines and the plurality of signal lines, including a p-type semiconductor layer 33, an i-type semiconductor layer 31, and an n-type semiconductor layer 32; and shielding wiring (a first shielding wiring SLsf-a and a second shielding wiring SLrst-a) overlapping the scan lines and extending along the first direction Dx. The shielding wiring is electrically connected to the power signal line SLsf, which supplies power potential to the transistors among the plurality of signal lines.

[0147] Therefore, it is possible to suppress the parasitic capacitance C1 formed between the read control scan line GLrd and the photodiode 30 (partial photodiode 30S) (refer to...). Figure 4 As a result, as shown in equation (2) above, the detection sensitivity of the detection device 1 can be improved. Furthermore, the parasitic capacitance C1 formed between the readout control scan line GLrd and the multiple partial photodiodes 30S at their proximity positions is effectively suppressed. Consequently, deviations in the parasitic capacitance C1 caused by the arrangement of the multiple partial photodiodes 30S can be suppressed. Therefore, detection deviations in the detection device 1 can be suppressed.

[0148] (Second Implementation)

[0149] Figure 11 This is a top view showing the multiple detection elements involved in the second embodiment. Figure 12 yes Figure 11 Sectional view of XII-XII'. Figure 13 This is a circuit diagram illustrating the detection element according to the second embodiment. Furthermore, in the following description, the same reference numerals are used for components that are the same as those described in the above embodiments, and repeated descriptions are omitted.

[0150] In the first embodiment, a structure has been described in which the shielded wiring (first shielded wiring SLsf-a and second shielded wiring SLrst-a) and each signal line are disposed on the same layer. However, the shielded wiring may also be disposed on a different layer from the signal lines.

[0151] like Figure 11As shown, in the detection apparatus 1A according to the second embodiment, the shielding wiring ML is formed of a metal layer disposed on a different layer from each signal line (power signal line SLsf, output signal line SL, reset signal line SLrst, and reference signal line SLcom). The shielding wiring ML is configured to extend along the first direction Dx, overlapping with the read control scan line GLrd, and intersect with the multiple signal lines (power signal line SLsf, output signal line SL, reset signal line SLrst, and reference signal line SLcom) arranged in the first direction Dx. The shielding wiring ML is electrically connected to the power signal line SLsf via the contact hole H20.

[0152] In the shielded wiring ML, similar to the first embodiment, it has a width larger than the read control scan line GLrd in the second direction Dy, and recesses ML-a and ML-b are formed in the region adjacent to a portion of the photodiode 30S. Furthermore, the shielded wiring ML has a shielded wiring branch ML-c that overlaps with the branch GLrd-a of the read control scan line GLrd and extends along the second direction Dy.

[0153] The shielded wiring ML is continuously arranged across multiple detection elements 3 (photodiodes 30) arranged in the first direction Dx. However, it is not limited to this, and slits can also be provided to separate the detection elements 3.

[0154] like Figure 12 As shown, the shielding wiring ML is disposed between the layer containing the read control scan line GLrd and the layer containing multiple signal lines (e.g., power signal lines SLsf). More specifically, the shielding wiring ML is disposed on the insulating film 24, and in a layer closer to the i-type semiconductor layer 31 and the n-type semiconductor layer 32 than the layer containing the p-type semiconductor layer 33. The insulating film 25 is disposed between the shielding wiring ML and the power signal lines SLsf. The shielding wiring ML is electrically connected to the power signal lines SLsf via contact holes H20 provided in the insulating film 25.

[0155] In the second embodiment, compared to the first embodiment described above, the shielding wiring ML is disposed in a layer close to the readout control scan line GLrd. Therefore, the shielding wiring ML can effectively shield the edge components of the electric field and suppress parasitic capacitance C1.

[0156] like Figure 13As shown, a parasitic capacitance C1-1 is formed between the shielding wiring ML and node N1 (the cathode (n-type semiconductor layer 32) of photodiode 30). Additionally, a parasitic capacitance C1-2 is formed between the shielding wiring ML and the read control scan line GLrd. Node N1 is capacitively coupled to the read control scan line GLrd via the shielding wiring ML. Therefore, even when a read control signal RD is supplied to the read control scan line GLrd and the potential of the read control scan line GLrd changes, the potential change of node N1 (the cathode of photodiode 30) is suppressed because the shielding wiring ML is connected to a fixed potential (power supply potential VDD). Furthermore, regarding... Figure 13 The description of the capacitive coupling between node N1 and the read control scan line GLrd can also be applied to the first embodiment described above.

[0157] The preferred embodiments of the present invention have been described above, but the present invention is not limited to such embodiments. The content disclosed in the embodiments is merely an example, and various modifications can be made without departing from the spirit of the present invention. Appropriate modifications made without departing from the spirit of the present invention are of course also within the technical scope of the present invention. Without departing from the spirit of the above embodiments and variations, at least one of various omissions, substitutions, and modifications of the constituent elements can be made.

[0158] Explanation of reference numerals in the attached figures

[0159] 1…Detection device; 2…Array substrate; 3…Detection element; 7…Optical filter; 10…Sensor section; 15…Scan line drive circuit; 16…Signal line selection circuit; 21…Substrate; 30…Photodiode; 30S, 30S-1, 30S-2, 30S-3, 30S-4, 30S-5, 30S-6, 30S-7, 30S-8…Some photodiodes; 31…I-type semiconductor layer; 32…N-type semiconductor layer; 33…P-type semiconductor layer; 34…Upper conductor Electrical layer; 35…lower conductive layer; BA1, BA2…base; CA1, CA2, CA2a…connection; Mrst…reset transistor; Mrd…read transistor; Msf…source follower transistor; ML…shielded wiring; R1…first region; R2…second region; R3…third region; SLsf…power signal line; SLrst…reset signal line; SLcom…reference signal line; SLsf-a…first shielded wiring; SLrst-a…second shielded wiring.

Claims

1. A detection device, characterized in that, have: substrate; Multiple transistors are disposed on the substrate; Multiple scan lines extend along the first direction; Multiple signal lines extend along a second direction that intersects the first direction; Multiple photodiodes are respectively disposed in a region surrounded by multiple scan lines and multiple signal lines, and include a p-type semiconductor layer, an i-type semiconductor layer and an n-type semiconductor layer; as well as The shielding wiring overlaps with the scan lines and extends along the first direction. The shielding wiring is electrically connected to the power signal line that supplies power potential to the transistor among the plurality of signal lines.

2. The detection device according to claim 1, characterized in that, The shielded wiring is located on the same layer as the multiple signal lines.

3. The detection device according to claim 1 or 2, characterized in that, The multiple signal lines include a reset signal line for supplying a reset signal to the photodiode. The shielding wiring includes: a first shielding wiring connected to the power signal line and extending in a direction intersecting the power signal line; and a second shielding wiring connected to the reset signal line and extending in a direction intersecting the reset signal line.

4. The detection device according to claim 3, characterized in that, The plurality of signal lines include output signal lines for outputting signals from the photodiode. The output signal line is configured to be separate from the first shielding wire and the second shielding wire in the first direction and between the first shielding wire and the second shielding wire.

5. The detection device according to claim 1 or 2, characterized in that, The shielding wiring has a wider width than the scan line in the second direction. When viewed from above, a recessed portion in the width direction is formed in the region of the shielding wiring adjacent to the photodiode.

6. The detection device according to claim 1 or 2, characterized in that, The plurality of signal lines include output signal lines, which are used to output signals from the photodiode. The detection device has a signal line selection circuit, which has multiple switching elements corresponding to each of the multiple output signal lines. The connection between the multiple output signal lines and the detection circuit is switched through the multiple switching elements.

7. The detection device according to claim 1 or 2, characterized in that, The plurality of photodiodes each have: The p-type semiconductor layer, the i-type semiconductor layer, and the n-type semiconductor layer are stacked together in a plurality of first regions directly connected to ground; and The second region is formed by stacking at least the p-type semiconductor layer and the i-type semiconductor layer separately. The adjacent first regions are connected by at least the p-type semiconductor layer.

8. The detection device according to claim 7, characterized in that, The p-type semiconductor layer and the semiconductor layer of the transistor are disposed on the same layer.

9. The detection device according to claim 7, characterized in that, When viewed from above in a direction perpendicular to the substrate, the first region is configured as a triangular lattice.

10. A detection device, characterized in that, have: substrate; Multiple transistors are disposed on the substrate; Multiple scan lines extend along the first direction; Multiple signal lines extend along a second direction that intersects the first direction; Multiple photodiodes are respectively disposed in a region surrounded by multiple scan lines and multiple signal lines, and include a p-type semiconductor layer, an i-type semiconductor layer and an n-type semiconductor layer; as well as The shielding wiring extends along the first direction in a manner that overlaps with the scan lines and is disposed in a layer between a layer having multiple scan lines and a layer having multiple signal lines. The shielding wiring is electrically connected to a power signal line among the multiple signal lines that supplies power potential to the transistor.

11. The detection device according to claim 10, characterized in that, The multiple signal lines include a reset signal line for supplying a reset signal to the photodiode. The shielding wiring includes: a first shielding wiring connected to the power signal line and extending in a direction intersecting the power signal line; and a second shielding wiring connected to the reset signal line and extending in a direction intersecting the reset signal line.

12. The detection device according to claim 11, characterized in that, The plurality of signal lines include output signal lines, which are used to output signals from the photodiode. The output signal line is configured to be separate from the first shielding wire and the second shielding wire in the first direction and between the first shielding wire and the second shielding wire.

13. The detection device according to claim 10, characterized in that, The shielding wiring is formed of a metal layer.

14. The detection device according to claim 13, characterized in that, The detection device has an insulating film disposed between the shielding wiring and the power signal line. The shielded wiring is electrically connected to the power signal line via a contact hole provided in the insulating film.

15. The detection device according to claim 13 or 14, characterized in that, The shielding wiring is configured to extend along the first direction, overlapping the scan lines when viewed from above, and intersect with multiple signal lines.

16. The detection device according to any one of claims 10 to 14, characterized in that, The shielding wiring has a wider width than the scan line in the second direction. When viewed from above, a recessed portion in the width direction is formed in the region of the shielding wiring adjacent to the photodiode.

17. The detection device according to any one of claims 10 to 14, characterized in that, The plurality of signal lines include output signal lines for outputting signals from the photodiode. The detection device has a signal line selection circuit, which has multiple switching elements corresponding to each of the multiple output signal lines. The connection between the multiple output signal lines and the detection circuit is switched through the multiple switching elements.

18. The detection device according to any one of claims 10 to 14, characterized in that, The plurality of photodiodes each have: The p-type semiconductor layer, the i-type semiconductor layer, and the n-type semiconductor layer are stacked together in a plurality of first regions directly connected to ground; and The second region is formed by stacking at least the p-type semiconductor layer and the i-type semiconductor layer separately. The adjacent first regions are connected by at least the p-type semiconductor layer.

19. The detection device according to claim 18, characterized in that, The p-type semiconductor layer and the semiconductor layer of the transistor are disposed on the same layer.

20. The detection device according to claim 18, characterized in that, When viewed from above in a direction perpendicular to the substrate, the first region is configured as a triangular lattice.

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