Array substrate and display panel

Abstract

An array substrate (2) and a display panel, the array substrate (2) comprising a base substrate (20), a pixel electrode (21) formed on the base substrate (20), a common electrode (22), and a first scanning line (23a), a second scanning line (23b) and a data line (24) formed between the base substrate (20) and the pixel electrode (21); the pixel electrode (21) has a plurality of first electrode strips (210) arranged at intervals along a row direction; the common electrode (22) is arranged in the same layer as the pixel electrode (21) and has a plurality of second electrode strips (220) arranged at intervals along a row direction; The two electrode strips (220) and the first electrode strip (210) are arranged alternately in a row direction; the first scanning line (23a) is located between two adjacent rows of pixel electrodes (21); the second scanning line (23b) is located between two adjacent columns of pixel electrodes (21) and is electrically connected to the first scanning line (23a) through a via structure (N); the second scanning line (23b) has a scanning signal input end; the data line (24) has a data signal input end; and the orthographic projection of the data line (24) on the base substrate (20) intersects with the central area of ​​the orthographic projection of the pixel electrode (21) on the base substrate (20).

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] With the popularization of the full-screen concept in small and medium-sized display products, large-size display products (such as TVs) are also pursuing an extremely fashionable appearance; among them, the TV market has moved towards the "borderless" era, and full-screen has become a new development direction of the TV market. However, large-size full-screen display products currently have picture quality problems such as Mura (uneven brightness).

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0004] The purpose of the present disclosure is to provide an array substrate and a display panel, which can improve image quality problems such as Mura in products and improve product quality.

[0005] A first aspect of the present disclosure provides an array substrate, comprising:

[0006] substrate substrate;

[0007] A plurality of pixel electrodes are arranged in an array on the substrate along row and column directions; the pixel electrodes have a plurality of first electrode strips arranged at intervals along the row direction;

[0008] A plurality of common electrodes are arranged in the same layer as the pixel electrodes, and the common electrodes have a plurality of second electrode strips arranged at intervals along the row direction, and the second electrode strips and the first electrode strips are arranged alternately in the row direction;

[0009] A plurality of rows of first scanning lines are formed between the base substrate and the pixel electrodes and are located between two adjacent rows of the pixel electrodes;

[0010] A plurality of columns of second scan lines are formed between the base substrate and the pixel electrodes; the second scan lines are located between two adjacent columns of the pixel electrodes and are electrically connected to the first scan lines through a via structure, and the second scan lines have a scan signal input terminal;

[0011] A plurality of columns of data lines are formed between the base substrate and the pixel electrode; the data lines have data signal input terminals; and both sides of the data lines in the row direction are located inside the two sides of the pixel electrode in the row direction.

[0012] In an exemplary embodiment of the present disclosure, the sizes of two sides of the data line in the row direction and the center of the pixel electrode in the row direction are equal.

[0013] In an exemplary embodiment of the present disclosure, two sides of the data line in the row direction are located inside two sides of the second electrode strip in the row direction.

[0014] In an exemplary embodiment of the present disclosure, the data line and the second scan line are arranged in the same layer.

[0015] In an exemplary embodiment of the present disclosure, in each row, the number of the common electrodes is less than the number of the pixel electrodes.

[0016] In an exemplary embodiment of the present disclosure, two sides of the second scan line in the row direction are located inside two sides of the second electrode strip in the row direction.

[0017] In an exemplary embodiment of the present disclosure, it further includes:

[0018] A plurality of rows of first common signal lines, wherein the first common signal lines and the first scanning lines are arranged in the same layer and are located between two adjacent rows of pixel electrodes;

[0019] Among them, a row of the first common signal lines and a row of the first scanning lines are arranged between two adjacent rows of the pixel electrodes, and the first common signal lines and the common electrodes are electrically connected through a via structure.

[0020] In an exemplary embodiment of the present disclosure, it further includes:

[0021] One or more columns of second common signal lines, the second common signal lines and the second scanning lines are arranged in the same layer; the second common signal lines are located between two adjacent columns of the pixel electrodes, and are electrically connected to the first common signal lines of each row through a via structure; the two sides of the second common signal lines in the row direction are located on the inner sides of the two sides of the second electrode strip in the row direction;

[0022] The second common signal line has a common signal input terminal.

[0023] In an exemplary embodiment of the present disclosure, one column of the second scanning lines is disposed between some two adjacent columns of the pixel electrodes; and one column of the second common signal lines is disposed between another two adjacent columns of the pixel electrodes.

[0024] In an exemplary embodiment of the present disclosure, the array substrate further includes a first metal line and a second metal line disposed in the same layer as the first scan line, and the first metal line and the second metal line are disconnected from the first scan line;

[0025] Among them, the orthographic projections of the first metal line and the second metal line on the substrate are located within the orthographic projection of the second electrode strip on the substrate, and are respectively located on both sides of the second scanning line in the row direction or respectively located on both sides of the second common signal line in the row direction.

[0026] In an exemplary embodiment of the present disclosure, the size of the second electrode strips in the common electrode corresponding to the data line, the second scan line and the second common signal line in the row direction is larger than the size of other second electrode strips in the row direction.

[0027] In an exemplary embodiment of the present disclosure, the scan signal input terminal of the second scan line, the common signal input terminal of the second common signal line, and the data signal input terminal of the data line are located on the same side of the base substrate.

[0028] In an exemplary embodiment of the present disclosure, each row of the first scan lines is electrically connected to two or more columns of the second scan lines.

[0029] In an exemplary embodiment of the present disclosure, it further includes: a plurality of driving transistors arranged in an array along a row direction and a column direction on the substrate; each of the driving transistors corresponds to one of the pixel electrodes;

[0030] The driving transistor comprises a gate electrode disposed in the same layer as the first scanning line, an active layer located at a side of the gate electrode away from the base substrate, and a source-drain electrode disposed in the same layer as the data line;

[0031] A gate insulating layer is formed between the gate electrode and the active layer, and the gate insulating layer covers the gate electrode and the first scan line; a passivation layer is formed between the source and drain electrodes and the pixel electrode, and the passivation layer covers the source and drain electrodes, the data line, and the second scan line;

[0032] The first scanning line is electrically connected to the gate electrode, the data line is electrically connected to the source electrode of the source-drain electrodes, and the pixel electrode is electrically connected to the drain electrode of the source-drain electrodes via a via structure penetrating the passivation layer.

[0033] In an exemplary embodiment of the present disclosure, an organic insulating layer is further included, which is formed between the passivation layer and the pixel electrode, and the pixel electrode is electrically connected to the drain electrode through a via structure penetrating the organic insulating layer and the passivation layer.

[0034] In an exemplary embodiment of the present disclosure, a color filter layer is further included, which is formed between the passivation layer and the organic insulating layer, and the pixel electrode is electrically connected to the drain electrode through a via structure that penetrates the organic insulating layer, the color filter layer and the passivation layer.

[0035] In an exemplary embodiment of the present disclosure, the first electrode strip and the second electrode strip are bent, and the bending angle of the first electrode strip and the second electrode strip is 150° to 170°.

[0036] A second aspect of the present disclosure provides a display panel, which includes the array substrate and an opposing substrate as described in any one of the above items.

[0037] The technical solution provided by the present disclosure can achieve the following beneficial effects:

[0038] The array substrate and display panel provided by the present disclosure can reduce the parasitic capacitance generated between the pixel electrode and the common electrode by arranging the pixel electrode and the common electrode in the same layer and interlocking them, thereby improving the pixel charging rate and the aperture ratio; in addition, by arranging the data line on the inner side of a pixel electrode and arranging the second scanning line between two adjacent columns of pixel electrodes, the spacing between the data line and the second scanning line can be increased, thereby reducing the problem of signal crosstalk between the second scanning line and the data line, thereby reducing the screen Mura phenomenon and improving the display effect.

[0039] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0041] Figure 1 This is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure;

[0042] Figure 2 for Figure 1 A cross-sectional view of the array substrate along line AA shown in FIG.

[0043] Figure 3 A schematic diagram of the distribution of various regions in an array substrate according to an embodiment of the present disclosure;

[0044] Figure 4is a structural schematic diagram of an array substrate according to another embodiment of the present disclosure;

[0045] Figure 5 for Figure 4 A cross-sectional view of an array substrate along line BB shown in FIG.

[0046] Figure 6 for Figure 4 A cross-sectional view of an array substrate along line CC as shown in ;

[0047] Figure 7 for Figure 4 A cross-sectional view of an array substrate along line DD shown in FIG.

[0048] Figure 8 for Figure 4 A schematic structural diagram of a first electrode strip of a pixel electrode in an array substrate shown in ;

[0049] Fig. 9 for Figure 4 A schematic structural diagram of a second electrode strip of a common electrode in an array substrate shown in ;

[0050] Fig.10 for Figure 4 A cross-sectional view of another array substrate along line BB shown in ;

[0051] Fig.11 for Figure 4 A cross-sectional view of another array substrate along line BB shown in ;

[0052] Fig.12 for Figure 4 A cross-sectional view of another array substrate along line CC shown in ;

[0053] Fig.13 for Figure 4 A cross-sectional view of another array substrate along line CC shown in ;

[0054] Fig.14 for Figure 4 A cross-sectional view of another array substrate along line DD shown in FIG.

[0055] Fig.15 for Figure 4 A cross-sectional view of another array substrate along line DD shown in ;

[0056] Fig.16 is a structural schematic diagram of an array substrate according to another embodiment of the present disclosure;

[0057] Fig.17 The figure is a schematic diagram of the positional relationship between an array substrate and an opposing substrate in a display panel according to an embodiment of the present disclosure.

[0058] Figure 1 and Figure 2 Reference numerals in the figures:

[0059] 10. horizontal scanning line; 11. vertical scanning line; 12. data line; 13. via structure; 14. sub-pixel; 140. pixel electrode; 140a. slit; 141. common electrode; 15. substrate;

[0060] Figures 3 to 17 Reference numerals in the figures:

[0061] 2. array substrate; 20. base substrate; 21. pixel electrode; 210. first electrode strip; 211. first conductive connection portion; 22. common electrode; 220. second electrode strip; 221. second conductive connection portion; 23a. first scan line; 23b. second scan line; 24. data line; 25. driving transistor; 250. gate electrode; 251. active layer; 252. source electrode; 253. drain electrode; 26a. first common signal line; 26b. second common signal line; 27a. gate insulating layer; 27b. passivation layer; 27c. organic insulating layer; 27d. color filter layer; 28a. first metal line; 28b. second metal line;

[0062] 3. Counter substrate; 30. Transparent substrate; 31. Black matrix layer. DETAILED DESCRIPTION

[0063] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail in conjunction with the accompanying drawings below. Note that the embodiments can be implemented in multiple different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily.

[0064] In the drawings, the size of each component, the thickness of a layer, or the area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to this size, and the shape and size of each component in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0065] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0066] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle area", "two side areas", "upper", "inner", "outer" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0067] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0068] In the present disclosure, unless otherwise specified, the term "same-layer arrangement" is used to mean that two layers, parts, components, elements or portions can be formed by the same patterning process, and the two layers, parts, components, elements or portions are generally formed of the same material.

[0069] In the present disclosure, unless otherwise specified, the expression "patterning process" generally includes steps such as photoresist coating, exposure, development, etching, photoresist stripping, etc. The expression "one-time patterning process" means a process of forming patterned layers, components, members, etc. using one mask.

[0070] In order to realize a full-screen design, the present disclosure provides an array substrate which can be applied to a liquid crystal display panel; Figure 1 As shown, the array substrate may include a horizontal scan line 10 extending in the row direction X, a vertical scan line 11 extending in the column direction Y, and a data line 12 extending in the column direction Y; the vertical scan line 11 is electrically connected to the horizontal scan line 10 through a via structure 13, and the scan signal input end of the vertical scan line 11 and the data signal input end of the data line 12 may be located on the same side of the array substrate, for example, the binding side of the array substrate, so that the other three non-display sides of the array substrate except the binding side can be made very narrow because there is no scan line input end and data line 12 input end, thereby improving the screen-to-body ratio, that is, increasing the area of ​​the display area, thereby realizing a full screen.

[0071] It should be noted that Figure 1 The structure of the area divided by the horizontal scanning line 10 and the data line 12 may be a sub-pixel 14; Figure 1 and Figure 2 As shown, a vertical scanning line 11 and a data line 12 are arranged between two adjacent columns of sub-pixels 14 , which causes a relatively large signal crosstalk problem between the vertical scanning line 11 and the data line 12 .

[0072] In addition, if Figure 2 As shown, the sub-pixel 14 may include a pixel electrode 140 and a common electrode 141, the pixel electrode 140 may be a slit electrode with a slit 140a, and the common electrode may be a plate-shaped electrode without a slit, wherein the common electrode 141 is located on the side of the pixel electrode 140 close to the base substrate 15; such a design makes the overlapping area between the pixel electrode 140 and the common electrode 141 larger, so that the parasitic capacitance generated between the pixel electrode 140 and the common electrode 141 is larger, and then the charging rate and aperture ratio of the pixel are greatly affected, resulting in the problem of poor display effect. It should be noted that the electric field between the common electrode 141 and the pixel electrode 140 is the electric field that drives the liquid crystal.

[0073] Based on the above content, the embodiment of the present disclosure further provides an array substrate which can be used in a liquid crystal display panel, such as Figure 3 As shown, the array substrate 2 can be divided into a display area A and a non-display area B arranged around the display area A. The non-display area B of the array substrate 2 can be provided with a sealing area B1 surrounding the display area A, a source electrostatic release area B2 located in the sealing area B1 close to the display area A, and a fan-out area B3 located in the sealing area B1 away from the display area A, and the source electrostatic release area B2 and the fan-out area B3 are located in the non-display area B (i.e., binding area) on the same side of the display area A.

[0074] Among them, Figures 4 to 7 As shown, the array substrate 2 may include a base substrate 20 and a pixel electrode 21, a common electrode 22, a first scan line 23a, a second scan line 23b, a data line 24, a driving transistor 25, a first common signal line 26a and a second common signal line 26b arranged on the base substrate 20, and the pixel electrode 21, the common electrode 22, the first scan line 23a, the second scan line 23b, the data line 24, the driving transistor 25, the first common signal line 26a and the second common signal line 26b are all arranged on the display area A of the base substrate 20.

[0075] The array substrate 2 of the embodiment of the present disclosure is described in detail below with reference to the accompanying drawings.

[0076] like Figures 5 to 7 As shown, the base substrate 20 may be a single-layer structure. For example, the base substrate 20 may be a glass substrate, but is not limited thereto and may also be a substrate of other materials. In addition, the base substrate 20 may also be a multi-layer structure, depending on the specific situation.

[0077] like Figure 4As shown, a plurality of pixel electrodes 21 may be provided, and the plurality of pixel electrodes 21 may be arranged in an array along the row direction X and the column direction Y; each pixel electrode 21 may have a plurality of first electrode strips 210 spaced apart along the row direction X, and each pixel electrode 21 may also have a first conductive connection portion 211 located on the same side of each first electrode strip 210 and connected to each first electrode strip 210, that is, the pixel electrode 21 as a whole may be shaped like a "comb".

[0078] Among them, Figure 4 and Figure 8 As shown, the first electrode strip 210 may be bent, and its bending angle α1 is 150° to 170°. Specifically, the first electrode strip 210 may include two parts, and the angle α1 between the two parts is 150° to 160°; for example: 150°, 156°, 162°, 166°, 170°, etc.; in other words, the angles α2 and α3 between the extension directions of the two parts and the column direction Y are 5° to 15°, for example: 5°, 7°, 9°, 12°, 15°, etc.

[0079] like Figure 4 As shown, a plurality of driving transistors 25 may be provided, and the plurality of driving transistors 25 are arranged in an array along the row direction X and the column direction Y, and each driving transistor 25 may correspond to a pixel electrode 21. Specifically, the driving transistor 25 may include a gate electrode 250, an active layer 251, and a source-drain electrode, and the source-drain electrode may include a source electrode 252 and a drain electrode 253 electrically connected to both ends of the active layer 251, respectively; the drain electrode 253 is electrically connected to a corresponding pixel electrode 21; for example, the gate electrode 250, the source electrode 252, and the drain electrode 253 may be made of metal materials such as aluminum and molybdenum.

[0080] like Figure 7 As shown, the driving transistor 25 may be a bottom gate type, that is, the active layer 251 is located on the side of the gate electrode 250 away from the base substrate 20. It should be understood that in order to insulate the active layer 251 from the gate electrode 250, a gate insulating layer may be formed between the gate electrode 250 and the active layer 251; that is, in the process of manufacturing the array substrate 2, the gate electrode 250 may be first formed on the base substrate 20; then, a gate insulating layer 27a covering the gate electrode 250 is formed; then, the active layer 251 facing the gate electrode 250 is formed on the gate insulating layer 27a. It should be noted that the gate insulating layer 27a is disposed on the base substrate 20 as a whole layer, that is, the gate insulating layer 27a not only covers the gate electrode 250, but also covers other metal structures disposed on the same layer as the gate electrode 250. It should be understood that the gate insulating layer 27a may be an inorganic insulating layer.

[0081] In addition, the driving transistor 25 is formed on a side of the pixel electrode 21 close to the base substrate 20. That is, in the process of manufacturing the array substrate 2, the driving transistor 25 can be first formed on the base substrate 20; then, the pixel electrode 21 can be formed. It should be noted that after the source and drain electrodes of the driving transistor 25 are formed on the base substrate 20 and before the pixel electrode 21 is formed, a passivation layer 27b can also be formed. Figure 7 As shown, the passivation layer 27 b covers the source and drain electrodes, and the pixel electrode 21 can be electrically connected to the drain electrode 253 via a via structure P penetrating through the passivation layer 27 b.

[0082] The passivation layer 27b is entirely disposed on the base substrate 20, that is, the passivation layer 27b not only covers the source and drain electrodes, but also covers other metal structures disposed on the same layer as the source and drain electrodes. It should be understood that the passivation layer 27b may be an inorganic insulating layer.

[0083] like Fig.10 , Fig.12 and Fig.14 As shown, an organic insulating layer 27c can also be formed between the passivation layer 27b and the pixel electrode 21. That is to say, in the process of manufacturing the array substrate 2, a passivation layer 27b can be first formed on the base substrate 20; then, an organic insulating layer 27c is formed on the passivation layer 27b; then, a pixel electrode 21 is formed on the organic insulating layer 27c; wherein the pixel electrode 21 can be electrically connected to the drain electrode 253 through a via structure P penetrating through the organic insulating layer 27c and the passivation layer 27b.

[0084] In the embodiment of the present disclosure, by setting the organic insulating layer 27c, while achieving planarization to facilitate the subsequent coating of the pixel electrode 21 material, the distance between the pixel electrode 21 and the layer where the source and drain electrodes are located can be increased, thereby avoiding interference of other signal lines on the layer where the source and drain electrodes are located with the pixel electrode 21.

[0085] It should be noted that the array substrate 2 of the embodiment of the present disclosure may not be provided with the organic insulating layer 27 c .

[0086] like Fig.11 , Fig.13 and Fig.15As shown, a color filter layer 27d can also be formed between the passivation layer 27b and the organic insulating layer 27c, that is, in the process of manufacturing the array substrate 2, a passivation layer 27b can be first formed on the base substrate 20; then, a color filter layer 27d is formed on the passivation layer 27b; then, an organic insulating layer 27c is formed on the color filter layer 27d; wherein the pixel electrode 21 can be electrically connected to the drain electrode 253 through a via structure P that penetrates the organic insulating layer 27c, the color filter layer 27d, and the passivation layer 27b; for example, the color filter layer 27d can include multiple color resist blocks such as red, green, and blue, and this color resist block can be set one-to-one with the pixel electrode 21.

[0087] It should be noted that the array substrate 2 of the embodiment of the present disclosure may not be provided with the color filter layer 27 d .

[0088] The driving transistor in the embodiment of the present disclosure is not limited to a bottom gate type, but may also be a top gate type, depending on the specific situation.

[0089] like Figure 4 As shown, a plurality of common electrodes 22 may be provided, and the common electrodes 22 may be provided in the same layer as the pixel electrodes 21; wherein each common electrode 22 may have a plurality of second electrode strips 220 spaced apart along the row direction X, and each common electrode 22 may also have a second conductive connection portion 221 located on the same side of each second electrode strip 220 and connected to each second electrode strip 220, that is, the common electrode 22 as a whole may also be in a shape similar to a "comb", wherein the second electrode strips 220 of the common electrode 22 and the first electrode strips 210 of the pixel electrode 21 are alternately arranged in the row direction X, that is, the common electrode 22 and the pixel electrode 21 located in the same row are interlocked with each other, such a design may reduce the parasitic capacitance generated between the pixel electrode 21 and the common electrode 22, thereby improving the pixel charging rate and the aperture ratio.

[0090] It should be understood that there should be a gap between the first electrode strip 210 and the first conductive connecting portion 211 of the pixel electrode 21 and the second electrode strip 220 and the second conductive connecting portion 221 of the common electrode 22 to avoid electrical conduction between the pixel electrode 21 and the common electrode 22 .

[0091] like Figure 4 and Fig. 9 As shown, the second electrode strip 220 may be bent, and its bending angle β1 is 150° to 170°. Specifically, the second electrode strip 220 may include two parts, and the angle β1 between the two parts is 150° to 160°; for example: 150°, 156°, 162°, 166°, 170°, etc.; in other words, the angles β2 and β3 between the extension directions of the two parts and the column direction Y are 5° to 15°, for example: 5°, 7°, 9°, 12°, 15°, etc.

[0092] It should be noted that the second electrode strips 220 and the first electrode strips 210 may be substantially parallel, that is, the bending angle β1 of the second electrode strips 220 may be the same as the bending angle α1 of the first electrode strips 210 .

[0093] Based on the above content, by setting the first electrode strips 210 of the pixel electrode 21 and the second electrode strips 220 of the common electrode 22 in a bent shape, the color deviation can be reduced and the display effect can be improved.

[0094] Among them, Figure 4 As shown, in each row, the number of common electrodes 22 may be less than the number of pixel electrodes 21; that is, one common electrode 22 in each row may be interlocked with multiple pixel electrodes 21; for example, in each row, multiple pixel electrodes 21 may be provided and one common electrode 22 may be provided, and one common electrode 22 may be interlocked with all the pixel electrodes 21 in each row; but not limited to this, in each row, multiple common electrodes 22 may also be provided, and the common electrodes 22 may be interlocked with the pixel electrodes 21 one-to-one or one-to-many, depending on the specific circumstances.

[0095] It should be noted that the common electrode 22 and the pixel electrode 21 mentioned above may be transparent electrodes, and the common electrode 22 may be made of metal materials such as nano silver wires, or made of semiconductor oxides such as ITO (indium tin oxide).

[0096] like Figure 4 As shown, the first common signal line 26a can be arranged in multiple rows; this first common signal line 26a can be formed between the base substrate 20 and the common electrode 22. As mentioned above, the common electrode 22 and the pixel electrode 21 are arranged in the same layer; that is, in the process of manufacturing the array substrate 2, the first common signal line 26a can be first formed on the base substrate 20, and then the pixel electrode 21 and the common electrode 22 are formed; wherein the first common signal line 26a can be located between two adjacent rows of pixel electrodes 21, and electrically connected to a row of common electrodes 22.

[0097] For example, Figure 4 As shown, the first common signal line 26a can be arranged in the same layer as the gate electrode 250 of the driving transistor 25. In this case, the first common signal line 26a needs to be electrically connected to the common electrode 22 through a via structure Q. It should be noted that the via structure Q mentioned here can at least penetrate the passivation layer 27b and the gate insulation layer 27a; when the array substrate 2 includes the aforementioned organic insulation layer 27c and the color filter layer 27d, the via structure Q penetrates the passivation layer 27b and the gate insulation layer 27a, and also penetrates the organic insulation layer 27c and the color filter layer 27d.

[0098] like Figure 4As shown, the second common signal line 26b can be arranged in one or more columns; this second common signal line 26b can be formed between the base substrate 20 and the common electrode 22. As mentioned above, the common electrode 22 and the pixel electrode 21 are arranged in the same layer; that is, in the process of manufacturing the array substrate 2, the second common signal line 26b can be first formed on the base substrate 20, and then the pixel electrode 21 and the common electrode 22 are formed; wherein, the second common signal line 26b can be located between two adjacent columns of pixel electrodes 21, and the two sides of the second common signal line 26b in the row direction X can be located on the inner side of the two sides of a second electrode strip 220 in a common electrode 22 in the row direction X; this second electrode strip 220 can play a role in shielding the signal, that is: it can shield the common signal on the second common signal line 26b to prevent the common signal from affecting the electric field formed between the pixel electrode 21 and the common electrode 22.

[0099] For example, the shape of the portion of the second common signal line 26b corresponding to the first electrode strip 210 may match the shape of the first electrode strip 210, that is, when the first electrode strip 210 is in a bent shape, the portion of the second common signal line 26b corresponding to the first electrode strip 210 may also be in a bent shape and may be basically parallel to the first electrode strip 210.

[0100] The size of the second common signal line 26b in the row direction X is d1. Figure 4 As shown, the size of the second electrode strip 220 located above the second common signal line 26b in the row direction X is d2, wherein the ratio between d1 and d2 is greater than 0.5 and less than 1, such as: 0.5, 0.6, 0.7, 0.8, 0.9, 0.95, etc., but not limited to this, the ratio between d1 and d2 may also be less than 0.5, depending on the specific situation.

[0101] It should be noted that the second electrode strip 220 located above the second common signal line 26 b mentioned in the embodiment of the present disclosure refers to: the second electrode strip 220 overlapping with the second common signal line 26 b in the orthographic projection on the base substrate 20 .

[0102] The second common signal line 26b can be electrically connected to each row of the first common signal line 26a. The second common signal line 26b can have a common signal input terminal, that is, the common signal can be transmitted to the common electrode 22 through the second common signal line 26b and the first common signal line 26a in sequence. For example, the second common signal line 26b can be arranged in the same layer as the source and drain electrodes of the driving transistor 25. In this case, Figure 4 As shown, the second common signal line 26b needs to be electrically connected to each row of the first common signal lines 26a through a via structure M; it should be noted that the via structure M mentioned here can penetrate the gate insulating layer 27a.

[0103] In the embodiment of the present disclosure, by providing the first common signal line 26a and the second common signal line 26b, the number of common signal terminals is greatly reduced while the common signal is transmitted to the common electrode 22 of the entire array substrate 2, thereby reducing the number of leads and reducing costs.

[0104] It should be understood that in the embodiment of the present disclosure, only the first common signal line 26 a or only the second common signal line 26 b may be provided, depending on the specific circumstances.

[0105] like Figure 4 As shown, the first scan line 23a can be set in multiple rows, and the first scan line 23a can be formed between the base substrate 20 and the pixel electrode 21. That is, in the process of manufacturing the array substrate 2, the first scan line 23a can be first formed on the base substrate 20, and then the pixel electrode 21 is formed; wherein the first scan line 23a can be located between two adjacent rows of pixel electrodes 21.

[0106] For example, the first scan line 23a can be disposed on the same layer as the first common signal line 26a. As mentioned above, the first common signal line 26a can be disposed on the same layer as the gate electrode 250 of the driving transistor 25. Therefore, the first scan line 23a is also disposed on the same layer as the gate electrode 250 of the driving transistor 25. It should be understood that there is a gap between the first scan line 23a and the first common signal line 26a. In other words, there is no electrical connection between the first scan line 23a and the first common signal line 26a; while there is an electrical connection between the first scan line 23a and the gate electrode 250 of the driving transistor 25.

[0107] Among them, a row of first common signal lines 26a and a row of first scanning lines 23a may be arranged between two adjacent rows of pixel electrodes 21. The first scanning line 23a is electrically connected to the gate electrode 250 of the driving transistor 25 corresponding to one row of pixel electrodes 21, and the first common signal line 26a is electrically connected to the common electrode 22 corresponding to another row of pixel electrodes 21 through a via structure Q.

[0108] like Figure 4 As shown, the second scan line 23b can be arranged in multiple columns, and the second scan line 23b can be formed between the base substrate 20 and the pixel electrode 21. That is to say, in the process of manufacturing the array substrate 2, the second scan line 23b can be first formed on the base substrate 20, and then the pixel electrode 21 is formed; wherein the second scan line 23b can be located between two adjacent columns of pixel electrodes 21. For example, the shape of the portion of the second scan line 23b corresponding to the first electrode strip 210 can match the shape of the first electrode strip 210, that is: when the first electrode strip 210 is bent, the portion of the second scan line 23b corresponding to the first electrode strip 210 can also be bent and can be basically parallel to the first electrode strip 210.

[0109] It should be noted that, since the first scan line 23a is located between two adjacent rows of pixel electrodes 21, and the second scan line 23b is located between two adjacent columns of pixel electrodes 21, in order to avoid electrical connection between the second scan line 23b and other unnecessary first scan lines 23a, the second scan line 23b and the first scan line 23a can be set in different layers, and an insulating layer can be set between the second scan line 23b and the first scan line 23a; wherein the second scan line 23b has a scan signal input terminal, in order to enable the scan signal received by the second scan line 23b to be transmitted to a specific first scan line 23a, such as Figure 4 As shown, a via structure N corresponding to the first scan line 23a can be set on the insulating layer, and the second scan line 23b can be electrically connected to the first scan line 23a through the via structure N. Based on this structure, it can be known that the scan signal can be transmitted to the gate electrode 250 of the corresponding driving transistor 25 through the second scan line 23b, the via structure N, and the first scan line 23a in sequence to control the on and off of this driving transistor 25.

[0110] For example, the second scan line 23b can be arranged on the same layer as the second common signal line 26b. Since it is mentioned above that the second common signal line 26b can be arranged on the same layer as the source and drain electrodes of the driving transistor 25, the second scan line 23b is also arranged on the same layer as the source and drain electrodes of the driving transistor 25. It should be noted that the second scan line 23b is electrically connected to the first scan line 23a through the via structure N, and the via structure N mentioned here can penetrate the passivation layer 27b.

[0111] In order to ensure display uniformity, the number of signal lines between two adjacent columns of pixel electrodes 21 in the array substrate 2 can be made consistent. Therefore, in the embodiment of the present disclosure, Figure 4 As shown, a column of second scanning lines 23 b may be disposed between two adjacent columns; and a column of second common signal lines 26 b may be disposed between two adjacent columns of pixel electrodes 21 in another part.

[0112] It should be noted that, as mentioned above, one common electrode 22 can be interlocked with a plurality of pixel electrodes 21 in each row, that is, a second electrode strip 220 of the common electrode 22 is also provided between the first electrode strips 210 of adjacent pixel electrodes 21; Figure 6 , Fig.12 and Fig.13 As shown, both sides of the second scan line 23b in the row direction X can be located on the inner side of both sides of the second electrode strip 220 in the row direction X. The second electrode strip 220 can play a role in shielding the signal, that is, shielding the scan signal on the second scan line 23b to prevent the scan signal from affecting the electric field formed between the pixel electrode 21 and the common electrode 22.

[0113] The size of the second scanning line 23b in the row direction X is d3. Figure 6 As shown, the size of the second electrode strip 220 located above the second scan line 23b in the row direction X is d4, wherein the ratio between d3 and d4 is greater than 0.5 and less than 1, such as: 0.5, 0.6, 0.7, 0.8, 0.9, 0.95, etc., but not limited to this, the ratio between d3 and d4 may also be less than 0.5, depending on the specific situation.

[0114] It should be noted that the second electrode strip 220 located above the second scan line 23 b mentioned in the embodiment of the present disclosure refers to: the second electrode strip 220 that overlaps with the second scan line 23 b in the orthographic projection on the base substrate 20 .

[0115] In the embodiments of the present disclosure, Fig.16 As shown, each row of the first scan line 23a can be electrically connected to two or more columns of the second scan lines 23b, that is, each row can be driven by two sets of scan signals or more scan signals, which can strengthen the scan signal to improve the display effect; in addition, this design can be used for spliced ​​display products.

[0116] It should be noted that each row of first scan lines 23a is not limited to being electrically connected to two or more columns of second scan lines 23b, but may also be electrically connected to only one column of second scan lines 23b, depending on the specific situation.

[0117] like Figure 4 As shown, the data line 24 can be arranged in multiple columns, and the data line 24 is formed between the base substrate 20 and the pixel electrode 21. That is, in the process of manufacturing the array substrate 2, the data line 24 can be first formed on the base substrate 20, and then the pixel electrode 21 is formed; wherein the data line 24 has a data signal input terminal, and the data line 24 can be electrically connected to the source electrode 252 of the driving transistor 25; that is, the data signal can be transmitted to the source electrode 252 through the data line 24.

[0118] For example, the data line 24 can be disposed on the same layer as the second scan line 23 b. As mentioned above, the second scan line 23 b can be disposed on the same layer as the source and drain electrodes of the driving transistor 25 , and therefore, the data line 24 is also disposed on the same layer as the source and drain electrodes of the driving transistor 25 .

[0119] As mentioned above, the second scanning line 23b is disposed between two adjacent columns of pixel electrodes 21. In order to reduce the problem of signal crosstalk between the second scanning line 23b and the data line 24, in the embodiment of the present disclosure, Figure 4 , Figure 5 , Fig.10 , Fig.11As shown, the two sides of the data line 24 in the row direction X can be located on the inner side of the two sides of a pixel electrode 21 in the row direction X. Compared with the solution of arranging the data line 24 and the second scan line 23b between the same two adjacent columns of pixel electrodes 21, this design increases the spacing between the second scan line 23b and the data line 24, thereby reducing the problem of signal crosstalk between the second scan line 23b and the data line 24, and then reducing the screen Mura phenomenon and improving the display effect.

[0120] Optionally, the sizes of the two sides of the data line 24 in the row direction X and the center of the pixel electrode 21 in the row direction X are equal, that is, the data line 24 can be centered relative to the pixel electrode 21 in the row direction X to balance the signal crosstalk problem on both sides of the data line 24 and ensure picture uniformity.

[0121] Among them, Figure 4 , Figure 5 , Fig.10 , Fig.11 As shown, the two sides of the aforementioned data line 24 in the row direction X are located on the inner side of the two sides of a second electrode strip 220 in the row direction X; this second electrode strip 220 can play a shielding role, that is, shielding the data signal on the data line 24 to prevent the data signal from affecting the electric field formed between the pixel electrode 21 and the common electrode 22.

[0122] For example, the shape of the portion of the data line 24 corresponding to the second electrode strip 220 can match the shape of the second electrode strip 220, that is, when the second electrode strip 220 is bent, the portion of the data line 24 corresponding to the second electrode strip 220 can also be bent and can be basically parallel to the second electrode strip 220.

[0123] The size of the data line 24 in the row direction X is d5. Figure 5 As shown, the size of the second electrode strip 220 located above the data line 24 in the row direction X is d6, wherein the ratio between d5 and d6 is greater than 0.5 and less than 1, such as: 0.5, 0.6, 0.7, 0.8, 0.9, 0.95, etc., but not limited to this, the ratio between d5 and d6 may also be less than 0.5, depending on the specific situation.

[0124] It should be noted that the second electrode strip 220 located above the data line 24 mentioned in the embodiment of the present disclosure refers to: the second electrode strip 220 that overlaps with the data line 24 in the orthographic projection on the base substrate 20 .

[0125] like Figure 4 , Figure 6 , Fig.12 and Fig.13As shown, the array substrate 2 of the disclosed embodiment may further include a first metal line 28a and a second metal line 28b, which may be arranged in the same layer as the first scanning line 23a, and the first metal line 28a and the second metal line 28b are disconnected from the first scanning line 23a, that is, they are not electrically connected.

[0126] The orthographic projections of the first metal line 28a and the second metal line 28b on the base substrate 20 may be located within the orthographic projection of a second electrode strip 220 on the base substrate 20, such as Figure 6 , Fig.12 and Fig.13 As shown, the first metal line 28a and the second metal line 28b can be respectively located on both sides of the second scanning line 23b in the row direction X. The first metal line 28a and the second metal line 28b can play a role in shielding signals, that is, they can shield the scanning signal of the second scanning line 23b to prevent the scanning signal from affecting the electric field formed between the pixel electrode 21 and the common electrode 22; in addition, the first metal line 28a and the second metal line 28b can also play a role in shading.

[0127] like Figure 4 As shown, when the array substrate 2 of the present disclosure has the second common signal line 26b mentioned above, the second common signal line 26b may also be provided with a first metal line 28a and a second metal line 28b on both sides in the row direction X. This design can shield the common signal and prevent the common signal from affecting the electric field formed between the pixel electrode 21 and the common electrode 22, while ensuring the uniformity of the picture.

[0128] In addition, the first metal line 28a and the second metal line 28b may be provided on both sides of the data line 24 in the row direction X. Such a design can shield the data signal and prevent the data signal from affecting the electric field formed between the pixel electrode 21 and the common electrode 22. However, the present invention is not limited to this, and the first metal line 28a and the second metal line 28b may not be provided on both sides of the data line 24 in the row direction X.

[0129] For example, the shapes of the first metal wire 28a and the second metal wire 28b may match the shape of the second electrode strip 220 , that is, when the second electrode strip 220 is bent, the first metal wire 28a and the second metal wire 28b may also be bent and may be substantially parallel to the second electrode strip 220 .

[0130] It should be noted that if Figure 4As shown, the size of the second electrode strips 220 corresponding to the data lines 24, the second scanning lines 23b, and the second common signal lines 26b in the common electrode 22 in the row direction X can be larger than the size of other second electrode strips 220 in the row direction X, so as to more effectively shield the data signals, scanning signals, and common signals, and prevent the data signals, scanning signals, and common signals from affecting the electric field formed between the pixel electrode 21 and the common electrode 22.

[0131] Among them, the second electrode strips 220 corresponding to the data lines 24, the second scanning lines 23b, and the second common signal lines 26b in the common electrode 22 have a size d7 in the row direction X, and the size of the other second electrode strips 220 in the row direction X is d8, wherein the ratio between d8 and d7 is 0.1 to 0.5, for example: 0.1, 0.2, 0.3, 0.4, 0.5, etc., but not limited to this, the ratio between d8 and d7 may also be greater than 0.5 and less than 1, depending on the specific circumstances.

[0132] In an embodiment of the present disclosure, the scan signal input terminal of the second scan line 23b, the common signal input terminal of the second common signal line 26b, and the data signal input terminal of the data line 24 mentioned above may be located on the same side of the base substrate 20, for example: the base substrate 20 has a first side and a second side relatively arranged in the column direction Y; the scan signal input terminal of the second scan line 23b, the common signal input terminal of the second common signal line 26b, and the data signal input terminal of the data line 24 are all close to the first side or are all close to the second side, so that the other sides of the base substrate 20 do not have the scan signal input terminal of the second scan line 23b, the common signal input terminal of the second common signal line 26b, and the data signal input terminal of the data line 24, therefore, the other sides can be made very narrow, thereby increasing the proportion of the display area A to achieve full-screen display.

[0133] It should be noted that if Figure 3 As shown, the region B4 where the gate driving circuit for providing a scanning signal for the second scanning line 23b is located can be located in the non-display area B, specifically between the source electrostatic discharge area B2 and the fan-out area B3, and inside the sealing area B1. However, it is not limited thereto, and the gate driving circuit for providing a scanning signal for the second scanning line 23b may not be disposed on the base substrate 20, and it may be electrically connected to the second scanning line 23b on the base substrate 20 through a flexible circuit board.

[0134] In addition, it should be noted that the via structures P, Q, M, and N mentioned in the present disclosure may be structures in which the vias are filled with conductive materials.

[0135] The embodiment of the present disclosure further provides a display panel, which includes the array substrate 2 described in any of the above embodiments; it should be understood that the display panel can be a liquid crystal panel, so Fig.17 As shown, the display panel may further include an opposing substrate 3 arranged in a box with the array substrate 2 and liquid crystal molecules ( Fig.17 not shown).

[0136] Among them, when the array substrate 2 has the aforementioned color filter layer 27d, the opposing substrate 3 may not need to be provided with a color filter layer 27d. At this time, the opposing substrate 3 may include a transparent substrate 30 and a black matrix layer 31 arranged on the side of the transparent substrate 30 facing the array substrate 2. The black matrix layer 31 is used to shield the opaque structures in the array substrate 2, such as: the driving transistor 25, the first scanning line 23a, the second scanning line 23b, the data line 24, the first common signal line 26a, the second common signal line 26b, the first metal line 28a and the second metal line 28b and other structures.

[0137] It should be understood that when the array substrate 2 does not have the aforementioned color filter layer 27 d , a color filter layer 27 d may be provided in the opposing substrate 3 .

[0138] An embodiment of the present disclosure further provides an electronic device, which includes the display panel described above.

[0139] In the embodiments of the present disclosure, the specific type of electronic device is not particularly limited, and any type of electronic device commonly used in the art can be used, such as LCD TVs, mobile phones, computers, watches, etc. Those skilled in the art can make corresponding choices based on the specific purpose of the electronic device, which will not be repeated here.

[0140] It should be noted that in addition to the display panel, the electronic device also includes other necessary components and components, such as the display for example, such as the housing, circuit board, power cord, etc. Those skilled in the art can make corresponding supplements based on the specific usage requirements of the electronic device, which will not be repeated here.

[0141] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. An array substrate, wherein: include: substrate substrate; A plurality of pixel electrodes are arranged in an array on the substrate along row and column directions; The pixel electrode has a plurality of first electrode strips arranged at intervals along the row direction; A plurality of common electrodes are arranged in the same layer as the pixel electrodes, and the common electrodes have a plurality of second electrode strips arranged at intervals along the row direction, and the second electrode strips and the first electrode strips are arranged alternately in the row direction; A plurality of rows of first scanning lines are formed between the base substrate and the pixel electrodes and are located between two adjacent rows of the pixel electrodes; A plurality of columns of second scan lines are formed between the base substrate and the pixel electrodes; the second scan lines are located between two adjacent columns of the pixel electrodes and are electrically connected to the first scan lines through a via structure, and the second scan lines have a scan signal input terminal; A plurality of columns of data lines are formed between the base substrate and the pixel electrode; the data lines have data signal input terminals; both sides of the data lines in the row direction are located inside the two sides of the pixel electrode in the row direction; A plurality of rows of first common signal lines, wherein the first common signal lines and the first scanning lines are arranged in the same layer and are located between two adjacent rows of pixel electrodes; a row of the first common signal lines and a row of the first scanning lines are arranged between two adjacent rows of pixel electrodes, and the first common signal lines and the common electrodes are electrically connected through a via structure; One or more columns of second common signal lines, the second common signal lines and the second scanning lines are arranged in the same layer; the second common signal lines are located between two adjacent columns of the pixel electrodes, and are electrically connected to the first common signal lines of each row through a via structure; both sides of the second common signal lines in the row direction are located inside the two sides of the second electrode strips in the row direction; the second common signal lines have a common signal input terminal; A column of the second scanning lines is arranged between some adjacent columns of pixel electrodes; a column of the second common signal lines is arranged between another adjacent columns of pixel electrodes; the scanning signal input end of the second scanning line, the common signal input end of the second common signal line and the data signal input end of the data line are located on the same side of the substrate.

2. The array substrate according to claim 1, wherein: The sizes of two sides of the data line in the row direction and the center of the pixel electrode in the row direction are equal.

3. The array substrate according to claim 2, wherein: Both sides of the data line in the row direction are located inside both sides of the second electrode strip in the row direction.

4. The array substrate according to claim 3, wherein: The data line and the second scanning line are arranged in the same layer.

5. The array substrate according to claim 4, wherein: In each row, the number of the common electrodes is smaller than the number of the pixel electrodes.

6. The array substrate according to claim 5, wherein: Both sides of the second scanning line in the row direction are located inside both sides of the second electrode strip in the row direction.

7. The array substrate according to claim 1, wherein: The array substrate further includes a first metal line and a second metal line disposed in the same layer as the first scan line, and the first metal line and the second metal line are disconnected from the first scan line; Among them, the orthographic projections of the first metal line and the second metal line on the substrate are located within the orthographic projection of the second electrode strip on the substrate, and are respectively located on both sides of the second scanning line in the row direction or respectively located on both sides of the second common signal line in the row direction.

8. The array substrate according to claim 1, wherein: The size of the second electrode strips in the common electrode corresponding to the data line, the second scanning line and the second common signal line in the row direction is larger than the size of the other second electrode strips in the row direction.

9. The array substrate according to claim 1, wherein: Each row of the first scanning lines is electrically connected to two or more columns of the second scanning lines.

10. The array substrate according to any one of claims 4 to 9, wherein: Also includes: A plurality of driving transistors are arranged in an array on the substrate along row and column directions; Each of the driving transistors corresponds to a pixel electrode; The driving transistor comprises a gate electrode disposed in the same layer as the first scanning line, an active layer located at a side of the gate electrode away from the base substrate, and a source-drain electrode disposed in the same layer as the data line; A gate insulating layer is formed between the gate electrode and the active layer, and the gate insulating layer covers the gate electrode and the first scan line; a passivation layer is formed between the source and drain electrodes and the pixel electrode, and the passivation layer covers the source and drain electrodes, the data line, and the second scan line; The first scanning line is electrically connected to the gate electrode, the data line is electrically connected to the source electrode of the source-drain electrodes, and the pixel electrode is electrically connected to the drain electrode of the source-drain electrodes via a via structure penetrating the passivation layer.

11. The array substrate according to claim 10, wherein: It also includes an organic insulating layer formed between the passivation layer and the pixel electrode, and the pixel electrode is electrically connected to the drain electrode through a via structure penetrating the organic insulating layer and the passivation layer.

12. The array substrate according to claim 11, wherein: It also includes a color filter layer formed between the passivation layer and the organic insulating layer, and the pixel electrode is electrically connected to the drain electrode via a via structure penetrating the organic insulating layer, the color filter layer and the passivation layer.

13. The array substrate according to claim 1, wherein: The first electrode strip and the second electrode strip are bent, and the bending angle of the first electrode strip and the second electrode strip is 150° to 170°.

14. A display panel, wherein: It comprises the array substrate and the counter substrate according to any one of claims 1 to 13.

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