A memory control method, system and related components
By introducing a controller between the processor and memory, and adjusting the memory status bits according to logical jump relationships, the problem of memory conflict crashes during programming is solved, thus improving programming efficiency and success rate.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- GUANGXIN MICROELECTRONICS (SUZHOU) CO LTD
- Filing Date
- 2022-12-16
- Publication Date
- 2026-06-16
AI Technical Summary
During the programming process of a computing device, the interrupt vector table in memory occupies the processor's startup address, which may lead to conflicts and system crashes during programming, and existing technologies cannot avoid this.
By introducing a controller between the processor and memory, the status bits of the memory are adjusted according to the logical jump relationship, ensuring that the processor can execute control instructions in an orderly manner and avoiding programming read-write conflicts.
It improves programming efficiency and success rate, avoids crashes caused by memory status bits not conforming to control instructions during programming, and ensures that the processor can execute instructions smoothly.
Smart Images
Figure CN115933980B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of device programming, and in particular to a memory control method, system, and related components. Background Technology
[0002] The current operating flow of computing devices (such as MCUs, Microcontroller Units) is that when the internal processor (such as the CPU, Central Processing Unit) executes a program, it automatically and continuously retrieves instruction data related to the program from a certain memory. Commonly used memories include embedded flash memory and static RAM (Random Access Memory). Flash memory is a non-volatile memory, and the data will not be lost when the power is off. It is the main program storage memory. Static RAM serves as a cache area. After the computing device is powered on, the data is moved from other memories to the cache area to provide instruction data to the processor.
[0003] Based on the above operating process, the programming operation of the computing device, that is, the action of changing the running program in its memory, requires both reading the running program in the memory and rewriting the running program. If the memory is in a programming state and cannot read the correct instructions, it will cause a system crash.
[0004] To address this issue, the programs required for programming operations within the computing device are typically moved to other memory locations before being written to the internal memory. This mitigates programming conflicts to some extent. However, the programming process still requires access to the interrupt vector table in internal memory. This interrupt vector table occupies the processor's startup address and is stored by default in a specific memory region, which is usually unchangeable. This means that conflicts and system crashes can still occur during programming.
[0005] Therefore, how to provide a solution to the above-mentioned technical problems is a problem that needs to be solved by those skilled in the art. Summary of the Invention
[0006] In view of this, the purpose of this invention is to provide a memory control method, system, and related components to avoid memory crashes caused by conflicts during programming. The specific solution is as follows:
[0007] A memory control method is applied to a controller, wherein a first port of the controller is connected to a processor, and a second port of the controller is connected to a memory to be programmed. The memory control method includes:
[0008] Receive control commands from the processor;
[0009] Determine the target status bit corresponding to the control command;
[0010] Obtain the current status bit of the memory;
[0011] Based on the logical jump relationship between the target state bit and the current state bit, the state bit of the memory is adjusted so that the processor executes the control instruction on the memory.
[0012] Preferably, the status bits include mutually transitional waiting states and occupied states. The process of adjusting the status bits of the memory according to the logical transition relationship between the target status bit and the current status bit includes:
[0013] Determine whether the current status bit is the waiting state;
[0014] If not, wait for the memory's state bit to jump from the current state bit to the waiting state, and then adjust the memory's state bit according to the target state bit;
[0015] If so, adjust the state bits of the memory according to the target state bit.
[0016] Preferably, the waiting state includes a first waiting state and a second waiting state, the occupancy state includes a first occupancy state corresponding to a programming write operation and a second occupancy state corresponding to other occupancy without a programming write operation, and the state bit also includes an intermediate state, which includes a first intermediate state and a second intermediate state.
[0017] The logical jump relationship includes: the jump object of the first waiting state includes the first intermediate state and the second occupied state; the jump object of the second waiting state includes the first occupied state and the second intermediate state; the jump object of the first intermediate state is the first occupied state; the jump object of the second intermediate state is the second intermediate state; the jump object of the first occupied state is the second waiting state; and the jump object of the second occupied state is the first waiting state.
[0018] Preferably, the first intermediate state is a programming preparation state, and the second intermediate state is an exit programming state.
[0019] Preferably, the process of adjusting the state bits of the memory according to the target state bit includes:
[0020] Based on the logical jump relationship and the preset time period corresponding to each state bit, the state bit of the memory is adjusted to the target state bit.
[0021] Preferably, the preset time period is determined based on the logical jump relationship and the control command.
[0022] Preferably, the control commands include write commands, and / or read commands, and / or erase commands.
[0023] Accordingly, this application also discloses a memory control system applied to a controller, wherein a first port of the controller is connected to a processor, and a second port of the controller is connected to a memory to be programmed, and the memory control system includes:
[0024] A receiving module is used to receive control commands from the processor;
[0025] The determination module is used to determine the target status bit corresponding to the control command;
[0026] An acquisition module is used to acquire the current status bits of the memory;
[0027] The control module is used to adjust the state bits of the memory according to the logical jump relationship between the target state bit and the current state bit, so that the processor executes the control instructions on the memory.
[0028] Accordingly, this application also discloses an electronic device, including:
[0029] Memory, used to store computer programs;
[0030] A processor for implementing the steps of the memory control method as described in any of the preceding descriptions when executing the computer program.
[0031] Accordingly, this application also discloses a readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the memory control method described in any of the above claims.
[0032] This application connects the peripheral controller between the processor and the memory. Based on the processor's control instructions and logical jump relationships, it controls the memory's status bits. It controls the memory's status bits according to different execution instructions. If the processor issues a data read control instruction while the memory is in programming mode, the controller will set the memory's status bits from programming mode to read mode. Then, the processor will perform the data read operation on the memory. During the control process, the memory will not be in programming mode and need to be read, thus ensuring that the processor can smoothly execute control instructions on the memory. This avoids conflicts between the processor's programming read / write operations on the memory during programming, improving programming efficiency and success rate. Attached Figure Description
[0033] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0034] Figure 1 This is a flowchart illustrating the steps of a memory control method according to an embodiment of the present invention;
[0035] Figure 2 This is a hardware connection diagram of a memory control method according to an embodiment of the present invention;
[0036] Figure 3 This is a structural distribution diagram of a logical jump relationship in an embodiment of the present invention;
[0037] Figure 4 This is a hardware structure diagram of a memory control method according to an embodiment of the present invention;
[0038] Figure 5 This is a structural distribution diagram of a memory control system according to an embodiment of the present invention. Detailed Implementation
[0039] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0040] During programming, there is still a need to read the interrupt vector table in the internal memory. This interrupt vector table requires the processor's startup address and is stored in a specific area of memory by default. It is usually impossible to change, which means that there is still a possibility of conflict and system crash during programming.
[0041] This application connects the peripheral controller between the processor and the memory, and controls the status bits of the memory according to the processor's control instructions and logical jump relationships, thereby ensuring that the processor can smoothly execute control instructions on the memory, avoiding conflicts between the processor and the memory during programming read and write, and improving programming efficiency and success rate.
[0042] This invention discloses a memory control method, see [link to relevant documentation]. Figure 1 As shown, this is applied to a controller. The first port of the controller is connected to the processor, and the second port of the controller is connected to the memory to be programmed. See [link to relevant documentation]. Figure 2As shown. Specifically, the memory control method includes:
[0043] S1: Receives control instructions from the processor;
[0044] S2: Determine the target status bit corresponding to the control command;
[0045] S3: Get the current status bits of the memory;
[0046] S4: Adjust the memory status bits according to the logical jump relationship between the target status bit and the current status bit, so that the processor can execute control instructions on the memory.
[0047] It is understandable that in this embodiment, the controller acts as a relay platform between the processor and the memory. The processor then executes control instructions on the memory after the controller adjusts the status bits of the memory. Unlike the traditional solution where the processor directly executes control instructions on the memory, this embodiment achieves a similar effect of asynchronous execution through the relay of the controller. The memory status bits are controlled in an orderly manner with logical jump relationships, which to a certain extent achieves the effect of asynchronous execution of control instructions. This avoids the situation where the system crashes due to direct execution of control instructions when the memory status bits do not conform to the control instructions.
[0048] It is understood that in this embodiment, the control instructions are operations performed by the processor on the memory, and therefore the control instructions include at least write instructions, and / or read instructions, and / or erase instructions.
[0049] Furthermore, since the control effect of the memory in this embodiment is to control it in an orderly manner according to the logical jump relationship, the logical jump relationship requires that the status bit of the memory can only jump to the status bit corresponding to another control instruction after the execution of one control instruction. In order to further ensure the control effect of the status bit, a waiting state can be set in the status bit. Once the current control instruction corresponding to the memory is completed, the status bit of the memory will immediately and automatically jump to the waiting state so as to receive the next control instruction and jump to the corresponding state again according to the next jump instruction.
[0050] Specifically, the status bits include mutually transitional waiting and occupied states. The process of adjusting the memory status bits according to the logical transition relationship between the target status bit and the current status bit includes:
[0051] Determine if the current status bit is in a waiting state;
[0052] If not, wait for the memory's status bit to jump from the current status bit to the wait state, and then adjust the memory's status bit according to the target status bit.
[0053] If so, adjust the memory status bits according to the target status bits.
[0054] Furthermore, regarding logical jump relationships, since multiple control instructions correspond to multiple occupied states, one or more waiting states can be set. For example, a waiting state can be set as the center, and all occupied states can be arranged in a star shape around the waiting state. Each occupied state can jump to the central waiting state. Another example is to set up a loop that alternates between waiting states and occupied states. It should be noted that this logical jump relationship restricts the jump path between occupied states to some extent. The logical jump relationship can be designed by considering the connection between occupied states and choosing a loop topology, a central topology, or a combination of loop topology and central topology.
[0055] Specifically, if the occupancy state is divided into occupancy states corresponding to programmed write operations and other occupancy states corresponding to non-programmed write operations, a logical jump relationship as a whole can be set up. The waiting state includes a first waiting state and a second waiting state, and the occupancy state includes a first occupancy state corresponding to programmed write operations and a second occupancy state corresponding to other occupancy states besides programmed write operations. Here, the second occupancy state includes the states corresponding to various operations other than programmed write operations. The jump relationship between multiple second occupancy states and any waiting state can be regarded as the central topology.
[0056] Furthermore, the status bits also include intermediate states, which include a first intermediate state and a second intermediate state. It can be understood that the intermediate states are the status bits required to enter or exit the occupied state, which can further clarify the jump direction in the logical jump relationship of the loop.
[0057] Specifically, refer to Figure 3 As shown, the logical jump relationship in this embodiment includes: the jump object of the first waiting state includes the first intermediate state and the second occupied state; the jump object of the second waiting state includes the first occupied state and the second intermediate state; the jump object of the first intermediate state is the first occupied state; the jump object of the second intermediate state is the second intermediate state; the jump object of the first occupied state is the second waiting state; and the jump object of the second occupied state is the first waiting state.
[0058] Furthermore, the first intermediate state is specifically the pre-programming state, and the second intermediate state is specifically the exit programming state.
[0059] It is understood that the memory control method in this embodiment can be applied to the programming of memory by the processor, such as the programming of internal memory by the internal processor in a computing device. Typically, the memory status bits during the programming process include: ready to program, programming in progress, and exit programming. In this embodiment, a first waiting state and a second waiting state are added, and the programming in progress state and other non-programming occupied states are used as the first and second occupied states, thereby establishing a logical jump relationship in the loop. According to this logical jump relationship, after the processor executes the programming write control instruction, it does not need to exit programming and can directly connect to the next programming write control instruction, achieving high efficiency in continuous programming. At the same time, the processor can also receive other control instructions during the execution of programming write, so that the memory executes each control instruction in an orderly manner according to the order of executing the current control instruction, exiting programming, and executing the next control instruction. No error response or erroneous data will be generated during the transition from continuous programming operation to read operation, and the smoothness of programming and other non-programming control instructions during continuous execution is further ensured.
[0060] It is understood that in this embodiment, the control instructions may also include an exit programming instruction, that is, the target state bit is the first waiting state, and the second intermediate state can directly jump to the first waiting state.
[0061] Furthermore, the process of adjusting the memory's state bits according to the target state bits includes:
[0062] Based on the logical jump relationship and the preset time period corresponding to each status bit, the status bits of the memory are adjusted to the target status bits.
[0063] Specifically, the preset time period is determined based on logical jump relationships and control instructions. It can be understood that in this embodiment, the jump target of the status bit has been determined according to the logical jump relationship. The jump trigger for each status bit can be implemented either based on the processor's execution feedback to the memory or by timing the duration. Specifically, the jump is triggered after the duration of the status bit reaches the corresponding preset time period. Each status bit corresponds to a certain preset time period. After determining the jump path from the current status bit to the target status bit through the logical jump relationship, each status bit traversed on the jump path needs to wait for the corresponding preset time period before the next jump can proceed. The timing of the duration of each status bit can be implemented using a counter, with the preset time period corresponding to a specific value on the counter.
[0064] Understandably, since the waiting state serves as a buffer and for waiting for instructions, the preset time period for the waiting state is zero. If the memory needs to jump from the waiting state to another state, it can jump directly without timing.
[0065] It is understood that in the memory control method of this embodiment, the logical jump relationship can be set by a finite state machine, and the duration of the state bit can be timed by a counter or other timing circuit. The counter is triggered by a start-counting signal issued by the finite state machine. Figure 4 As shown, the finite state machine is used to output the signal controlling the state bit of the memory. Therefore, the finite state machine knows the state bit of the memory at any time and no longer needs to reacquire its current state bit. The controller can be simplified into two parts: a finite state machine and a counter. The memory control method in this embodiment is implemented by the finite state machine and the counter.
[0066] This application connects the peripheral controller between the processor and the memory. Based on the processor's control instructions and logical jump relationships, it controls the memory's status bits. It controls the memory's status bits according to different execution instructions. If the processor issues a data read control instruction while the memory is in programming mode, the controller will set the memory's status bits from programming mode to read mode. Then, the processor will perform the data read operation on the memory. During the control process, the memory will not be in programming mode and need to be read, thus ensuring that the processor can smoothly execute control instructions on the memory. This avoids conflicts between the processor's programming read / write operations on the memory during programming, improving programming efficiency and success rate.
[0067] Accordingly, this application also discloses a memory control system applied to a controller, wherein a first port of the controller is connected to a processor, and a second port of the controller is connected to a memory to be programmed. See [link to relevant documentation]. Figure 5 As shown, the memory control system includes:
[0068] Receiving module 1 is used to receive control commands from the processor;
[0069] Module 2 is used to determine the target status bit corresponding to the control command;
[0070] Acquisition module 3 is used to acquire the current status bit of the memory;
[0071] Control module 4 is used to adjust the state bits of the memory according to the logical jump relationship between the target state bit and the current state bit, so that the processor executes the control instructions on the memory.
[0072] This application connects the peripheral controller between the processor and the memory. Based on the processor's control instructions and logical jump relationships, it controls the memory's status bits. It controls the memory's status bits according to different execution instructions. If the processor issues a data read control instruction while the memory is in programming mode, the controller will set the memory's status bits from programming mode to read mode. Then, the processor will perform the data read operation on the memory. During the control process, the memory will not be in programming mode and need to be read, thus ensuring that the processor can smoothly execute control instructions on the memory. This avoids conflicts between the processor's programming read / write operations on the memory during programming, improving programming efficiency and success rate.
[0073] In some specific embodiments, the status bits include mutually transitional waiting states and occupied states. The process by which the control module 4 adjusts the memory status bits according to the logical transition relationship between the target status bit and the current status bit includes:
[0074] Determine if the current status bit is in a waiting state;
[0075] If not, wait for the memory's status bit to jump from the current status bit to the wait state, and then adjust the memory's status bit according to the target status bit.
[0076] If so, adjust the memory status bits according to the target status bits.
[0077] In some specific embodiments, the waiting state includes a first waiting state and a second waiting state, the occupancy state includes a first occupancy state corresponding to a programming write operation and a second occupancy state corresponding to other occupancy without a programming write operation, and the state bit also includes an intermediate state, which includes a first intermediate state and a second intermediate state.
[0078] The logical jump relationships include: the jump objects of the first waiting state include the first intermediate state and the second occupied state; the jump objects of the second waiting state include the first occupied state and the second intermediate state; the jump object of the first intermediate state is the first occupied state; the jump object of the second intermediate state is the second intermediate state; the jump object of the first occupied state is the second waiting state; and the jump object of the second occupied state is the first waiting state.
[0079] In some specific embodiments, the first intermediate state is specifically a programming preparation state, and the second intermediate state is specifically an exit programming state.
[0080] In some specific embodiments, the process by which the control module 4 adjusts the state bits of the memory according to the target state bit includes:
[0081] Based on the logical jump relationship and the preset time period corresponding to each status bit, the status bits of the memory are adjusted to the target status bits.
[0082] In some specific embodiments, the preset time period is determined based on logical jump relationships and control instructions.
[0083] In some specific embodiments, the control instructions include write instructions, and / or read instructions, and / or erase instructions.
[0084] Accordingly, this application also discloses an electronic device, including:
[0085] Memory, used to store computer programs;
[0086] A processor, configured to implement the steps of the memory control method as described in any of the above embodiments when executing the computer program.
[0087] Accordingly, this application also discloses a readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the memory control method as described in any of the above embodiments.
[0088] For details regarding the memory control method, please refer to the specific description in the above embodiments, which will not be repeated here.
[0089] In this embodiment, the electronic device and the readable storage medium have the same technical effects as the memory control method described in the previous embodiment, and will not be repeated here.
[0090] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0091] The present invention has provided a detailed description of a memory control method, system, and related components. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.
Claims
1. A memory control method, characterized in that, Applied to a controller, wherein a first port of the controller is connected to a processor, and a second port of the controller is connected to a memory to be programmed, the memory control method includes: Receive control commands from the processor; Determine the target status bit corresponding to the control command; Obtain the current status bit of the memory; Based on the logical transition relationship between the target state bit and the current state bit, the state bit of the memory is adjusted so that the processor executes the control instruction on the memory; wherein: The status bits include mutually transitional waiting and occupied states. The process of adjusting the status bits of the memory according to the logical transition relationship between the target status bit and the current status bit includes: Determine whether the current status bit is the waiting state; If not, wait for the memory's state bit to jump from the current state bit to the waiting state, and then adjust the memory's state bit according to the target state bit; If so, adjust the state bits of the memory according to the target state bit; The waiting state includes a first waiting state and a second waiting state. The occupancy state includes a first occupancy state corresponding to a programming write operation and a second occupancy state corresponding to other occupancy states besides non-programming write operations. The state bit also includes an intermediate state, which includes a first intermediate state and a second intermediate state. The logical jump relationship includes: the jump object of the first waiting state includes the first intermediate state and the second occupied state; the jump object of the second waiting state includes the first occupied state and the second intermediate state; the jump object of the first intermediate state is the first occupied state; the jump object of the second intermediate state is the second intermediate state; the jump object of the first occupied state is the second waiting state; and the jump object of the second occupied state is the first waiting state.
2. The memory control method according to claim 1, characterized in that, The first intermediate state is specifically the programming preparation state, and the second intermediate state is specifically the programming exit state.
3. The memory control method according to claim 1, characterized in that, The process of adjusting the state bits of the memory according to the target state bit includes: Based on the logical jump relationship and the preset time period corresponding to each state bit, the state bit of the memory is adjusted to the target state bit.
4. The memory control method according to claim 3, characterized in that, The preset time period is determined based on the logical jump relationship and the control command.
5. The memory control method according to any one of claims 1 to 4, characterized in that, The control commands include write commands, and / or read commands, and / or erase commands.
6. A memory control system, characterized in that, An application is made in a controller, wherein a first port of the controller is connected to a processor, and a second port of the controller is connected to a memory to be programmed. The memory control system includes: A receiving module is used to receive control commands from the processor; The determination module is used to determine the target status bit corresponding to the control command; An acquisition module is used to acquire the current status bits of the memory; The control module is configured to adjust the state bits of the memory according to the logical transition relationship between the target state bit and the current state bit, so that the processor executes the control instructions on the memory; wherein: The status bits include mutually transitional waiting and occupied states. The process of adjusting the status bits of the memory according to the logical transition relationship between the target status bit and the current status bit includes: Determine whether the current status bit is the waiting state; If not, wait for the memory's state bit to jump from the current state bit to the waiting state, and then adjust the memory's state bit according to the target state bit; If so, adjust the state bits of the memory according to the target state bit; The waiting state includes a first waiting state and a second waiting state. The occupancy state includes a first occupancy state corresponding to a programming write operation and a second occupancy state corresponding to other occupancy states besides non-programming write operations. The state bit also includes an intermediate state, which includes a first intermediate state and a second intermediate state. The logical jump relationship includes: the jump object of the first waiting state includes the first intermediate state and the second occupied state; the jump object of the second waiting state includes the first occupied state and the second intermediate state; the jump object of the first intermediate state is the first occupied state; the jump object of the second intermediate state is the second intermediate state; the jump object of the first occupied state is the second waiting state; and the jump object of the second occupied state is the first waiting state.
7. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for implementing the steps of the memory control method as described in any one of claims 1 to 5 when executing the computer program.
8. A readable storage medium, characterized in that, The readable storage medium stores a computer program that, when executed by a processor, implements the steps of the memory control method according to any one of claims 1 to 5.